WO2020042383A1 - 低温多晶硅薄膜晶体管阵列基板及其制造方法 - Google Patents

低温多晶硅薄膜晶体管阵列基板及其制造方法 Download PDF

Info

Publication number
WO2020042383A1
WO2020042383A1 PCT/CN2018/116302 CN2018116302W WO2020042383A1 WO 2020042383 A1 WO2020042383 A1 WO 2020042383A1 CN 2018116302 W CN2018116302 W CN 2018116302W WO 2020042383 A1 WO2020042383 A1 WO 2020042383A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
insulating layer
gate
inter
film transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/116302
Other languages
English (en)
French (fr)
Inventor
陈辰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to US16/308,824 priority Critical patent/US10714504B2/en
Publication of WO2020042383A1 publication Critical patent/WO2020042383A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/431—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present application relates to the field of display technology, and in particular to a low temperature poly-silicon (LTPS) thin film transistor (Thin Film Transistor, TFT) array substrate and a manufacturing method thereof.
  • LTPS low temperature poly-silicon
  • TFT Thin Film Transistor
  • LTPS technology is increasingly favored by manufacturers such as mobile phones and flat screens due to its lower product costs and high electronic mobility of devices.
  • FIG. 1 is a TFT device film structure formed by using a conventional LTPS technology.
  • the TFT device film structure includes a glass substrate 100, a light shielding layer 101 provided on the glass substrate 100, the glass substrate 100, and the light shielding structure.
  • FIG. 2 is a main process flow of the TFT device film layer structure shown in FIG.
  • This process flow diagram requires at least 6 photomasks to manufacture the TFT device film structure shown in FIG. 1.
  • major manufacturers are seeking ways to reduce the number of photomasks used.
  • the object of the present application is to provide a low-temperature polysilicon thin film transistor array substrate and a manufacturing method thereof.
  • the manufacturing method of the low-temperature polysilicon thin film transistor array substrate can effectively reduce the number of photomasks used, thereby reducing production costs.
  • a method for manufacturing a low-temperature polysilicon thin film transistor array substrate includes the following steps:
  • At least one gate insulating layer and at least one insulating layer are sequentially formed on the polysilicon layer, and a first photoresist layer is coated on the gate insulating layer or the inter insulating layer, and the first photoresist layer
  • the gate insulating layer and the inter-insulating layer are processed by an etching process to form source and drain holes and expose a portion of the polysilicon layer. Forming a gate trench on the inter-insulating layer, peeling off the gate insulating layer or the first photoresist layer remaining on the inter-insulating layer;
  • a second photoresist layer is coated on the layer, and after the second photoresist layer is exposed by the photomask and developed by a developing solution, the gate layer is subjected to an etching process to correspond to a portion below the gate trench Forming a gate line on a gate insulating layer or an inter-insulating layer;
  • the depth of the gate trench is less than the sum of the thicknesses of the gate insulating layer and the inter-insulating layer.
  • the gate insulating layer and the inter-insulating layer are formed by chemical vapor deposition at one time.
  • the gate insulating layer is any one of a silicon nitride layer, a silicon oxide layer, a silicon oxide layer, and a composite layer of a silicon nitride layer; and the inter-insulating layer is a silicon nitride layer. Any of a silicon oxide layer, a silicon oxide layer, and a composite layer of a silicon nitride layer.
  • sequentially forming at least one gate insulating layer and at least one insulating layer on the polysilicon layer includes the following steps: forming a first gate insulating layer sequentially stacked on the polysilicon layer, A first interlayer insulating layer, a second gate interlayer, and a second interlayer insulating layer; the first interlayer insulating layer and the first interlayer insulating layer are all silicon oxide layers; the second interlayer insulating layer and the second interlayer insulating layer; The insulating layers are all silicon nitride layers.
  • the thickness of the gate line is the same as the depth of the gate trench.
  • the gate trench is obtained by processing the gate insulating layer and the inter-insulating layer through a dry etching process or a wet etching process.
  • the gate layer is made of at least one of molybdenum, aluminum, copper, and titanium.
  • the method for manufacturing the low-temperature polysilicon thin film transistor array substrate further includes forming a buffer layer on the substrate by using plasma enhanced chemical vapor deposition.
  • the method for manufacturing the low-temperature polysilicon thin film transistor array substrate further includes forming a light-shielding layer on the substrate.
  • the method for manufacturing the low-temperature polysilicon thin film transistor array substrate further includes: forming a data line, the data line is formed on a source electrode, and the source electrode and the gate line are manufactured by a same process .
  • a low-temperature polysilicon thin film transistor array substrate includes:
  • At least one gate insulating layer and at least one insulating layer, the gate insulating layer and the inter insulating layer are sequentially formed on the polysilicon layer;
  • a gate trench is formed on the gate insulating layer or the inter-insulating layer
  • a gate line is formed on the gate insulating layer or the inter-insulating layer corresponding to the gate trench;
  • the depth of the gate trench is less than the sum of the thicknesses of the gate insulating layer and the inter-insulating layer.
  • the gate insulating layer and the inter-insulating layer are formed by chemical vapor deposition at one time.
  • the gate insulating layer is any one of a silicon nitride layer, a silicon oxide layer, a silicon oxide layer, and a composite layer of a silicon nitride layer; and the inter-insulating layer is a silicon nitride layer. Any of a silicon oxide layer, a silicon oxide layer, and a composite layer of a silicon nitride layer.
  • sequentially forming the gate insulating layer and the inter-insulating layer on the polysilicon layer includes the following steps: forming a first gate insulating layer, a first Inter-insulating layer, second gate insulating layer, and second inter-insulating layer, the first gate insulating layer and the first inter-insulating layer are both silicon oxide layers, and the second gate insulating layer and the second inter-insulation layer are insulated
  • the layers are all silicon nitride layers.
  • the thickness of the gate line is the same as the depth of the gate trench.
  • the gate trench is obtained by processing the gate insulating layer and the inter-insulating layer by using a dry etching process or a wet etching process.
  • the gate layer is made of at least one of molybdenum, aluminum, copper, and titanium.
  • the low-temperature polysilicon thin film transistor array substrate further includes a buffer layer formed on the substrate and located between the substrate and the polysilicon layer.
  • the low-temperature polysilicon thin film transistor array substrate further includes a light shielding layer formed on the substrate and located between the substrate and the polysilicon layer.
  • the low-temperature polysilicon thin film transistor array substrate further includes a data line, the data line is formed on a source electrode, and the source electrode and the gate line are made by a same process.
  • the present application provides a low-temperature polysilicon thin film transistor array substrate and a manufacturing method thereof, which are prepared by stacking a gate insulating layer and an inter-insulating layer to provide conditions for forming a gate trench.
  • the gate insulating layer and the inter-insulating layer are prepared by stacking, and a via hole is formed on the gate insulating layer and the inter-insulating layer to form a via pattern (source-drain hole and gate trench) and fill the gate trench.
  • the trenches are used to prepare gate lines and other steps, so that the formation of the gate lines and the formation of the via patterns on the gate insulating layer and the inter-insulating layer can be completed by using the same photomask.
  • the manufacturing process of the low-temperature polysilicon thin film transistor array substrate of the present application can reduce the use of a photomask, that is, the manufacturing method of the low-temperature polysilicon thin film transistor array substrate of the present application reduces the required light compared to the traditional manufacturing method.
  • the number of hoods reduces production costs.
  • FIG. 1 is a schematic diagram of a film structure of a TFT device manufactured by a conventional LTPS process
  • FIG. 2 is a main process flow chart for manufacturing the film structure of the TFT device shown in FIG. 1;
  • FIG. 2 is a main process flow chart for manufacturing the film structure of the TFT device shown in FIG. 1;
  • FIG. 3 is a main process flow chart of a low-temperature polysilicon thin film transistor array substrate according to an embodiment of the present application
  • FIG. 4 is a main process flow chart of a low-temperature polysilicon thin film transistor array substrate according to another embodiment of the present application.
  • 5A, 5B, 5C, 5D, 5E, 5F, 5G, 5H, 5I, and 5J are schematic structural diagrams of the main process flowchart shown in FIG. 4 in each process section.
  • FIG. 3 is a main flowchart of a method for manufacturing a low-temperature polysilicon thin film transistor array substrate according to an embodiment of the present application, including the following steps:
  • the depth of the gate trench is smaller than the sum of the thicknesses of the gate insulating layer and the inter-insulating layer.
  • This embodiment provides a method for manufacturing a low-temperature polysilicon thin film transistor array substrate, which is prepared by stacking a gate insulating layer and an inter-insulating layer to provide conditions for the formation of a gate trench.
  • the thickness of a conventional gate insulating layer is generally only 0.1 micron, and the thickness of the gate line is at least 0.1 micron.
  • the gate insulating layer and the inter-insulating layer are prepared by stacking, and a via hole is formed on the gate insulating layer and the inter-insulating layer to form a via pattern (source-drain hole and gate trench), and Steps such as filling the gate trench to prepare a gate line, so that the formation of the gate line and the formation of the via patterns (source-drain holes and gate trenches) on the gate insulating layer and the inter-insulating layer can be the same
  • the photomask (the photomask used in step S21 and step S22 are the same) can be completed, thereby reducing the number of photomasks used and reducing production costs. Compared with the traditional manufacturing process, the manufacturing process of the low-temperature polysilicon thin film transistor array substrate of the present application can reduce the use of a photomask.
  • FIG. 4 is a main process flow chart of a low-temperature polysilicon thin film transistor array substrate according to another embodiment of the present application, including:
  • a substrate is provided.
  • the substrate is a glass substrate.
  • a light-shielding layer is formed on the glass substrate.
  • a glass substrate 200 is provided, and a light-shielding layer 201 is formed on the glass substrate 200 by using a first photomask.
  • the light-shielding layer 201 is made of metal, and its main function is to block the light emitted to the semiconductor component in the thin film transistor, so as to prevent the light from affecting the electron migration process in the semiconductor component.
  • a buffer layer 202 is optionally formed on the light shielding layer 201 and the glass substrate 200.
  • the buffer layer 202 may be a single-layer structure formed of an insulating material, or may be a stacked structure formed of at least two insulating materials.
  • the buffer layer 202 may be a light-shielding layer formed by a plasma enhanced chemical vapor deposition (PECVD) process.
  • PECVD plasma enhanced chemical vapor deposition
  • the SiN x / SiO x laminated structure formed on 201 and the glass substrate 200, and the buffer layer 202 functions to prevent metal ions (aluminum, barium, sodium, etc.) in the glass substrate from diffusing into the active area of the LTPS during the thermal process.
  • a second photomask is used to form a polysilicon layer on the buffer layer 202.
  • the step of forming the polysilicon layer 203 includes:
  • the polysilicon layer 203 needs to be patterned to obtain an active layer, and then the third photomask is used to perform ion implantation on the active layer.
  • a chemical vapor deposition is used to sequentially form a gate insulating layer 204 and an inter-insulating layer 206 on the polysilicon layer 203.
  • the gate insulating layer 204 and the inter-insulating layer 206 are formed by a first gate insulating layer sequentially superposed on the polysilicon layer,
  • the first insulating layer, the second gate insulating layer, and the second insulating layer are composed of a first insulating layer and a second insulating layer having a thickness of about 0.1 micrometers, and a second insulating layer and a second insulating layer.
  • the thickness of the inter-insulation is 0.4-0.6 microns
  • the gate insulating layer is any one of a silicon nitride layer (SiN x ), a silicon oxide layer (SiO x ), and a composite layer of a silicon nitride layer and a silicon oxide layer.
  • the insulating layer is also any one of a silicon nitride layer (SiN x ), a silicon oxide layer (SiO x ), and a composite layer of a silicon nitride layer and a silicon oxide layer.
  • the first gate insulating layer and the first One insulation layer is a silicon oxide layer
  • the second gate insulation layer and the second insulation layer are silicon nitride layers
  • the first gate insulation layer and the first insulation layer are silicon oxide layers.
  • the second gate insulating layer and the second interlayer insulating layer are made of silicon nitride Enough to play a role of blocking impurities and improving electrical performance and electrical performance, such a preferred preparation method of the gate insulating layer 204 and the inter-insulating layer 206 can further improve the overall performance of the low-temperature polysilicon thin film transistor array substrate.
  • the gate insulating layer and the inter-insulating layer can be produced in one process, compared with the traditional method (the gate insulating layer and the inter-insulating layer are spaced apart). And obtained in two steps), the one-shot process method of this embodiment can shorten the overall process time, thereby improving production efficiency;
  • a first negative photoresist layer 212 is coated on the second insulating layer.
  • a source is formed on the first negative photoresist layer 212.
  • the positioning holes of the drain holes and the positioning grooves of the gate trenches (as shown in FIG. 5C), and then the gate insulating layer and the inter-insulating layer are subjected to a dry etching process or a wet etching process, and the source and drain holes are processed.
  • Source and drain holes 207 are formed on the gate insulating layer 204 and the inter-insulating layer 206 below the corresponding positioning holes, and a portion of the polysilicon layer 203 is exposed.
  • the first inter-insulating layer corresponding to the positioning grooves of the gate trenches A gate trench 211 is formed thereon, and the first negative photoresist layer 212 remaining on the second interlayer insulation layer is peeled off. After this step, the structure shown in FIG. 5D is obtained.
  • the source-drain hole 207 and the gate trench 211 are filled, and a gate layer 210 is formed on the partially exposed polysilicon layer 203 and the second interlayer insulating layer (as shown in FIG. 5E), and the gate layer 210 is coated on A first positive photoresist layer 213 is formed. After the first positive photoresist layer 213 is exposed through a fourth photomask and developed by a developing solution, a first positive photoresist layer 213 is formed to protect the source-drain electrode pattern and the gate line pattern (see FIG. 5F).
  • a gate line 205 is formed above, and a source-drain electrode (208, 209) is formed in the source-drain hole 207. After this step, a structure as shown in FIG. 5G is obtained;
  • the gate layer is made of a conductive material, such as at least one of molybdenum, aluminum, copper, and titanium.
  • the thickness of the gate line is the same as the depth of the gate trench. In this way, the gate trench can be accurately designed. The depth of the trench improves the accuracy of the gate line. Moreover, the thickness of the gate line is higher than the depth of the gate trench, which will increase the difficulty of controlling the etching process, that is, the thickness of the gate line is the same as the depth of the gate trench. It is also beneficial to being able to simplify the formation of the gate layer and reduce unnecessary etching processes.
  • the data line layer 215 is formed on the source-drain electrodes (208, 209), the gate line 205, and the second interlayer insulating layer by physical deposition, as shown in FIG. 5H;
  • a second positive photoresist layer 214 is coated on the data line layer 215.
  • a second positive photoresist layer 214 that protects the data line pattern is left.
  • the other data line layers 215 other than the data line pattern are processed by an etching process, and the remaining second photoresist layer 214 is peeled off to form a data line 216 on the source, as shown in FIG. 5J.
  • the present application also provides a low-temperature polysilicon thin film transistor array substrate manufactured by the above method.

Landscapes

  • Thin Film Transistor (AREA)

Abstract

在多晶硅层（203）上依次形成栅极绝缘层（204）和间绝缘层（206）及其上的过孔图案，该过孔图案包括栅极沟槽（211）和源漏极孔（207）；通过采用栅极绝缘层（204）和间绝缘层（206）的叠层制备，为栅极沟槽（211）的形成提供条件；栅极绝缘层（204）和间绝缘层（206）的叠层制备，配合在栅极绝缘层（204）和间绝缘层（206）上制备过孔以形成过孔图案以及填充过孔图案以制备栅极线（205）等步骤，使得栅极线（205）的形成和过孔图案的形成可以采用相同的光罩即可完成，从而减少光罩使用数量，降低生产成本。

Description

低温多晶硅薄膜晶体管阵列基板及其制造方法 技术领域
本申请涉及显示技术领域，具体涉及一种低温多晶硅（Low Temperature Poly-silicon, LTPS）薄膜晶体管(Thin Film Transistor, TFT)阵列基板及其制造方法。
 背景技术
在显示屏制造领域中，LTPS技术由于其产品成本较低及器件电子迁移率高等特点，越来越受到手机和平板屏幕等制造商的青睐。
传统的LTPS技术所需的膜层较多且膜层结构复杂，造成LTPS的制程过程存在所需曝光次数多及所需光罩数量较多的问题。图1为采用传统LTPS技术形成的TFT器件膜层结构，该TFT器件膜层结构包括玻璃基板100、设于所述玻璃基板100上的遮光层101、设于所述玻璃基板100及所述遮光层101上的缓冲层102、设于所述缓冲层102上的多晶硅层103、设于所述多晶硅层103及所述缓冲层102上的栅极绝缘层104、设于所述栅极绝缘层104上的栅极线105、设于所述栅极线105及所述栅极绝缘层104上的间绝缘层106、设于所述间绝缘层106上且通过源极孔连接所述多晶硅层103的源电极108及设于所述间绝缘层106上且通过漏极孔与所述多晶硅层103连接的漏电极109；图2为图1所示TFT器件膜层结构的主要工艺流程，利用该工艺流程图制造图1所示的TFT器件膜层结构需至少6块光罩。为了解决LTPS TFT器件的制程过程存在所需光罩数量较多导致生产成本提高的问题，各大厂商均在寻求减少光罩使用数量的方法。
 技术问题
本申请的目的在于提供一种低温多晶硅薄膜晶体管阵列基板及其制造方法，该低温多晶硅薄膜晶体管阵列基板的制造方法能够有效地减少光罩使用数量，从而降低生产成本。
 技术解决方案
一种低温多晶硅薄膜晶体管阵列基板的制造方法，包括以下步骤：
提供一基板，在所述基板上形成多晶硅层；
在所述多晶硅层上依次形成至少一栅极绝缘层和至少一间绝缘层，在所述栅极绝缘层或所述间绝缘层上涂布第一光阻层，所述第一光阻层经过一光罩曝光及显影液显影后，采用蚀刻制程处理所述栅极绝缘层和所述间绝缘层以形成源漏极孔并暴露部分的多晶硅层，同时于所述栅极绝缘层或所述间绝缘层上形成栅极沟槽，剥离所述栅极绝缘层或所述间绝缘层上剩余的所述第一光阻层；
填充所述源漏极孔及所述栅极沟槽并在所述部分暴露的多晶硅层、所述栅极绝缘层或/和所述间绝缘层上形成栅极层，再在所述栅极层上涂布第二光阻层，所述第二光阻层经过所述光罩曝光及显影液显影后，对所述栅极层进行蚀刻制程处理以在所述栅极沟槽下方对应的栅极绝缘层或间绝缘层上形成栅极线；
其中，所述栅极沟槽的深度小于所述栅极绝缘层和所述间绝缘层的厚度之和。
在其中一些实施例中，采用化学气相沉积一次形成所述栅极绝缘层和所述间绝缘层。
在其中一些实施例中，所述栅极绝缘层为氮化硅层、氧化硅层、氧化硅层及氮化硅层的复合层中的任意一种；所述间绝缘层为氮化硅层、氧化硅层、氧化硅层及氮化硅层的复合层中的任意一种。
在其中一些实施例中，所述在所述多晶硅层上依次形成至少一栅极绝缘层和至少一间绝缘层包括如下步骤：在所述多晶硅层上形成依次叠加的第一栅极绝缘层、第一间绝缘层、第二栅极绝缘层和第二间绝缘层，所述第一栅极绝缘层和第一间绝缘层都为氧化硅层，所述第二栅极绝缘层和第二间绝缘层都为氮化硅层。
在其中一些实施例中，所述栅极线的厚度与所述栅极沟槽的深度相同。
在其中一些实施例中，所述栅极沟槽是通过干法刻蚀制程或湿法刻蚀制程处理所述栅极绝缘层和所述间绝缘层得到。
在其中一些实施例中，所述栅极层的制备材料为钼、铝、铜、钛中的至少一种。
在其中一些实施例中，在所述基板上形成所述多晶硅层之前，所述低温多晶硅薄膜晶体管阵列基板的制造方法还包括采用等离子体增强化学气相沉积在所述基板上形成缓冲层。
在其中一些实施例中，在所述基板上形成所述多晶硅层之前，所述低温多晶硅薄膜晶体管阵列基板的制造方法还包括在所述基板上形成遮光层。
在其中一些实施例中，所述低温多晶硅薄膜晶体管阵列基板的制造方法还包括：形成数据线，所述数据线形成于源电极上，所述源电极与所述栅极线通过同一制程制得。
一种低温多晶硅薄膜晶体管阵列基板，包括：
一基板，于所述基板上形成的多晶硅层；
至少一栅极绝缘层和至少一间绝缘层，所述栅极绝缘层和所述间绝缘层依次形成于所述多晶硅层上；
栅极沟槽，于所述栅极绝缘层或所述间绝缘层上形成；
栅极线，于所述栅极沟槽下方对应的所述栅极绝缘层或间绝缘层上形成；
其中，所述栅极沟槽的深度小于所述栅极绝缘层和所述间绝缘层的厚度之和。
在其中一些实施例中，采用化学气相沉积一次形成所述栅极绝缘层和所述间绝缘层。
在其中一些实施例中，所述栅极绝缘层为氮化硅层、氧化硅层、氧化硅层及氮化硅层的复合层中的任意一种；所述间绝缘层为氮化硅层、氧化硅层、氧化硅层及氮化硅层的复合层中的任意一种。
在其中一些实施例中，所述栅极绝缘层和所述间绝缘层依次形成于所述多晶硅层上包括如下步骤：在所述多晶硅层上形成依次叠加的第一栅极绝缘层、第一间绝缘层、第二栅极绝缘层和第二间绝缘层，所述第一栅极绝缘层和第一间绝缘层都为氧化硅层，所述第二栅极绝缘层和第二间绝缘层都为氮化硅层。
在其中一些实施例中，所述栅极线的厚度与所述栅极沟槽的深度相同。
在其中一些实施例中，所述栅极沟槽是通过采用干法刻蚀制程或湿法刻蚀制程处理所述栅极绝缘层和所述间绝缘层得到。
在其中一些实施例中，所述栅极层的制备材料为钼、铝、铜、钛中的至少一种。
在其中一些实施例中，所述低温多晶硅薄膜晶体管阵列基板还包括缓冲层，所述缓冲层形成于所述基板上且位于所述基板和所述多晶硅层之间。
在其中一些实施例中，所述低温多晶硅薄膜晶体管阵列基板还包括遮光层，所述遮光层形成于所述基板上且位于所述基板和所述多晶硅层之间。
在其中一些实施例中，所述低温多晶硅薄膜晶体管阵列基板还包括数据线，所述数据线形成于源电极上，所述源电极与所述栅极线通过同一制程制得。
 有益效果
本申请提供一种低温多晶硅薄膜晶体管阵列基板及其制造方法，通过栅极绝缘层和间绝缘层的叠层制备，为栅极沟槽的形成提供条件。另外，栅极绝缘层和间绝缘层的叠层制备，配合在栅极绝缘层和间绝缘层上制备过孔以形成过孔图案（源漏极孔及栅极沟槽）以及填充栅极沟槽以制备栅极线等步骤，使得栅极线的形成和栅极绝缘层和间绝缘层上的过孔图案的形成可以采用相同的光罩即可完成。相对于传统的制造工艺，本申请低温多晶硅薄膜晶体管阵列基板的制造过程可以减少一块光罩的使用，即本申请的低温多晶硅薄膜晶体管阵列基板的制造方法相对传统的制造方法减少了所需的光罩数量，从而降低生产成本。
 附图说明
图1为采用传统的LTPS工艺制造的TFT器件膜层结构示意图；
图2为制造图1所示TFT器件膜层结构的主要工艺流程图；
图3为本申请一实施例的低温多晶硅薄膜晶体管阵列基板的主要工艺流程图；
图4为本申请另一实施例的低温多晶硅薄膜晶体管阵列基板的主要工艺流程图；
图5A、5B、5C、5D、5E 、5F、5G、5H、5I及5J为图4所示主要工艺流程图在各个工艺段的结构示意图。
附图中示出的部件标注如下：
100、200玻璃基板；101、201 遮光层；102、202缓冲层；103、203 多晶硅层；104、204 栅极绝缘层；105、205 栅极线；106、206 间绝缘层；207 源漏极孔；108、208源电极；109、209漏电极；210 栅极层；211 栅极沟槽；212、213、214 光阻层；215数据线层；216 数据线
 本发明的实施方式
下面结合本申请实施例中的附图，对本申请所提供的各个示例性的实施例的技术方案进行清楚、完整地描述。在不冲突的情况下，下述各个实施例以及实施例中的特征可以相互组合。并且，本申请全文所采用的方向性术语，例如“上”、“下”等，均是为了更好的描述各个实施例的技术方案，并非用于限制本申请的保护范围。
请参阅图3，为本申请一实施例的低温多晶硅薄膜晶体管阵列基板的制造方法的主要流程图，包括以下步骤：
S20，提供一基板，在基板上形成多晶硅层；
S21，在多晶硅层上依次形成至少一栅极绝缘层和至少一间绝缘层，在栅极绝缘层或间绝缘层上涂布第一光阻层，第一光阻层经过一光罩曝光及显影液显影后，采用蚀刻制程处理栅极绝缘层和间绝缘层以形成源漏极孔并暴露部分的多晶硅层，同时于栅极绝缘层或间绝缘层上形成栅极沟槽，剥离栅极绝缘层或间绝缘层上剩余的第一光阻层；
S22，填充源漏极孔及栅极沟槽并在部分暴露的多晶硅层、栅极绝缘层或/和间绝缘层上形成栅极层，再在栅极层上涂布第二光阻层，第二光阻层经过光罩曝光及显影液显影后，对栅极层进行蚀刻制程处理以在栅极沟槽下方对应的栅极绝缘层或间绝缘层上形成栅极线；
其中，栅极沟槽的深度小于栅极绝缘层和间绝缘层的厚度之和。
本实施例提供的是低温多晶硅薄膜晶体管阵列基板的制造方法，通过栅极绝缘层和间绝缘层的叠层制备，为栅极沟槽的形成提供条件；传统的栅极绝缘层的厚度一般仅为0.1微米，而栅极线的厚度至少为0.1微米，通过在栅极绝缘层上形成栅极沟槽并填充栅极沟槽以恰好形成栅极线时，单层栅极绝缘层的厚度不能满足栅极沟槽的厚度需求。而在本申请中，栅极绝缘层和间绝缘层的叠层制备，配合在栅极绝缘层和间绝缘层上制备过孔以形成过孔图案（源漏极孔及栅极沟槽）以及填充栅极沟槽以制备栅极线等步骤，使得栅极线的形成和栅极绝缘层和间绝缘层上的过孔图案（源漏极孔及栅极沟槽）的形成可以采用相同的光罩(步骤S21和步骤S22中使用的光罩是相同的)即可完成，从而减少光罩使用数量，降低生产成本。相对于传统的制造工艺，本申请低温多晶硅薄膜晶体管阵列基板的制造过程可以减少一块光罩的使用。
请参阅图4，为本申请另一实施例的低温多晶硅薄膜晶体管阵列基板的主要工艺流程图，包括：
S200，提供一基板，该基板为玻璃基板，可选地，在玻璃基板上形成遮光层；
具体地，提供一玻璃基板200，利用第一光罩在玻璃基板200上形成遮光层201。遮光层201由金属制成，主要作用是遮挡射向薄膜晶体管中半导体构件的光线，以避免该光线对半导体构件中的电子迁移过程产生影响。经过上述步骤，得到如图5A所示的结构。
S201，形成缓冲层和多晶硅层；
具体地，在形成多晶硅层203之前，可选地，在遮光层201和玻璃基板200上形成缓冲层202。该缓冲层202可以是由绝缘材料形成的单层结构，也可以是由至少两种绝缘材料形成的叠层结构，例如缓冲层202可为通过等离子体增强化学气相沉积（PECVD ）工艺在遮光层201和玻璃基板200上形成的SiN x/SiO x叠层结构，缓冲层202的作用是防止玻璃基板中的金属离子（铝、钡以及钠等）在热工艺中扩散到LTPS的有源区。
接着，再利用第二光罩在缓冲层202上形成多晶硅层，形成多晶硅层203的步骤包括：
通过化学气相沉积在缓冲层202上形成非晶硅层，通过准分子激光退火法将非晶硅层202进行晶化处理后，得到多晶硅层203；
经过此步骤得到如图5B所示的结构。
S202，离子植入；
具体地，在离子植入之前，需要对多晶硅层203进行图案化处理以得到有源层，再利用第三光罩对有源层进行离子植入。
S203，在多晶硅层上依次形成至少一栅极绝缘层和至少一间绝缘层，在栅极绝缘层或间绝缘层上涂布第一光阻层，第一光阻层经过一光罩曝光及显影液显影后，采用蚀刻制程处理栅极绝缘层和间绝缘层以形成源漏极孔并暴露部分的多晶硅层，同时于栅极绝缘层或间绝缘层上形成栅极沟槽，剥离栅极绝缘层或间绝缘层上剩余的第一光阻层；
具体地，采用化学气相沉积在多晶硅层203上依次形成栅极绝缘层204和间绝缘层206，栅极绝缘层204和间绝缘层206由依次叠加在多晶硅层上的第一栅极绝缘层、第一间绝缘层、第二栅极绝缘层以及第二间绝缘层组成，其中，第一栅极绝缘层和第二栅极绝缘层的厚度为0.1微米左右，第二间绝缘层和第二间绝缘的厚度为0.4-0.6微米，栅极绝缘层是氮化硅层（SiN x）、氧化硅层（SiO x）以及氮化硅层与氧化硅层的复合层中的任意一种，间绝缘层也是氮化硅层（SiN x）、氧化硅层（SiO x）以及氮化硅层与氧化硅层的复合层中的中的任意一种，优选地，第一栅极绝缘层和第一间绝缘层都为氧化硅层，第二栅极绝缘层和第二间绝缘层为氮化硅层，第一栅极绝缘层和第一间绝缘层都为氧化硅层能够起到保温以及抗氧化作用，第二栅极绝缘层和第二间绝缘层为氮化硅层能够起到阻隔杂质并提高电性能和电学表现的作用，栅极绝缘层204和间绝缘层206的此种优选制备方法相互配合能够进一步地提高低温多晶硅薄膜晶体管阵列基板的综合性能。此外，由于栅极绝缘层和间绝缘层的叠层结构，使得栅极绝缘层和间绝缘层可以采用一次制程制得，相较于传统方法（栅极绝缘层和间绝缘层是被间隔开且分两次制得的），本实施例的一次制程法能够缩短整体的制程时间，从而提高生产效率；
接着，在第二间绝缘层上涂布第一负光阻层212，第一负光阻层212经过第四光罩曝光并经过显影液显影后，在第一负光阻层212上形成源漏极孔的定位孔和栅极沟槽的定位槽（如图5C所示），再对栅极绝缘层和间绝缘层进行干法蚀刻制程或湿法刻蚀制程处理，在源漏极孔的定位孔下方所对应的栅极绝缘层204和间绝缘层206上形成源漏极孔207并暴露部分的多晶硅层203，同时在栅极沟槽的定位槽下方所对应的第一间绝缘层上形成栅极沟槽211，剥离第二间绝缘层上剩余的第一负光阻层212，经过此步骤得到如图5D所示的结构。
S204，填充源漏极孔及栅极沟槽并在部分暴露的多晶硅层、栅极绝缘层或/和间绝缘层上形成栅极层，再在栅极层上涂布第二光阻层，第二光阻层经过光罩曝光及显影液显影后，对栅极层进行蚀刻制程处理以在栅极沟槽下方对应的栅极绝缘层或间绝缘层上形成栅极线；其中，栅极沟槽的深度小于栅极绝缘层和间绝缘层的厚度之和；
具体地，填充源漏极孔207及栅极沟槽211并在部分暴露的多晶硅层203、第二间绝缘层上形成栅极层210（如图5E所示），在栅极层210上涂布第一正光阻层213，第一正光阻层213经过第四光罩曝光及显影液显影后，形成对源漏电极图案以及栅极线图案进行保护的第一正光阻层213(如图5F所示)，再对未被第一正光阻层213保护的栅极层210进行蚀刻制程处理，然后处理剩余的第一正光阻层213，在栅极沟槽211下方对应的第一间绝缘层上方形成栅极线205，同时，在源漏极孔207中形成源漏电极（208，209），经过此步骤得到如图5G所示的结构；
其中，栅极层的制备材料为导电材料，例如钼、铝、铜、钛中的至少一种；栅极线的厚度与栅极沟槽的深度相同，如此，可以通过准确地设计栅极沟槽的深度从而提高栅极线的精确度，而且，栅极线的厚度高于栅极沟槽的深度，会提高蚀刻制程的控制难度，即栅极线的厚度与栅极沟槽的深度相同也有利于能够简化栅极层的形成并减少不必要的刻蚀制程。
S205，形成数据线；
具体地，采用物理沉积在源漏电极（208，209）、栅极线205以及第二间绝缘层上形成数据线层215，如图5H所示；
接着，在数据线层215上涂布第二正光阻层214，第二正光阻层214经过第五光罩曝光后及显影液显影后，剩下保护数据线图案的第二正光阻层214(如图5I所示)，通过蚀刻制程处理掉数据线图案之外的其他数据线层215，再剥离剩余的第二光阻层214，在源极上形成数据线216，如图5J所示。
此外，本申请还提供一种通过上述方法制造的低温多晶硅薄膜晶体管阵列基板。
在此基础上，以上所述仅为本申请的实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，例如各实施例之间技术特征的相互结合，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (20)

  1. 一种低温多晶硅薄膜晶体管阵列基板的制造方法，其中，包括以下步骤：
    提供一基板，在所述基板上形成多晶硅层；
    在所述多晶硅层上依次形成至少一栅极绝缘层和至少一间绝缘层，在所述栅极绝缘层或所述间绝缘层上涂布第一光阻层，所述第一光阻层经过一光罩曝光及显影液显影后，采用蚀刻制程处理所述栅极绝缘层和所述间绝缘层以形成源漏极孔并暴露部分的多晶硅层，同时于所述栅极绝缘层或所述间绝缘层上形成栅极沟槽，剥离所述栅极绝缘层或所述间绝缘层上剩余的所述第一光阻层；
    填充所述源漏极孔及所述栅极沟槽并在所述部分暴露的多晶硅层、所述栅极绝缘层或/和所述间绝缘层上形成栅极层，再在所述栅极层上涂布第二光阻层，所述第二光阻层经过所述光罩曝光及显影液显影后，对所述栅极层进行蚀刻制程处理以在所述栅极沟槽下方对应的栅极绝缘层或间绝缘层上形成栅极线；
    其中，所述栅极沟槽的深度小于所述栅极绝缘层和所述间绝缘层的厚度之和。
  2. 根据权利要求1所述的低温多晶硅薄膜晶体管阵列基板的制造方法，其中，所述在所述多晶硅层上依次形成至少一栅极绝缘层和至少一间绝缘层的步骤包括：采用化学气相沉积一次形成所述栅极绝缘层和所述间绝缘层。
  3. 根据权利要求1所述的低温多晶硅薄膜晶体管阵列基板的制造方法，其中，所述栅极绝缘层为氮化硅层、氧化硅层、氧化硅层及氮化硅层的复合层中的任意一种；所述间绝缘层为氮化硅层、氧化硅层、氧化硅层及氮化硅层的复合层中的任意一种。
  4. 根据权利要求1所述的低温多晶硅薄膜晶体管阵列基板的制造方法，其中，所述在所述多晶硅层上依次形成至少一栅极绝缘层和至少一间绝缘层包括如下步骤：在所述多晶硅层上形成依次叠加的第一栅极绝缘层、第一间绝缘层、第二栅极绝缘层和第二间绝缘层，所述第一栅极绝缘层和第一间绝缘层都为氧化硅层，所述第二栅极绝缘层和第二间绝缘层都为氮化硅层。
  5. 根据权利要求1所述的低温多晶硅薄膜晶体管阵列基板的制造方法，其中，所述栅极线的厚度与所述栅极沟槽的深度相同。
  6. 根据权利要求1所述的低温多晶硅薄膜晶体管阵列基板的制造方法，其中，所述栅极沟槽是通过干法刻蚀制程或湿法刻蚀制程处理所述栅极绝缘层和所述间绝缘层得到。
  7. 根据权利要求1所述的低温多晶硅薄膜晶体管阵列基板的制造方法，其中，所述栅极层的制备材料为钼、铝、铜、钛中的至少一种。
  8. 根据权利要求1所述的低温多晶硅薄膜晶体管阵列基板的制造方法，其中，在所述基板上形成所述多晶硅层之前，所述低温多晶硅薄膜晶体管阵列基板的制造方法还包括采用等离子体增强化学气相沉积在所述基板上形成缓冲层。
  9. 根据权利要求1所述的低温多晶硅薄膜晶体管阵列基板的制造方法，其中，在所述基板上形成所述多晶硅层之前，所述低温多晶硅薄膜晶体管阵列基板的制造方法还包括在所述基板上形成遮光层。
  10. 根据权利要求1所述的低温多晶硅薄膜晶体管阵列基板的制造方法，其中，所述低温多晶硅薄膜晶体管阵列基板的制造方法还包括：形成数据线，所述数据线形成于源电极上，所述源电极与所述栅极线通过同一制程制得。
  11. 一种低温多晶硅薄膜晶体管阵列基板，其中，包括：
    一基板，于所述基板上形成的多晶硅层；
    至少一栅极绝缘层和至少一间绝缘层，所述栅极绝缘层和所述间绝缘层依次形成于所述多晶硅层上；
    栅极沟槽，于所述栅极绝缘层或所述间绝缘层上形成；
    栅极线，于所述栅极沟槽下方对应的所述栅极绝缘层或间绝缘层上形成；
    其中，所述栅极沟槽的深度小于所述栅极绝缘层和所述间绝缘层的厚度之和。
  12. 根据权利要求11所述的低温多晶硅薄膜晶体管阵列基板，其中，采用化学气相沉积一次形成所述栅极绝缘层和所述间绝缘层。
  13. 根据权利要求11所述的低温多晶硅薄膜晶体管阵列基板，其中，所述栅极绝缘层为氮化硅层、氧化硅层、氧化硅层及氮化硅层的复合层中的任意一种；所述间绝缘层为氮化硅层、氧化硅层、氧化硅层及氮化硅层的复合层中的任意一种。
  14. 根据权利要求11所述的低温多晶硅薄膜晶体管阵列基板，其中，所述栅极绝缘层和所述间绝缘层依次形成于所述多晶硅层上包括如下步骤：在所述多晶硅层上形成依次叠加的第一栅极绝缘层、第一间绝缘层、第二栅极绝缘层和第二间绝缘层，所述第一栅极绝缘层和第一间绝缘层都为氧化硅层，所述第二栅极绝缘层和第二间绝缘层都为氮化硅层。
  15. 根据权利要求11所述的低温多晶硅薄膜晶体管阵列基板，其中，所述栅极线的厚度与所述栅极沟槽的深度相同。
  16. 根据权利要求11所述的低温多晶硅薄膜晶体管阵列基板，其中，所述栅极沟槽是通过采用干法刻蚀制程或湿法刻蚀制程处理所述栅极绝缘层和所述间绝缘层得到。
  17. 根据权利要求11所述的低温多晶硅薄膜晶体管阵列基板，其中，所述栅极层的制备材料为钼、铝、铜、钛中的至少一种。
  18. 根据权利要求11所述的低温多晶硅薄膜晶体管阵列基板，其中，所述低温多晶硅薄膜晶体管阵列基板还包括缓冲层，所述缓冲层形成于所述基板上且位于所述基板和所述多晶硅层之间。
  19. 根据权利要求11所述的低温多晶硅薄膜晶体管阵列基板，其中，所述低温多晶硅薄膜晶体管阵列基板还包括遮光层，所述遮光层形成于所述基板上且位于所述基板和所述多晶硅层之间。
  20. 根据权利要求11所述的低温多晶硅薄膜晶体管阵列基板，其中，所述低温多晶硅薄膜晶体管阵列基板还包括数据线，所述数据线形成于源电极上，所述源电极与所述栅极线通过同一制程制得。
PCT/CN2018/116302 2018-08-29 2018-11-20 低温多晶硅薄膜晶体管阵列基板及其制造方法 Ceased WO2020042383A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/308,824 US10714504B2 (en) 2018-08-29 2018-11-20 Low temperature poly-silicon thin film transistor array substrate and method of producing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810995637.7A CN109300849B (zh) 2018-08-29 2018-08-29 低温多晶硅薄膜晶体管阵列基板及其制造方法
CN201810995637.7 2018-08-29

Publications (1)

Publication Number Publication Date
WO2020042383A1 true WO2020042383A1 (zh) 2020-03-05

Family

ID=65165870

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/116302 Ceased WO2020042383A1 (zh) 2018-08-29 2018-11-20 低温多晶硅薄膜晶体管阵列基板及其制造方法

Country Status (3)

Country Link
US (1) US10714504B2 (zh)
CN (1) CN109300849B (zh)
WO (1) WO2020042383A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104637955A (zh) * 2015-01-30 2015-05-20 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN105097550A (zh) * 2015-08-04 2015-11-25 深圳市华星光电技术有限公司 低温多晶硅薄膜晶体管的制作方法及低温多晶硅薄膜晶体管
CN106847744A (zh) * 2017-02-20 2017-06-13 合肥京东方光电科技有限公司 阵列基板的制备方法、阵列基板及显示装置
CN107946368A (zh) * 2017-11-22 2018-04-20 深圳市华星光电半导体显示技术有限公司 顶栅型薄膜晶体管的制作方法及顶栅型薄膜晶体管

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5080978B2 (ja) * 2005-09-30 2012-11-21 シャープ株式会社 薄膜トランジスタアレイ基板の製造方法
CN105355588B (zh) * 2015-09-30 2018-06-12 深圳市华星光电技术有限公司 Tft阵列基板的制备方法、tft阵列基板及显示装置
CN106981520B (zh) * 2017-04-12 2020-07-07 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、阵列基板和显示装置
US10249654B1 (en) 2017-11-22 2019-04-02 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Manufacturing method of top-gate TFT and top-gate TFT

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104637955A (zh) * 2015-01-30 2015-05-20 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN105097550A (zh) * 2015-08-04 2015-11-25 深圳市华星光电技术有限公司 低温多晶硅薄膜晶体管的制作方法及低温多晶硅薄膜晶体管
CN106847744A (zh) * 2017-02-20 2017-06-13 合肥京东方光电科技有限公司 阵列基板的制备方法、阵列基板及显示装置
CN107946368A (zh) * 2017-11-22 2018-04-20 深圳市华星光电半导体显示技术有限公司 顶栅型薄膜晶体管的制作方法及顶栅型薄膜晶体管

Also Published As

Publication number Publication date
CN109300849B (zh) 2020-12-25
US20200111818A1 (en) 2020-04-09
CN109300849A (zh) 2019-02-01
US10714504B2 (en) 2020-07-14

Similar Documents

Publication Publication Date Title
CN103715137B (zh) 阵列基板及其制造方法、显示装置
CN105390451B (zh) 低温多晶硅tft基板的制作方法
CN103123910B (zh) 阵列基板及其制造方法、显示装置
US10236388B2 (en) Dual gate oxide thin-film transistor and manufacturing method for the same
WO2019223755A1 (zh) 阵列基板及其制造方法、显示面板
WO2014012334A1 (zh) 阵列基板的制造方法及阵列基板、显示装置
WO2016112663A1 (zh) 制作阵列基板的方法和阵列基板
WO2021248609A1 (zh) 一种阵列基板及其制备方法以及显示面板
CN111341849A (zh) 显示基板及其制备方法、显示面板
CN109509707A (zh) 显示面板、阵列基板、薄膜晶体管及其制造方法
WO2020006831A1 (zh) 一种阵列基板及其制作方法
CN110098201A (zh) 晶体管器件及其制造方法、显示基板、显示装置
WO2015188594A1 (zh) 多晶硅层及显示基板的制备方法、显示基板
WO2021026990A1 (zh) 一种阵列基板及其制作方法
US9711602B2 (en) Method of making thin film transistor array and source/drain contact via-interconnect structures formed thereby
CN105355588A (zh) Tft阵列基板的制备方法、tft阵列基板及显示装置
CN105097950A (zh) 薄膜晶体管及制作方法、阵列基板、显示装置
WO2020147216A1 (zh) Tft阵列基板的制备方法及tft阵列基板
CN109037241B (zh) Ltps阵列基板及其制造方法、显示面板
WO2020037850A1 (zh) 阵列基板及其制造方法、显示面板
WO2019210602A1 (zh) 阵列基板及其制造方法、显示面板
CN105990332A (zh) 薄膜晶体管基板及其显示面板
WO2020042278A1 (zh) 一种ltps阵列基板的制造方法
WO2015096239A1 (zh) 一种薄膜电晶体场效应管及其制造方法
WO2019095562A1 (zh) Tft基板的制作方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18932099

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18932099

Country of ref document: EP

Kind code of ref document: A1