WO2020042278A1 - 一种ltps阵列基板的制造方法 - Google Patents

一种ltps阵列基板的制造方法 Download PDF

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WO2020042278A1
WO2020042278A1 PCT/CN2018/109315 CN2018109315W WO2020042278A1 WO 2020042278 A1 WO2020042278 A1 WO 2020042278A1 CN 2018109315 W CN2018109315 W CN 2018109315W WO 2020042278 A1 WO2020042278 A1 WO 2020042278A1
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layer
insulation
gate
gate line
inter
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陈辰
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1303—Apparatus specially adapted to the manufacture of LCDs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/44—Physical vapour deposition [PVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials

Definitions

  • the present application relates to the field of liquid crystal display, and in particular, to a method for manufacturing a low temperature poly-silicon (LTPS) array substrate.
  • LTPS low temperature poly-silicon
  • LTPS low temperature poly-silicon
  • the LTPS array substrate needs to undergo two chemical vapor deposition processes on the polysilicon layer during the manufacturing process in order to form a gate insulation layer.
  • Insulator (GI) and Interlayer Dielectric (ILD) are used as the LTPS array substrate.
  • ILD Interlayer Dielectric
  • FIG. 1 is a schematic cross-sectional structure diagram of a conventional LTPS array substrate.
  • the light shielding layer 102, the buffer layer 103, and the polysilicon layer 104 are sequentially stacked on the glass substrate 101, and then the chemical vapor deposition (CVD) is performed on the polysilicon layer 104 twice.
  • CVD chemical vapor deposition
  • the existing LTPS array substrate manufacturing method requires more films, the manufacturing method is complicated, the manufacturing time is longer, and the production cost is higher. Therefore, it is necessary to provide a LTPS array substrate manufacturing method to improve this defect.
  • the present application provides a manufacturing method of an LTPS array substrate, which is used to solve the technical problems that the existing LTPS array substrate manufacturing process technology requires a large number of film layers and a complicated manufacturing method.
  • the LTPS array substrate includes at least a metal light-shielding layer, a buffer layer, a polysilicon layer, a gate insulation and inter-insulation layer, a gate layer, and a source and drain layer;
  • the manufacturing method includes at least:
  • Step S10 providing a transparent substrate, depositing a metal layer on the transparent substrate, patterning the metal layer to form the metal light-shielding layer;
  • Step S20 forming the buffer layer on the metal light-shielding layer
  • Step S30 forming the polysilicon layer on the buffer layer
  • Step S40 forming the gate insulation and the inter-insulation layer by chemical vapor deposition on the polysilicon layer
  • Step S50 forming the gate line layer on the gate insulation and inter-insulation layer.
  • Step S60 forming the source and drain layers on the gate insulation and inter-insulation layers.
  • the step S50 includes:
  • Step S501 coating a negative photoresist on the gate insulation and inter-insulation layer for exposure to form a patterned photoresist layer;
  • Step S502 performing a dry etching process on the gate insulation and inter-insulation layer after development to etch the gate line trench;
  • Step S503 forming the gate line layer in the gate line trench by a physical vapor deposition method
  • Step S504 coating a positive photoresist on the gate line layer, and performing an exposure etching process to form a gate line pattern;
  • the gate insulation and the inter-insulation layer have a two-layer structure.
  • step 502 a dry etching process is performed on the gate insulation and the inter-insulation layer to etch the gate line trench. groove.
  • a cross-sectional shape of the gate line trench is rectangular.
  • the step S60 includes:
  • a source electrode and a drain electrode are formed on the via hole, and the source electrode and the drain electrode are respectively in contact with a polysilicon layer through the corresponding via hole to form the source electrode and the drain layer.
  • the cross-sectional shape of the via hole is an inverted trapezoid.
  • the gate line layer material is a stack combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the buffer layer material is silicon nitride, silicon oxide, or a combination of the two; the gate insulation and the inter-insulation layer are used in the LTPS array substrate manufacturing process.
  • the materials used include silicon nitride, silicon oxide, or a combination of the two.
  • the material of the metal light-shielding layer is molybdenum aluminum alloy, chromium, molybdenum, or other materials having both light-shielding function and conductive properties.
  • the beneficial effect of the present invention is that without changing the structure of the original semiconductor device, the gate insulation and the inter-insulation layer formed by performing two chemical vapor deposition processes can be reduced to one chemical vapor deposition process through optimization of the process method.
  • the formation reduces the thickness of the LTPS array substrate film layer, reduces the process steps, saves the process time, and reduces the production cost.
  • FIG. 1 is a schematic cross-sectional structure diagram of a conventional LTPS array substrate
  • FIG. 2 is a schematic cross-sectional structure diagram of a chemical vapor deposition gate insulation and an inter-insulation layer described in a manufacturing method provided by the present application;
  • FIG. 3 is a schematic cross-sectional structure diagram of a gate line trench in a manufacturing method provided by the present application.
  • FIG. 4 is a schematic cross-sectional structure diagram of a gate line layer in a manufacturing method provided by the present application.
  • FIG. 5 is a schematic cross-sectional structure diagram of an LTPS array substrate obtained by the manufacturing method described in this application;
  • FIG. 6 is a schematic diagram of steps of the manufacturing method described in this application.
  • FIG. 7 is another schematic cross-sectional structure diagram of an LTPS array substrate obtained by the manufacturing method described in this application.
  • a method for manufacturing an LTPS array substrate is provided in this application. The manufacturing method is described in detail below with reference to FIGS. 2 to 6.
  • the manufacturing method includes the following steps:
  • a substrate 201 is provided.
  • the substrate 201 is usually made of a transparent glass substrate.
  • a metal layer is deposited on the substrate 201, and the metal layer is patterned by a photolithography process to form a metal light-shielding layer 202 on the substrate 201.
  • the material of the metal light-shielding layer 202 is molybdenum aluminum alloy, Chromium, molybdenum, or other materials that have both light shielding and conductive properties.
  • a buffer layer 203 is formed on the metal light-shielding layer 202.
  • the material of the buffer layer 203 is silicon nitride, silicon oxide, or a combination of the two.
  • step S30 an amorphous silicon layer is deposited on the buffer layer 203, and the amorphous silicon layer is subjected to a dehydrogenation process using a high-temperature oven to prevent hydrogen explosion during the crystallization process.
  • the amorphous silicon layer is crystallized by a crystallization process such as a laser annealing process, a metal induced crystallization process, and a solid phase crystallization process, and a polysilicon layer 204 is formed on the buffer layer 203.
  • Step S40 using a chemical vapor deposition method to form a first gate insulation and inter-insulation layer 205 and a second gate insulation and inter-insulation layer 206 on the buffer layer 203 and the polysilicon layer 204, the gate insulation and inter-insulation layer
  • the selected material is silicon nitride or silicon oxide or a combination of the two.
  • a negative photoresist is coated on the second gate insulation and inter-insulation layer 206 for exposure to form a patterned photoresist layer;
  • a dry etching process is performed on the insulating layer 206 to etch a gate line trench 301.
  • the gate line trench 301 has a rectangular cross-section, and the negative photoresist material is molybdenum aluminum alloy, chromium, molybdenum, or Other conductive materials with low resistance.
  • a gate line layer 404 is formed in the gate line trench 301 by a physical vapor deposition method, and the material of the gate line layer is one or more of molybdenum, titanium, aluminum, and copper.
  • a stack combination and then coating a positive photoresist 402 on the gate line layer 401 by an exposure and etching process to form a gate line pattern.
  • a first via hole 501 and a second via hole 502 are formed through the gate insulation and the interlayer insulation layer through dry etching.
  • the cross-sectional shape of the via hole is an inverted trapezoid, and the first The exposed portion of the second via 502 of the via 501 is a patterned polysilicon layer 204.
  • a source 503 is formed in the first via 501, and a drain 504 is formed in the second via 502.
  • the source 503 and The drain electrode 504 is in contact with the polysilicon layer 204 via the first via hole 501 and the second via hole 502, respectively.
  • the gate line layer 401 is in the same layer as the source electrode 503 and the drain electrode 504, reducing the thickness of the array substrate film layer. .
  • a gate line trench is formed by digging a groove in the formed gate insulation and inter-insulation layer, and then a gate line is formed in the gate line trench to realize the gate line.
  • the design on the same layer as the source and the drain is simpler and reduces the thickness of the array substrate film. However, it requires a process of forming the gate trench through exposure etching and physical vapor deposition.
  • a polysilicon layer 701 a first gate insulation layer, and Structures such as the inter-insulating layer 702, the second gate insulation, and the inter-insulation layer 703 are directly coated with a layer of positive photoresist on the second gate insulation and the inter-insulation layer 703.
  • an etching process is performed. A via hole and a subsequent pattern are formed at the etching position.
  • a first via hole 704 and a second via hole 708 are formed through the gate insulation and the interlayer insulation layer through a dry etching process, and the exposed portions of the first via hole 704 and the second via hole 708 are patterned.
  • the obtained polysilicon layer 701 forms a source electrode 707 on the first via hole 704 and a drain electrode 705 on the second via hole 708.
  • the source electrode 707 and the drain electrode 705 respectively pass through the first via hole. 704 and the second via 708 are in contact with the polysilicon layer.
  • the gate insulation and the inter-insulation layer that need to be formed by two chemical vapor deposition processes can be shortened to one chemical vapor deposition process, which can reduce the cost.
  • the thickness of the LTPS array substrate film layer reduces the number of process steps, saves process time, and reduces production costs.

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  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

一种LTPS阵列基板的制造方法， LTPS阵列基板至少包括金属遮光层、缓冲层、多晶硅层（204）、栅极绝缘及间绝缘层（205，206）、栅极线层（401）以及源漏电极层（503，504），采用一次化学气相沉积制程形成栅极绝缘及间绝缘层，并通过在栅极绝缘及间绝缘层上形成栅极线沟槽，降低了LTPS阵列基板膜层的厚度，减少了制程步骤。

Description

一种LTPS阵列基板的制造方法 技术领域
本申请涉及液晶显示领域，尤其涉及一种低温多晶硅（Low Temperature Poly-silicon，LTPS）阵列基板的制造方法。
 背景技术
在显示屏制造中，低温多晶硅（Low Temperature Poly-silicon，LTPS）技术由于其产品成本较低、器件电子迁移率高等特点，越来越受到手机、平板屏幕等制造商的青睐。
在传统的LTPS制程工艺中，LTPS阵列基板在制程中需要在多晶硅层上经过2次化学气相沉积制程，才能形成栅极绝缘层（Gate Insulator，GI）及间绝缘层（Interlayer Dielectric，ILD），而且栅极绝缘层和间绝缘层各自为两层结构。
 技术问题
如图1所示，图1是现有技术LTPS阵列基板的截面结构示意图。在现有的LTPS阵列基板的结构中，遮光层102、缓冲层103和多晶硅层104依次层叠形成于玻璃基板101上，然后在多晶硅层104上通过2次化学气相沉积（Chemical Vapor Deposition，CVD）制程，形成第一栅极绝缘层105、第二栅极绝缘层106、栅极线层112、第一间绝缘层107和第二间绝缘层108，最后通过曝光刻蚀制程形成源极111与漏极109的过孔110，源极111和漏极109通过过孔110与多晶硅层104相接触。
因此，现有LTPS阵列基板制程方法所需膜层较多，制程方法复杂，制程时间较长，生产成本较高。故，有必要提供一种LTPS阵列基板制程方法来改善这一缺陷。
 技术解决方案
本申请提供一种LTPS阵列基板的制造方法，用于解决现有LTPS阵列基板制程技术所需膜层较多，制程方法复杂的技术问题。
本申请提供的制作方法中，所述LTPS阵列基板至少包括金属遮光层、缓冲层、多晶硅层、栅极绝缘及间绝缘层、栅极层以及源极和漏极层；
在本申请实施例所提供的LTPS阵列基板的制造方法中，所述制作方法至少包括：
步骤S10：提供一透明基板，在所述透明基板上沉积一金属层，图案化所述金属层，形成所述金属遮光层；
步骤S20：在所述金属遮光层上形成所述缓冲层；
步骤S30：在所述缓冲层上形成所述多晶硅层；
步骤S40：在所述多晶硅层上通过化学气相沉积形成所述栅极绝缘及间绝缘层；
步骤S50：在所述栅极绝缘及间绝缘层上，形成所述栅极线层。
步骤S60：在所述栅极绝缘及间绝缘层上形成所述源极和漏极层。
在本申请实施例所提供的LTPS阵列基板的制造方法中，所述步骤S50包括：
步骤S501：在所述栅极绝缘及间绝缘层上涂布一层负性光阻进行曝光，形成图案化的光阻层；
步骤S502：显影后在所述栅极绝缘及间绝缘层上进行干刻蚀制程，刻蚀出栅极线沟槽；
步骤S503：在所述栅极线沟槽中通过物理气相沉积方法形成所述栅极线层；
步骤S504：在所述栅极线层上涂布正性光阻，进行曝光刻蚀制程形成栅极线图案；
在本申请实施例所提供的LTPS阵列基板的制造方法中，所述栅极绝缘及间绝缘层为两层结构。
在本申请实施例所提供的LTPS阵列基板的制造方法中，所述步骤502中，在所述栅极绝缘及间绝缘层的上方进行干刻蚀制程，以刻蚀出所述栅极线沟槽。
在本申请实施例所提供的LTPS阵列基板的制造方法中，所述栅极线沟槽的截面形状为矩形。
在本申请实施例所提供的LTPS阵列基板的制造方法中，所述步骤S60包括：
S601：在所述栅极绝缘及间绝缘层上对应于所述多晶硅层的上方曝光显影后，进行刻蚀制程，刻蚀出过孔及后续图案；
S602：在所述过孔上形成源极和漏极，所述源极和所述漏极分别经由对应的所述过孔与多晶硅层相接触，构成所述源极和漏极层。
在本申请实施例所提供的LTPS阵列基板的制造方法中，所述过孔的截面形状为倒置梯形。
在本申请实施例所提供的LTPS阵列基板的制造方法中，所述栅极线层材料是钼、钛、铝和铜中的一种或多种的堆栈组合。
在本申请实施例所提供的LTPS阵列基板的制造方法中，所述缓冲层材料为氮化硅、氧化硅或两者的结合；所述栅极绝缘及间绝缘层在LTPS阵列基板制程中所使用的材料包括氮化硅、氧化硅或者两者的结合。
在本申请实施例所提供的LTPS阵列基板的制造方法中，所述金属遮光层的材料为钼铝合金、铬、钼或是其他同时具有遮光功能和导电性质的材料。
 有益效果
本发明的有益效果：在不改变原始半导体器件结构的情况下，通过制程方法的优化，将需要进行两次化学气相沉积制程形成的栅极绝缘及间绝缘层减少为一次化学气相沉积制程就能够形成，降低了LTPS阵列基板膜层的厚度，减少了制程步骤，节省制程时间，从而降低生产成本。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术LTPS阵列基板的截面结构示意图；
图2为本申请提供制作方法中所述化学气相沉积的栅极绝缘及间绝缘层的截面结构示意图；
图3为本申请提供制作方法中所述栅极线沟槽的截面结构示意图；
图4为本申请提供制作方法中所述栅极线层的截面结构示意图；
图5为本申请所述制作方法获得的LTPS阵列基板的截面结构示意图；
图6位本申请所述制作方法的步骤示意图。
图7为本申请所述制作方法获得的LTPS阵列基板的另一截面结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
下面结合附图和具体实施例对本发明做进一步的说明：
实施例一：
在本申请提供一种LTPS阵列基板的制造方法，以下结合图2至图6对所述制作方法进行详细描述。
如图所示，所述制作方法包括以下步骤：
步骤S10，如图2所示，提供一基板201，所述基板201通常选用透明玻璃基板材质。在所述基板201上沉积一层金属层，通过光刻蚀制程图案化所述金属层，在所述基板201上形成金属遮光层202，通常所述金属遮光层202的材料为钼铝合金、铬、钼或是其他同时具有遮光功能和导电性质的材料。
步骤S20，在所述金属遮光层202上形成缓冲层203。所述缓冲层203的材料为氮化硅、氧化硅或者两者的结合。
步骤S30，在缓冲层203上沉积一层非晶硅层，采用高温烤箱对所述非晶硅层进行脱氢工艺处理，以防止在晶化过程中出现氢爆现象。脱氢工艺完成后，采用激光退火工艺、金属诱导结晶工艺、固相结晶工艺等结晶化工艺方法对非晶硅层进行结晶化处理，在缓冲层203上形成多晶硅层204。
步骤S40，采用化学气相沉积的方法在缓冲层203和多晶硅层204上形成第一栅极绝缘及间绝缘层205和第二栅极绝缘及间绝缘层206，所述栅极绝缘及间绝缘层选用的材料为氮化硅或氧化硅或者两者的结合。
步骤S50，如图3所示，在第二栅极绝缘及间绝缘层206上涂布一层负性光阻进行曝光，形成图案化的光阻层；显影后在第二栅极绝缘及间绝缘层206上进行干刻蚀制程，刻蚀出栅极线沟槽301，所述栅极线沟槽301的截面形状为矩形，所述负性光阻材料为钼铝合金、铬、钼或者是其他低电阻的导电材料。如图4所示，在栅极线沟槽301中通过物理气相沉积的方法形成栅极线层404，所述栅极线层材料是钼、钛、铝和铜中的一种或多种的堆栈组合；再在所述栅极线层401上涂布正性光阻402曝光刻蚀制程，形成栅极线图案。
步骤S60，如图5所示，用干刻蚀形成贯穿所述栅极绝缘及间绝缘层的第一过孔501第二过孔502所述过孔的截面形状是倒置梯形，所述第一过孔501第二过孔502露出的部分是图形化处理的多晶硅层204，在所述第一过孔501形成源极503，在所述第二过孔502形成漏极504，源极503和漏极504分别经由第一过孔501和第二过孔502与多晶硅层204相接触，所述栅极线层401与源极503、漏极504处于同一层，减少了阵列基板膜层的厚度。
实施例二：
在实施例一中，通过在形成的栅极绝缘及间绝缘层中挖槽的方法，形成栅极线沟槽，再在栅极线沟槽中形成栅极线，实现了所述栅极线与源极、漏极处于同一层的设计，这样的结构较为简单，减少了阵列基板膜层的厚度，但需要经过曝光刻蚀、物理气相沉积等形成栅极沟槽的工艺流程。
如图7所示，在本实施例中，取消了栅极线沟槽的制作步骤，在经过如同实施例一中所述的步骤S10~S40之后，形成多晶硅层701、第一栅极绝缘及间绝缘层702、第二栅极绝缘及间绝缘层703等结构，直接在第二栅极绝缘及间绝缘层703上涂布一层正性光刻胶，进行曝光显影后，进行刻蚀制程，刻蚀处形成过孔以及后续的图案。
通过干刻蚀制程形成贯穿所述栅极绝缘及间绝缘层的第一过孔704和第二过孔708，所述第一过孔704和第二过孔708所暴露出来的部分是图形化处理得到的多晶硅层701，在所述第一过孔704上形成源极707，在所述第二过孔708上形成漏极705，所述源极707和漏极705分别经由第一过孔704和第二过孔708与多晶硅层相接触。
本申请在不改变原始半导体器件结构的情况下，通过制程方法的优化，将需要进行两次化学气相沉积制程形成的栅极绝缘及间绝缘层缩短为一次化学气相沉积制程就能够形成，降低了LTPS阵列基板膜层的厚度，减少了制程步骤，节省制程时间，从而降低生产成本。
综上所述，虽然本申请以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为基准。

Claims (10)

  1. 一种LTPS阵列基板的制造方法，其中：LTPS阵列基板至少包括金属遮光层、缓冲层、多晶硅层、栅极绝缘及间绝缘层、栅极线层以及源极和漏极层，所述制作方法至少包括：
    步骤S10：提供一透明基板，在所述透明基板上沉积一金属层，图案化所述金属层，形成所述金属遮光层；
    步骤S20：在所述金属遮光层上形成所述缓冲层；
    步骤S30：在所述缓冲层上形成所述多晶硅层；
    步骤S40：在所述多晶硅层上通过化学气相沉积形成所述栅极绝缘及间绝缘层；
    步骤S50：在所述栅极绝缘及间绝缘层上，形成所述栅极线层；
    步骤S60：在所述栅极绝缘及间绝缘层上形成所述源极和漏极层。
  2. 如权利要求1所述的制作方法，其中：所述步骤S50包括：
    步骤S501：在所述栅极绝缘及间绝缘层涂布一层负性光阻进行曝光，形成图案化的光阻层；
    步骤S502：显影后在所述栅极绝缘及间绝缘层上进行干刻蚀制程，刻蚀出栅极线沟槽；
    步骤S503：在所述栅极线沟槽中通过物理气相沉积形成所述栅极线层；
    步骤S504：在所述栅极线层上涂布正性光阻，进行曝光刻蚀制程制程栅极线图案。
  3. 如权利要求2所述的制作方法，其中：所述栅极绝缘及间绝缘层为两层结构。
  4. 如权利要求3所述的制作方法，其中：所述步骤502中，在所述栅极绝缘及间绝缘层的上方进行干刻蚀制程，以刻蚀出所述栅极线沟槽。
  5. 如权利要求4所述的制作方法，其中：所述栅极线沟槽的截面形状为矩形。
  6. 如权利要求1所述的制作方法，其中：所述步骤S60包括：
    S601：在所述栅极绝缘及间绝缘层上对应于所述多晶硅层的上方曝光显影后，进行刻蚀制程，刻蚀出过孔及后续图案；
    S602：在所述过孔中形成源极和漏极，所述源极和所述漏极分别经由对应的所述过孔与多晶硅层相接触，形成所述源极和漏极层。
  7. 如权利要求6所述的制作方法，其中：所述过孔的截面形状为倒置梯形。
  8. 如权利要求1所述的制作方法，其中：所述栅极线层材料是钼、钛、铝和铜中的一种或多种的堆栈组合。
  9. 如权利要求1所述的制作方法，其中：所述缓冲层材料为氮化硅、氧化硅或两者的结合；所述栅极绝缘及间绝缘层在所述LTPS阵列基板制程中所使用的材料包括氮化硅、氧化硅或者两者的结合。
  10. 如权利要求1所述的制作方法，其中：所述金属遮光层的材料为钼铝合金、铬、钼或是其他同时具有遮光功能和导电性质的材料。
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