Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
  • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
  • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
  • H01L21/0274—Photolithographic processes
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
  • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
  • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
  • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
  • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
  • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76841—Barrier, adhesion or liner layers
  • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76841—Barrier, adhesion or liner layers
  • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
  • H01L21/76846—Layer combinations
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76841—Barrier, adhesion or liner layers
  • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/5226—Via connections in a multilevel interconnection structure
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
  • H01L21/76832—Multiple layers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76841—Barrier, adhesion or liner layers
  • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
  • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal

Definitions

• the invention relates to semiconductor micro fabrication including systems and processes for patterning, deposition, and removal of materials on a given substrate or wafer.
• creating patterned layers includes application of a thin layer of radiation-sensitive material, such as photoresist, to an upper surface of a substrate.
• the thin layer of radiation-sensitive material is transformed into a relief pattern which can be used as an etch mask to transfer a pattern into an underlying layer on a substrate.
• Patterning of the thin layer of radiation-sensitive material generally involves an exposure process to actinic radiation through a reticle (and associated optics) onto the thin layer of radiation-sensitive material by using, for example, a photo-lithography system.
• the exposure process can then be followed by a removal of irradiated regions of the thin layer of radiation-sensitive material (as in a case of positive photoresist), or non-irradiated regions (as in a case of negative resist) by using a developing solvent.
• the etch mask can further include multiple sub-layers.
• CMOS complementary metal-oxide-semiconductor
• CMOS complementary metal-oxide-semiconductor
• an additional challenge is associated with overlay between two photolithographic processes, such as photolithographic misalignment. If masks and patterns are not properly aligned, device defects and failures can occur. For example, lines can be either partially cut or not cut at desired locations, openings can be misplaced, or shorts can be otherwise created. Such a misalignment also brings challenges during metallization of substrates when multiple layers of metal lines and vias are interconnected with underlying transistors. Another challenge associated with the metallization is to create trenches and vias without damaging surrounding dielectric material.
• Techniques (or methods) herein include methods for patterning substrates, such as forming patterns during metallization in back end of line (BEOL). Techniques herein enable fully self-aligned vias and lines. Techniques herein include using selective growth of bilayer dielectrics to enable self-alignment of trench and via patterning without using etch-stop layers or films with undesirable compositions.
• a first dielectric layer can provide electric isolation from adjacent metal lines, while a second dielectric layer can prevent etching of the first dielectric during formation of trench and via patterning. Both the dielectric layers can be deposited in a same chamber and remain on the substrate within a wiring layer instead of being removed like most etch-stop layers.
• a method for processing a substrate is provided.
• a substrate is provided.
• the substrate includes a first dielectric layer, and a plurality of conductive structures formed in the first dielectric layer.
• a top surface of the first dielectric layer is level with top surfaces of the conductive structures.
• a conductive cap layer is then formed over the conductive structures, where the conductive cap layer is selectively positioned over the conductive structures with a top surface and sidewalls.
• a second dielectric layer is subsequently formed over the first dielectric layer. The second dielectric layer is selectively positioned over the first dielectric layer so that the top surface of the conductive cap layer is exposed or uncovered, and the sidewalls of the conductive cap layer are in direct contact with the second dielectric layer
• a third dielectric layer is formed over the second dielectric layer, where the third dielectric layer is selectively positioned over the second dielectric layer so that the top surface of the conductive cap layer is exposed or uncovered, and is lower than a top surface of the third dielectric layer.
• a fourth dielectric layer is then formed over the plurality of conductive structures and the third dielectric layer.
• An interconnect structure is subsequently formed within the fourth dielectric layer.
• the interconnect structure includes a via structure that has a first portion positioned over the conductive cap layer so that sidewalls of the first portion are in direct contact with the third dielectric layer, and a second portion disposed over the first portion and the third dielectric layer.
• the third dielectric layer can have an etch selectivity to the fourth dielectric layer such that an etching plasma can remove the fourth dielectric layer faster than remover the third dielectric layer.
• the third dielectric layer can be made of metal-containing dielectric material, or any dielectric material which has some degree of etch selectivity to the fourth dielectric layer.
• the conductive cap layer is selectively deposited on the plurality of conductive structures after the second dielectric layer is formed.
• each of the conductive structures includes at least one of a via structure and a line structure.
• the conductive cap layer can include at least one of ruthenium, tungsten, nickel, or cobalt.
• the third dielectric layer can be made of metal-containing dielectric material.
• a height of the second dielectric layer is at least twice as great as a height of the third dielectric layer.
• the second dielectric layer and the third dielectric layer are formed in a same deposition chamber.
• the conductive cap layer, the second and third dielectric layers are formed by using a common processing tool.
• the processing tool includes one or more chambers that are configured to form the conductive cap layer, the second dielectric layer and the third dielectric layer respectively.
• an interconnect opening can be formed in the fourth dielectric layer, where the interconnect opening includes a trench opening and a via opening that is positioned below the trench opening and exposes one of the plurality of the conductive structures.
• a barrier layer (or liner) is formed to cover the interconnect opening and the exposed (or uncovered) one of the plurality of conductive structures.
• a conductive layer is subsequently formed over the barrier layer to fill the interconnect opening, where the conductive layer further covers a top surface of the fourth dielectric layer.
• a surface planarization process is performed to remove excessive conductive layer over the top surface of the fourth dielectric layer.
• the conductive layer can be formed through multiple approaches including (a) bottom-fill deposition in which the top of the conductive layer is level with the top surface of the fourth dielectric film, (b) a deposition of the conductive layer such that the resulting over-burden of the conductive layer relative to the fourth dielectric film is minimal and very uniform where either an etch-recess or surface planarization process can be performed to remove excessive conductive layer over the top surface of the fourth dielectric layer, or (c) a traditional deposition of the conductive layer where the conductive layer covers a top surface of the fourth dielectric layer where a surface
• planariazation process can be performed to remove excessive conductive layer over the top surface of the fourth dielectric layer
• the third dielectric layer is configured to protect the second dielectric layer from the etching process when the interconnect opening is formed within the fourth dielectric layer.
• the height of the second dielectric layer is in a range from 3nm to 15nm so that the second dielectric layer prevents an electric short between the conductive structures and the interconnect structure.
• a semiconductor device is provided.
• a plurality of conductive structures are arranged in a first dielectric layer, where top surfaces of the plurality of the conductive structures and a top surface of the first dielectric layer are co-planar.
• a conductive cap layer is selectively positioned over the conductive structures with a top surface and sidewalls.
• a second dielectric layer is selectively positioned over the first dielectric layer so that the sidewalls of the conductive cap layer are in direct contact with the second dielectric layer.
• a third dielectric layer is selectively positioned over the second dielectric layer so that the top surface of the conductive cap layer is lower than a top surface of the third dielectric layer.
• the height difference mentioned above between the conductive cap layer and the third dielectric layer provides a self- alignment for a subsequently formed via structure.
• a fourth dielectric layer is arranged over the plurality of conductive structures and the third dielectric layer.
• An interconnect structure is further posited in the fourth dielectric layer.
• the interconnect structure includes a trench structure and a via structure that is positioned below the trench structure and connected to the trench structure.
• the via structure has a first portion positioned over the conductive cap layer so that sidewalls of the first portion are in direct contact with the third dielectric layer, and a second portion disposed over the first portion and the third dielectric layer.
• the height difference between the conductive cap layer and the third dielectric layer, and the etch selectivity between the third dielectric layer and the fourth dielectric layer provides the self-alignment between the via structure and the conductive cap layer.
• a first conductive structure is formed in a first dielectric layer, where the first conductive structure extends into the first dielectric layer from a top surface of the first dielectric layer.
• a conductive cap layer is selectively disposed over the conductive structure with a top surface and sidewalls. Further, a dielectric stack is
• the disclosed device also includes a second conductive structure that is formed over the first conductive structure.
• the second conductive structure has a first portion positioned over the conductive cap layer so that sidewalls of the first portion are in direct contact with the dielectric stack, and a second portion disposed over the first portion and the dielectric stack.
• FIGS. 1 -6 are cross-sectional views of various intermediate steps of
• FIG. 7 is a schematic view of a first semiconductor equipment configured to form an interconnect structure, in accordance with some embodiments.
• FIG. 8 is a schematic view of a second semiconductor equipment configured to form an interconnect structure, in accordance with some embodiments.
• FIG. 9 is a schematic view of a third semiconductor equipment configured to form an interconnect structure, in accordance with some embodiments.
• FIG. 10 is a flowchart of a process for manufacturing an interconnect structure, in accordance with some embodiments.
• spatially relative terms such as“beneath,”“below,”“lower,”“above,” “upper” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures.
• the spatially relative terms are intended to encompass different orientations of the apparatus in use or operation in addition to the orientation depicted in the figures.
• the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted
• embodiment means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment, but do not denote that they are present in every embodiment.
• appearances of the phrases“in one embodiment” in various places through the specification are not necessarily referring to the same embodiment.
• particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.
• Techniques disclosed herein include methods of patterning substrates such as for back end of line (BEOL) metallization processes.
• Techniques disclosed herein enable fully self-aligned vias and lines, which includes using selective growth of bilayer dielectrics to enable self-alignment of trench and via patterning without using etch-stop layers or films with undesirable compositions.
• a first dielectric layer can provide electric isolation from adjacent conductive components, such as metal lines, while a second dielectric layer can prevent etching of the first dielectric during the formation of the trench and via patterns.
• Both the first and second dielectric layers can be deposited in a same chamber and remain on the substrate within a wiring layer (also referred to as a dielectric layer) instead of being removed like most etch-stop layers.
• one related technique provides self-alignment of conductive structures by recessing copper lines and vias below a top surface of surrounding dielectric material.
• a copper recessing can introduce significant integration issues (e.g., edge placement error) and bring potential contamination issues.
• one or more dielectric layers can be introduced that surround an underlying conductive structure through a vertically deposited/regrown process to help provide a self-alignment between the underlying conductive structure and a overlying conductive structure.
• the one or more selectively deposited dielectric layers can include two layers that are made of two different dielectric materials.
• the selectively deposited dielectric layers can include a silicon dioxide structure with a relatively thin, metal oxide cap.
• Both the bi-layer oxide (e.g., S1O2 and metal oxide) layers can be deposited in situ in a same processing chamber or in a same tool/platform. In the disclosed techniques, via CD tolerances can be reduced by 10 nanometers.
• the metal oxide layer i.e. , the second dielectric layer
• the metal oxide layer can function as a protection layer to prevent etching of the first dielectric layers that is disposed under the metal oxide layer during the formation of the trench and via patterns, where the first and second dielectric layers provide the self-alignment between the underlying conductive structure (e.g., a copper metal line, a tungsten contact, a copper via, and the like) and the trench and via patterns.
• an etch stop layer is normally deposited above the underlying conductive structure. During the formation of the trench and via patterns, the etch stop layer needs to be removed. The removal of the etch stop layer can cause damage of the underlying conductive structure.
• FIGS. 1 -6 are cross-sectional views of various intermediate steps of
• a substrate 100 is provided (received, obtained, or otherwise fabricated).
• the substrate 100 has a plurality of conductive structures 106 that are made of a first conductive material.
• the conductive structures 106 can be formed within a first wiring layer (also referred to as a first dielectric layer) 102 that is made of a first dielectric material.
• a first wiring layer also referred to as a first dielectric layer
• three conductive structures 106a-106b are formed in the first wiring layer 102.
• the first wiring layer 102 defines a planar surface 102a that is uncovered (exposed or otherwise accessible) with which top surfaces of the conductive structures 106 are level so that the top surfaces of the conductive structures 106 are also uncovered.
• such a substrate can include a given first wiring layer 102 after copper fill and chemical-mechanical polishing to complete the conductive structures 106.
• the conductive structures 106 can be lines and/or vias.
• such a substrate 100 can be ready for fabricating an additional wiring layer or additional structure over the top surface 102a.
• the first wiring layer (or first dielectric layer) 102 can be a low-K film, a SiO layer, or other suitable dielectric layer.
• the conductive structures can be made of copper, ruthenium, tungsten, nickel, cobalt, or other suitable conductive materials.
• a barrier layer 104 can be formed between the conductive structures 106 and the first wiring layer 102.
• the barrier layer 104 can be made of Ti, TiN, Ta, TaN, or other suitable materials.
• a conductive cap layer (or metal cap) 108 can be selectively deposited on the uncovered top surfaces of the conductive structures 106 without being deposited on the top surface 102a of the first wiring layer 102.
• the conductive cap layer 108 can have a top surface 108a and sidewalls 108b.
• the conductive cap layer can include, but are not limited to, ruthenium, cobalt, tungsten, and nickel.
• FIG. 2B are three images obtained through a scanning transmission electron microscopy (STEM) to illustrate an exemplary conductive cap layer.
• a left image illustrates a conductive structure and a conductive cap layer that is formed over the conductive structure based on the STEM.
• a middle image illustrates an elemental analysis data obtained from the conductive structure. The middle image shows that the conductive structure is made of copper.
• a right image illustrates another elemental analysis data obtained from the conductive cap layer. The right image shows that the conductive cap layer is a ruthenium layer.
• the conductive cap layer 108 can be made through a CVD process, a PVD process, a sputter process, a diffusion process, an atomic layer deposition process or other suitable deposition processes.
• FIGS. 7-9 exemplary equipment that can form the conductive cap layer 108 can be illustrated in FIGS. 7-9.
• a second dielectric layer 1 10 is selectively grown/deposited on the uncovered top surface 102a of the first dielectric layer 102. Accordingly, the top surface 108a of the conductive cap layer 108 is exposed (or uncovered), and the sidewalls 108b of the conductive cap layer 108 are in direct contact with the second dielectric layer 1 10. In some embodiments, the sidewalls 108b of the conductive cap layer 108 are surrounded by the second dielectric layer 1 10.
• the first and second dielectric layers can be made of a same material.
• the first dielectric layer 102 is made of S1O2
• the second dielectric layer 1 10 is also made of S1O2.
• the first and the second dielectric layers are made of different materials.
• the first dielectric layer 102 is a low-k layer and the second dielectric layer 1 10 is a SiO layer.
• the second dielectric layer 1 10 can have a thickness in a range from 3nm to 15nm.
• a k-value of the second dielectric layer 1 10 can be less than 4.
• other suitable k-values can be applied according to the circuit design requirements.
• a top surface 1 10a of the second dielectric layer 1 10 can be higher than the top surface 108a of the conductive cap layer 108.
• the top surface 1 10a of the second dielectric layer 1 10 can be lower than the top surface 108a of the conductive cap layer 108 according to the deposition process.
• the second dielectric layer 1 10 can be made through a CVD process, a PVD process, a sputter process, a diffusion process, an atomic layer deposition process or other suitable deposition processes.
• An exemplary equipment that can form the second dielectric layer 1 10 can be illustrated in FIGS. 7-9.
• a third dielectric layer 1 12 can be selectively grown on the second dielectric layer 1 10. Accordingly, the top surface 108a of the conductive cap layer 108 is still exposed or uncovered, and is lower than a top surface 1 12a of the third dielectric layer 1 12.
• a plurality of recess regions 1 13 can be formed in the third dielectric layer 1 12.
• the recess regions 1 13 can have sidewalls that expose the third dielectric layers 1 12. In some embodiments, the sidewalls of the recess regions 1 13 can further expose a portion of the second dielectric layers 1 10.
• the recess regions 1 13 can have a bottom portion that expose the conductive cap layer 108.
• the third dielectric layer 1 12 can have an etch resistivity that differs from an etch resistivity of the second dielectric layer 1 10.
• the third dielectric layer 1 12 can have a thickness between 1 nm and 5nm.
• the third dielectric layer 1 12 can be made of a metal-containing dielectric or metal oxide, such as AI2O3, Hf02, Zr02, T1O2, and combinations thereof.
• the third dielectric layer 1 12 can be a non-metal containing dielectric, such as SiC or SiCN, that has an etch selectivity to the fourth dielectric layer such that an etching plasma can remove the fourth dielectric layer faster than remover the third dielectric layer.
• the third dielectric layer 1 12 can be relatively thin as compared to the second dielectric layer 1 10.
• a height of the second dielectric layer can be at least twice as great as a height of the third dielectric layer.
• the second and third dielectric layers can have other thickness ratio according to different manufacturing conditions.
• a second wiring layer (also referred to as fourth dielectric layer) 1 14 is formed over the third dielectric layer 1 12 and the conductive cap layer 108 so that the recess regionsl 13 are filled by the second wiring layer 1 14.
• the second wiring layer 1 14 is made of a fourth dielectric material, such as a low-K material, S1O2, or other suitable dielectric materials.
• the fourth dielectric layer 1 14 can cover the second and third dielectric layers and the conductive cap layer, and provide a planar top surface.
• the substrate 100 can be coated with the fourth dielectric layer 1 14 in order to form additional metal layer in the subsequent steps.
• integrated circuits can have a number of wiring layers, such as 10-20 wiring layers. After one wiring layer is completed (usually after metallization and planarization of a given layer), a next wiring layer can be created.
• a hard mask layer 1 16 can be formed over the fourth dielectric layer 1 14.
• the hard mask layer 1 16 can be a single layer, such as a TiN layer, or include multiple layers.
• a photoresist layer (not shown) can be deposited and patterned through a lithography process (e.g.,
• photolithography or e-beam lithography which may further include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, photoresist developing, rinsing, drying (e.g., spin-drying and/or hard baking), and the like. Patterns formed in the photoresist can be subsequently transferred by an etching process into the hard mask layer, and further into portions of the second wiring layer 1 14 to form one or more interconnect openings (not shown). Each of the interconnect openings can have a trench opening and/or via opening for subsequent metallization to form one or more interconnect structures, such as one or more dual damascene structures. [0043] In FIG.
• the interconnect openings formed therein can be metallized, that is, filled with a conductive material 120.
• the conductive material 120 can be copper, tungsten, ruthenium, cobalt, or other suitable materials.
• Such a metallization can include depositing a liner (or barrier layer) 122 followed by depositing the bulk conductive material 120.
• the bulk conductive material 120 can further cover a top surface of the fourth dielectric layer 1 14.
• a surface planarization process such as a CMP process, can be applied to remove excessive conductive material 120 from the top surface of the fourth dielectric layer.
• the conductive material 120 that remains in the interconnect openings become the interconnect structures.
• the liner 122 can be made of Ti, TiN, Ta, Ta, or other suitable materials.
• an interconnect structure 1 18 is formed in the fourth dielectric layer 1 14.
• the interconnect structure 1 18 can have a trench structure 1 18a and a via structure 1 18b that is positioned below the trench structure and connected to the trench structure.
• the via structure 1 18b can have a first portion 1 18b’ and a second portion 1 18b”.
• the first portion 1 18b’ of the via structure is positioned over the conductive cap layer 108, and sidewalls of the first portion 1 18b’ are in direct contact with the third dielectric layer 1 12. In some embodiments, the sidewalls of the first portion 1 18b’ are surrounded by the third dielectric layer 1 12.
• the sidewalls of the first portion 1 18b’ are also in direction contact with a portion of the second dielectric layer 1 10 based on the process conditions.
• the second portion 1 18b” is disposed over the first portion 1 18b’.
• the second portion 1 18b” can further be positioned on the third dielectric layer 1 12 and in direct contact with the third dielectric layer 1 12.
• the interconnect structure 1 18 is electrically coupled to the conductive structure 106b through the via structure 1 18b.
• the semiconductor device 200 has a substrate 100.
• the substrate 100 has the conductive structures 106 formed in the first dielectric layer 102.
• the conductive cap layer 108 is selectively positioned.
• the second dielectric layer 1 10 is selectively disposed over the first dielectric layer 102 so that the sidewalls of the conductive cap layer 108 are surrounded by the second dielectric layer 1 10.
• the third dielectric layer 1 12 is formed selectively over the second dielectric layer 1 10 so that the top surface of the third dielectric layer 1 12 is above the top surface of the conductive cap layer 108.
• the interconnect structure 1 18 is formed.
• the interconnect structure 1 18 is electrically coupled to one of the conductive structures 106b through the via structure of the interconnect structure.
• the selectively grown bilayer dielectric (e.g., the first and second dielectric layers) provides a self-alignment between the via structure (e.g., 1 18b) and the underlying conductive structure (e.g., 106b) and a protection from capacitance issues that are driven by a misalignment.
• the bilayer dielectric can guide the via opening to the intended underlying metal line (e.g., the conductive structure 106b) or other conductive structure because the third dielectric layer has a lower etch rate comparing to the fourth dielectric layer.
• a height of the bilayer dielectric is more than a height of the conductive cap layer, which can prevent the via structure 1 18b from overlapping any adjacent conductive structures and provide a sufficient distance between the via structure 1 18b and adjacent underlying conductive structures to prevent defects, such as electrical shorts.
• the first, second, and fourth dielectric layers can be made of a same dielectric material.
• the first dielectric layer can be made of ultra low-K material
• the second dielectric layer can be made of silicon oxide
• the third dielectric layer can be made of metal oxide
• the fourth dielectric layer can be an ultra low-K film. Accordingly, a SiCN etch stop layer is not needed over the active metal (e.g., the conductive structures 106) and the ultra low-k material (e.g., the fourth dielectric layer 1 14) can be formed over an underlying metal layer (e.g., the conductive structures 106)/wiring layer (e.g., the first dielectric layer).
• the introduced bilayer dielectric and the introduced conductive cap layer only result in an approximately 1 -2% increase in self-capacitance (parasite capacitance).
• the via resistance can be reduced by more than 5% through allowing a via size to be increased given that the first portion of the via structure can be self-aligned to the underlying conductive structures and the second portion of the via has an increased via size than the first portion to reduce the via resistance.
• techniques herein provide a benefit to reduce defectivity (e.g., misalignment) with minimal effect on performance.
• the disclosed method also provides a benefit of throughput.
• the disclosed method can be implemented within a common platform or common tool, where different chambers are used for metal cap deposition and dielectric layer deposition respectively, and all corresponding modules can be connected to a single platform or wafer serving system. In other embodiments, a same chamber can be used for depositing both dielectric materials.
• FIG. 7 is schematic view of a first semiconductor equipment 700 configured to form an interconnect structure, in accordance with some embodiments of the present disclosure.
• the equipment 700 can provide a chemical vapor deposition (CVD) process.
• the equipment 700 can include a plurality of wafer load ports 702 configured to receive wafers, and a wafer handler 704 configured to transport the wafers from the wafer load ports to the load locks 706.
• the load locks 706 function as secondary vacuum chambers to house wafers and further transfer the wafers to processing chambers.
• the equipment 700 also includes a plurality of processing chambers 710-716 and a wafer transfer mechanism 708 configured to transfer the wafers between the processing chambers.
• the equipment 700 can include a first processing chamber 710 configured to deposit the conductive cap layer, such as ruthenium, and a treatment chamber 712 configured to remove surface oxide on the conductive structures through a plasma process or a H2O vapor process.
• the treatment chamber 712 can also provide an annealing process, and a deposition of a self-alignment monolayer (SAM) that helps selective growths of the conductive cap layer, the second dielectric layer and the third dielectric layer.
• SAM self-alignment monolayer
• the equipment 700 further includes a second deposition chamber 714 configured to form the second dielectric layer that can be made of SiO, and a third deposition chamber 716 configured to form the third dielectric layer that can be made of metal oxide.
• An exemplary deposition process based on the equipment 700 to form the SiO can involve in applying processing gases of SiFU and N2O, a processing temperature between 300°C and 400°C, and a processing pressure between 2 and 3 Torr.
• An exemplary deposition process to form the ruthenium can involve in introducing Ru CVD precursors into the first processing chamber 710 and a processing temperature between 400°C and 600°C.
• the Ru CVD precursors include Ru(acac)3 (acac also referred to as acetylacetinate), Ru(EtCp)2 (EtCp also referred to as
• FIG. 8 is a schematic view of a second semiconductor equipment 800 configured to form an interconnect structure, in accordance with some embodiments of the present disclosure.
• the semiconductor equipment 800 can include a plurality of wafer load ports 802, a wafer handler 804, one or more load locks 806, a plurality of processing chambers 810-814, and a wafer transfer mechanism 808.
• the processing chambers include a first processing chamber 810 configured to form a metal layer, such as the conductive cap layer, a treatment chamber 812 that has a similar function as the treatment chamber 712 mentioned above, and a second processing chamber 814.
• the second processing chamber 814 can produce a SiO dielectric layer and a metal oxide layer in situ. In other words, the second processing chamber 814 can form a SiO layer at first and then form a metal oxide layer subsequently.
• FIG. 9 is a schematic view of a third semiconductor equipment 900 configured to form an interconnect structure, in accordance with some embodiments of the present disclosure. Comparing to the equipment 700 or 800, the equipment 900 can provide a more concise layout and a higher throughput. As shown in FIG. 9, the equipment 900 can includes a plurality of wafer load ports 902, a wafer handler 904, one or more load locks 906 and two platforms A and B. The platform A is configured to perform deposition of metal and treatment.
• the platform A includes a first chamber 910 configured to operate metal deposition, a first purge chamber 912 to purge out pre-cursor from a previous step, a plasma treatment chamber 914 configured to operate plasma treatment, such as Ar or H2 plasma treatment to remove surface oxide from the conductive structures, a second purge chamber 916, and a treatment chamber 918.
• the treatment chamber can operate annealing, or form a self-alignment monolayer.
• the platform B of the equipment 900 is configured to produce the dielectric layers.
• the platform B has a first preparation chamber 920 that is configure to form a first dielectric material, a first purge chamber 922 configured to purge the pre- cursor from the previous step, a second preparation chamber 924 configured to produce a second dielectric material, a second purge chamber 926, a third preparation chamber 928 configured to produce a third dielectric material, and a third purge chamber 930.
• a wafer can be sent to the platform A.
• the wafer can receive a plasma treatment to remove surface oxide on top surfaces of the underlying conductive structures (e.g., conductive structures 106) in the plasma treatment chamber 914.
• the wafer is then sent to the second purge chamber 916 to remove residual of the processing gas from plasma treatment chamber 914.
• the wafer can then receive a metal layer deposition, such as Ru deposition in the first chamber 910, and then be sent to the first purge chamber 922 to remove the Ru CVD pre-cursor.
• the wafer is then sent to the platform B through the wafer transfer mechanism 908.
• the wafer can receive a first dielectric material (e.g., the second dielectric layer) in the first preparation chamber 920, and then be sent to the first purge chamber 922 to remove the CVD pre-cursor from formation of the first dielectric material.
• the wafer is then sent to the second preparation chamber 924 to receive a second dielectric material (e.g., the third dielectric layer).
• the wafer is then transferred to the second purge chamber 926 to remove the pre-cursor from formation of the second dielectric material.
• the wafer is further sent to the third preparation chamber 928 to receive the third dielectric material (e.g., the fourth dielectric layer), and is subsequently sent to the third purge chamber 930 to remove the pre-cursor from formation of the third dielectric material.
• FIG. 10 is a flowchart of a process 300 for manufacturing an interconnect structure.
• the process 300 begins at step 310 where a conductive cap layer is selectively formed over a plurality of conductive structures.
• the conductive structures are formed in a first dielectric layer, where a top surface of the first dielectric layer is level with top surfaces of the conductive structures.
• steps 310 can be performed as illustrated with reference to FIGS. 1 , 2A and 2B.
• the process 300 then proceeds to step 320 where a second dielectric layer is formed over the first dielectric layer.
• step 320 can be performed as illustrated with reference to FIG. 3.
• step 330 a third dielectric layer is formed over the second dielectric layer.
• the third dielectric layer is selectively positioned over the second dielectric layer so that the top surface of the conductive cap layer is exposed or uncovered, and is lower than a top surface of the third dielectric layer.
• steps 330 can be performed as illustrated with reference to FIG. 4.
• a fourth dielectric layer is formed over the plurality of conductive structures and the third dielectric layer.
• step 340 can be performed as illustrated with reference to FIG. 5.
• step 350 an interconnect structure is formed within the fourth dielectric layer.
• the interconnect structure includes a via structure that has a first portion positioned over the conductive cap layer so that sidewalls of the first portion are surrounded by the third dielectric layer, and a second portion disposed over the first portion and the third dielectric layer.
• step 350 can be performed as illustrated with reference to FIG. 6.
• interconnect structures e.g., metallization layers having conductive lines and/or vias
• Such interconnect structures electrically connect the semiconductor device 200 with other contact structures and/or active devices to form functional circuits.
• Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.
• substrate or“target substrate” as used herein generically refers to an object being processed in accordance with the invention.
• the substrate may include any material portion or structure of a device, particularly a semiconductor or other electronics device, and may, for example, be a base substrate structure, such as a semiconductor wafer, reticle, or a layer on or overlying a base substrate structure such as a thin film.
• substrate is not limited to any particular base structure, underlying layer or overlying layer, patterned or un-patterned, but rather, is contemplated to include any such layer or base structure, and any combination of layers and/or base structures.
• the description may reference particular types of substrates, but this is for illustrative purposes only.

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