WO2020001658A1 - 编码器信号采样方法及装置 - Google Patents

编码器信号采样方法及装置 Download PDF

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WO2020001658A1
WO2020001658A1 PCT/CN2019/094159 CN2019094159W WO2020001658A1 WO 2020001658 A1 WO2020001658 A1 WO 2020001658A1 CN 2019094159 W CN2019094159 W CN 2019094159W WO 2020001658 A1 WO2020001658 A1 WO 2020001658A1
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signal
sampling
encoder
frequency
preset
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PCT/CN2019/094159
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English (en)
French (fr)
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陈理辉
石金博
郑荣魁
王彬
刘江
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东莞市李群自动化技术有限公司
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Priority to EP19824577.1A priority Critical patent/EP3817235A4/en
Priority to JP2020571419A priority patent/JP7354160B2/ja
Priority to US17/254,026 priority patent/US11177827B2/en
Publication of WO2020001658A1 publication Critical patent/WO2020001658A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/60—General implementation details not specific to a particular type of compression
    • H03M7/6011—Encoder aspects
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/22—Analogue/digital converters pattern-reading type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • H03M1/1255—Synchronisation of the sampling frequency or phase to the input frequency or phase
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
    • G01D5/00—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable
    • G01D5/12—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means
    • G01D5/244—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing characteristics of pulses or pulse trains; generating pulses or pulse trains
    • G01D5/24404—Interpolation using high frequency signals

Definitions

  • the present disclosure relates to the field of servo control technology, and in particular, to a method and device for sampling an encoder signal.
  • the existing technology usually uses a logic chip to perform a single acquisition of the signal directly at a fixed communication clock edge, and then performs cyclic redundancy on the acquired signal. Check (Cyclic Redundancy Check, CRC) judgment. If the CRC is correct, the collected position is fed back to the position loop for corresponding loop control.
  • CRC Cyclic Redundancy Check
  • one object of the present disclosure is to provide an encoder signal sampling method and device to at least partially solve the above problems.
  • the present disclosure provides an encoder signal sampling method.
  • the encoder signal sampling method includes:
  • Denoising the sampled signal based on a preset algorithm.
  • the step of sampling an encoder input signal with the high-frequency clock signal as a reference to obtain a sampled signal includes:
  • the preset actions include turning on the insulated gate bipolar transistor and turning off the insulation.
  • sampling is stopped, and sampling is continued after the preset duration ends.
  • the preset duration occupies 3% to 5% of an effective time period determined based on the communication rate of the encoder.
  • the step of performing denoising processing on the sampling signal based on a preset algorithm includes:
  • the step of determining that the sampling signal is an effective level in the effective time includes:
  • the sampling signal is a low level during the valid time.
  • the step of determining a clock frequency according to the data frequency includes:
  • a product of the data frequency and a preset coefficient is determined as the clock frequency.
  • the step of performing denoising processing on the sampling signal based on a preset algorithm includes:
  • a level at which the proportion in each valid time period reaches a set threshold is determined as an effective level of the sampling signal in the valid time period.
  • different valid time periods correspond to different set thresholds.
  • the present disclosure also provides an encoder signal sampling device, where the encoder signal sampling device includes:
  • a parameter obtaining unit configured to obtain a data frequency of the encoder
  • a clock frequency determining unit configured to determine a clock frequency according to the data frequency
  • a signal generating unit configured to generate a high-frequency clock signal based on the clock frequency
  • a sampling unit configured to sample an encoder input signal based on the high-frequency clock signal to obtain a sampling signal
  • the denoising unit is configured to perform denoising processing on the sampling signal based on a preset algorithm.
  • sampling unit is specifically configured to:
  • the preset actions include turning on the insulated gate bipolar transistor and turning off the insulation.
  • the preset duration occupies 3% to 5% of an effective time period determined based on the communication rate of the encoder.
  • the denoising unit is configured to determine multiple valid times of the sampling signal and valid levels within each valid time;
  • the denoising unit is further configured to determine that the sampling signal is an effective level when the ratio of the effective level in the effective time is greater than or equal to a preset threshold.
  • the denoising unit is further configured to determine the sampling signal during the valid time when the high level is valid and the proportion of the high level is greater than or equal to a preset threshold. High
  • the denoising unit is further configured to determine that the sampling signal is a low level during the valid time when the low level is valid and the proportion of the low level is greater than or equal to a preset threshold. .
  • the clock frequency determining unit is configured to determine a product of the data frequency and a preset coefficient as the clock frequency.
  • the denoising unit is specifically configured to:
  • different valid time periods correspond to different set thresholds.
  • FIG. 1 shows a flowchart of an encoder signal sampling method provided by the present disclosure.
  • FIG. 2 shows a sampling diagram of sampling an encoder input signal with a common clock signal as a reference to obtain a sampling signal.
  • FIG. 3 shows a sampling diagram of sampling an encoder input signal with a high-frequency clock signal as a reference to obtain a sampling signal.
  • FIG. 4 shows a specific flowchart of step S105 in FIG. 1.
  • FIG. 5 shows waveforms before and after the denoising processing is performed on the sampled signal.
  • FIG. 6 shows a functional block diagram of an encoder signal sampling device provided by the present disclosure.
  • Icon 100-encoder signal sampling device; 110-parameter acquisition unit; 120-clock frequency determination unit; 130-signal generation unit; 140-sampling unit; 150-denoising unit.
  • the disclosure provides an encoder signal sampling method, which is applied to a programmable logic device electrically connected to the encoder.
  • the programmable logic device may be a field-programmable gate array (FPGA) or a complex FPGA.
  • Programmable logic device Complex Programmable Logic Device, CPLD.
  • the encoder signal sampling method is used to filter interference noise and improve the accuracy of sampling the encoder input signal. Please refer to FIG. 1, which is a flowchart of an encoder signal sampling method provided by the present disclosure.
  • the encoder signal sampling method includes:
  • Step S101 Obtain the data frequency of the encoder.
  • the data frequency refers to the output frequency of the encoder. It is related to the number of pulses generated by the encoder per revolution or the communication protocol of the encoder.
  • Step S102 Determine the clock frequency according to the data frequency.
  • a product of a data frequency and a preset coefficient may be determined as a clock frequency.
  • clock frequency should be much larger than the data frequency in order to obtain more sampling points.
  • the clock frequency should be at least 20 times the data frequency to ensure that sufficient sampling points are obtained during subsequent sampling to restore the encoder input signal as much as possible.
  • the preset coefficient is 50.
  • Step S103 Generate a high-frequency clock signal based on the clock frequency.
  • the high-frequency clock signal is generated by a phase-locked loop (PLL) inside the FPGA.
  • Phase-locked loop is a circuit that uses the externally input reference signal to control the frequency and phase of the internal oscillation signal of the loop to achieve the automatic tracking of the output signal frequency to the input signal frequency.
  • Step S104 The encoder input signal is sampled based on the high-frequency clock signal to obtain a sampled signal.
  • FIG. 2 is a sampling diagram of sampling the encoder input signal based on a common clock signal.
  • FIG. 3 is a sampling diagram of sampling the encoder input signal based on the high-frequency clock signal.
  • X1 is an ordinary clock signal
  • X2 is a high-frequency clock signal
  • Y1 is an encoder input signal
  • Y2 is a sampling signal.
  • the encoder input signal is sampled by using a high-frequency clock signal, which has more sampling points and sufficient sample signals, and the obtained sampling signals are also Closer to the encoder input signal.
  • the obtained sampling signal is completely inconsistent with the input signal of the encoder and an error occurs.
  • step S104 may include the following processing flow:
  • the preset actions include turning on an insulated gate bipolar transistor (IGBT), turning off an IGBT, turning on a metal oxide semiconductor field effect transistor (MOSFET), and turning off a MOSFET.
  • IGBT insulated gate bipolar transistor
  • MOSFET metal oxide semiconductor field effect transistor
  • the preset duration may be 3% to 5% of the effective time period.
  • the effective time period is determined according to the communication speed of the encoder. For example, if the communication speed of the encoder is 2.5 MHz (400 ns), then the effective time is equal to 400 ns.
  • Step S105 The processor performs denoising processing on the sampled signal based on a preset algorithm.
  • step S105 includes:
  • Sub-step S1051 determining multiple valid times of the sampling signal and valid levels within each valid time.
  • the meaning of the valid time is consistent with the above valid time period, and refers to the length of time that the encoder data is valid in the sampling signal.
  • the effective level is a level other than the level caused by noise in the sampling signal.
  • the active level can be high or low.
  • Sub-step S1052 It is determined whether the proportion of the effective level in the valid time is greater than or equal to a preset threshold, and if so, execute sub-step S1053.
  • the sub-step S1053 is performed.
  • the sub-step S1053 is performed.
  • Sub-step S1053 It is determined that the sampling signal within the effective time is an effective level.
  • the sampling signal is high during the valid time.
  • the sampling signal is a low level within the valid time.
  • the preset threshold should be greater than or equal to 70%.
  • step S105 may be implemented through the following processing flow:
  • a level at which the proportion in each valid time period reaches a set threshold is determined as an effective level of the sampling signal in the valid time period.
  • the sampling time period refers to the entire time span of the sampling signal.
  • the sampling signal may have a high level and / or a low level during each valid time period, and each level that it has will last for a certain time. For example, in a valid period T0, if the proportion of the high-level duration in the valid period T0 reaches a set threshold, it can be determined that the valid level of the sampling signal in the valid period T0 is high. Similarly, if the proportion of the low-level duration in the valid period T0 reaches the set threshold within the valid period T0, it is determined that the valid level of the sampling signal in the valid period T0 is low.
  • the set threshold may be determined according to a site environment where the site is located. For example, when the site environment is harsh, the set threshold may be lower than 70%, and may be greater than or equal to 70%. In this embodiment, the meaning of the set threshold is the same as the meaning of the foregoing preset threshold.
  • a sliding window may be used to perform denoising processing on the obtained sampling signal, that is, different setting thresholds may be set for different effective time periods.
  • the set thresholds corresponding to different effective time periods are different.
  • the size of the set threshold corresponding to each valid time period may be specifically determined based on the communication rate of the encoder, and there is no limitation in this embodiment. In this way, the denoising effect can be further improved.
  • FIG. 5 shows a waveform diagram before and after the sample signal is denoised.
  • Y2 is a sampling signal
  • Y3 is a sampling signal after denoising processing
  • the t2 segment and the t3 segment are noise signals.
  • FIG. 6 is a functional block diagram of an encoder signal sampling device 100 according to an embodiment of the present disclosure. It should be noted that the basic principle and technical effect of the encoder signal sampling device 100 provided in this embodiment are the same as those of the above embodiment. For a brief description, the parts not mentioned in this embodiment can be referred to the above. Corresponding content in the examples.
  • the encoder signal sampling device 100 includes a parameter acquisition unit 110, a clock frequency determination unit 120, a signal generation unit 130, a sampling unit 140, and a denoising unit 150.
  • the parameter obtaining unit 110 is configured to obtain a data frequency of the encoder.
  • the parameter obtaining unit 110 may be configured to execute step S101.
  • the clock frequency determination unit 120 is configured to determine a clock frequency according to a data frequency.
  • a product of a data frequency and a preset coefficient is determined as a clock frequency.
  • the clock frequency determining unit 120 may be configured to execute step S102.
  • the signal generating unit 130 is configured to generate a high-frequency clock signal based on a clock frequency.
  • the signal generating unit 130 may be configured to execute step S103.
  • the sampling unit 140 is configured to sample an encoder input signal with a high-frequency clock signal as a reference to obtain a sampling signal.
  • sampling unit 140 may be configured to execute step S104.
  • the sampling unit 140 may be specifically configured to determine, when a clock edge of the high-frequency clock signal is detected, based on a communication rate of the encoder, whether any one of preset actions currently exists, and the preset action includes turning on Insulated gate bipolar transistor, turned off insulated gate bipolar transistor, turned on metal-oxide-semiconductor field-effect transistor, and turned off metal-oxide-semiconductor field-effect transistor; if it is determined that any one of the preset actions exists, stop sampling And continue sampling after the preset time is over.
  • the preset duration occupies 3% -5% of the effective time period determined based on the communication rate of the encoder.
  • the denoising unit 150 is configured to perform denoising processing on the sampled signal using a processor based on a preset algorithm.
  • the denoising unit 150 is configured to determine a plurality of valid times of the sampling signal and a valid level within each valid time. The denoising unit 150 is further configured to determine whether the proportion of the effective level in the valid time is greater than or equal to a preset threshold, and configured to determine that the proportion of the effective level in the valid time is greater than or equal to a preset threshold When it is determined, the sampling signal within the valid time is the valid level.
  • the denoising unit 150 is further configured to determine whether the proportion of the high level is greater than or equal to a preset threshold when the high level is valid within the valid time, and if so, determine that the sampling signal is high during the valid time. Level.
  • the denoising unit 150 is further configured to determine whether the proportion of the low level is greater than or equal to a preset threshold when the low level is valid within the valid time, and if yes, determine that the sampling signal is a low level within the valid time.
  • the denoising unit 150 may be specifically configured to divide the sampling time period of the sampling signal into multiple valid time periods, where the valid time periods are determined based on the communication rate of the encoder; The proportion of each level of the sampling signal in each valid time period; the level at which the proportion in each valid time period reaches a set threshold is determined as the effective level of the sampling signal in the valid time period .
  • different valid time periods correspond to different set thresholds.
  • the denoising unit 150 may be configured to perform step S105.
  • the encoder signal sampling method and device obtain a data frequency of the encoder, determine a clock frequency based on the data frequency, and then generate a high-frequency clock signal based on the clock frequency, and then use the high-frequency clock signal as The benchmark samples the encoder input signal to obtain a sampled signal, and finally uses the processor to denoise the sampled signal based on a preset algorithm; the high-frequency clock signal is used to sample the encoder input signal to obtain more samples Point to obtain enough signal samples for subsequent data analysis and denoising processing. Due to the effect of high-frequency clock signals, the effective signal in the signal samples is significantly larger than the noise signal, so the noise signal pair The effect of the sampled signal is even smaller, thereby ensuring the accuracy of the sampled signal.
  • each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, which contains one or more components for implementing a specified logical function Executable instructions.
  • the functions marked in the blocks may also occur in a different order than those marked in the drawings.
  • each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts can be implemented in a dedicated hardware-based system that performs the specified function or action. , Or it can be implemented with a combination of dedicated hardware and computer instructions.
  • the functional modules in the various embodiments of the present disclosure may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
  • the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium.
  • the technical solution of the present disclosure is essentially a part that contributes to the existing technology or a part of the technical solution may be embodied in the form of a software product, which is stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in various embodiments of the present disclosure.
  • the foregoing storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disks or optical disks and other media that can store program codes .
  • the encoder signal sampling method and device provided by the present disclosure can obtain enough signal samples for subsequent data analysis and denoising processing. Due to the effect of the high-frequency clock signal, the effective signal in the signal sample is significantly larger than the noise signal. The ratio is larger, so the influence of the noise signal on the sampling signal is smaller, thereby ensuring the accuracy of the sampling signal.

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Abstract

公开了一种编码器信号采样方法及装置，涉及伺服控制技术领域。该方法及装置通过获取编码器的数据频率，并依据数据频率确定时钟频率，然后基于时钟频率生成高频时钟信号，接着以高频时钟信号为基准对编码器输入信号进行采样以获得采样信号，最后利用处理器基于预设定的算法对采样信号进行去噪处理；利用高频时钟信号对编码器输入信号进行采样，从而获得更多的采样点，以此获得足够多的信号样本来进行后续的数据分析、去噪处理，由于在高频时钟信号的作用下，信号样本中有效信号明显比噪音信号的占比更大，因此噪音信号对采样信号的影响便更小，从而保证了采样信号的准确性。

Description

编码器信号采样方法及装置
相关申请的交叉引用
本申请要求于2018年06月29日提交中国专利局的申请号为2018107013138，名称为“一种编码器信号采样方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及伺服控制技术领域，具体而言，涉及一种编码器信号采样方法及装置。
背景技术
工业自动化应用中电机的使用是必不可少的，尤其随着工业4.0以及国家扶持制造业的崛起。绝对值编码器不管是在生产车间的电机系统还是在工业机器人中的电机系统都被广泛应用。
在绝对值编码器信号的采集过程中，现有的技术通常都是使用逻辑芯片按照特定的节拍，固定的通讯时钟沿直接对信号进行单次的采集，然后将采集到的信号进行循环冗余校验(Cyclic Redundancy Check,CRC)判断，如果CRC没错，则将采集到的位置反馈给位置环进行对应的环路控制。但目前逻辑芯片在对编码器信号进行采样时，由于编码器信号对于逻辑芯片来说是异步采样信号，且在工业现场往往存在各种干扰，导致逻辑芯片在采样编码器输入信号时往往出现采样错误，误将噪声信号当做有效数据，从而导致无法通过CRC校验，无法实现绝对值编码器位置信息的实时更新，最终导致无法精确控制电机的运动，给环路控制带来不稳定性或大大降低了系统的性能指标。
发明内容
有鉴于此，本公开的目的之一在于提供一种编码器信号采样方法及装置，以至少部分地解决上述问题。
为了实现上述目的，本公开采用的技术方案如下：
第一方面，本公开提供了一种编码器信号采样方法，所述编码器信号采样方法包括：
获取编码器的数据频率；
依据所述数据频率确定时钟频率；
基于所述时钟频率生成高频时钟信号；
以所述高频时钟信号为基准对编码器输入信号进行采样以获得采样信号；
基于预设定的算法对所述采样信号进行去噪处理。
可选地，所述以所述高频时钟信号为基准对编码器输入信号进行采样以获得采样信号 的步骤，包括：
在检测到所述高频时钟信号的时钟沿时，基于所述编码器的通讯速率确定当前是否存在预设动作中的任意一个，所述预设动作包括开启绝缘栅双极型晶体管、关闭绝缘栅双极型晶体管、开启金属氧化物半导体场效应晶体管以及关闭金属氧化物半导体场效应晶体管；
如果确定存在所述预设动作中的任意一个，则停止采样，并在结束预设时长后继续进行采样。
可选地，所述预设时长占基于所述编码器的通讯速率确定的有效时间段的3％-5％。
可选地，所述基于预设定的算法对所述采样信号进行去噪处理的步骤，包括：
确定所述采样信号的多个有效时间及每个有效时间内的有效电平；
当在所述有效时间内有效电平的占比大于或等于预设定的阈值时，确定所述有效时间内所述采样信号为有效电平。
可选地，所述当在所述有效时间内有效电平的占比大于或等于预设定的阈值时，确定所述有效时间内所述采样信号为有效电平的步骤，包括：
当在所述有效时间内高电平有效且高电平的占比大于或等于预设定的阈值时，确定所述有效时间内所述采样信号为高电平；
当在所述有效时间内低电平有效且低电平的占比大于或等于预设定的阈值时，确定所述有效时间内所述采样信号为低电平。
可选地，所述依据所述数据频率确定时钟频率的步骤，包括：
将所述数据频率与预设定的系数的乘积确定为所述时钟频率。
可选地，所述基于预设定的算法对所述采样信号进行去噪处理的步骤，包括：
将所述采样信号的采样时间段划分为多个有效时间段，所述有效时间段基于所述编码器的通讯速率确定；
分别统计每个有效时间段内所述采样信号的每种电平的占比；
将每个有效时间段内占比达到设定阈值的电平确定为所述采样信号在该有效时间段内的有效电平。
可选地，不同有效时间段与不同的设定阈值对应。
第二方面，本公开还提供了一种编码器信号采样装置，所述编码器信号采样装置包括：
参数获取单元，配置成获取编码器的数据频率；
时钟频率确定单元，配置成依据所述数据频率确定时钟频率；
信号生成单元，配置成基于所述时钟频率生成高频时钟信号；
采样单元，配置成以所述高频时钟信号为基准对编码器输入信号进行采样以获得采样 信号；
去噪单元，配置成基于预设定的算法对所述采样信号进行去噪处理。
可选地，所述采样单元具体配置成：
在检测到所述高频时钟信号的时钟沿时，基于所述编码器的通讯速率确定当前是否存在预设动作中的任意一个，所述预设动作包括开启绝缘栅双极型晶体管、关闭绝缘栅双极型晶体管、开启金属氧化物半导体场效应晶体管以及关闭金属氧化物半导体场效应晶体管；如果确定存在所述预设动作中的任意一个，则停止采样，并在结束预设时长后继续进行采样。
可选地，所述预设时长占基于所述编码器的通讯速率确定的有效时间段的3％-5％。
可选地，所述去噪单元配置成确定所述采样信号的多个有效时间及每个有效时间内的有效电平；
所述去噪单元还配置成当在所述有效时间内有效电平的占比大于或等于预设定的阈值时，确定所述有效时间内所述采样信号为有效电平。
可选地，所述去噪单元还配置成当在所述有效时间内高电平有效且高电平的占比大于或等于预设定的阈值时，确定所述有效时间内所述采样信号为高电平；
所述去噪单元还配置成当在所述有效时间内低电平有效且低电平的占比大于或等于预设定的阈值时，确定所述有效时间内所述采样信号为低电平。
可选地，所述时钟频率确定单元配置成将所述数据频率与预设定的系数的乘积确定为所述时钟频率。
可选地，所述去噪单元具体配置成：
将所述采样信号的采样时间段划分为多个有效时间段，所述有效时间段基于所述编码器的通讯速率确定；分别统计每个有效时间段内所述采样信号的每种电平的占比；将每个有效时间段内占比达到设定阈值的电平确定为所述采样信号在该有效时间段内的有效电平。
可选地，不同有效时间段与不同的设定阈值对应。
为使本公开的上述目的、特征和优点能更明显易懂，下文特举较佳实施例，并配合所附附图，作详细说明如下。
附图说明
为了更清楚地说明本公开的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本公开的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图 获得其他相关的附图。
图1示出了本公开提供的编码器信号采样方法的流程图。
图2示出了以普通时钟信号为基准对编码器输入信号进行采样以获得采样信号的采样图。
图3示出了以高频时钟信号为基准对编码器输入信号进行采样以获得采样信号的采样图。
图4示出了为图1中步骤S105的具体流程图。
图5示出了采样信号进行去噪处理前后的波形图。
图6示出了本公开提供的编码器信号采样装置的功能模块图。
图标：100-编码器信号采样装置；110-参数获取单元；120-时钟频率确定单元；130-信号生成单元；140-采样单元；150-去噪单元。
具体实施方式
下面将结合本公开中附图，对本公开中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开的一部分实施例，而不是全部的实施例。通常在此处附图中描述和示出的本公开的组件可以以各种不同的配置来布置和设计。
因此，以下对在附图中提供的本公开的实施例的详细描述并非旨在限制要求保护的本公开的范围，而是仅仅表示本公开的选定实施例。基于本公开的实施例，本领域技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
需要说明的是，术语“第一”和“第二”等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
本公开提供了一种编码器信号采样方法，应用于一与编码器电连接的可编程逻辑器件，该可编程逻辑器件可以为现场可编程门阵列(Field－Programmable Gate Arra，FPGA)或是复杂可编程逻辑器件(Complex Programmable Logic Device，CPLD)。该编码器信号采样方法用于滤除干扰噪声，提高对编码器输入信号的采样的准确性。请参阅图1，为本公开提供的编码器信号采样方法的流程图。该编码器信号采样方法包括：
步骤S101：获取编码器的数据频率。
需要说明的是，该数据频率是指编码器的输出频率。与编码器每转产生的脉冲数或编码器的通讯协议有关。
步骤S102：依据数据频率确定时钟频率。
具体地，可以将数据频率与预设定的系数的乘积确定为时钟频率。
需要说明的是，该时钟频率应当远远大于数据频率，才能获得更多的采样点。
具体地，该时钟频率至少应当为数据频率的20倍以上，才能保证后续采样时，获得足够的采样点，尽可能还原编码器输入信号。
在一种可选的实施方式中，该预设定的系数为50。
步骤S103：基于时钟频率生成高频时钟信号。
可以理解地，该高频时钟信号由FPGA内部的锁相环(phase locked loop，PLL)产生。锁相环是一种利用外部输入的参考信号控制环路内部振荡信号的频率和相位，实现输出信号频率对输入信号频率的自动跟踪的电路。
步骤S104：以高频时钟信号为基准对编码器输入信号进行采样以获得采样信号。
请参阅图2，为以普通时钟信号为基准对编码器输入信号进行采样以获得采样信号的采样图。
请参阅图3，为以高频时钟信号为基准对编码器输入信号进行采样以获得采样信号的采样图。
其中，X1为普通时钟信号，X2高频时钟信号，Y1为编码器输入信号，Y2为采样信号。
可以理解地，通过图2与图3中的采样信号对比可得，利用高频时钟信号对编码器输入信号进行采样，具有更多的采样点，具有足够的样本信号，同时获得的采样信号也更接近编码器输入信号。例如，图2中，t1段波形，则由于普通时钟信号的频率过大，导致了获得的采样信号与编码器输入信号完全不一致，出现错误。
可选地，为了进一步提高采样信号的有效性及信噪比，步骤S104可以包括如下所示的处理流程：
在检测到所述高频时钟信号的时钟沿时，基于所述编码器的通讯速率确定当前是否存在预设动作中的任意一个，如果确定存在所述预设动作中的任意一个，则停止采样，并在结束预设时长后继续进行采样。
其中，所述预设动作包括开启绝缘栅双极型晶体管(Insulated Gate Bipolar Transistor，IGBT)、关闭IGBT、开启金属氧化物半导体场效应晶体管(Metal Oxide Semiconductor Field Effect Transistor，MOSFET)及关闭MOSFET。
其中，所述预设时长可以是有效时间段的3％-5％。所述有效时间段依据编码器的通讯速率确定，例如，编码器的通讯速率为2.5MHz(400ns)，那么有效时间则等于400ns。
步骤S105：利用处理器基于预设定的算法对采样信号进行去噪处理。
请参阅图4，为步骤S105在一种实施方式中的具体流程图。该步骤S105包括：
子步骤S1051：确定所述采样信号的多个有效时间及每个有效时间内的有效电平。
需要说明的是，该有效时间的含义与上述的有效时间段一致，是指采样信号内，编码器数据有效的时间长度。
需要说明的是，该有效电平是采样信号中，除由噪声产生的电平以外的其他电平。该有效电平可以是高电平，也可以为低电平。
子步骤S1052：判断在有效时间内有效电平的占比是否大于或等于预设定的阈值，如果是，则执行子步骤S1053。
具体地，当在有效时间内高电平有效时，判断高电平的占比是否大于或等于预设定的阈值，如果是，则执行子步骤S1053。
当在有效时间内低电平有效时，判断低电平的占比是否大于或等于预设定的阈值，如果是，则执行子步骤S1053。
子步骤S1053：确定有效时间内采样信号为有效电平。
当在有效时间内有效电平的占比大于或等于预设定的阈值时，确定有效时间内采样信号为有效电平。
具体地，当在有效时间内高电平有效且高电平的占比大于或等于预设定的阈值时，确定有效时间内采样信号为高电平。
当在有效时间内低电平有效且低电平的占比大于或等于预设定的阈值时，确定有效时间内采样信号为低电平。
需要说明的是，该预设定的阈值应当大于或等于70％。
在另一种实施方式中，步骤S105可以通过以下处理流程实现：
将所述采样信号的采样时间段划分为多个有效时间段，所述有效时间段基于所述编码器的通讯速率确定；
分别统计每个有效时间段内所述采样信号的每种电平的占比；
将每个有效时间段内占比达到设定阈值的电平确定为所述采样信号在该有效时间段内的有效电平。
其中，所述采样时间段是指采样信号的整个时间跨度。
示例性地，在每个有效时间段内，采样信号可能具有高电平和/或低电平，且具有的每 种电平将持续一定时间。例如，在一个有效时间段T0中，如果高电平持续时间占该有效时间段T0的比重达到了设定阈值，则可以确定采样信号在有效时间段T0内的有效电平是高电平。类似地，如果在有效时间段T0内，低电平持续时间占有效时间段T0的比重达到了设定阈值，则确定采样信号在有效时间段T0内的有效电平是低电平。
其中，所述设定阈值可以依据所处的现场环境确定，例如，当所处现场环境恶劣时，所述设定阈值可以低于70％，反之可以大于或等于70％。本实施例中，所述设定阈值的含义与前述的预设定的阈值的含义相同。
可选地，可以采用滑动窗口来对得到的采样信号进行去噪处理，即，可以为不同的有效时间段设置不同的设定阈值。再换句话说，不同有效时间段对应的设定阈值不同。每个有效时间段对应的设定阈值的大小具体可以基于所述编码器的通讯速率确定，本实施例没有限制。如此，可以进一步改善去噪效果。
以图5为例，图5示出了采样信号进行去噪处理前后的波形图。其中，Y2为采样信号，Y3为进行去噪处理后的采样信号，t2段以及t3段均为噪音信号。
由于采样信号的采样点足够多，而噪音信号通常是在IGBT模块的MOS管关断的时候产生，从而噪音信号能影响的采样点是非常少的，接着利用子步骤S1051～子步骤S1054所提供的方法，将占比很少的噪音信号滤除，而保证了采样信号的准确性。
请参阅图6，图6为本公开实施例提供的一种编码器信号采样装置100的功能模块图。需要说明的是，本实施例所提供的编码器信号采样装置100，其基本原理及产生的技术效果和上述实施例相同，为简要描述，本实施例部分未提及之处，可参考上述的实施例中相应内容。该编码器信号采样装置100包括参数获取单元110、时钟频率确定单元120、信号生成单元130、采样单元140以及去噪单元150。
其中，参数获取单元110配置成获取编码器的数据频率。
可以理解地，在一种可选的实施例中，该参数获取单元110可配置成执行步骤S101。
时钟频率确定单元120配置成依据数据频率确定时钟频率。
具体地，将数据频率与预设定的系数的乘积确定为时钟频率。
可以理解地，在一种可选的实施例中，该时钟频率确定单元120可配置成执行步骤S102。
信号生成单元130配置成基于时钟频率生成高频时钟信号。
可以理解地，在一种可选的实施例中，该信号生成单元130可配置成执行步骤S103。
采样单元140配置成以高频时钟信号为基准对编码器输入信号进行采样以获得采样信 号。
可以理解地，在一种可选的实施例中，该采样单元140可配置成执行步骤S104。
其中，采样单元140具体可以配置成在检测到所述高频时钟信号的时钟沿时，基于所述编码器的通讯速率确定当前是否存在预设动作中的任意一个，所述预设动作包括开启绝缘栅双极型晶体管、关闭绝缘栅双极型晶体管、开启金属氧化物半导体场效应晶体管以及关闭金属氧化物半导体场效应晶体管；如果确定存在所述预设动作中的任意一个，则停止采样，并在结束预设时长后继续进行采样。
其中，所述预设时长占基于所述编码器的通讯速率确定的有效时间段的3％-5％。
去噪单元150配置成利用处理器基于预设定的算法对采样信号进行去噪处理。
其中，去噪单元150配置成确定采样信号的多个有效时间及每个有效时间内的有效电平。去噪单元150还配置成判断在有效时间内有效电平的占比是否大于或等于预设定的阈值，以及配置成当在有效时间内有效电平的占比大于或等于预设定的阈值时，确定有效时间内采样信号为有效电平。
具体地，去噪单元150还配置成当在有效时间内高电平有效时，判断高电平的占比是否大于或等于预设定的阈值，如果是，则确定有效时间内采样信号为高电平。
去噪单元150还配置成当在有效时间内低电平有效时，判断低电平的占比是否大于或等于预设定的阈值，如果是，确定有效时间内采样信号为低电平。
可选地，所述去噪单元150具体还可以配置成将所述采样信号的采样时间段划分为多个有效时间段，所述有效时间段基于所述编码器的通讯速率确定；分别统计每个有效时间段内所述采样信号的每种电平的占比；将每个有效时间段内占比达到设定阈值的电平确定为所述采样信号在该有效时间段内的有效电平。
可选地，不同有效时间段与不同的设定阈值对应。
可以理解地，在一种可选的实施例中，该去噪单元150可配置成执行步骤S105。
综上所述，本公开提供的编码器信号采样方法及装置，通过获取编码器的数据频率，并依据数据频率确定时钟频率，然后基于时钟频率生成高频时钟信号，接着以高频时钟信号为基准对编码器输入信号进行采样以获得采样信号，最后利用处理器基于预设定的算法对采样信号进行去噪处理；利用高频时钟信号对编码器输入信号进行采样，从而获得更多的采样点，以此获得足够多的信号样本来进行后续的数据分析、去噪处理，由于在高频时钟信号的作用下，信号样本中有效信号明显比噪音信号的占比更大，因此噪音信号对采样信号的影响便更小，从而保证了采样信号的准确性。
在本公开所提供的几个实施例中，应该理解到，所揭露的装置和方法，也可以通过其 它的方式实现。以上所描述的装置实施例仅仅是示意性的，例如，附图中的流程图和框图显示了根据本公开的多个实施例的装置、方法和计算机程序产品的可能实现的体系架构、功能和操作。在这点上，流程图或框图中的每个方框可以代表一个模块、程序段或代码的一部分，所述模块、程序段或代码的一部分包含一个或多个用于实现规定的逻辑功能的可执行指令。也应当注意，在有些作为替换的实现方式中，方框中所标注的功能也可以以不同于附图中所标注的顺序发生。例如，两个连续的方框实际上可以基本并行地执行，它们有时也可以按相反的顺序执行，这依所涉及的功能而定。也要注意的是，框图和/或流程图中的每个方框、以及框图和/或流程图中的方框的组合，可以用执行规定的功能或动作的专用的基于硬件的系统来实现，或者可以用专用硬件与计算机指令的组合来实现。
另外，在本公开各个实施例中的各功能模块可以集成在一起形成一个独立的部分，也可以是各个模块单独存在，也可以两个或两个以上模块集成形成一个独立的部分。
所述功能如果以软件功能模块的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本公开的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本公开各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述仅为本公开的选定实施例而已，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。
工业实用性
本公开提供的编码器信号采样方法及装置能够获得足够多的信号样本来进行后续的数据分析、去噪处理，由于在高频时钟信号的作用下，信号样本中有效信号明显比噪音信号的占比更大，因此噪音信号对采样信号的影响便更小，从而保证了采样信号的准确性。

Claims (15)

  1. 一种编码器信号采样方法，其特征在于，所述编码器信号采样方法包括：
    获取编码器的数据频率；
    依据所述数据频率确定时钟频率；
    基于所述时钟频率生成高频时钟信号；
    以所述高频时钟信号为基准对编码器输入信号进行采样以获得采样信号；
    基于预设定的算法对所述采样信号进行去噪处理。
  2. 根据权利要求1所述的编码器信号采样方法，其特征在于，所述以所述高频时钟信号为基准对编码器输入信号进行采样以获得采样信号的步骤，包括：
    在检测到所述高频时钟信号的时钟沿时，基于所述编码器的通讯速率确定当前是否存在预设动作中的任意一个，所述预设动作包括开启绝缘栅双极型晶体管、关闭绝缘栅双极型晶体管、开启金属氧化物半导体场效应晶体管以及关闭金属氧化物半导体场效应晶体管；
    如果确定存在所述预设动作中的任意一个，则停止采样，并在结束预设时长后继续进行采样。
  3. 根据权利要求2所述的编码器信号采样方法，其特征在于，所述预设时长占基于所述编码器的通讯速率确定的有效时间段的3％-5％。
  4. 根据权利要求1-3中任意一项所述的编码器信号采样方法，其特征在于，所述基于预设定的算法对所述采样信号进行去噪处理的步骤，包括：
    确定所述采样信号的多个有效时间及每个有效时间内的有效电平；
    当在所述有效时间内有效电平的占比大于或等于预设定的阈值时，确定所述有效时间内所述采样信号为所述有效电平。
  5. 根据权利要求4所述的编码器信号采样方法，其特征在于，所述当在所述有效时间段内有效电平的占比大于或等于预设定的阈值时，确定所述有效时间段内所述采样信号为有效电平的步骤，包括：
    当在所述有效时间内高电平有效且高电平的占比大于或等于预设定的阈值时，确定所述有效时间内所述采样信号为高电平；
    当在所述有效时间内低电平有效且低电平的占比大于或等于预设定的阈值时，确定所述有效时间内所述采样信号为低电平。
  6. 根据权利要求1-3中任意一项所述的编码器信号采样方法，其特征在于，所述依据所述数据频率确定时钟频率的步骤包括：
    将所述数据频率与预设定的系数的乘积确定为所述时钟频率。
  7. 根据权利要求1-3中任意一项所述的编码器信号采样方法，其特征在于，所述基于预设定的算法对所述采样信号进行去噪处理的步骤包括：
    将所述采样信号的采样时间段划分为多个有效时间段，所述有效时间段基于所述编码器的通讯速率确定；
    分别统计每个有效时间段内所述采样信号的每种电平的占比；
    将每个有效时间段内占比达到设定阈值的电平确定为所述采样信号在该有效时间段内的有效电平。
  8. 根据权利要求7所述的编码器信号采样方法，其特征在于，不同有效时间段与不同的设定阈值对应。
  9. 一种编码器信号采样装置，其特征在于，所述编码器信号采样装置包括：
    参数获取单元，配置成获取编码器的数据频率；
    时钟频率确定单元，配置成依据所述数据频率确定时钟频率；
    信号生成单元，配置成基于所述时钟频率生成高频时钟信号；
    采样单元，配置成以所述高频时钟信号为基准对编码器输入信号进行采样以获得采样信号；
    去噪单元，用于基于预设定的算法对所述采样信号进行去噪处理。
  10. 根据权利要求9所述的编码器信号采样装置，其特征在于，所述采样单元具体配置成：
    在检测到所述高频时钟信号的时钟沿时，基于所述编码器的通讯速率确定当前是否存在预设动作中的任意一个，所述预设动作包括开启绝缘栅双极型晶体管、关闭绝缘栅双极型晶体管、开启金属氧化物半导体场效应晶体管以及关闭金属氧化物半导体场效应晶体管；如果确定存在所述预设动作中的任意一个，则停止采样，并在结束预设时长后继续进行采样。
  11. 根据权利要求10所述的编码器信号采样装置，其特征在于，所述预设时长占所述编码器的通讯速率确定有效时间段的3％-5％。
  12. 根据权利要求9-11中任意一项所述的编码器信号采样装置，其特征在于，所述去噪单元配置成确定所述采样信号的多个有效时间及每个有效时间内的有效电平；
    所述去噪单元还配置成当在所述有效时间内有效电平的占比大于或等于预设定的阈值时，确定所述有效时间内所述采样信号为有效电平。
  13. 根据权利要求12所述的编码器信号采样装置，其特征在于，所述去噪单元还配置成当在所述有效时间内高电平有效且高电平的占比大于或等于预设定的阈值时，确定所述 有效时间内所述采样信号为高电平；
    所述去噪单元还配置成当在所述有效时间内低电平有效且低电平的占比大于或等于预设定的阈值时，确定所述有效时间内所述采样信号为低电平。
  14. 根据权利要求9-11中任意一项所述的编码器信号采样装置，其特征在于，所述时钟频率确定单元配置成将所述数据频率与预设定的系数的乘积确定为所述时钟频率。
  15. 根据权利要求9-11中任意一项所述的编码器信号采样装置，其特征在于，所述去噪单元具体配置成：
    将所述采样信号的采样时间段划分为多个有效时间段，所述有效时间段基于所述编码器的通讯速率确定；分别统计每个有效时间段内所述采样信号的每种电平的占比；将每个有效时间段内占比达到设定阈值的电平确定为所述采样信号在该有效时间段内的有效电平。
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