WO2020000713A1 - 一种石墨烯沟道碳化硅功率半导体晶体管 - Google Patents
一种石墨烯沟道碳化硅功率半导体晶体管 Download PDFInfo
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- WO2020000713A1 WO2020000713A1 PCT/CN2018/107329 CN2018107329W WO2020000713A1 WO 2020000713 A1 WO2020000713 A1 WO 2020000713A1 CN 2018107329 W CN2018107329 W CN 2018107329W WO 2020000713 A1 WO2020000713 A1 WO 2020000713A1
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- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 title claims abstract description 90
- 229910021389 graphene Inorganic materials 0.000 title claims abstract description 87
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 33
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 18
- 229920005591 polysilicon Polymers 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 18
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 25
- 229910052760 oxygen Inorganic materials 0.000 claims description 25
- 239000001301 oxygen Substances 0.000 claims description 25
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- 238000002161 passivation Methods 0.000 claims description 11
- 229910002804 graphite Inorganic materials 0.000 claims description 2
- 239000010439 graphite Substances 0.000 claims description 2
- 230000005540 biological transmission Effects 0.000 abstract description 10
- 230000015556 catabolic process Effects 0.000 abstract description 9
- 230000000694 effects Effects 0.000 abstract description 5
- 230000002708 enhancing effect Effects 0.000 abstract description 2
- 210000003850 cellular structure Anatomy 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 27
- 238000000034 method Methods 0.000 description 15
- 238000005530 etching Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- 238000000151 deposition Methods 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 9
- 238000005468 ion implantation Methods 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- 238000009826 distribution Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 230000037230 mobility Effects 0.000 description 4
- -1 aluminum ions Chemical class 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000005693 optoelectronics Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000005355 Hall effect Effects 0.000 description 1
- 230000003471 anti-radiation Effects 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005087 graphitization Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1606—Graphene
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
Definitions
- the invention belongs to the field of high-voltage power semiconductor devices, in particular to a graphene channel silicon carbide power semiconductor device.
- Graphene is a single-layer carbon polymer whose conduction and valence bands meet at the Dirac point, which is called a zero-bandgap semiconductor.
- graphene As an emerging material, graphene has extremely high carrier mobility, submicron-scale ballistic transmission characteristics at room temperature, quantum Hall effect, excellent mechanical properties, electron spin transport, and superconductivity.
- the most ideal electrode and semiconductor material it has a very broad development prospect in the direction of nanoelectronics and spintronics components.
- the shape of the graphene material industry is basically formed, and it is mainly used in the fields of optoelectronic semiconductors, biomedicine, aerospace industry, sensors, and microelectronic devices.
- Figure 1 shows a conventional graphene channel silicon carbide power semiconductor device, including: an N-type substrate, a drain metal is provided on one side of the N-type substrate, and an N-type is provided on the other side of the N-type substrate In the drift region, a P-type base region is symmetrically provided at both ends of the N-type drift region, an N + -type source region and a P + -type body contact region, and a gate oxygen layer is provided on the surface of the P-type base region and the N-type drift region.
- a continuous graphene layer is provided above the base region and inside the gate oxygen, and the graphene layer is in contact with the p-type base region.
- a polysilicon gate is provided on the surface of the gate oxygen layer.
- the upper passivation layer is wrapped around the polysilicon gate.
- a source metal over the source region and the P + type body contact region.
- electrons are injected into the N-type drift region and the N-type substrate from the N + -type source region through the graphene channel above the p-type base region under the effect of the positive drain voltage, and finally reach the drain. end.
- the graphene channels on the surface are used to conduct electricity directly.
- the device has low on-resistance and strong current transmission capability.
- the continuous high mobility graphene layer The current density is large. Under the condition of high leakage voltage and zero gate voltage, the conductive channel of the device cannot be completely depleted, resulting in large off-state leakage current, low breakdown voltage, and low reliability.
- the present invention addresses the above problems, and proposes a graphene channel silicon carbide power semiconductor device capable of enhancing the effect of auxiliary depletion, further reducing the overall off-state leakage current of the device, and increasing the breakdown voltage.
- a graphene channel silicon carbide power semiconductor transistor includes: an N-type substrate, a drain metal is connected to one side of the N-type substrate, and an N-type drift region is provided on the other side, and the two ends of the N-type drift region are provided respectively.
- P + -type body contact regions and N + -type source regions are provided in each P-type base region.
- a gate oxygen layer is provided on the surface of the N-type drift region, and both ends of the gate oxygen layer extend into the gate region.
- a polysilicon gate is provided on the surface of the gate oxygen layer, a passivation layer is provided on the polysilicon gate, and the passivation layer surrounds both sides of the polysilicon gate, in the N + -type source region and the P + -type body.
- a source metal is provided on the contact region, and graphene strips as the transistor channel are provided in the P-type base region, and both ends of the graphene strips respectively touch the N + -type source region and the P-type base region.
- the boundary and the boundary between the P-type base region and the N-type drift region, and the graphene strip is embedded in the surface of the P-type base region.
- the graphene array may be arranged to extend from the intersection of the N + -type source region and the P-type base region to the N-type drift region at intervals in the gate length direction, as shown in FIG. 4 in the gate width direction. Continuous or spaced cross distribution.
- the present invention has the following advantages:
- a graphene strip is embedded on the surface of the P-type base region, and the graphene is in contact with the surface of the gate oxygen, and is distributed in a honeycomb shape in the direction of the gate width.
- the P-type base region is separated by graphene strips, which enhances the role of auxiliary depletion, further reduces the overall off-state leakage current of the device, and increases the breakdown voltage.
- the graphene strips are distributed in a honeycomb shape, so that the P-type base region is spaced apart and there is multifaceted contact with graphene.
- zero gate pressure and high leakage pressure are present, electrons are present in the graphene, and there are many subspaces with the P-type base region.
- Cavity recombination forms a space charge region, enhances the auxiliary depletion effect, and reduces the overall off-state leakage current of the device. Therefore, compared with a semiconductor device in which graphene is continuously distributed in the gate oxygen, the off-state leakage current of the device is smaller, the breakdown voltage is higher, and the reliability is stronger.
- the honeycomb graphene array is embedded in the P-type base region.
- the multi-electrons in the N + source region will be directly injected into the N-type drift region and the N-type substrate through the graphene channel. Reaching the drain, forming a current path.
- the on-resistance of the device is high, and current transmission is not uniform. Therefore, compared with the graphene space distribution in the gate oxygen, the device has a lower on-resistance, better on-state I-V characteristics, and stronger current transmission capability.
- the on-resistance of the present invention is basically unchanged, and the current transmission capacity is almost unchanged.
- the silicon carbide epitaxial growth method is one of the methods for preparing graphene.
- the silicon carbide single crystal is heated at a high temperature to cause the graphitization phenomenon to obtain graphene based on the silicon carbide substrate, which is excellent in performance with existing devices. Process compatible.
- a graphene channel is proposed in a graphene channel silicon carbide power semiconductor transistor.
- the carrier transport in the channel is affected by temperature. Low, good on-resistance stability at high temperatures.
- FIG. 1 is a perspective view of the structure of a conventional graphene channel silicon carbide power semiconductor device in which graphene is continuously distributed in the gate oxygen.
- FIG. 2 is a perspective view of a structure of the present invention.
- Fig. 3 is a top sectional view of a honeycomb-shaped distribution along the A-A 'line parallel to the gate width direction according to the embodiment of the present invention.
- Fig. 4 is a top sectional view taken along a line A-A 'parallel to the gate width direction according to another embodiment of the present invention.
- Fig. 5 is a side cross-sectional perspective view of the present invention parallel to the gate width direction along a line B-B '.
- FIG. 6 is a breakdown characteristic of a silicon carbide power semiconductor device continuously distributed with graphene according to the present invention at a gate voltage of 0 V. It can be seen that the device of the present invention has a smaller leakage current and a larger breakdown voltage.
- FIG. 7 is a comparison diagram of the IV curve of a graphene channel silicon carbide power semiconductor device provided with graphene continuously or spaced in the gate oxygen at a gate voltage of 5V. It can be seen that the device of the present invention is compared with graphene
- the on-resistance of the devices continuously distributed in the gate oxygen is basically unchanged, and the current transmission capability is unchanged. Compared with the graphene-spaced devices in the gate oxygen, the on-resistance is significantly reduced, and the current transmission capability is enhanced.
- FIG. 8 is a schematic structural diagram of forming a silicon carbide epitaxial layer on a silicon carbide N-type substrate according to the manufacturing method of the present invention.
- FIG. 9 is a schematic structural diagram of a silicon carbide P-type base region formed on the N-type drift region by photolithography and ion implantation in the manufacturing method of the present invention.
- FIG. 10 is a schematic structural diagram of a silicon carbide P + -type body contact region formed by photolithography and ion implantation in a silicon carbide P-type base region according to the manufacturing method of the present invention.
- FIG. 11 is a schematic structural diagram of a silicon carbide N + type source region formed by photolithography and ion implantation in a silicon carbide P-type base region according to the manufacturing method of the present invention.
- FIG. 12 is a schematic structural diagram of a method for manufacturing the present invention by etching a graphene trench in a silicon carbide P-type base region.
- FIG. 13 is a schematic structural diagram of a graphene array formed by deposition in a trench of a silicon carbide P-type base region according to the manufacturing method of the present invention.
- FIG. 14 is a schematic structural diagram of a gate oxygen formed on the surface of an N-type drift region and a P-type base region by thermal oxidation growth and etching in the manufacturing method of the present invention.
- FIG. 15 is a schematic structural diagram of depositing and etching a polysilicon gate on a gate oxygen layer by a deposition and etching process according to the manufacturing method of the present invention.
- FIG. 16 is a schematic structural diagram of the manufacturing method of the present invention after depositing and etching a metal to form a metal contact and performing a passivation process.
- a graphene channel silicon carbide power semiconductor transistor includes: an N-type substrate 1, a drain metal 10 is connected to one side of the N-type substrate 1, and an N-type drift region 2 is provided on the other side.
- P-type base regions 3 are provided at both ends of the P-type base region 3
- P + -type body contact regions 4 and N + -type source regions 5 are respectively provided in the P-type base regions 3
- a gate oxide layer 7 is provided on the surface of the N-type drift region 2 and Two ends of the gate oxygen layer 7 respectively extend into the P-type base regions 3 on both sides.
- a polysilicon gate 8 is provided on the surface of the gate oxygen layer 7, a passivation layer 6 is provided on the polysilicon gate 8, and the passivation is performed.
- the layer 6 covers both sides of the polysilicon gate 8, a source metal 9 is provided on the N + -type source region 5 and the P + -type body contact region 4, and graphite is used as the transistor channel in the P-type base region 3.
- the graphene stripe 11 and the two ends of the graphene stripe respectively touch the boundary between the N + -type source region 5 and the P-type base region 3 and the boundary between the P-type base region 3 and the N-type drift region 2, the graphene stripe 11
- the surface of the P-type base region 3 is embedded.
- the graphene bar should be understood or interpreted in a broad sense.
- the graphene bar is relative to the entire graphene, and can include or be interpreted as a hollowed out graphene, and can further include the following methods:
- the graphene strip 11 is honeycomb in the gate width direction, see FIG. 3; (2) The graphene strip 11 is straight, as shown in FIG.
- a graphene block 12 may be provided in each of the P-type base regions formed by dividing the P-type base region 3 by the graphene stripe 11.
- a graphene channel silicon carbide power semiconductor transistor includes: an N-type substrate 1, a drain metal 10 is provided on one side of the N-type substrate 1, and an N-type drift region 2 is provided on the other side.
- a pair of P-type base regions 3 are provided at both ends of the region 2, and a P + -type body contact region 4 and an N + -type source region 5 are provided in each P-type base region 3, and a gate oxygen layer is provided on the surface of the N-type drift region 2.
- a polysilicon gate 8 is provided on the surface of the gate oxygen layer 7
- a passivation layer 6 is provided on the polysilicon gate 8 and the The passivation layer 6 covers both sides of the polysilicon gate 8, and a source metal 9 is provided on the N + type source region 5 and the P + type body contact region 4.
- the graphene embedded in the P-type base region 3 extends from the intersection of the N + -type source region 5 and the P-type base region 3 toward the N-type drift region 5 at intervals in the gate length direction, and the graphene block 12 has a length It is 0.1 ⁇ m, the interval is 0.1 ⁇ m, and the thickness is 1 nm.
- the graphene strips 12 are interconnected with graphene diagonally in the gate width direction, and are distributed in a honeycomb shape.
- the graphene embedded in the P-type base region 3 extends from the intersection of the N + -type source region 5 and the P-type base region 3 to the N-type drift region 5 at intervals in the gate length direction.
- the graphene block 12 has a length of 0.1 ⁇ m, an interval of 0.1 ⁇ m, and a thickness of 1 nm; the graphene strips 11 are continuously or spacedly cross-distributed in the gate width direction.
- the devices distributed in a honeycomb shape in Example 1 are connected to each other in the gate width direction, and the on-resistance is smaller and the current transmission capability is stronger.
- the honeycomb graphene makes the P-type base interval more obvious, the auxiliary depletion effect is stronger, the off-state leakage current is smaller, and the breakdown voltage is higher. Therefore, the overall performance of the graphene channel silicon carbide power semiconductor devices distributed in a honeycomb shape is better.
- the present invention is prepared by the following method:
- the first step using an epitaxial process to grow a thick epitaxial layer on the surface of the N-type substrate 1 to form an N-type drift region 2;
- Step 2 Use photolithography and ion implantation to symmetrically implant aluminum ions at both ends of the N-type drift region 2 to form a P-type base region 3;
- the third step using photolithography and ion implantation processes, implanting aluminum ions into the P-type base region 3 to form a P + -type body contact region 4;
- the fourth step using photolithography and ion implantation processes, implanting phosphorus ions into the P-type base region 3 to form an N + -type source region 5;
- Step 5 Etching and depositing the graphene array 11 in the P-type base region 3 using an etching and deposition process
- a gate oxide layer 7 is formed on the P-type body region 3, the graphene array 11 and the N-type drift region 2 by using a thermal oxidation or deposition and etching process;
- the seventh step using a deposition and etching process, depositing polysilicon over the gate oxygen layer 7 and etching out the polysilicon gate 8;
- Step 8 Using a deposition and etching process, a metal layer is deposited on the surface of the device, the electrode contact area is etched to lead out the electrode, and finally passivation is performed.
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Abstract
Description
Claims (4)
- 一种石墨烯沟道碳化硅功率半导体晶体管,包括:N型衬底(1),在N型衬底(1)的一侧连接漏极金属(10),另一侧有N型漂移区(2),在N型漂移区(2)两端分别设置P型基区(3),在各P型基区(3)内分别设有P+型体接触区(4)和N+型源区(5),在N型漂移区(2)的表面设有栅氧层(7)且所述栅氧层(7)的两端分别延伸进入两侧的P型基区(3),在栅氧层(7)的表面设有多晶硅栅(8),在多晶硅栅(8)上设有钝化层(6)且所述钝化层(6)包裹多晶硅栅(8)的两侧,在N+型源区(5)和P+型体接触区(4)上设有源极金属(9),其特征在于,在所述P型基区(3)内设有作为所述晶体管沟道的石墨烯条(11)且石墨烯条(11)的两端分别触及N+型源区(5)与P型基区(3)之间的边界和P型基区(3)与N型漂移区(2)之间的边界,所述石墨烯条(11)内嵌P型基区(3)表面。
- 根据权利要求1所述的一种石墨烯沟道碳化硅功率半导体晶体管,其特征在于,所述石墨烯条(11)在栅宽方向呈蜂窝状。
- 根据权利要求1所述的一种石墨烯沟道碳化硅功率半导体晶体管,其特征在于,所述石墨烯条(11)呈直条状。
- 根据权利要求1、2或3所述的一种石墨烯沟道碳化硅功率半导体晶体管,其特征在于,在由石墨烯条(11)分割P型基区(3)形成的各个P型基区小区域中分别设有石墨烯块体(12)。
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US16/486,494 US11158708B1 (en) | 2018-06-27 | 2018-09-25 | Graphene channel silicon carbide power semiconductor transistor |
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CN102449732A (zh) * | 2009-10-13 | 2012-05-09 | 住友电气工业株式会社 | 制造碳化硅衬底的方法和碳化硅衬底 |
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US6246077B1 (en) * | 1996-10-16 | 2001-06-12 | Kabushiki Kaisha Toshiba | Semiconductor device |
US20090090919A1 (en) * | 2007-10-03 | 2009-04-09 | Oki Electric Industry Co., Ltd. | Semiconductor device and method of producing the same |
CN102449732A (zh) * | 2009-10-13 | 2012-05-09 | 住友电气工业株式会社 | 制造碳化硅衬底的方法和碳化硅衬底 |
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