WO2020000581A1 - 一种多晶硅半导体层的制备方法、薄膜晶体管及制备方法 - Google Patents

一种多晶硅半导体层的制备方法、薄膜晶体管及制备方法 Download PDF

Info

Publication number
WO2020000581A1
WO2020000581A1 PCT/CN2018/098433 CN2018098433W WO2020000581A1 WO 2020000581 A1 WO2020000581 A1 WO 2020000581A1 CN 2018098433 W CN2018098433 W CN 2018098433W WO 2020000581 A1 WO2020000581 A1 WO 2020000581A1
Authority
WO
WIPO (PCT)
Prior art keywords
ion
amorphous silicon
silicon layer
ions
semiconductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/098433
Other languages
English (en)
French (fr)
Inventor
吕明仁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US16/095,376 priority Critical patent/US10790377B2/en
Publication of WO2020000581A1 publication Critical patent/WO2020000581A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0217—Manufacture or treatment of FETs having insulated gates [IGFET] forming self-aligned punch-through stoppers or threshold implants under gate regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3451—Structure
    • H10P14/3452—Microstructure
    • H10P14/3454—Amorphous
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/28—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by an annealing step, e.g. for activation of dopants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to the technical field of display manufacturing, and in particular, to a method for preparing a polysilicon semiconductor layer, a thin film transistor, and a method for preparing the same.
  • Vth channel implantation
  • Vth channel implantation
  • the channel implantation method using B + has the following disadvantages: because the amount of B + ions dissociated by BF3 gas is about 5 times that of B2 + ions, and it is also much higher than the dissociated B3 + ions, so the display panel is being manufactured In the case of more sophisticated devices, the channel implantation method using B + ions is difficult to achieve small and precise control during B + ion implantation, so the current of the B + ion beam cannot be smaller and more stable, so the channel implantation cannot be controlled very accurately. .
  • the invention provides a method for preparing a polysilicon semiconductor layer, a thin film transistor, and a preparation method, which can implant ions into the corresponding doped regions by a fast and accurate channel implantation method, which can reduce the defective rate of the product, thereby reducing the production cost. .
  • the invention provides a method for preparing a polysilicon semiconductor layer.
  • the method includes the following steps:
  • Step S10 dissociate a preset gas containing ions to be implanted, and screen the dissociated ions for implantation to obtain a low content of a first ion and a high content of a second ion;
  • Step S11 Doping with the second ion in a heavily doped region corresponding to the amorphous silicon layer
  • Step S12 Doping with the first ion in a lightly doped region corresponding to the amorphous silicon layer
  • Step S13 annealing the amorphous silicon layer, so that the amorphous silicon layer doped with the first ion and the second ion forms a polysilicon semiconductor layer.
  • the method specifically includes the following steps:
  • Step S101 dissociate a gas containing BF3, and screen to obtain B2 + / B3 + ions and B + ions;
  • Step S111 Doping with the B + ion in the heavily doped region corresponding to the amorphous silicon layer
  • Step S121 Doping with the B2 + / B3 + ions in the lightly doped region corresponding to the amorphous silicon layer;
  • Step S131 annealing the amorphous silicon layer to form a polysilicon semiconductor layer on the amorphous silicon layer.
  • a method for doping the amorphous silicon layer includes bombarding a surface of the amorphous silicon layer with an ion beam containing the ions to be implanted.
  • a method for obtaining the ion beam includes generating an electron beam through a filament, and bombarding an ion source with the electron beam to generate an ion beam containing the ions to be implanted.
  • ions of different masses in the ion beam are separated by a mass separator, and impurity ions are filtered out.
  • the invention also provides a method for preparing a thin film transistor, which method comprises the following steps:
  • Step S20 Provide a substrate on which an amorphous silicon layer is prepared, dissociate a predetermined gas, and screen the dissociated ions for implanting the amorphous silicon layer to obtain a low-content One ion and high content of second ion;
  • Step S21 Doping with the second ion in a heavily doped region corresponding to the amorphous silicon layer
  • Step S22 Doping with the first ion in a lightly doped region corresponding to the amorphous silicon layer
  • Step S23 annealing the amorphous silicon layer, so that the amorphous silicon layer forms a polysilicon semiconductor layer including a source contact region and a drain contact region;
  • Step S24 forming a source electrode and a drain electrode at corresponding positions of the source contact region and the drain contact region, the source electrode and the drain electrode being in contact with the source contact region and the drain electrode, respectively. District electrical connection.
  • the first ion is a B2 + / B3 + ion
  • the second ion is a B + ion
  • the method further includes the following steps:
  • Step S25 forming a gate insulating layer on the polysilicon semiconductor layer
  • Step S26 A gate is formed on the gate insulating layer corresponding to a predetermined position of the polysilicon semiconductor layer.
  • the method before preparing the amorphous silicon layer on the substrate, the method further includes the following steps:
  • Step S201 preparing a gate on the substrate, and preparing a gate insulating layer on the gate;
  • Step S202 preparing the amorphous silicon layer on the gate insulating layer.
  • the invention also provides a thin film transistor prepared by using the above preparation method.
  • the beneficial effects of the present invention are: the method for preparing the polysilicon semiconductor layer, the thin film transistor, and the method for preparing the polysilicon semiconductor layer of the present invention are used for doping by adjusting B2 + / B3 + ions with low ion content as the starting voltage for channel implantation
  • the lightly doped region of the polysilicon layer is easy to adjust and control because the current generated by the ion beam is smaller and more stable.
  • This solution can be used on LTPS products and OLED TFT LCD, and can form a fast and accurate channel implantation (Vth) method. It can avoid too much variation in channel implantation (Vth) due to the large ion beam current that is difficult to control, which can improve product quality, reduce product defect rate, and thus reduce production costs! It does not need to purchase additional IMP machines and processes. Existing machines can implement this solution.
  • FIG. 1 is a flowchart of a method for preparing a polysilicon semiconductor layer according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a channel implantation device provided by the present invention.
  • FIG. 3 is a flowchart of a method for manufacturing a thin film transistor according to the present invention.
  • the present invention is directed to a method for preparing a polysilicon semiconductor layer in the prior art, because it is difficult to achieve a small amount and precise control during B + ion implantation, so the technical problem of channel implantation cannot be controlled very accurately. This embodiment can solve this defect.
  • FIG. 1 a flowchart of a method for preparing a polysilicon semiconductor layer according to an embodiment of the present invention is shown. The method includes the following steps:
  • Step S10 dissociate a preset gas containing ions to be implanted, and screen the dissociated ions for implantation to obtain a low content of a first ion and a high content of a second ion;
  • the step S10 specifically includes:
  • Step S101 dissociate a gas containing BF3, and screen to obtain B2 + / B3 + ions and B + ions;
  • the preset gas may be BF3 gas, BH3 gas, etc. that dissociate to produce B2 + / B3 + ions.
  • BF3 gas is taken as an example, ion dissociation and screening are performed by a channel implantation device, and a filament of the device is implanted through the channel. An electron beam is generated, and an ion source is bombarded with the electron beam, the ion source including one or more of the above gases to generate an ion beam containing ions to be implanted.
  • the ion beam includes B +, B2 + or / and B3 +.
  • the channel implantation device further includes a substrate carrying table for carrying a substrate to be doped (ion implanted), an amorphous silicon layer is prepared on the substrate, and the surface of the amorphous silicon layer is performed on the ion beam.
  • a mass separator between the substrate carrier and the ion source can separate ions of different masses in the ion beam, filter out impurity ions, and retain only the ions to be implanted.
  • Step S11 Doping with the second ion in a heavily doped region corresponding to the amorphous silicon layer
  • the step S11 specifically includes:
  • Step S111 Doping with the B + ion in the heavily doped region corresponding to the amorphous silicon layer
  • a method of doping the amorphous silicon layer includes bombarding a surface of the amorphous silicon layer with an ion beam of the ions to be implanted. Due to the relatively high dose of implanted ions in the heavily doped region, the required dose for the process is generally about 1E15ions / cm2, so the ions that can be implanted and have a high content are formed to form an ion beam to dope the region. Since the amount of B + ions dissociated by the BF3 gas is about 5 times that of the B2 + ions, and the content of the B + ions is much higher than the content of the B3 + ions, the doping with the B + ions can greatly shorten the process. time.
  • Step S12 Doping with the first ion in a lightly doped region corresponding to the amorphous silicon layer
  • the step S12 specifically includes:
  • Step S121 Doping with the B2 + / B3 + ions in the lightly doped region corresponding to the amorphous silicon layer;
  • the required dose in the manufacturing process is generally about 1E12ions / cm2, which requires that the accuracy of the ion beam during bombardment is high and easy to control.
  • B + ions with high ion content are generally used for bombardment, which often affects the conductive performance of thin film transistors due to inaccurate control.
  • ion implantation is performed on the heavily doped region of the amorphous silicon layer. In other embodiments, ion implantation may also be performed on the lightly doped region of the amorphous silicon layer. It depends on the actual process.
  • Step S13 annealing the amorphous silicon layer, so that the amorphous silicon layer doped with the first ion and the second ion forms a polysilicon semiconductor layer.
  • the step S13 specifically includes:
  • Step S131 annealing the amorphous silicon layer to form a polysilicon semiconductor layer on the amorphous silicon layer.
  • FIG. 2 a schematic structural diagram of a channel implantation device according to the present invention is provided.
  • the device includes: an ion source 1, which is used to generate an ion beam 2 after dissociation; and the ion beam 2 includes a manufacturing process.
  • the path of the ion beam 2 changes under the action of the mass separation magnetic field 3, and ions of different masses have different paths, so that ions of different masses are separated to filter out Most of the impurity ions; the separated ions are further filtered through the slit 4 to filter out the impurity ions, leaving only the ions to be implanted (lightly doped as B2 + / B3 + ions, and heavily doped as B + Ions); the purity of the ions to be implanted is increased after filtering, and the substrate 6 prepared with the polysilicon layer is bombarded with the purified ion beam to be implanted for ion implantation; the two substrates 6 can be moved up and down Set on the channel implantation device, a measuring instrument 7 is used to measure the ion implantation on the substrate 6, and the ion beam to be implanted passes through the plasma liquid-cooled gun 5 (PFG) and between the two substrates 6 in order.
  • FIG. 3 a flowchart of a method for manufacturing a thin film transistor according to the present invention is provided. The method includes the following steps:
  • Step S20 Provide a substrate on which an amorphous silicon layer is prepared, dissociate a predetermined gas, and screen the dissociated ions for implanting the amorphous silicon layer to obtain a low-content One ion and high content of second ion;
  • the preset gas is the same as that in the foregoing embodiment, and is preferably a BF3 gas.
  • the gas is dissociated through the channel implantation device and screened for lower B2 + / B3 + ions and higher B + ions.
  • Step S21 Doping with the second ion in a heavily doped region corresponding to the amorphous silicon layer
  • Step S22 Doping with the first ion in a lightly doped region corresponding to the amorphous silicon layer
  • the B + ion content in the ions available for implantation is higher and the B2 + / B3 + ion content is lower, they are used for the heavily doped regions of the amorphous silicon layer and for specific methods of ion implantation in the lightly doped region, please refer to the description in the above embodiments.
  • Step S23 annealing the amorphous silicon layer, so that the amorphous silicon layer forms a polysilicon semiconductor layer including a source contact region and a drain contact region;
  • Step S24 forming a source electrode and a drain electrode at corresponding positions of the source contact region and the drain contact region, the source electrode and the drain electrode being in contact with the source contact region and the drain electrode, respectively. District electrical connection.
  • step S24 If it is a thin film transistor with a top-gate structure, the following steps are performed after the step S24 is completed:
  • Step S25 forming a gate insulating layer on the polysilicon semiconductor layer
  • Step S26 A gate is formed on the gate insulating layer corresponding to a predetermined position of the polysilicon semiconductor layer.
  • the gate corresponds to a corresponding undoped position in the amorphous silicon layer.
  • an interlayer dielectric layer is formed on the gate, and a source electrode penetrating the interlayer dielectric layer and the gate insulating layer is formed above the source contact region and the drain contact region.
  • a contact hole and a drain contact hole, a source electrode and a drain electrode are respectively formed at corresponding positions of the interlayer dielectric layer corresponding to the source contact region and the drain contact region, and the source electrode and the drain electrode are respectively formed
  • the electrodes are electrically connected to the source contact region and the drain contact region through the source contact hole and the drain contact hole, respectively.
  • the method further includes the following steps:
  • Step S201 preparing a gate on the substrate, and preparing a gate insulating layer on the gate;
  • Step S202 preparing the amorphous silicon layer on the gate insulating layer.
  • the invention also provides a thin film transistor prepared by using the above preparation method.
  • the invention also provides an array substrate prepared by using the above preparation method.
  • the method for preparing a polysilicon semiconductor layer, the thin film transistor and the preparation method of the present invention are used for doping a lightly doped region of a polysilicon layer by adjusting B2 + / B3 + ions with a lower ion content as a starting voltage for channel implantation. Because the current generated by the ion beam is smaller and more stable, it is easy to adjust and control.
  • This solution can be used on LTPS products and OLED TFT LCD, and can form a fast and accurate channel implantation (Vth) method. It can avoid too much variation in channel implantation (Vth) due to the large ion beam current that is difficult to control, which can improve product quality, reduce product defect rate, and thus reduce production costs! It does not need to purchase additional IMP machines and processes. Existing machines can implement this solution.

Landscapes

  • Thin Film Transistor (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)

Abstract

本发明提供一种多晶硅半导体层的制备方法、薄膜晶体管及制备方法，该多晶硅半导体层的制备方法包括以下步骤：解离预设气体，并筛选出用于植入的低含量的第一离子以及高含量的第二离子；以所述第二离子掺杂重掺杂区域，以所述第一离子掺杂轻掺杂区域；再进行退火处理，使得所述非晶硅层形成多晶硅半导体层。

Description

一种多晶硅半导体层的制备方法、薄膜晶体管及制备方法 技术领域
本发明涉及显示制造技术领域，尤其涉及一种多晶硅半导体层的制备方法、薄膜晶体管及制备方法。
 背景技术
因应手持式智慧型移动装置的崛起，对于面板萤幕的表现与高品质要求越来越高，为了增加产品可靠度目前主流产品制程设计需求通道植入(Vth)是主要重点之一，由于目前显示面板的开口率越来越大，内部一些器件的制作越来越精密，如何更稳定更微小调整制作方法更显得重要之重。
目前有透过离子B+的通道植入(Vth)作法来改善Vth起始电压，例如薄膜晶体管中多晶硅层的掺杂，由于轻掺杂部所需离子剂量低，需求制程的控制准确度要高，而重掺杂部由于所需离子的剂量高，对离子的吞吐量要求也高。但采用B+的通道植入法存在如下缺点：由于BF3气体解离出的B+离子是B2+离子的约5倍的量，以及相较于解离的B3+离子同样高出很多，因此在制作显示面板内较为精密的器件时，采用B+离子的通道植入法由于B+离子注入时难以实现小量且精准的控制，所以B+离子束的电流无法更小更稳定，因此无法很精确的控制通道植入。
因此，有必要提供一种多晶硅半导体层的制备方法，以解决现有技术所存在的问题。
 技术问题
本发明提供一种多晶硅半导体层的制备方法、薄膜晶体管及制备方法，能够以一种快速且精确的通道植入方法将离子植入相应的掺杂区域，能降低产品不良率，从而降低生产成本。
 技术解决方案
本发明提供一种多晶硅半导体层的制备方法，所述方法包括以下步骤：
步骤S10、对含有待植入离子的预设气体进行解离，在解离出的用于植入的离子中筛选得到低含量的第一离子以及高含量的第二离子；
步骤S11、在非晶硅层对应的重掺杂区域，以所述第二离子进行掺杂；
步骤S12、在所述非晶硅层对应的轻掺杂区域，以所述第一离子进行掺杂；
步骤S13、对所述非晶硅层进行退火处理，使得掺杂有所述第一离子与所述第二离子的所述非晶硅层形成多晶硅半导体层。
根据本发明一优选实施例，所述方法具体包括以下步骤：
步骤S101、对含有BF3的气体进行解离，筛选得到B2+/B3+离子以及B+离子；
步骤S111、在所述非晶硅层对应的所述重掺杂区域，以所述B+离子进行掺杂；
步骤S121、在所述非晶硅层对应的所述轻掺杂区域，以所述B2+/B3+离子进行掺杂；
步骤S131、对所述非晶硅层进行退火处理，使所述非晶硅层形成多晶硅半导体层。
根据本发明一优选实施例，对所述非晶硅层进行掺杂的方法包括采用含有所述待植入离子的离子束对所述非晶硅层表面进行轰击。
根据本发明一优选实施例，获得所述离子束的方法包括通过灯丝产生电子束，利用所述电子束轰击离子源，以产生含有所述待植入离子的离子束。
根据本发明一优选实施例，采用离子束对所述非晶硅层表面进行轰击前，通过质量分离器对所述离子束中不同质量的离子进行分离，滤掉杂质离子。
本发明还提供一种薄膜晶体管的制备方法，所述方法包括以下步骤：
步骤S20、提供一基板，所述基板上制备有非晶硅层，对预设气体进行解离，在解离出的用于植入所述非晶硅层的离子中筛选得到低含量的第一离子以及高含量的第二离子；
步骤S21、在非晶硅层对应的重掺杂区域，以所述第二离子进行掺杂；
步骤S22、在所述非晶硅层对应的轻掺杂区域，以所述第一离子进行掺杂；
步骤S23、对所述非晶硅层进行退火处理，使得所述非晶硅层形成包括源极接触区和漏极接触区的多晶硅半导体层；
步骤S24、在所述源极接触区和所述漏极接触区的相应位置形成源极与漏极，所述源极与所述漏极分别与所述源极接触区和所述漏极接触区电连接。
根据本发明一优选实施例，所述第一离子为B2+/B3+离子，所述第二离子为B+离子。
根据本发明一优选实施例，所述方法还包括以下步骤：
步骤S25、在所述多晶硅半导体层上形成栅极绝缘层；
步骤S26、在所述栅极绝缘层上对应所述多晶硅半导体层的预设位置形成栅极。
根据本发明一优选实施例，在所述基板上制备所述非晶硅层之前，还包括以下步骤：
步骤S201、在所述基板上制备栅极，并在所述栅极上制备一层栅绝缘层；
步骤S202、在所述栅绝缘层上制备所述非晶硅层。
本发明还提供一种采用上述制备方法制备的薄膜晶体管。
 有益效果
本发明的有益效果为：本发明的多晶硅半导体层的制备方法、薄膜晶体管及制备方法，通过将离子含量较低的B2+/B3+离子做为通道植入的起始电压的调整，用于掺杂多晶硅层的轻掺杂区域，由于该离子束产生的电流更小更稳定，所以易于调整控制。本方案可用于LTPS产品以及OLED TFT LCD等产品上，可以形成一种快速且精确的通道植入(Vth)方法。可避免通道植入(Vth)由于离子束电流过大不易控制而导致太大的变异，可提升产品的品质，降低产品不良率，从而降低生产成本！且不需要增购额外的IMP机台与制程，现有机台可以实现该方案。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的多晶硅半导体层的制备方法流程图；
图2为本发明提供一种通道植入装置结构示意图；
图3为本发明提供一种薄膜晶体管的制备方法流程图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本发明针对现有技术的多晶硅半导体层的制备方法由于B+离子注入时难以实现小量且精准的控制，因此无法很精确的控制通道植入的技术问题，本实施例能够解决该缺陷。
参阅图1，为本发明实施例提供的多晶硅半导体层的制备方法流程图。所述方法包括以下步骤：
步骤S10、对含有待植入离子的预设气体进行解离，在解离出的用于植入的离子中筛选得到低含量的第一离子以及高含量的第二离子；
所述步骤S10具体包括：
步骤S101、对含有BF3的气体进行解离，筛选得到B2+/B3+离子以及B+离子；
该预设气体可以为解离产生B2+/B3+离子的BF3气体、BH3气体等，本实施例以BF3气体为例，通过通道植入设备进行离子解离以及筛选，通过该通道植入设备的灯丝产生电子束，利用所述电子束轰击离子源，该离子源包括上述一种或一种以上的气体，以产生含有待植入离子的离子束。所述离子束中包含B+、B2+或/和B3+。该通道植入设备还包括基板承载台，用来承载待掺杂（离子植入）的基板，所述基板上制备有非晶硅层，在所述离子束对所述非晶硅层表面进行轰击前，在所述基板承载台与所述离子源之间的质量分离器可以对所述离子束中不同质量的离子进行分离，滤掉杂质离子，只保留待植入离子。
步骤S11、在非晶硅层对应的重掺杂区域，以所述第二离子进行掺杂；
所述步骤S11具体包括：
步骤S111、在所述非晶硅层对应的所述重掺杂区域，以所述B+离子进行掺杂；
对所述非晶硅层进行掺杂的方法包括采用所述待植入离子的离子束对所述非晶硅层表面进行轰击。由于所述重掺杂区域相应植入的离子剂量较高，制程需求的剂量一般为1E15ions/cm2左右，所以筛选出可以用来植入的且含量较高的离子形成离子束对该区域进行掺杂，由于所述BF3气体解离的所述B+离子是所述B2+离子约5倍的量，而且也大大高于所述B3+离子的含量，所以以所述B+离子进行掺杂可以大大缩短制程时间。
步骤S12、在所述非晶硅层对应的轻掺杂区域，以所述第一离子进行掺杂；
所述步骤S12具体包括：
步骤S121、在所述非晶硅层对应的所述轻掺杂区域，以所述B2+/B3+离子进行掺杂；
由于所述非晶硅层的轻掺杂区域需求植入的离子剂量相对较低，制程需求的剂量一般为1E12ions/cm2左右，这就要求离子束在轰击时的准确度要高且易于控制，现有技术中一般采用离子含量较高的B+离子进行轰击，往往由于不能精确的控制而影响薄膜晶体管的导电性能。由于所述B2+/B3+离子在解离出的可用于植入的离子中的含量较低，且所述B2+/B3+离子形成的离子束的电流相较于所述B+离子形成离子束的电流可以更小更稳定，从而在对所述非晶硅层的所述轻掺杂区域进行轰击时可以更容易控制，进而能够精确的控制该通道植入，保证薄膜晶体管的电性。本实施例先对所述非晶硅层的所述重掺杂区域进行离子植入，在其他实施例中也可先对所述非晶硅层的所述轻掺杂区域进行离子植入，具体根据实际制程而定。
步骤S13、对所述非晶硅层进行退火处理，使得掺杂有所述第一离子与所述第二离子的所述非晶硅层形成多晶硅半导体层。
所述步骤S13具体包括：
步骤S131、对所述非晶硅层进行退火处理，使所述非晶硅层形成多晶硅半导体层。
如图2所示，为本发明提供一种通道植入装置结构示意图，该装置包括：离子源1，所述离子源1用于解离后产生离子束2；所述离子束2包含有制程所需的植入离子以及杂质离子；所述离子束2在质量分离磁场3的作用下路径发生改变，且不同质量的离子具有不同的路径，以此将不同质量的离子进行分离，以过滤掉大部分的所述杂质离子；分离后的离子经过狭缝4进一步过滤，过滤掉所述杂质离子，只留下所述待植入离子（轻掺杂为B2+/B3+离子，重掺杂为B+离子）；经过过滤后的所述待植入离子的纯度提高，用提纯后的待植入离子束轰击制备有多晶硅层的基板6上，进行离子植入；两所述基板6可上下移动的设置于该通道植入装置上，测量仪7用于测量所述基板6上离子植入情况，所述待植入离子束依次经过等离子液冷枪5（PFG）和两所述基板6之间的间隙入射到所述测量仪7上，通过所述测量仪7所测量的结果及时调整控制所述待植入离子束。
如图3所示，为本发明提供一种薄膜晶体管的制备方法流程图，所述方法包括以下步骤：
步骤S20、提供一基板，所述基板上制备有非晶硅层，对预设气体进行解离，在解离出的用于植入所述非晶硅层的离子中筛选得到低含量的第一离子以及高含量的第二离子；
其中，该预设气体与上述实施例中的一致，优选为BF3气体。该气体通过通道植入设备进行解离并筛选出含量较低的B2+/B3+离子以及含量较高的B+离子。
步骤S21、在非晶硅层对应的重掺杂区域，以所述第二离子进行掺杂；
步骤S22、在所述非晶硅层对应的轻掺杂区域，以所述第一离子进行掺杂；
具体地，由于解离出可用于植入的离子中所述B+离子含量较高，所述B2+/B3+离子含量较低，因此分别用于所述非晶硅层的所述重掺杂区域以及所述轻掺杂区域的离子植入，具体方法请参照上述实施例中描述。
步骤S23、对所述非晶硅层进行退火处理，使得所述非晶硅层形成包括源极接触区和漏极接触区的多晶硅半导体层；
步骤S24、在所述源极接触区和所述漏极接触区的相应位置形成源极与漏极，所述源极与所述漏极分别与所述源极接触区和所述漏极接触区电连接。
如果是顶栅结构的薄膜晶体管，则在所述步骤S24完成之后执行以下步骤：
步骤S25、在所述多晶硅半导体层上形成栅极绝缘层；
步骤S26、在所述栅极绝缘层上对应所述多晶硅半导体层的预设位置形成栅极。
其中，所述栅极对应所述非晶硅层中未被掺杂的相应位置。接着在所述栅极上形成层间介电层，在对应所述源极接触区和所述漏极接触区的上方形成贯穿所述层间介电层和所述栅极绝缘层的源极接触孔与漏极接触孔，在所述层间介电层的对应所述源极接触区和所述漏极接触区的相应位置分别形成源极与漏极，所述源极与所述漏极分别通过所述源极接触孔与所述漏极接触孔电性连接于所述源极接触区与所述漏极接触区。
如果是底栅结构的薄膜晶体管，则在所述基板上制备所述非晶硅层之前，还包括以下步骤：
步骤S201、在所述基板上制备栅极，并在所述栅极上制备一层栅绝缘层；
步骤S202、在所述栅绝缘层上制备所述非晶硅层。
本发明还提供一种采用上述制备方法制备的薄膜晶体管。
本发明还提供一种采用上述制备方法制备的阵列基板。
本发明的多晶硅半导体层的制备方法、薄膜晶体管及制备方法，通过将离子含量较低的B2+/B3+离子做为通道植入的起始电压的调整，用于掺杂多晶硅层的轻掺杂区域，由于该离子束产生的电流更小更稳定，所以易于调整控制。本方案可用于LTPS产品以及OLED TFT LCD等产品上，可以形成一种快速且精确的通道植入(Vth)方法。可避免通道植入(Vth)由于离子束电流过大不易控制而导致太大的变异，可提升产品的品质，降低产品不良率，从而降低生产成本！且不需要增购额外的IMP机台与制程，现有机台可以实现该方案。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (10)

  1. 一种多晶硅半导体层的制备方法，其中，所述方法包括以下步骤：
    步骤S10、对含有待植入离子的预设气体进行解离，在解离出的用于植入的离子中筛选得到低含量的第一离子以及高含量的第二离子；
    步骤S11、在非晶硅层对应的重掺杂区域，以所述第二离子进行掺杂；
    步骤S12、在所述非晶硅层对应的轻掺杂区域，以所述第一离子进行掺杂；
    步骤S13、对所述非晶硅层进行退火处理，使得掺杂有所述第一离子与所述第二离子的所述非晶硅层形成多晶硅半导体层。
  2. 根据权利要求1所述的制备方法，其中，所述方法具体包括以下步骤：
    步骤S101、对含有BF3的气体进行解离，筛选得到B2+/B3+离子以及B+离子；
    步骤S111、在所述非晶硅层对应的所述重掺杂区域，以所述B+离子进行掺杂；
    步骤S121、在所述非晶硅层对应的所述轻掺杂区域，以所述B2+/B3+离子进行掺杂；
    步骤S131、对所述非晶硅层进行退火处理，使所述非晶硅层形成多晶硅半导体层。
  3. 根据权利要求1所述的制备方法，其中，对所述非晶硅层进行掺杂的方法包括采用含有所述待植入离子的离子束对所述非晶硅层表面进行轰击。
  4. 根据权利要求3所述的制备方法，其中，获得所述离子束的方法包括通过灯丝产生电子束，利用所述电子束轰击离子源，以产生含有所述待植入离子的离子束。
  5. 根据权利要求3所述的制备方法，其中，采用离子束对所述非晶硅层表面进行轰击前，通过质量分离器对所述离子束中不同质量的离子进行分离，滤掉杂质离子。
  6. 一种薄膜晶体管的制备方法，其中，所述方法包括以下步骤：
    步骤S20、提供一基板，所述基板上制备有非晶硅层，对预设气体进行解离，在解离出的用于植入所述非晶硅层的离子中筛选得到低含量的第一离子以及高含量的第二离子；
    步骤S21、在非晶硅层对应的重掺杂区域，以所述第二离子进行掺杂；
    步骤S22、在所述非晶硅层对应的轻掺杂区域，以所述第一离子进行掺杂；
    步骤S23、对所述非晶硅层进行退火处理，使得所述非晶硅层形成包括源极接触区和漏极接触区的多晶硅半导体层；
    步骤S24、在所述源极接触区和所述漏极接触区的相应位置形成源极与漏极，所述源极与所述漏极分别与所述源极接触区和所述漏极接触区电连接。
  7. 根据权利要求6所述的制备方法，其中，所述第一离子为B2+/B3+离子，所述第二离子为B+离子。
  8. 根据权利要求6所述的制备方法，其中，所述方法还包括以下步骤：
    步骤S25、在所述多晶硅半导体层上形成栅极绝缘层；
    步骤S26、在所述栅极绝缘层上对应所述多晶硅半导体层的预设位置形成栅极。
  9. 根据权利要求6所述的制备方法，其中，在所述基板上制备所述非晶硅层之前，还包括以下步骤：
    步骤S201、在所述基板上制备栅极，并在所述栅极上制备一层栅绝缘层；
    步骤S202、在所述栅绝缘层上制备所述非晶硅层。
  10. 一种采用如权利要求6所述的制备方法制备的薄膜晶体管。
PCT/CN2018/098433 2018-06-27 2018-08-03 一种多晶硅半导体层的制备方法、薄膜晶体管及制备方法 Ceased WO2020000581A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/095,376 US10790377B2 (en) 2018-06-27 2018-08-03 Manufacturing method of polysilicon semiconductor layer,thin film transistor and manufacturing method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810677628.3A CN108962734B (zh) 2018-06-27 2018-06-27 一种多晶硅半导体层的制备方法、薄膜晶体管及制备方法
CN201810677628.3 2018-06-27

Publications (1)

Publication Number Publication Date
WO2020000581A1 true WO2020000581A1 (zh) 2020-01-02

Family

ID=64486964

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/098433 Ceased WO2020000581A1 (zh) 2018-06-27 2018-08-03 一种多晶硅半导体层的制备方法、薄膜晶体管及制备方法

Country Status (3)

Country Link
US (1) US10790377B2 (zh)
CN (1) CN108962734B (zh)
WO (1) WO2020000581A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0864549A (ja) * 1994-08-24 1996-03-08 Sony Corp イオンドーピング方法及びイオンドーピング装置
KR20020050525A (ko) * 2000-12-21 2002-06-27 박종섭 Ｌｄｄ 구조를 갖는 반도체 장치의 제조방법
US6440809B1 (en) * 2001-03-13 2002-08-27 United Microelectronics Corp. Method of preventing fluorine ions from residing in a gate to result in boron ion penetration into a gate oxide
CN1610051A (zh) * 2003-10-24 2005-04-27 应用材料有限公司 离子源中的阴极和反阴极装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3609131B2 (ja) * 1994-12-06 2005-01-12 株式会社半導体エネルギー研究所 イオンドーピング装置のクリーニング方法
US6743679B2 (en) * 1999-03-03 2004-06-01 Koninklijke Philips Electronics N.V. Integrated circuit devices with high and low voltage components and processes for manufacturing these devices
US20040207026A1 (en) * 2002-04-19 2004-10-21 Xi-Wei Lin Integrated circuit devices with high and voltage components and processes for manufacturing these devices
US7635618B2 (en) * 1999-03-03 2009-12-22 Nxp B.V. Integrated circuit devices with high and low voltage components and processes for manufacturing these devices
JP4869509B2 (ja) * 2001-07-17 2012-02-08 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6686595B2 (en) * 2002-06-26 2004-02-03 Semequip Inc. Electron impact ion source
JP2007258453A (ja) * 2006-03-23 2007-10-04 Toshiba Matsushita Display Technology Co Ltd 薄膜トランジスタ、及びその製造方法
US7732309B2 (en) * 2006-12-08 2010-06-08 Applied Materials, Inc. Plasma immersed ion implantation process
JP5424299B2 (ja) * 2008-12-16 2014-02-26 国立大学法人東北大学 イオン注入装置、イオン注入方法、及び半導体装置
US7858503B2 (en) * 2009-02-06 2010-12-28 Applied Materials, Inc. Ion implanted substrate having capping layer and method
CN102779714A (zh) * 2012-08-20 2012-11-14 杭州士兰集成电路有限公司 一种Bipolar电路中的二价硼离子注入工艺
US9315892B2 (en) * 2013-03-15 2016-04-19 Taiwan Semiconductor Manufacturing Company Limited Method and apparatus for controlling beam angle during ion implantation of a semiconductor wafer based upon pressure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0864549A (ja) * 1994-08-24 1996-03-08 Sony Corp イオンドーピング方法及びイオンドーピング装置
KR20020050525A (ko) * 2000-12-21 2002-06-27 박종섭 Ｌｄｄ 구조를 갖는 반도체 장치의 제조방법
US6440809B1 (en) * 2001-03-13 2002-08-27 United Microelectronics Corp. Method of preventing fluorine ions from residing in a gate to result in boron ion penetration into a gate oxide
CN1610051A (zh) * 2003-10-24 2005-04-27 应用材料有限公司 离子源中的阴极和反阴极装置

Also Published As

Publication number Publication date
US10790377B2 (en) 2020-09-29
CN108962734B (zh) 2021-01-01
US20200006524A1 (en) 2020-01-02
CN108962734A (zh) 2018-12-07

Similar Documents

Publication Publication Date Title
CN107482066B (zh) 薄膜晶体管及其制备方法、阵列基板和显示装置
US5397718A (en) Method of manufacturing thin film transistor
WO2015027590A1 (zh) 阵列基板及其制备方法和显示装置
CN104282696B (zh) 一种阵列基板及其制作方法、显示装置
JP3146113B2 (ja) 薄膜トランジスタの製造方法および液晶表示装置
CN101542743A (zh) 半导体装置及其制造方法
CN103383946A (zh) 一种阵列基板、显示装置及阵列基板的制备方法
CN107275191B (zh) 一种薄膜晶体管及制备方法、阵列基板和显示面板
CN110034178B (zh) 薄膜晶体管及其制备方法、阵列基板和显示装置
CN109860307A (zh) 一种晶体管及其制备方法、显示基板和显示装置
CN105161459A (zh) 低温多晶硅阵列基板及其制作方法
WO2020000581A1 (zh) 一种多晶硅半导体层的制备方法、薄膜晶体管及制备方法
CN108258021B (zh) 薄膜晶体管、其制备方法、阵列基板及显示装置
CN109103105A (zh) 薄膜晶体管及其制备方法、显示装置
CN104617151B (zh) 低温多晶硅薄膜晶体管及制作方法、阵列基板及显示装置
US10797166B2 (en) Manufacturing method for IGZO active layer and oxide thin film transistor
US20080078958A1 (en) Method for controlling charge amount of ion beam and a wafer applied in the method
CN107068771B (zh) 低温多晶硅薄膜晶体管及其制造方法
CN105140237B (zh) 阵列基板及其制备方法以及液晶显示器
CN109659235A (zh) Tft的制备方法、tft、阵列基板及显示装置
CN104900708B (zh) 一种改善漏极电流的薄膜晶体管
JPH1012890A (ja) 薄膜半導体装置の製造方法
US10825930B2 (en) Thin film transistor and manufacture method thereof
US10615051B2 (en) Thin-film transistor and method of manufacturing the same, array substrate, and display apparatus
JPH0786603A (ja) 半導体膜の製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18924689

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18924689

Country of ref document: EP

Kind code of ref document: A1