WO2019237825A1 - 时间同步装置、电子设备、时间同步系统及时间同步方法 - Google Patents

时间同步装置、电子设备、时间同步系统及时间同步方法 Download PDF

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Publication number
WO2019237825A1
WO2019237825A1 PCT/CN2019/082926 CN2019082926W WO2019237825A1 WO 2019237825 A1 WO2019237825 A1 WO 2019237825A1 CN 2019082926 W CN2019082926 W CN 2019082926W WO 2019237825 A1 WO2019237825 A1 WO 2019237825A1
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Prior art keywords
frequency
circuit
output
time
signal
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PCT/CN2019/082926
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English (en)
French (fr)
Inventor
魏祥野
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京东方科技集团股份有限公司
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Priority to KR1020207018704A priority Critical patent/KR102391323B1/ko
Priority to US16/620,547 priority patent/US11429137B2/en
Priority to MX2020006929A priority patent/MX2020006929A/es
Priority to JP2020536774A priority patent/JP7389037B2/ja
Priority to AU2019285968A priority patent/AU2019285968B2/en
Priority to EP19819039.9A priority patent/EP3806355A4/en
Priority to BR112020013384-1A priority patent/BR112020013384A2/pt
Priority to RU2020121188A priority patent/RU2758838C1/ru
Publication of WO2019237825A1 publication Critical patent/WO2019237825A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/14—Time supervision arrangements, e.g. real time clock
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L1/00—Stabilisation of generator output against variations of physical values, e.g. power supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L1/00—Stabilisation of generator output against variations of physical values, e.g. power supply
    • H03L1/02—Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only
    • H03L1/022—Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature
    • H03L1/027—Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature by using frequency conversion means which is variable with temperature, e.g. mixer, frequency divider, pulse add/substract logic circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H03L7/0996—Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays

Definitions

  • Embodiments of the present disclosure relate to a time synchronization device, an electronic device, a time synchronization system, and a time synchronization method.
  • the clock synchronization of various devices in the network system is very important.
  • the key of the network clock synchronization technology is the frequency of the local clock of each device. If the frequency of the clock is larger, the time accuracy of synchronization from the network to the local is higher, and the work coordination and consistency between the devices are better.
  • At least one embodiment of the present disclosure provides a time synchronization device for an electronic device, which includes a signal generating circuit and a time adjusting circuit.
  • the signal generating circuit includes a control circuit and a signal conditioning circuit, the control circuit is configured to generate a frequency control word; the signal conditioning circuit is configured to receive an input signal having an initial frequency and the frequency control word, and according to the frequency control word and the frequency control word The input signal generates and outputs an output signal having a target frequency.
  • the time adjustment circuit is configured to perform a synchronous adjustment operation on a clock signal of the electronic device based on an output signal having the target frequency.
  • control circuit is configured to generate the frequency control word according to an influence parameter of a crystal drift.
  • the signal generating circuit further includes a parameter acquisition circuit configured to acquire the influence parameter.
  • the parameters affecting the crystal drift include a temperature parameter
  • the parameter acquisition circuit includes a temperature detection sub-circuit
  • the temperature detection sub-circuit is configured to detect the Temperature parameters.
  • the temperature detection sub-circuit includes a temperature detector and a first counter, the temperature detector is configured to detect an ambient temperature, and the temperature parameter includes the Ambient temperature, the first counter is configured to record a frequency change amount according to the ambient temperature and a reference temperature.
  • control circuit is configured to generate the frequency control word based on the ambient temperature based on the following formula:
  • F N represents the frequency control word
  • F TO represents a reference frequency control word corresponding to the reference temperature
  • f ⁇ represents a frequency in a reference time unit
  • ⁇ f represents the frequency change amount
  • r, p, d, and g are constants
  • ⁇ T represents the difference between the ambient temperature and the reference temperature
  • ⁇ T T1-T2
  • T1 represents the ambient temperature
  • T2 represents The reference temperature
  • n is a positive integer.
  • the influence parameter of the crystal drift includes an aging parameter
  • the parameter acquisition circuit includes an aging read sub-circuit
  • the aging read sub-circuit is configured to read Take the aging parameter of the crystal source.
  • the aging read sub-circuit includes an aging reading element and a second counter, and the aging reading element is configured to read the aging of the crystal source. Rate, and reading a reference time corresponding to the aging rate, the aging parameter includes the aging rate and the reference time, and the second counter is configured to record the number of the reference time.
  • control circuit is configured to generate the frequency control word according to the aging rate based on the following formula:
  • F N the frequency control word
  • F AO the reference frequency control word
  • ⁇ the product of the aging parameters
  • ⁇ ⁇ ⁇ t
  • ⁇ the aging rate
  • t the reference time. Number
  • Number, and t is a natural number.
  • the signal conditioning circuit includes a reference time unit generation sub-circuit and a frequency adjustment sub-circuit, and the reference time unit generation sub-circuit is configured to receive a signal having the initial frequency.
  • a frequency adjustment sub-circuit is configured to generate and output the output signal having the target frequency according to the frequency control word and the reference time unit .
  • the reference time unit generating sub-circuit includes: a voltage-controlled delay, a second phase-locked loop circuit, and K output terminals, and the voltage-controlled delay Including one or more cascaded delay units, and configured to generate a delay signal according to the input signal and an output signal of the second phase-locked loop circuit;
  • the second phase-locked loop circuit is configured To lock the output frequency of the voltage-controlled delay device to a reference output frequency according to the input signal and the delay signal;
  • the frequency adjusting sub-circuit is configured to determine the target frequency according to the frequency control word and the reference time unit based on the following formula:
  • f TAF-DPS represents the target frequency
  • F represents the frequency control word
  • the frequency regulator circuit includes a time-averaged frequency direct period synthesizer.
  • At least one embodiment of the present disclosure further provides an electronic device including the time synchronization device according to any one of the above.
  • the electronic device provided by at least one embodiment of the present disclosure further includes a frequency source configured to provide an input signal having the initial frequency.
  • At least one embodiment of the present disclosure also provides a time synchronization system, including: a plurality of electronic devices. At least one of the plurality of electronic devices is the electronic device according to any one of the above.
  • At least one embodiment of the present disclosure further provides a time synchronization method, which is applied to the time synchronization device according to any one of the foregoing.
  • the time synchronization method includes: generating a frequency control word; and according to the frequency control word and the input A signal to generate and output an output signal having the target frequency; and perform a synchronous adjustment operation on a clock signal of the electronic device based on the output signal having the target frequency.
  • FIG. 1 is a schematic diagram of a clock network distribution
  • FIG. 2 is a schematic block diagram of an electronic device according to at least one embodiment of the present disclosure.
  • FIG. 3 is a schematic block diagram of a time synchronization apparatus for an electronic device according to at least one embodiment of the present disclosure
  • FIG. 4 is a schematic block diagram of a signal generating circuit provided by at least one embodiment of the present disclosure.
  • FIG. 5 is another schematic block diagram of a signal generating circuit provided by at least one embodiment of the present disclosure.
  • 6A is a schematic structural diagram of a reference time unit generating sub-circuit provided by at least one embodiment of the present disclosure
  • 6B is a schematic structural diagram of another reference time unit generating sub-circuit provided by at least one embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of K reference output signals with evenly spaced phases provided by at least one embodiment of the present disclosure
  • FIG. 8 is a schematic block diagram of a frequency adjusting sub-circuit provided by at least one embodiment of the present disclosure
  • FIG. 9 is a schematic diagram of a working principle of a frequency regulator circuit provided by at least one embodiment of the present disclosure.
  • FIG. 10A is a schematic structural diagram of a frequency regulator circuit provided by at least one embodiment of the present disclosure.
  • 10B is a schematic structural diagram of another frequency regulator circuit according to at least one embodiment of the present disclosure.
  • FIG. 11 is a schematic block diagram of a time synchronization system according to at least one embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of time synchronization based on a network time synchronization protocol NTP in a time synchronization system provided by at least one embodiment of the present disclosure
  • FIG. 13 shows a schematic flowchart of a time synchronization method according to at least one embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram of a clock network distribution.
  • a large data network such as the Internet
  • multiple clock links need to be used to drive all network nodes, so that the clocks of all network nodes are synchronized.
  • clock synchronization includes one-way timing, two-way timing, network clock synchronization technology, and clock correction through network packets (for example, NTP, PTP technology).
  • the accuracy of unidirectional and bidirectional timing is low.
  • the accuracy of network clock synchronization technology and clock correction through network packets is higher than that of unidirectional and bidirectional timing.
  • the method of clock synchronization also includes the method of frequency synchronization. For example, using a cable or optical cable to directly transfer standard frequencies such as 10MHz and 5MHz (but this method has many limiting factors).
  • the time difference between the master and slave clocks can be obtained by measurement and the master and slave clocks can be locked. The time difference achieves frequency lock, or indirectly calculates frequency deviation to complete frequency correction.
  • the correction accuracy of time accuracy is limited, and there are differences in factors such as hardware, software, and network links between the server and the client. Therefore, changes in each factor will affect the network The time correction of each device affects.
  • At least one embodiment of the present disclosure provides a time synchronization device, an electronic device, a time synchronization system, and a time synchronization method for an electronic device.
  • the time synchronization device can synthesize an output signal with a sufficiently large frequency through a signal generating circuit, and the frequency granularity of the output signal is high, so that the electronic device can obtain a more accurate synchronous clock, and the electronic device's work coordination and consistency in the network system are more it is good.
  • FIG. 2 is a schematic block diagram of an electronic device according to at least one embodiment of the present disclosure
  • FIG. 3 is a schematic block diagram of a time synchronization device for an electronic device according to at least one embodiment of the present disclosure
  • a schematic block diagram of a signal generating circuit provided by at least one embodiment is disclosed.
  • FIG. 5 is another schematic block diagram of a signal generating circuit provided by at least one embodiment of the present disclosure.
  • the electronic device 50 provided by at least one embodiment of the present disclosure may include a time synchronization device 1000 provided by at least one embodiment of the present disclosure.
  • the electronic device 50 may be, for example, any device having a data transmission function, including, but not limited to, a smart phone, a tablet computer, an e-book reader, a laptop computer, a desktop computer, and the like, which are not limited in the embodiments of the present disclosure.
  • the time synchronization device 1000 provided by at least one embodiment of the present disclosure includes a signal generation circuit 100 and a time adjustment circuit 150.
  • the signal generating circuit 100 includes a control circuit 11 and a signal conditioning circuit 12.
  • the control circuit 11 is configured to generate a frequency control word.
  • the signal conditioning circuit 12 is configured to receive an input signal and a frequency control word having an initial frequency, and generate and output an output signal having a target frequency based on the frequency control word and the input signal.
  • the time adjustment circuit 150 is configured to adjust a clock signal of the electronic device based on an output signal having a target frequency to obtain a synchronized clock signal.
  • the electronic device 50 may further include a frequency source 200.
  • the frequency source 200 is configured to provide an input signal having an initial frequency and transmit the input signal to the signal generating circuit 100.
  • the initial frequency may represent the frequency of a signal that is actually generated and output by the frequency source 200.
  • the target frequency indicates the frequency of the signal desired by the user.
  • the target frequency indicates a frequency that a signal output from the signal generating circuit 100 can reach.
  • the target frequency is greater than the initial frequency.
  • the target frequency is related to the time synchronization accuracy of the terminal device that needs to perform clock synchronization.
  • the network clock synchronization system includes a first terminal device and a second terminal device, and the first terminal device and the second terminal device need to perform time synchronization. If the frequency of the local clock signal of the first terminal device is f, then the frequency accuracy that the first terminal device can adjust is 1 / f. The time error that needs to be corrected between the first terminal device and the second terminal device is t. If t> 1 / f, then the first terminal device can better correct the time error between it and the second terminal device. To better achieve time synchronization between the first terminal device and the second terminal device.
  • the range of the target frequency f TAF-DPS can be: f TAF-DPS > 1 / t.
  • the frequency source 200 may include a self-excited oscillation source and a synthetic frequency source.
  • Self-oscillating sources include crystal oscillators, cavity oscillators, and voltage-controlled oscillators.
  • Synthetic frequency sources include direct analog frequency sources, direct digital frequency sources, indirect analog frequency sources, and indirect digital frequency sources.
  • the frequency source 200 may include an ordinary crystal oscillator (XO), a temperature-compensated crystal oscillator (TCXO), and a constant-temperature crystal oscillator (OCXO).
  • XO ordinary crystal oscillator
  • TCXO temperature-compensated crystal oscillator
  • OCXO constant-temperature crystal oscillator
  • clock synchronization techniques may include synchronization time detection, remote clock estimation, and local clock calibration.
  • the formula for the synchronization time accuracy of electronic equipment can be expressed as:
  • ⁇ indicates the synchronization time accuracy
  • ⁇ indicates the uncertainty of the transmission delay when reading the remote clock
  • G1 indicates the clock drift (that is, the frequency drift of the crystal oscillator)
  • G2 indicates the read clock granularity
  • u indicates the adjustment granularity ratio
  • Gs indicates Clock setting granularity.
  • C 1 , C 2 , C 3 , C 4 and C 5 represent weight factors.
  • G2, u, and Gs are all directly or indirectly related to the initial frequency f c of the input signal generated by the frequency source.
  • the frequency drift of the crystal source has an influence on the synchronization time accuracy, and the frequency drift of the crystal source is usually caused by the working ambient temperature and the aging of the device. Therefore, it is necessary to compensate the influence of the frequency drift of the crystal oscillator on the target frequency of the output signal, thereby improving the synchronization time accuracy.
  • the frequency control word can be used to control the target frequency of the output signal. Therefore, the frequency control word can be changed according to the frequency drift of the crystal oscillator source, so as to achieve compensation for the target frequency of the output signal.
  • control circuit 11 is configured to obtain an influence parameter of the crystal drift, and generate a frequency control word according to the influence parameter.
  • the frequency control word can be changed according to the influence parameter of the crystal drift.
  • the influence parameter of the crystal drift changes, the frequency control word changes accordingly.
  • the input signal and output signal are both pulse signals.
  • the frequency control word is used to control the target frequency of the output signal.
  • the signal adjustment circuit 12 may generate an output signal according to the frequency control word and the initial frequency of the input signal, and make the frequency of the generated output signal a target frequency, thereby meeting the accuracy requirements of time synchronization of different devices. For example, for the same initial frequency, when the frequency control word changes, the target frequency also changes accordingly, so that input signals with the same initial frequency can be converted into output signals with different target frequencies to meet the needs of different electronic devices.
  • the signal generation circuit 100 further includes a parameter acquisition circuit 13.
  • the parameter acquisition circuit 13 is configured to detect an influence parameter of the crystal oscillator drift, thereby compensating for an influence of the influence parameter of the crystal oscillator drift on the target frequency of the output signal.
  • the initial frequency of the input signal generated by the frequency source is different under different conditions.
  • factors that affect crystal drift can include ambient temperature and frequency source aging.
  • the frequency error of the initial frequency can reach ⁇ 10 ppm. Due to the influence of the aging of the frequency source, the frequency error of the initial frequency of the input signal generated by the frequency source increases with time and gradually accumulates.
  • the signal adjustment circuit 12 may generate a compensated output signal according to the frequency control word.
  • the target frequency of the output signal is closer to or even equal to the frequency preset by the user, so as to compensate for the error of the target frequency of the output signal due to the influence parameter of the crystal drift. Therefore, the signal generating circuit 100 provided by at least one embodiment of the present disclosure can implement frequency compensation of the output signal without changing the physical structure of the frequency source, correct the frequency error of the output signal, and improve the time of each device in the network system. Accuracy of synchronization.
  • the initial frequency of the input signal generated by the frequency source may have a fixed manufacturing error, thereby affecting the target frequency of the output signal. Therefore, the factors affecting the crystal oscillator drift may also include manufacturing errors and the like, which is not limited in this disclosure.
  • the parameters of the crystal drift include the temperature parameter T 0 .
  • the parameter acquisition circuit 13 includes a temperature detection sub-circuit 131.
  • the temperature detection sub-circuit 131 is configured to detect a temperature parameter T 0 to compensate for an error in a target frequency of an output signal due to an ambient temperature.
  • the temperature detection sub-circuit 131 may include a temperature detector and a first counter.
  • the temperature detector is configured to detect an ambient temperature
  • the temperature parameter T 0 may include the ambient temperature.
  • the first counter is configured to record the amount of frequency change according to the ambient temperature and the reference temperature.
  • the relationship between the temperature parameter and the frequency change amount is non-linear, but is not limited to this.
  • a special temperature sensor may also output a linear proportional relationship between the temperature parameter and the frequency change amount.
  • the relationship between the temperature parameter and the amount of frequency change can be expressed as:
  • ⁇ f represents the frequency change amount
  • r, p, d, and g are all constants
  • ⁇ T the difference between the ambient temperature and the reference temperature
  • ⁇ T T1-T2
  • T1 represents the ambient temperature
  • T2 represents the reference temperature
  • n is a positive integer
  • the reference temperature may also be other values, which is not limited in the present disclosure.
  • the values of the temperature coefficients r, p, d, and g can be specifically set according to the actual situation.
  • the number of temperature coefficients in the above-mentioned relationship is related to n. If the relationship between the temperature parameter and the frequency change is a second-order nonlinear relationship, then n is 2. At this time, the relationship between the temperature parameter and the frequency change can be expressed as:
  • the amount of frequency change represents the amount of change in the target frequency of the output signal generated by the signal conditioning circuit 12, that is, the amount of frequency change can be expressed as:
  • f1 represents the target frequency of the output signal at the current ambient temperature
  • f2 represents the target frequency of the output signal at the reference temperature
  • the relationship between the frequency control word and the frequency change can be expressed as:
  • F N represents a frequency control word
  • F TO represents a reference frequency control word corresponding to a reference temperature (that is, a frequency control word at a reference temperature)
  • f ⁇ represents a frequency in a reference time unit.
  • the reference frequency control word F TO can be detected in advance and stored in the memory of the electronic device.
  • the control circuit may be configured to generate a frequency control word based on the ambient temperature based on equation (1).
  • the ambient temperature can be detected by a temperature detector, and the temperature parameter can be fed back to the control circuit 11 in real time.
  • the control circuit 11 can adjust the frequency control word according to the temperature parameter in real time so Compensates the frequency error of the target frequency of the output signal due to temperature.
  • the influence parameters of the crystal drift include the aging parameter A 0 .
  • the parameter acquisition circuit 13 may include an aging read sub-circuit 132.
  • the aging read sub-circuit 132 is configured to read the aging parameter A 0 of the crystal source to compensate for the error of the target frequency of the output signal due to the aging of the frequency source.
  • the aging read sub-circuit 132 may include a aging reading element and a second counter.
  • the aging read element is configured to read the aging rate of the crystal oscillator source and read a reference time corresponding to the aging rate of the crystal oscillator source, and the aging parameters include the aging rate and the reference time.
  • the second counter is configured to record the number of reference times.
  • the aging rate is determined by the properties of the crystal oscillator itself. In the process of using the crystal oscillator source, the aging rate can be considered as a fixed value.
  • the aging rate can be provided by the manufacturer producing the crystal oscillator, and the aging rate can be stored in the memory of the electronic device. When the parameter of the aging rate is required, the aging reading element reads directly from the memory of the electronic device.
  • the aging rate of a crystal oscillator can be expressed in ppm (parts per million) or ppb (parts per billion). For example, if the aging rate of a crystal source is ⁇ 5ppm / year, It means that the error value of the frequency of the signal generated by the crystal source within one year is within ⁇ 5ppm; if the aging rate of the crystal source is ⁇ 1ppm / mouth, it means that the error value of the frequency of the signal generated by the crystal source within one month is within ⁇ 1ppm .
  • the reference time is related to the aging rate. If the unit of the aging rate of the crystal source is years, for example, the aging rate of the crystal source is ⁇ 5ppm / year, the reference time is one year; and if the unit of the aging rate of the crystal source is a unit The time is month. For example, if the aging rate of the crystal source is ⁇ 1ppm / month, the reference time is January.
  • the relationship between the frequency control word and the aging parameter can be expressed as:
  • F N represents the frequency control word
  • F AO represents the reference frequency control word
  • the reference frequency control word F AO may indicate a frequency control word corresponding to a frequency source when used for the first time, and the reference frequency control word F AO may be detected in advance and stored in a memory of the electronic device.
  • the control circuit may be configured to generate a frequency control word based on the aging rate based on equation (2).
  • the unit time of the aging rate is year, that is, if the reference time is one year, when the frequency source 200 is used for less than one year, t is 0; when the frequency source 200 is used for more than one year and For less than two years, t is 1, and so on.
  • the aging read sub-circuit 132 may transmit the aging parameter A 0 to the control circuit 11 at predetermined intervals, thereby performing aging correction on the frequency control word.
  • the scheduled time can be 10 days, one month, one year, and so on.
  • the predetermined time may be the same as the reference time. For example, if the reference time is one year, the predetermined time may also be one year, that is, the frequency control word is subjected to aging correction once every one year.
  • the parameter acquisition circuit 13 may include a temperature detection sub-circuit 131 and an aging read sub-circuit 132 at the same time, so as to simultaneously compensate the influence of the ambient temperature and the frequency source aging on the output signal.
  • the control circuit 11 may include a calculation sub-circuit 111 and an output sub-circuit 112.
  • the calculation sub-circuit 111 is configured to obtain an influence parameter of the crystal oscillator drift (for example, the influence parameter includes an aging parameter A 0 and a temperature parameter T 0, etc.) from the parameter acquisition circuit 13, and generate a frequency control word F according to the influence parameter of the crystal oscillator drift.
  • the output sub-circuit 112 is configured to output the frequency control word F to the signal conditioning circuit 12.
  • the calculation sub-circuit 111 may calculate a frequency control word according to the foregoing formula (1) and / or formula (2).
  • the output sub-circuit 112 may output the frequency control word F calculated by the calculation sub-circuit 111 to the signal conditioning circuit 12 under the control of a clock signal.
  • control circuit 11 may be implemented using a hardware circuit.
  • the calculation sub-circuit 111 and the output sub-circuit 112 may be implemented using a hardware circuit.
  • the calculation sub-circuit 111 may be constituted by, for example, a transistor, a resistor, a capacitor, and an amplifier.
  • the output sub-circuit 112 may be configured using, for example, a flip-flop.
  • the functions of the control circuit 11 can also be implemented by software.
  • the functions of the calculation sub-circuit 111 and the output sub-circuit 112 may also be implemented by software.
  • the instructions and data stored in the memory may be executed by the processor to implement the functions of the calculation sub-circuit 111 and the output sub-circuit 112.
  • the signal adjustment circuit 12 may include a reference time unit generation sub-circuit 121 and a frequency adjustment sub-circuit 122.
  • the reference time unit generating sub-circuit 121 is configured to receive an input signal having an initial frequency f c and generate and output a reference time unit ⁇ according to the initial frequency.
  • the frequency adjustment sub-circuit 122 is configured to generate and output an output signal having a target frequency f TAF-DPS based on the frequency control word F and the reference time unit ⁇ .
  • FIG. 6A shows a schematic structural diagram of a reference time unit generation sub-circuit provided by at least one embodiment of the present disclosure
  • FIG. 6B shows a schematic diagram of another reference time unit generation sub-circuit provided by at least one embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of K reference output signals with evenly spaced phases provided by at least one embodiment of the present disclosure.
  • the reference time unit generating sub-circuit 121 is configured to generate and output K reference output signals with evenly spaced phases and reference time units according to the initial frequency.
  • the reference time unit generating sub-circuit 121 may include a phase locked loop (PLL) or a delay locked loop (DLL).
  • PLL phase locked loop
  • DLL delay locked loop
  • the reference time unit generation sub-circuit 121 may include a PLL.
  • the reference time unit generating sub-circuit 121 may include a voltage-controlled oscillator (VCO) 1211, a first phase-locked loop circuit 1212, and K output terminals 1213.
  • the voltage-controlled oscillator 1211 is configured to oscillate at a predetermined oscillation frequency;
  • the first phase-locked loop circuit 1212 is configured to lock the output frequency of the voltage-controlled oscillator 1211 to a reference output frequency;
  • K output terminals 1213 are configured to output K
  • the reference time unit can be expressed as ⁇ , and the reference output frequency can be expressed as f d .
  • the reference time unit ⁇ is a time span between any two adjacent output signals output by the K output terminals 1213.
  • the reference time unit ⁇ is usually generated by a multi-stage voltage controlled oscillator 1211.
  • the reference time unit ⁇ can be calculated using the following formula:
  • T d represents a period of a signal generated by the multi-stage voltage controlled oscillator 1211.
  • the first phase-locked loop circuit 1212 includes a phase detector (PFD), a loop filter (LPF), and a frequency divider (N).
  • PFD phase detector
  • LPF loop filter
  • N frequency divider
  • an input signal having an initial frequency may be input to a phase detector, then into a loop filter, then into a voltage-controlled oscillator, and finally, the voltage-controlled oscillator generates a predetermined oscillation frequency.
  • the signal of f vco can be divided by a frequency divider to obtain the divided frequency f vco / N of the divided signal.
  • the divided frequency f vco / N is fed back to the phase detector.
  • the phase detector is used to compare the initial frequency f of the input signal.
  • the loop filter may be a low-pass filter.
  • the frequency division coefficient of the frequency divider is N, N is a real number, and N is greater than or equal to 1.
  • the reference output frequency f d is related to the initial frequency f c .
  • the reference time unit generating sub-circuit 121 may include a DLL.
  • DLL can be realized by CMOS technology, so DLL can be easily integrated into any chip and circuit, which reduces the cost of signal generation circuit and improves efficiency.
  • the reference time unit generating sub-circuit 121 includes a voltage-controlled delay circuit 1214, a second phase-locked loop circuit 1215, and K output terminals 1213.
  • the voltage-controlled delay unit 1214 may include one or more cascaded delay units, and is configured to generate a delay signal according to an input signal and an output signal of the second phase-locked loop circuit 1215; the second phase-locked loop circuit 1215 Is configured to lock the output frequency of the voltage-controlled delay device 1214 to the reference output frequency according to the input signal and the delay signal; the K output terminals 1213 are configured to output K output signals with evenly spaced phases, where K is a positive integer greater than 1 .
  • the second phase-locked loop circuit 1215 may include a phase detector (PFD), a charge pump (not shown), a loop filter (LPF), and the like.
  • the phase detector is used to detect a phase difference between the initial frequency f c of the input signal and the frequency f db of the feedback delayed signal, and output the phase difference to a charge pump; the charge pump is used to output and phase difference according to the phase difference
  • the proportional voltage signal is output to the loop filter.
  • the loop filter is used to filter the higher harmonics of the voltage signal, so as to obtain the control voltage Vcom for controlling the voltage-controlled retarder 1214.
  • the delay unit may include a two-to-one multiplex gate (MUX2_1) and the like.
  • the delay time of the delay unit can be changed with the control voltage Vcom.
  • the control voltage of the delay unit is Vcom
  • the delay time is Tvcol
  • Vcom is proportional to Tvcol.
  • the reference output frequency is expressed as f d and the reference time unit is expressed as ⁇ .
  • the time granularity of the input signal is 1 / f d .
  • an output signal having a target frequency f TAF-DPS can be obtained, and the output signal
  • the time granularity is ⁇ , which is 1 / (K ⁇ f d ), K is a positive integer greater than 1, the time granularity of the output signal 1 / (K ⁇ f d ) is smaller than the time granularity of the input signal 1 / f d , and The time synchronization accuracy of the electronic equipment of the signal generating circuit is higher, and the work coordination is better.
  • an output signal is obtained.
  • the time granularity of the output signal is ⁇ , and the frequency granularity is 1 / (K ⁇ f c ).
  • ⁇ can be very small.
  • K is 1024
  • ⁇ can be 48.8ps. Therefore, the time granularity of the output signal is 48.8ps, and the frequency granularity of the output signal is 4.9 ⁇ 10 -11 . Therefore, compared with the input
  • the time granularity and frequency granularity of signals and output signals are all increased by K (ie 1024) times.
  • the signal generation circuit of the present disclosure can obtain an output signal after adjusting the input signal. Since the target frequency of the output signal is greater than the initial frequency of the input signal, both the time granularity and the frequency granularity of the output signal are improved.
  • circuit structure shown in FIG. 6A and FIG. 6B is only an exemplary implementation manner of the reference time unit generating sub-circuit 121.
  • the specific structure of the reference time unit generating sub-circuit 121 is not limited to this, and it can also be constructed by other circuit structures, which is not limited in this disclosure.
  • FIG. 8 shows a schematic block diagram of a frequency regulator circuit provided by at least one embodiment of the present disclosure
  • FIG. 9 shows a schematic diagram of a working principle of a frequency regulator circuit provided by at least one embodiment of the present disclosure.
  • the frequency adjustment sub-circuit 122 includes a first input module 1221, a second input module 1222, and an output module 1223.
  • the first input module 1221 is configured to receive the K phase-equally spaced reference output signals and the reference time unit from the reference time unit generation sub-circuit 121.
  • the second input module 1222 is configured to receive a frequency control word from the control circuit 11.
  • the output module 1223 is configured to generate and output an output signal having a target frequency that matches a frequency control word and a reference time unit.
  • the frequency adjustment sub-circuit 122 may include a time-averaged frequency direct period synthesizer (TAF-DPS synthesizer).
  • TAF-DPS Time-Average-Frequency Direct Period Synthesis
  • TAF-DPS time-Average-Frequency Direct Period Synthesis
  • the output frequency of the TAF-DPS synthesizer can be changed instantaneously, that is, it has the rapidity of frequency switching. The experiment proves that the frequency granularity of the TAF-DPS synthesizer can reach several ppb (parts per billion).
  • TAF-DPS synthesizer Being able to generate any frequency and being able to switch frequencies quickly are the main advantages of TAF-DPS synthesizers over conventional frequency sources.
  • the TAF-DPS synthesizer can be used as a specific implementation of the frequency adjusting sub-circuit 122 in the embodiment of the present disclosure.
  • the advantages of the signal generating circuit include, but are not limited to:
  • the TAF-DPS-based frequency compensator can be completely digitally designed and burned into a programmable logic device (for example, FPGA) through HDL coding.
  • the parameters of the frequency compensator can also be easily reset at any time. Therefore, the function of the frequency compensator can be realized without using a special dedicated circuit, and using a general FPGA or other programmable devices.
  • ASIC can also be used to implement the function of the frequency compensator.
  • the frequency / period of the pulse signal output by TAF-DPS can be precisely controlled, and its frequency resolution can reach one billion fractions, which can effectively improve the time synchronization accuracy.
  • a TAF-DPS synthesizer can be implemented using a programmable logic device (eg, an ASIC or FPGA).
  • the TAF-DPS synthesizer can be implemented using conventional analog circuit devices. The disclosure is not limited herein.
  • the frequency adjustment sub-circuit 122 based on the TAF-DPS synthesizer 510 has two inputs: a reference time unit 520 and a frequency control word 530.
  • the TAF-DPS synthesizer 510 has one output CLK 550.
  • the CLK 550 is a synthesized time average frequency clock signal.
  • the CLK 550 is an output signal having a target frequency.
  • the output CLK 550 is a clock pulse train 540, and the clock pulse train 540 is composed of a first period T A 541 and a second period T B 542 in an interleaved manner.
  • the score r is used to control the appearance probability of the second period T B. Therefore, r can also determine the appearance probability of the first period T A.
  • the period T TAF-DPS of the output signal CLK 550 can be expressed by the following formula:
  • T TAF-DPS (1-r) ⁇ T A + r ⁇ T B
  • T TAF-DPS F ⁇ ⁇ (4)
  • the period T TAF-DPS of the output signal CLK output by the TAF-DPS synthesizer 510 is linearly proportional to the frequency control word 530.
  • the frequency control word 530 changes, the period T TAF-DPS of the output signal output by the TAF-DPS synthesizer 510 will also change in the same form.
  • the target frequency of the output signal can also follow approximately linearly.
  • the waveform of the frequency control word (F) changes.
  • the control circuit 11 can generate a frequency control word according to the influence parameter of the crystal oscillator drift, and then the TAF-DPS synthesizer 510 generates an output signal having a target frequency according to the frequency control word.
  • the target frequency corresponds to the frequency control word, and the frequency control word is adjusted by adjusting the frequency control word.
  • the target frequency can be adjusted.
  • the target frequency is expressed as:
  • f TAF-DPS represents the target frequency
  • F represents the frequency control word
  • the frequency adjustment sub-circuit may be configured to determine a target frequency based on the formula based on a frequency control word and a reference time unit.
  • FIG. 10A is a schematic structural diagram of a frequency regulator circuit provided by at least one embodiment of the present disclosure
  • FIG. 10B is a schematic structural diagram of another frequency regulator circuit provided by at least one embodiment of the present disclosure.
  • the first input module 1221 includes a K ⁇ 1 multiplexer 711.
  • the K ⁇ 1 multiplexer 711 has a plurality of input terminals, control input terminals, and output terminals for receiving K reference output signals with evenly spaced phases.
  • the output module 1223 includes a trigger circuit 730.
  • the trigger circuit 730 is used to generate a pulse train.
  • the pulse train is composed of, for example, a pulse signal of a first period T A and a pulse signal of a second period T B in an interleaved manner.
  • the trigger circuit 730 includes a D flip-flop, an inverter, and an output terminal.
  • the D flip-flop includes a data input terminal, a clock input terminal for receiving an output from an output terminal of the K ⁇ 1 multiplexer 711, and an output terminal for outputting a first clock signal CLK1.
  • the inverter includes an inverter input terminal for receiving a first clock signal CLK1 and an inverter output terminal for outputting a second clock signal CLK2.
  • An output terminal of the trigger circuit 730 is configured to output a first clock signal CLK1 as an output signal S out having a target frequency.
  • the first clock signal CLK1 includes a burst.
  • the second clock signal CLK2 is connected to a data input terminal of the D flip-flop.
  • the second input module 1222 includes a logic control circuit 740.
  • the logic control circuit 740 includes an input terminal for receiving a frequency control word F output from the control circuit 11, a clock input terminal for receiving a first clock signal CLK1, and a K ⁇ 1 multiplexer connected to the first input module 1221. Output of the control input.
  • the first input module 1221 includes a first K ⁇ 1 multiplexer 721, a second K ⁇ 1 multiplexer 723, and a 2 ⁇ 1 multiplexer.
  • Multiplexer 725 The first K ⁇ 1 multiplexer 721 and the second K ⁇ 1 multiplexer 723 respectively include a plurality of input terminals, control input terminals, and output terminals for receiving K signals with evenly spaced phases.
  • the 2 ⁇ 1 multiplexer 725 includes a control input terminal, an output terminal, a first input terminal for receiving the output of the first K ⁇ 1 multiplexer 721, and a second K ⁇ 1 multiplexer for receiving the output.
  • the output module 1223 includes a trigger circuit.
  • the trigger circuit is used to generate a burst.
  • the trigger circuit includes a D flip-flop 761, an inverter 763, and an output terminal 762.
  • the D flip-flop 761 includes a data input terminal, a clock input terminal for receiving an output from the output terminal of the 2 ⁇ 1 multiplexer 725, and an output terminal for outputting the first clock signal CLK1.
  • the inverter 763 includes an input terminal for receiving a first clock signal CLK1 and an output terminal for outputting a second clock signal CLK2.
  • the output terminal 762 of the trigger circuit is used to output the first clock signal CLK1 as an output signal S out having a target frequency.
  • the first clock signal CLK1 is connected to the control input terminal of the 2 ⁇ 1 multiplexer 725, and the second clock signal CLK2 is connected to the data input terminal of the D flip-flop 761.
  • the second input module 1222 includes a first logic control circuit 70 and a second logic control circuit 74.
  • the first logic control circuit 70 includes a first adder 701, a first register 703, and a second register 705.
  • the second logic control circuit 74 includes a second adder 741, a third register 743, and a fourth register 745.
  • the first adder 701 adds the frequency control word (F) and the most significant bits (for example, 5 bits) stored in the first register 703, and then adds the result at the rising edge of the second clock signal CLK2 Save to the first register 703; or, the first adder 701 adds the frequency control word (F) and all the information stored in the first register 703, and then saves the addition result at the rising edge of the second clock signal CLK2 Into the first register 703.
  • the most significant bit stored in the first register 703 will be stored in the second register 705 and used as the selection signal of the first K ⁇ 1 multiplexer 721 for One signal is selected from the K multi-phase input signals as the first output signal of the first K ⁇ 1 multiplexer 721.
  • the second adder 741 adds the frequency control word (F) and the most significant bit stored in the first register 703, and then saves the addition result in the third register 743 at the rising edge of the second clock signal CLK2. At the rising edge of the next first clock signal CLK1, the information stored in the third register 743 will be stored in the fourth register 745 and used as the selection signal of the second K ⁇ 1 multiplexer 723 for One of the multi-phase input signals is selected as the second output signal of the second K ⁇ 1 multiplexer 723.
  • 2 ⁇ 1 multiplexer 725 selects the first output signal from the first K ⁇ 1 multiplexer 721 and the second K ⁇ 1 multiplexer at the rising edge of the first clock signal CLK1
  • One of the second output signals of 723 is used as an output signal of the 2 ⁇ 1 multiplexer 725 as an input clock signal of the D flip-flop 761.
  • the period (T TAF-DPS ) of the output signal S out output by the TAF-DPS synthesizer shown in FIGS. 10A and 10B can be calculated by the above formula (4).
  • FIG. 11 shows a schematic block diagram of a time synchronization system provided by at least one embodiment of the present disclosure
  • FIG. 12 shows a time synchronization system based on a network time synchronization protocol NTP to perform time provided by at least one embodiment of the present disclosure Schematic of synchronization.
  • the time synchronization system 60 may include multiple electronic devices. At least one of the plurality of electronic devices is the electronic device according to any one of the above.
  • the signal generation circuit of the electronic device can generate an output signal with a target frequency; the time adjustment circuit of the electronic device can perform synchronous adjustment operations on the clock signal of the electronic device based on the output signal with the target frequency, thereby synchronizing the network time of the electronic device Higher accuracy.
  • each electronic device in the time synchronization system 60 may be an electronic setting according to any one of the above embodiments, so that each electronic device in the time synchronization system 60 may adjust its clock based on an output signal having a target frequency. Signal to synchronize multiple electronic devices in the time synchronization system 60. Because the target frequency of the output signal is greater than the initial frequency of the input signal output by the original frequency source, the time synchronization accuracy of multiple electronic devices in the time synchronization system 60 is high, and the work consistency and coordination of each electronic device is better.
  • the time synchronization system 60 includes two electronic devices, and is a first electronic device 61 and a second electronic device 62, respectively.
  • the first electronic device 61 may be located on the client, and the second electronic device 62 may be located on the server.
  • the first electronic device 61 is configured to send a first network packet to the second electronic device 62 at a first time stamp.
  • the first network message is accompanied by time information of the first electronic device 61 at a first time stamp.
  • the time on the first electronic device 61 is T1, so that the first network packet includes the time T1, the time on the second electronic device 62 is T1 + d1, and d1 is the first electronic device 61 and the first
  • the synchronization time error between the two electronic devices 62 is due to the position difference between the first electronic device 61 and the second electronic device 62, and the second electronic device 62 receives the first network packet at a second time stamp.
  • the time on the second electronic device 62 is T2, and at this time, the time on the first electronic device 61 is T2-d1.
  • the second electronic device 62 After a time delay of the internal system of the second electronic device 62, the second electronic device 62 outputs a second network packet to the first electronic device 61 at a third time stamp.
  • the second network message is accompanied by the time information of the second electronic device 62 at the second time stamp, the time signal of the second electronic device 62 at the third time stamp, and the first electronic device 61 included in the first network message. Time information for the first timestamp.
  • the time on the second electronic device 62 is T3, and the time on the first electronic device 61 is T3-d1. Therefore, the second network message includes time T1, time T2, and time T3.
  • the first electronic device 61 accepts the second network message at the fourth timestamp.
  • the first electronic device 61 may calculate a time deviation between the first electronic device 61 and the second electronic device 62 according to the times T1, T2, T3, and T4, thereby adjusting the clock signal of the first electronic device 61 to obtain A synchronous clock signal of the first electronic device 61.
  • the synchronized clock signal of the first electronic device 61 indicates a clock signal synchronized with the second electronic device 62, that is, the synchronized clock signal is synchronized with the clock signal of the second electronic device 62.
  • the accuracy of the synchronization clock signal of the first electronic device 61 is positively related to the value of the target frequency of the output signal output by the signal generating circuit of the first electronic device 61.
  • the synchronization clock of the first electronic device 61 The higher the accuracy of the signal. For example, if the target frequency is 100 Hz, the time granularity (ie, synchronization accuracy) of the synchronization clock signal of the first electronic device 61 may be 0.01 s.
  • d2 may represent the one-way average delay time consumed by a network message transmitted between the first electronic device 61 and the second electronic device 62, and d2 may be expressed as:
  • d21 (hereinafter referred to as the first transmission delay time) may represent a transmission delay time during the transmission of the first network packet from the first electronic device 61 to the second electronic device 62
  • d22 (below (Represented as the second transmission delay time) can represent the transmission delay time during the transmission of the second network packet from the second electronic device 62 to the first electronic device 61
  • the synchronization time error d1 can be expressed as:
  • the synchronization time error d1 can be expressed as:
  • the time of the first electronic device 61 differs from the time of the second electronic device 62 by [(T2-T1) + (T3-T4)] / 2.
  • the network packet is transmitted unidirectionally.
  • the corrected time error is 1 hour.
  • the first transmission delay time d21 and the second transmission delay time d22 may also be different, that is, d21 and d22 are not equal.
  • the network time synchronization NTP protocol may include a client / server mode, a peer mode, a broadcast mode, a multicast mode, and the like. Under different working modes, the time synchronization modes of electronic devices are different, and this disclosure does not limit this. For example, in the above example, the time T3 is 11:00:02.
  • the time T4 of the first electronic device 61 can be directly updated to T3 + d2 (1s) is enough, that is, at the fourth time stamp, the clock signal of the first electronic device 61 is 11:00:03, and the clock signal of the second electronic device 62 is 11:00:03. That is, the clock signal of the first electronic device 61 is synchronized with the clock signal of the second electronic device 62.
  • the first electronic device 61 needs to adjust its clock signal to achieve time synchronization with the second electronic device 62.
  • the first electronic device 61 can correct the time error between it and the second electronic device 62, and the corrected time is 0.07s, so that the first electronic device The time of the device 61 and the second electronic device 62 are completely synchronized.
  • the time granularity of the output signal of the first electronic device 61 is 0.02s.
  • the first electronic device 61 cannot completely correct the time error between it and the second electronic device 62.
  • the time that the first electronic device 61 can correct is 0.06s.
  • the time between the first electronic device 61 and the second electronic device 62 is The corrected time error is 0.01s. If the time error threshold between the first electronic device 61 and the second electronic device 62 is 0.02 s, and the corrected time error is less than the time error threshold, the clock signal of the first electronic device 61 after the correction satisfies the time of the time synchronization system. Synchronization requirements.
  • FIG. 13 shows a schematic flowchart of a time synchronization method according to at least one embodiment of the present disclosure.
  • the time synchronization method provided by at least one embodiment of the present disclosure may be applied to a time synchronization apparatus according to any embodiment of the present disclosure.
  • the time synchronization method may include the following steps:
  • S12 Generate and output an output signal having a target frequency according to the frequency control word and the input signal;
  • the time synchronization method provided by the embodiment of the present disclosure can synthesize an output signal with a sufficiently large target frequency, that is, the frequency granularity of the output signal is high, so that each electronic device obtains a more accurate synchronized clock, and the work coordination of each electronic device in the network system Better sex and consistency.
  • step S11 may include: detecting an influence parameter of the crystal oscillator drift through a parameter acquisition circuit; generating a frequency control word according to the influence parameter of the crystal oscillator drift; and outputting the frequency control word to a signal conditioning circuit.
  • step S12 may include: receiving an input signal having an initial frequency, generating and outputting a reference time unit based on the input signal having the initial frequency; and generating and outputting an output signal having a target frequency according to the frequency control word and the reference time unit.
  • an output signal with a target frequency can be generated by a TAF-DPS synthesizer.
  • step S11 and step S12 may be implemented by a signal generating circuit in the time synchronization device according to any embodiment of the present disclosure, and step S13 may be performed by time adjustment in the time synchronization device according to any embodiment of the present disclosure.
  • the circuit is implemented, and similar operations or steps are not repeated here.
  • step S13 after synchronizing and adjusting the clock signal of the electronic device, the synchronous clock signal of the electronic device and the rest of the electronic devices in the time synchronization system can be obtained, and the accuracy of the synchronous clock signal and the output signal generated by the electronic device can be obtained.
  • the value of the target frequency is positively correlated.
  • the time synchronization system may include a first electronic device and a second electronic device.
  • the time synchronization method may include the following steps:
  • the first electronic device sends a first network message to the second electronic device.
  • the time on the first electronic device is T1
  • the first network message includes time T1.
  • the second electronic device receives the first network packet. At this time, the time on the second electronic device is T2;
  • the second electronic device sends a second network message to the first electronic device.
  • the time on the second electronic device is T3, and the second network message includes time T1 and time T2.
  • the first electronic device receives the second network packet. At this time, the time on the first electronic device is T4;
  • S25 Calculate a synchronization time error between the first electronic device and the second electronic device according to the times T1, T2, T3, and T4;
  • S26 Perform a synchronous adjustment operation on the clock signal of the first electronic device based on the output signal with the target frequency generated by the first electronic device to eliminate the synchronization time error.
  • step S26 if the target frequency of the output signal generated by the first electronic device is f, and the synchronization time error between the first electronic device and the second electronic device is ⁇ T, and ⁇ T> 1 / f, the first An electronic device can better correct the synchronization time error, so that the time of the first electronic device and the second electronic device can be synchronized.
  • step S26 may include steps S11-S13.
  • time synchronization method shown in FIG. 13 may be implemented by the time synchronization system described in any embodiment of the present disclosure, and similar operations or steps are not repeated here.

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Abstract

一种用于电子设备的时间同步装置(1000)、电子设备(50)、时间同步系统(60)和时间同步方法。该时间同步装置(1000)包括：信号生成电路(100)和时间调节电路(150)。信号生成电路(100)包括：控制电路(11)，被配置为生成频率控制字(F)；信号调节电路(12)，被配置为接收具有初始频率的输入信号和所述频率控制字(F)，并根据所述频率控制字(F)和所述输入信号生成并输出具有目标频率的输出信号。时间调节电路(150)被配置为基于具有所述目标频率的输出信号对所述电子设备的时钟信号进行同步调节操作。该时间同步装置(1000)可以通过信号生成电路(100)合成频率足够大的输出信号，输出信号的频率粒度较高，从而使电子设备获得更精准的同步时钟，电子设备在网络系统中的工作协调性和一致性更好。

Description

时间同步装置、电子设备、时间同步系统及时间同步方法
相关申请的交叉引用
本申请要求于2018年6月11日递交的第201810596413.9号中国专利申请的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种时间同步装置、电子设备、时间同步系统和时间同步方法。
背景技术
在分布式网络信息时代，为了使网络系统中的各个设备实现工作协调一致，信息传输无误，在许多行业中，例如信息技术(information technology，IT)行业的“整点开拍”、“领袖选举”，金融行业的“股市开盘收盘”，通信行业的“同步组网”等业务处理，网络系统中的各个设备的时钟同步十分重要。网络时钟同步技术的关键在于各设备的本地时钟的频率，若该时钟的频率越大，则从网络中同步到本地的时间精度越高，各个设备之间的工作协调性和一致性更好。
发明内容
本公开至少一实施例提供一种用于电子设备的时间同步装置，包括：信号生成电路和时间调节电路。信号生成电路包括控制电路和信号调节电路，控制电路被配置为生成频率控制字；信号调节电路被配置为接收具有初始频率的输入信号和所述频率控制字，并根据所述频率控制字和所述输入信号生成并输出具有目标频率的输出信号。所述时间调节电路被配置为基于具有所述目标频率的输出信号对所述电子设备的时钟信号进行同步调节操作。
例如，在本公开至少一实施例提供的时间同步装置中，所述控制电路被配置为根据晶振漂移的影响参数生成所述频率控制字。
例如，在本公开至少一实施例提供的时间同步装置中，信号生成电路还包括参数获取电路，所述参数获取电路被配置为获取所述影响参数。
例如，在本公开至少一实施例提供的时间同步装置中，所述晶振漂移的影响参数包括温度参数，所述参数获取电路包括温度检测子电路；所述温度检测子电路被配置为检测所述温度参数。
例如，在本公开至少一实施例提供的时间同步装置中，所述温度检测子电路包括温度检测器和第一计数器，所述温度检测器被配置为检测环境温度，所述温度参数包括所述环境温度，所述第一计数器被配置为根据所述环境温度和参考温度记录频率变化量。
例如，在本公开至少一实施例提供的时间同步装置中，所述控制电路被配置为基于下式根据所述环境温度生成所述频率控制字：
Figure PCTCN2019082926-appb-000001
其中，F N表示所述频率控制字，F TO表示与所述参考温度对应的参考频率控制字，f Δ表示基准时间单位的频率，以及
Δf＝r·ΔT n+p·ΔT n-1+...+d·ΔT+g
其中，Δf表示所述频率变化量，r、p、d和g为常数，ΔT表示所述环境温度和所述参考温度的差值，ΔT＝T1-T2，T1表示所述环境温度，T2表示所述参考温度，n为正整数。
例如，在本公开至少一实施例提供的时间同步装置中，所述晶振漂移的影响参数包括老化参数，所述参数获取电路包括老化读取子电路；所述老化读取子电路被配置为读取晶振源的所述老化参数。
例如，在本公开至少一实施例提供的时间同步装置中，所述老化读取子电路包括老化读取元件和第二计数器，所述老化读取元件被配置为读取所述晶振源的老化速率，以及读取与所述老化速率相对应的参考时间，所述老化参数包括所述老化速率和所述参考时间，所述第二计数器被配置为记录所述参考时间的数量。
例如，在本公开至少一实施例提供的时间同步装置中，所述控制电路被配置为基于下式根据所述老化速率生成所述频率控制字：
F N＝F AO·(1+γ)
其中，F N表示所述频率控制字，F AO表示参考频率控制字，γ表示所述老化参数的乘积，其中，γ＝ν·t，ν表示所述老化速率，t表示所述参考时间的数量，且t为自然数。
例如，在本公开至少一实施例提供的时间同步装置中，所述信号调节电路包括基准时间单位生成子电路和频率调节子电路，基准时间单位生成子电路被配置为接收具有所述初始频率的所述输入信号，并根据所述初始频率生成并输出基准时间单位；频率调节子电路被配置为根据所述频率控制字和所述基准时间单位生成并输出具有所述目标频率的所述输出信号。
例如，在本公开至少一实施例提供的时间同步装置中，所述基准时间单位生成子电路包括：压控振荡器，被配置为以预定振荡频率振荡；第一锁相环回路电路，被配置为将所述压控振荡器的输出频率锁定为基准输出频率；K个输出端，被配置为输出K个相位均匀间隔的输出信号，其中，K为大于1的正整数，所述基准输出频率表示为f d，所述基准时间单位是所述K个输出端输出的任意两个相邻的输出信号之间的时间跨度，所述基准时间单位表示为△，并且△＝1/(K·f d)。
例如，在本公开至少一实施例提供的时间同步装置中，所述基准时间单位生成子电路包括：压控延迟器、第二锁相环回路电路和K个输出端，所述压控延迟器包括一个或者多个级联的延时单元，且被配置为根据所述输入信号和所述第二锁相环回路电路的输出信号产生延时信号；所述第二锁相环回路电路被配置为根据所述输入信号和所述延时信号将所述压控延迟器的输出频率锁定为基准输出频率；所述K个输出端，被配置为输出K个相位均匀间隔的输出信号，其中，K为大于1的正整数，述基准输出频率表示为f d，所述基准时间单位是所述K个输出端输出的任意两个相邻的输出信号之间的时间跨度，所述基准时间单位表示为△，并且△＝1/(K·f d)。
例如，在本公开至少一实施例提供的时间同步装置中，所述频率调节子电路被配置为基于下式根据所述频率控制字和所述基准时间单位确定所述目标频率：
f TAF-DPS＝1/(F·△)＝(K·f d)/F
其中，f TAF-DPS表示所述目标频率，F表示所述频率控制字。
例如，在本公开至少一实施例提供的时间同步装置中，所述频率调节子 电路包括时间平均频率直接周期合成器。
本公开至少一实施例还提供一种电子设备，其包括根据上述任一项所述的时间同步装置。
例如，本公开至少一实施例提供的电子设备还包括频率源，所述频率源被配置为提供具有所述初始频率的输入信号。
本公开至少一实施例还提供一种时间同步系统，包括：多个电子设备。所述多个电子设备中的至少一个为根据上述任一项所述的电子设备。
本公开至少一实施例还提供一种时间同步方法，应用于根据上述任一项所述的时间同步装置，所述时间同步方法包括：生成频率控制字；根据所述频率控制字和所述输入信号，生成并输出具有所述目标频率的输出信号；基于具有所述目标频率的输出信号对所述电子设备的时钟信号进行同步调节操作。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种时钟网络分布的示意图；
图2为本公开至少一实施例提供的一种电子设备的示意性框图；
图3为本公开至少一实施例提供的一种用于电子设备的时间同步装置的示意性框图；
图4为本公开至少一实施例提供的一种信号生成电路的示意性框图；
图5为本公开至少一实施例提供的一种信号生成电路的另一示意性框图；
图6A为本公开至少一实施例提供一种基准时间单位生成子电路的示意性结构图；
图6B为本公开至少一实施例提供另一种基准时间单位生成子电路的示意性结构图；
图7为本公开至少一实施例提供的一种K个相位均匀间隔的基准输出信号的示意图；
图8为本公开至少一实施例提供的一种频率调节子电路的示意性框图；
图9为本公开至少一实施例提供的一种频率调节子电路的工作原理示意图；
图10A为本公开至少一实施例提供的一种频率调节子电路的结构示意图；
图10B为本公开至少一实施例提供的另一种频率调节子电路的结构示意图；
图11为本公开至少一实施例提供的一种时间同步系统的示意性框图；
图12为本公开至少一实施例提供的一种时间同步系统的基于网络时间同步协议NTP进行时间同步的示意图；
图13示出了本公开至少一实施例提供的一种时间同步方法的示意性流程图。
具体实施方式
为了使得本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
为了保持本公开实施例的以下说明清楚且简明，本公开省略了已知功能和已知部件的详细说明。
图1为一种时钟网络分布的示意图。如图1所示，在面向大数据网络(比如因特网)时，需要使用多条时钟链路驱动所有网络节点，从而使所有网络节点的时钟同步。时钟同步的方法有很多种，例如纯软件方法、纯硬件方法、硬件和软件相结合的方法等。具体地，时钟同步的方法包括单向授时、双向授时、网络时钟同步技术、通过网络报文完成时钟修正(例如NTP、PTP技术)。单向授时和双向授时的精度较低，网络时钟同步技术和通过网络报文完成时钟修正的精度比单向授时和双向授时高。时钟同步的方法还包括频率同步的方法，例如，利用电缆或光缆直接传递10MHz、5MHz等标准频率(但是此方法的限制因素较多)、通过测量得到主从时钟的时间差并通过锁定主从时钟的时间差实现频率锁定、或者间接计算频率偏差从而完成频率修正等。然而，上述所有的时钟同步的方法中，时间精度的修正幅度有限，服务器与客户端之间存在硬件、软件以及网络链路等因素的差异，因此，每一种因素的变化都会对网络中的各个设备的时间修正造成影响。
本公开至少一实施例提供一种用于电子设备的时间同步装置、电子设备、时间同步系统和时间同步方法。该时间同步装置可以通过信号生成电路合成频率足够大的输出信号，输出信号的频率粒度较高，从而使电子设备获得更精准的同步时钟，电子设备在网络系统中的工作协调性和一致性更好。
下面结合附图对本公开的实施例进行详细说明，但是本公开并不限于这些具体的实施例。
图2为本公开至少一实施例提供的一种电子设备的示意性框图；图3为本公开至少一实施例提供的一种用于电子设备的时间同步装置的示意性框图；图4为本公开至少一实施例提供的一种信号生成电路的示意性框图；图5为本公开至少一实施例提供的一种信号生成电路的另一示意性框图。
例如，如图2所述，本公开至少一实施例提供的电子设备50可包括本公开至少一实施例提供的时间同步装置1000。电子设备50例如可以是具有数据传输功能的任何设备，包括但不限于智能手机、平板电脑、电子书阅读器、膝上型便携计算机和台式计算机等等，本公开的实施例对此不作限制。
例如，如图3所示，本公开至少一实施例提供的时间同步装置1000包括信号生成电路100和时间调节电路150。如图4所示，信号生成电路100包括控制电路11和信号调节电路12。控制电路11被配置为生成频率控制字。 信号调节电路12被配置为接收具有初始频率的输入信号和频率控制字，并根据频率控制字和输入信号生成并输出具有目标频率的输出信号。例如，时间调节电路150被配置为基于具有目标频率的输出信号调节该电子设备的时钟信号，以得到同步时钟信号。
例如，如图2所示，电子设备50还可以包括频率源200。频率源200被配置为提供具有初始频率的输入信号，并将该输入信号传输到信号生成电路100中。例如，初始频率可以表示频率源200实际生成并输出的信号的频率。目标频率表示用户期望得到的信号的频率。例如，目标频率表示信号生成电路100输出的信号能够达到的频率。例如，目标频率大于初始频率。目标频率与需要进行时钟同步的终端设备的时间同步精度相关。
例如，网络时钟同步系统包括第一终端设备和第二终端设备，且第一终端设备和第二终端设备需要进行时间同步。若第一终端设备的本地时钟信号的频率为f，那么，该第一终端设备可以调节的频率准确度为1/f。第一终端设备和第二终端设备之间的需要修正的时间误差是t，如果t>1/f，那么，第一终端设备可以较好地修正其与第二终端设备之间的时间误差，以较好地实现第一终端设备和第二终端设备之间的时间同步。修正的时间误差为t 0＝N 0/f，其中，N 0为整数，N 0可以表示最接近于t除以1/f的结果(即t×f)的整数，第一终端设备的同步时间修正能力可以表示为：δ＝t-t 0＝t-N 0/f，δ可以表示即修正第一终端设备的时间后第一终端设备和第二终端设备之间的时间误差。f越大，则N 0与t×f越接近，则时间误差δ越小。但是，如果要修正的时间误差t<1/f，那么，通过该第一终端设备则很难完成时间误差的修正，或者，对第一终端设备的时间修正后得到的修正时间与第二终端设备的时间仍然存在较大的误差。综上所述，当终端设备需要修正的时间误差为t时，则目标频率f TAF-DPS的范围可以为：f TAF-DPS>1/t。
例如，频率源200可以包括自激振荡源和合成频率源。自激振荡源包括晶体振荡器、腔体振荡器以及压控振荡器等。合成频率源包括直接模拟式频率源、直接数字式频率源、间接模拟式频率源和间接数字式频率源。
例如，频率源200可以包括普通晶体振荡器(Crystal Oscillator，XO)、温补晶体振荡器(Temperature Compensated Crystal Oscillator，TCXO)和恒温晶体振荡器(Oven Controlled Crystal Oscillator，OCXO)等晶振源。
例如，时钟同步技术可以包括同步时间检测、远程时钟预估和本地时钟校准。电子设备的同步时间精度的公式可以表示为：
π＝C 1·ε+C 2·G1+C 3·G2+C 4·u+C 5·Gs
其中，π表示同步时间精度，ε表示读取远程时钟时的传输延迟不确定度，G1表示时钟漂移(即晶振源的频率漂移)，G2表示读取时钟粒度，u表示调整粒度比率，Gs表示时钟设置粒度。C 1、C 2、C 3、C 4和C 5表示权重因子。G2、u和Gs都直接或间接与频率源生成的输入信号的初始频率f c相关。由于电子设备的时钟的计数器随输入信号的初始频率f c的步长(1/f c)增长，因此，f c越高，则同步时间精度π越高(π越小，则表示同步时间精度越高)。
例如，从上述同步时间精度的公式可知，晶振源的频率漂移对同步时间精度有影响，而晶振源的频率漂移通常有工作的环境温度和器件老化所引起。因此，需要补偿由于晶振源的频率漂移对输出信号的目标频率的影响，从而提高同步时间精度。频率控制字可以用于控制输出信号的目标频率，由此，可以根据晶振源的频率漂移改变频率控制字，从而实现对输出信号的目标频率的补偿。
例如，控制电路11被配置为获取晶振漂移的影响参数，并根据影响参数生成频率控制字。也就是说，频率控制字可以根据晶振漂移的影响参数而变化。当晶振漂移的影响参数产生变化，则频率控制字产生相应的变化。
例如，输入信号和输出信号均为脉冲信号。
例如，频率控制字用于控制输出信号的目标频率。信号调节电路12可以根据该频率控制字和输入信号的初始频率来生成输出信号，且使得生成的输出信号的频率为目标频率，从而满足不同设备的时间同步的精度需求。例如，对于相同的初始频率，频率控制字产生变化，则目标频率也产生相应的变化，从而具有相同初始频率的输入信号可以转换为具有不同目标频率的输出信号，以满足不同电子设备的需求。
例如，如图4所示，信号生成电路100还包括参数获取电路13。参数获取电路13被配置为检测晶振漂移的影响参数，从而补偿由于晶振漂移的影响参数对输出信号的目标频率的影响。
例如，由于晶振漂移的影响参数，频率源生成的输入信号的初始频率在不同的条件下不相同。例如，影响晶振漂移的因素可以包括环境温度和频率 源老化等。例如，在一些示例中，由于环境温度的影响，初始频率的频率误差可以达到±10ppm。由于频率源老化的影响，频率源生成的输入信号的初始频率的频率误差随时间递增且逐渐累加。在本公开的实施例中，通过检测晶振漂移的影响参数，并根据该晶振漂移的影响参数生成频率控制字，然后信号调节电路12可以根据频率控制字生成补偿后的输出信号。也就是说，该输出信号的目标频率更加接近甚至等于用户预设的频率，从而实现补偿由于晶振漂移的影响参数造成的输出信号的目标频率的误差。由此，本公开至少一实施例提供的信号生成电路100可以在不改变频率源的物理结构的基础上实现对输出信号的频率补偿，校正输出信号的频率误差，提高网络系统中各个设备的时间同步的准确性。
需要说明的是，由于制造误差的影响，频率源生成的输入信号的初始频率可能具有一个固定不变的制造误差，从而影响输出信号的目标频率。由此，影响晶振漂移的因素还可以包括制造误差等，本公开对此不作限制。
例如，在一些示例中，如图5所示，晶振漂移的影响参数包括温度参数T 0。参数获取电路13包括温度检测子电路131。温度检测子电路131被配置为检测温度参数T 0，以补偿由于环境温度而造成输出信号的目标频率的误差。
例如，温度检测子电路131可以包括温度检测器和第一计数器。温度检测器被配置为检测环境温度，温度参数T 0可以包括环境温度。第一计数器被配置为根据环境温度和参考温度记录频率变化量。
例如，温度参数与频率变化量的关系为非线性，但不限于此，特殊的温度传感器也可以输出温度参数与频率变化量的线性比例关系。例如，在本公开中，温度参数与频率变化量的关系式可以表示为：
Δf＝r·ΔT n+p·ΔT n-1+...+d·ΔT+g
其中，Δf表示频率变化量，r、p、d和g均为常数，ΔT表示环境温度和参考温度的差值，ΔT＝T1-T2，T1表示环境温度，T2表示参考温度，n为正整数。例如，参考温度可以为25℃，即T2＝25。但不限于此，参考温度也可以为其他值，本公开对此不作限制。
例如，温度系数r、p、d和g的值可以根据实际情况具体设置。上述关系式中的温度系数的数量与n相关。若温度参数与频率变化量之间的关系为 二阶非线性关系，则n为2，此时，温度参数与频率变化量的关系式可以表示为：
Δf＝r·ΔT 2+p·ΔT 1+g
从而，上述关系式中仅包括三个温度系数，即r、p和g。而当n为其他值时，上述关系式中的温度系数的数量也会相应变化。
例如，频率变化量表示信号调节电路12生成的输出信号的目标频率的变化量，也就是说，频率变化量可以表示为：
Δf＝f 1-f 2＝r·ΔT n+p·ΔT n-1+...+d·ΔT+g
其中，f1表示在当前环境温度下输出信号的目标频率，f2表示在参考温度下输出信号的目标频率。
例如，频率控制字与频率变化量的关系式可以表示为：
Figure PCTCN2019082926-appb-000002
其中，F N表示频率控制字，F TO表示与参考温度对应的参考频率控制字(即在参考温度下的频率控制字)，f Δ表示基准时间单位的频率。参考频率控制字F TO可以预先检测并存储在电子设备的存储器中。例如，控制电路可被配置为基于式(1)根据环境温度生成频率控制字。
例如，在本公开至少一实施例提供的信号生成电路中，可以通过温度检测器检测环境温度，并向控制电路11实时反馈温度参数，控制电路11可以根据温度参数实时调节频率控制字，从而实时补偿由于温度造成的输出信号的目标频率的频率误差。
例如，在另一些示例中，如图5所示，晶振漂移的影响参数包括老化参数A 0。参数获取电路13可以包括老化读取子电路132。老化读取子电路132被配置为读取晶振源的老化参数A 0，以补偿由于频率源老化而造成输出信号的目标频率的误差。
例如，老化读取子电路132可以包括老化读取元件和第二计数器。老化读取元件被配置为读取晶振源的老化速率，以及读取与晶振源的老化速率相对应的参考时间，老化参数包括老化速率和参考时间。第二计数器被配置为 记录参考时间的数量。
需要说明的是，老化速率由晶振源本身的性质决定，在使用该晶振源的过程中，老化速率可以被认为是一个固定不变的值。老化速率可以由生产该晶振源的厂家提供，该老化速率可以存储在电子设备的存储器中，当需要使用老化速率这一参数时，由老化读取元件直接从电子设备的存储器中读取。
例如，晶振源的老化速率可以用ppm(parts per million,百万分之一)或者ppb(parts per billion,十亿分之一)表示，例如，若晶振源的老化速率为±5ppm/year，则表示一年内晶振源生成的信号的频率的误差值在±5ppm以内；若晶振源的老化速率为±1ppm/mouth，则表示一个月内晶振源生成的信号的频率的误差值在±1ppm以内。
例如，参考时间与老化速率相关，如果晶振源的老化速率的单位时间是年，例如，晶振源的老化速率为±5ppm/year，则参考时间为一年；而如果晶振源的老化速率的单位时间是月，例如，晶振源的老化速率为±1ppm/month，则参考时间为一月。
例如，频率控制字与老化参数的关系式可以表示为：
F N＝F AO·(1+γ)    (2)
其中，F N表示频率控制字，F AO表示参考频率控制字，γ表示老化参数的乘积，其中，γ＝ν·t，ν表示老化速率，t表示参考时间的数量，且t为自然数，即0，1，2……。参考频率控制字F AO可以表示初次使用频率源时所对应的频率控制字，参考频率控制字F AO可以预先检测并存储在电子设备的存储器中。例如，控制电路可被配置为基于式(2)根据老化速率生成频率控制字。
例如，若老化速率的单位时间是年，即若参考时间为一年时，则当频率源200投入使用的时间小于一年，t均为0；当频率源200投入使用的时间大于一年且小于两年时，t则为1，依次类推。
例如，在本公开至少一实施例提供的信号生成电路中，老化读取子电路132可以每间隔预定时间向控制电路11传输老化参数A 0，从而对频率控制字进行老化校正。预定时间可以为10天、一个月、一年等。例如，预定时间可以与参考时间相同。例如，若参考时间为一年，则预定时间也可以为一年，即每间隔一年对频率控制字进行一次老化校正。
值得注意的是，在一些实施例中，参数获取电路13可以同时包括温度检测子电路131和老化读取子电路132，从而同时补偿环境温度和频率源老化对输出信号的影响。
例如，如图5所示，控制电路11可以包括计算子电路111和输出子电路112。计算子电路111被配置为从参数获取电路13处获取晶振漂移的影响参数(例如，影响参数包括老化参数A 0和温度参数T 0等)，并根据晶振漂移的影响参数生成频率控制字F。输出子电路112被配置为将频率控制字F输出至信号调节电路12。
例如，计算子电路111可以根据上述的公式(1)和/或公式(2)计算得到频率控制字。
例如，输出子电路112可以在时钟信号的控制下，将计算子电路111计算的频率控制字F输出至信号调节电路12。
例如，控制电路11可以利用硬件电路实现。例如，计算子电路111和输出子电路112可以利用硬件电路实现。计算子电路111例如可以采用晶体管、电阻、电容和放大器等元件构成。输出子电路112例如可以采用触发器等元件构成。当然，控制电路11的功能也可以通过软件实现。例如，计算子电路111和输出子电路112的功能也可以通过软件实现。例如，可以通过处理器执行存储器中存储的指令和数据以实现计算子电路111和输出子电路112的功能。
例如，如图5所示，信号调节电路12可以包括基准时间单位生成子电路121和频率调节子电路122。基准时间单位生成子电路121被配置为接收具有初始频率f c的输入信号，并根据初始频率生成并输出基准时间单位Δ。频率调节子电路122被配置为根据频率控制字F和基准时间单位Δ生成并输出具有目标频率f TAF-DPS的输出信号。
图6A示出了本公开至少一实施例提供一种基准时间单位生成子电路的示意性结构图；图6B示出了本公开至少一实施例提供另一种基准时间单位生成子电路的示意性结构图；图7示出了本公开至少一实施例提供的一种K个相位均匀间隔的基准输出信号的示意图。
例如，基准时间单位生成子电路121被配置为根据初始频率生成并输出K个相位均匀间隔的基准输出信号以及基准时间单位。基准时间单位生成子 电路121可以包括锁相环(phase locked loop,PLL)或延迟锁相环(delay locked loop,DLL)。
例如，在一些示例中，基准时间单位生成子电路121可以包括PLL。如图6A所示，基准时间单位生成子电路121可以包括压控振荡器(VCO)1211、第一锁相环回路电路1212和K个输出端1213。压控振荡器1211被配置为以预定振荡频率振荡；第一锁相环回路电路1212被配置为将压控振荡器1211的输出频率锁定为基准输出频率；K个输出端1213被配置为输出K个相位均匀间隔的输出信号，K为大于1的正整数，例如，K＝16、32、128或其他数值。
例如，基准时间单位可以表示为△，基准输出频率可以表示为f d。如图7所示，基准时间单位△是K个输出端1213输出的任意两个相邻的输出信号之间的时间跨度(time span)。基准时间单位△通常由多级压控振荡器1211生成。压控振荡器1211生成的信号的频率f vco可以通过第一锁相环回路电路1212锁定到已知的基准输出频率f d，即f d＝f vco。
例如，基准时间单位△可以使用以下公式计算：
Δ＝T d/K＝1/(K·f d)    (3)
其中，T d表示多级压控振荡器1211生成的信号的周期。f Δ表示基准时间单位的频率，即f Δ＝1/Δ＝K·f d。
例如，第一锁相环回路电路1212包括相位检测器(PFD)、环路滤波器(LPF)和分频器(N)。例如，在本公开实施例中，首先，具有初始频率的输入信号可以被输入到相位检测器，然后进入环路滤波器，接着进入压控振荡器，最后压控振荡器生成的具有预定振荡频率f vco的信号可以通过分频器进行分频以得到分频信号的分频频率f vco/N，分频频率f vco/N反馈到相位检测器，相位检测器用于比较输入信号的初始频率f c与分频频率f vco/N，当初始频率f c与分频频率f vco/N的频率和相位相等时，两者之间的误差为零，此时，PLL处于锁定状态。
需要说明的是，环路滤波器可以为低通滤波器。分频器的分频系数为N，N为实数，且N大于或等于1。
例如，基准输出频率f d与初始频率f c相关。例如，压控振荡器1211生成的信号的频率f vco与初始频率f c之间的关系可以表示为：f vco＝N×f c，由于f d＝f vco， 从而基准时间单位△可以表示为：Δ＝T d/K＝1/(K·f d)＝1/(K·N·f c)。若分频系数N为1，则f vco＝f c，同时由于f d＝f vco，从而基准输出频率f d可以与初始频率f c相等，也就是说，f d＝f c。
例如，在另一些示例中，基准时间单位生成子电路121可以包括DLL。DLL可以通过CMOS技术实现，从而DLL容易被集成到任意的芯片和电路中，降低信号生成电路的成本，提高效率。例如，如图6B所示，基准时间单位生成子电路121包括压控延迟器1214、第二锁相环回路电路1215和K个输出端1213。压控延迟器1214可以包括一个或者多个级联的延时单元，且被配置为根据输入信号和第二锁相环回路电路1215的输出信号产生延时信号；第二锁相环回路电路1215被配置为根据输入信号和延时信号将压控延迟器1214的输出频率锁定为基准输出频率；K个输出端1213被配置为输出K个相位均匀间隔的输出信号，K为大于1的正整数。
例如，如图6B所示，第二锁相环回路电路1215可以包括相位检测器(PFD)、电荷泵(未示出)和环路滤波器(LPF)等。相位检测器用于检测输入信号的初始频率f c和反馈的延时信号的频率f db之间的相位差，并将该相位差输出至电荷泵；电荷泵用于根据该相位差输出与相位差成正比的电压信号，并将电压信号输出至环路滤波器；环路滤波器用于滤除该电压信号的高次谐波，从而得到控制压控延迟器1214的控制电压Vcom。
例如，延时单元可以包括二选一多路复用门电路(MUX2_1)等。延时单元的延迟时间可以随控制电压Vcom而变化，例如，延时单元的控制电压为Vcom，延迟时间为Tvcol，Vcom与Tvcol成正比。
例如，基准输出频率表示为f d，基准时间单位表示为△。基准时间单位△是K个输出端输出的任意两个相邻的输出信号之间的时间跨度，△＝1/(K·f d)。基准输出频率f d与初始频率f c相等，从而△＝1/(K·f c)。
例如，频率源200生成的输入信号的初始频率为f c，若基准输出频率f d与初始频率f c相等，即f d＝f c。则输入信号的时间粒度为1/f d，当利用信号生成电路100对频率源输出的输入信号的初始频率f c进行调节后，可以得到具有目标频率f TAF-DPS的输出信号，且输出信号的时间粒度为△，即1/(K·f d)，K为大于1的正整数，输出信号的时间粒度1/(K·f d)小于输入信号的时间粒度1/f d，从而包括该信号生成电路的电子设备的时间同步的精度更高，工作 协调性更好。例如，在一个示例中，频率源200生成的输入信号的初始频率为f c＝20MHz，则输入信号的时间粒度是50ns，频率粒度是5×10 -8。当信号生成电路对该输入信号进行处理后，得到输出信号，输出信号的时间粒度为△，频率粒度为1/(K·f c)。△可以非常小，例如，当K为1024时，△可以为48.8ps，由此，输出信号的时间粒度为48.8ps，输出信号的频率粒度为4.9×10 -11，由此，相较于输入信号，输出信号的时间粒度和频率粒度均提升了K(即1024)倍。
输入信号和输出信号的时间粒度和频率粒度之间的对应关系可以如下面的表格1所示。
表格1
Figure PCTCN2019082926-appb-000003
通过上述表格1可知，本公开的信号生成电路对输入信号进行调节后，可以得到输出信号，由于输出信号的目标频率大于输入信号的初始频率，从而输出信号的时间粒度和频率粒度均得到提高。
值得注意的是，图6A和图6B所示的电路结构仅是基准时间单位生成子电路121的一种示例性的实现方式。基准时间单位生成子电路121的具体结构并不限于此，其还可以由其他电路结构构建而成，本公开在此不作限制。
图8示出了本公开至少一实施例提供的一种频率调节子电路的示意性框图；图9示出了本公开至少一实施例提供的一种频率调节子电路的工作原理示意图。
例如，如图8所示，频率调节子电路122包括第一输入模块1221、第二输入模块1222和输出模块1223。第一输入模块1221被配置为接收来自基准时间单位生成子电路121的K个相位均匀间隔的基准输出信号和基准时间单位。第二输入模块1222被配置为接收来自控制电路11的频率控制字。输出模块1223被配置为生成并输出与频率控制字和基准时间单位相匹配的具有目标频率的输出信号。
例如，频率调节子电路122可以包括时间平均频率直接周期合成器(TAF-DPS合成器)。时间平均频率直接周期合成(Time-Average-Frequency Direct Period Synthesis，TAF-DPS)技术是一种新兴的频率合成技术，其可以生成任何频率的脉冲信号。也就是说，TAF-DPS合成器能够实现小频率粒度的精细频率调整。此外，因为每个单个脉冲是直接构建的，所以TAF-DPS合成器的输出频率可以瞬间改变，也即具有频率切换的迅速性。实验证明，TAF-DPS合成器的频率粒度可以达到几个ppb(parts per billion)。能够生成任何频率和能够迅速进行频率切换是TAF-DPS合成器相比于常规频率源的主要优点。TAF-DPS合成器可以作为本公开实施例中的频率调节子电路122的一种具体实现方式。
由此，本公开实施例提供的信号生成电路的优点包括，但不限于：
(1)低成本和实现的灵活性。基于TAF-DPS的频率补偿器可以完全使用数字化设计，通过HDL编码烧制到可编程的逻辑器件中(例如，FPGA)，频率补偿器的参数也可以方便地随时重新设置。因此，无需使用特制的专用电路，使用一般的FPGA或其他可编程器件即可实现频率补偿器的功能。当然，也可以采用ASIC来实现频率补偿器的功能。
(2)高精度。TAF-DPS输出的脉冲信号的频率/周期可以精确地被控制，其频率分辨率可以到达十亿分率，从而可以有效提高时间的同步精度。
例如，TAF-DPS合成器可以使用可编程逻辑器件(例如，ASIC或FPGA)来实现。或者，TAF-DPS合成器可以使用传统的模拟电路器件来实现。本公开在此不作限定。
下面，将参考图9描述基于TAF-DPS合成器的频率调节子电路的工作原理。
例如，如图9所示，基于TAF-DPS合成器510的频率调节子电路122具有两个输入：基准时间单位520和频率控制字530。频率控制字530表示为F，F＝I+r，且I是大于1的整数，r是分数。
例如，TAF-DPS合成器510具有一个输出CLK 550。该CLK 550是合成的时间平均频率时钟信号。在本公开的至少一实施例中，CLK 550即为具有目标频率的输出信号。根据基准时间单位520，TAF-DPS合成器510可以产生两种类型的周期，即第一周期T A＝I·Δ和第二周期T B＝(I+1)·Δ。输 出CLK 550是时钟脉冲串540，且该时钟脉冲串540由第一周期T A 541和第二周期T B 542以交织的方式构成。分数r用于控制第二周期T B的出现概率，因此，r也可以确定第一周期T A的出现概率。
例如，如图9所示，输出信号CLK 550的周期T TAF-DPS可以用下面的公式表示：
T TAF-DPS＝(1-r)·T A+r·T B
＝T A+r·(T B-T A)＝T A+r·△＝I·△+r·△＝(I+r)·△
因此，当频率控制字530为F＝I+r时，可以得到：
T TAF-DPS＝F·△     (4)
由上面的公式(4)可知，TAF-DPS合成器510输出的输出信号CLK的周期T TAF-DPS与频率控制字530呈线性比例。当频率控制字530发生变化时，TAF-DPS合成器510输出的输出信号的周期T TAF-DPS也将以相同的形式发生变化。
此外，因为周期T与频率f成反比，所以当满足预定条件下，例如，当频率控制字530的变化量非常小时(小于预定阈值时)，输出信号的目标频率也可以近似地以线性方式跟随频率控制字(F)的波形变化。控制电路11可以根据晶振漂移的影响参数生成频率控制字，然后TAF-DPS合成器510根据该频率控制字生成具有目标频率的输出信号，该目标频率与频率控制字相对应，通过调节频率控制字即可调节目标频率，当基于温度参数和老化参数对频率控制字进行补偿后，相应地，目标频率也得到补偿。
例如，基于上述公式(3)和公式(4)，目标频率表示为：
f TAF-DPS＝1/T TAF-DPS＝1/(F·△)＝(K·f d)/F
其中，f TAF-DPS表示目标频率，F表示频率控制字。例如，频率调节子电路可被配置为基于该式根据频率控制字和基准时间单位确定目标频率。
图10A为本公开至少一实施例提供的一种频率调节子电路的结构示意图；图10B为本公开至少一实施例提供的另一种频率调节子电路的结构示意图。
下面，将参考图10A和10B描述TAF-DPS合成器的电路结构。
例如，如图10A所示，在一些实施例中，第一输入模块1221包括K→1多路复用器711。K→1多路复用器711具有用于接收K个相位均匀间隔的基 准输出信号的多个输入端、控制输入端和输出端。
例如，输出模块1223包括触发电路730。触发电路730用于生成脉冲串。脉冲串例如由第一周期T A的脉冲信号和第二周期T B的脉冲信号以交织方式构成。触发电路730包括D触发器、反相器和输出端。D触发器包括数据输入端、用于接收来自K→1多路复用器711的输出端的输出的时钟输入端和用于输出第一时钟信号CLK1的输出端。反相器包括用于接收第一时钟信号CLK1的反相器输入端和用于输出第二时钟信号CLK2的反相器输出端。触发电路730的输出端用于输出第一时钟信号CLK1作为具有目标频率的输出信号S out。
例如，第一时钟信号CLK1包括脉冲串。第二时钟信号CLK2连接到D触发器的数据输入端。
例如，第二输入模块1222包括逻辑控制电路740。逻辑控制电路740包括用于接收控制电路11输出的频率控制字F的输入端、用于接收第一时钟信号CLK1的时钟输入端和连接到第一输入模块1221的K→1多路复用器的控制输入端的输出端。
例如，如图10B所示，在另一些实施例中，第一输入模块1221包括第一K→1多路复用器721、第二K→1多路复用器723和2→1多路复用器725。第一K→1多路复用器721和第二K→1多路复用器723分别包括用于接收K个相位均匀间隔的信号的多个输入端、控制输入端和输出端。2→1多路复用器725包括控制输入端、输出端、用于接收第一K→1多路复用器721的输出的第一输入端和用于接收第二K→1多路复用器723的输出的第二输入端。
例如，如图10B所示，输出模块1223包括触发电路。触发电路用于生成脉冲串。触发电路包括D触发器761、反相器763和输出端762。D触发器761包括数据输入端、用于接收来自2→1多路复用器725的输出端的输出的时钟输入端和用于输出第一时钟信号CLK1的输出端。反相器763包括用于接收第一时钟信号CLK1的输入端和用于输出第二时钟信号CLK2的输出端。触发电路的输出端762用于输出第一时钟信号CLK1作为具有目标频率的输出信号S out。
例如，第一时钟信号CLK1连接到2→1多路复用器725的控制输入端，第二时钟信号CLK2连接到D触发器761的数据输入端。
例如，如图10B所示，第二输入模块1222包括第一逻辑控制电路70和第二逻辑控制电路74。第一逻辑控制电路70包括第一加法器701、第一寄存器703和第二寄存器705。第二逻辑控制电路74包括第二加法器741、第三寄存器743和第四寄存器745。
第一加法器701将频率控制字(F)和第一寄存器703存储的最高有效位(most significant bits，例如，5比特)相加，然后在第二时钟信号CLK2的上升沿时将相加结果保存到第一寄存器703中；或者，第一加法器701将频率控制字(F)和第一寄存器703存储的所有信息相加，然后在第二时钟信号CLK2的上升沿时将相加结果保存到第一寄存器703中。在下一个第二时钟信号CLK2的上升沿时，第一寄存器703存储的最高有效位将被存储到第二寄存器705中，并作为第一K→1多路复用器721的选择信号，用于从K个多相位输入信号中选择一个信号作为第一K→1多路复用器721的第一输出信号。
第二加法器741将频率控制字(F)和第一寄存器703存储的最高有效位相加，然后在第二时钟信号CLK2的上升沿时将相加结果保存到第三寄存器743中。在下一个第一时钟信号CLK1的上升沿时，第三寄存器743存储的信息将被存储到第四寄存器745中，并作为第二K→1多路复用器723的选择信号，用于从K个多相位输入信号中选择一个信号作为第二K→1多路复用器723的第二输出信号。
2→1多路复用器725在第一时钟信号CLK1的上升沿时，选择来自第一K→1多路复用器721的第一输出信号和来自第二K→1多路复用器723的第二输出信号中的一个作为2→1多路复用器725的输出信号，以作为D触发器761的输入时钟信号。
例如，图10A和图10B所示的TAF-DPS合成器输出的输出信号S out的周期(T TAF-DPS)可以由上面的公式(4)计算得到。例如，频率控制字以F＝I+r的形式设置，其中，I是在[2，2K]的范围内的整数，r是在[0,1)的范围内的小数。
另外，关于TAF-DPS的工作原理，可以参考文献L.XIU,“Nanometer Frequency Synthesis beyond the Phase-Locked Loop”,Piscataway,NJ 08854,USA,John Wiley IEEE-press,2012和L.XIU,“From Frequency to Time-Average-Frequency:a Paradigm Shift in the Design of Electronic System”, Piscataway,NJ 08854,USA,John Wiley IEEE-press,2015。在此通过引用并入其全部内容作为参考。
图11示出了本公开至少一实施例提供的一种时间同步系统的示意性框图；图12示出了本公开至少一实施例提供的一种时间同步系统的基于网络时间同步协议NTP进行时间同步的示意图。
例如，本公开至少一实施例提供的时间同步系统60可以包括多个电子设备。多个电子设备中的至少一个为根据上述任一项所述的电子设备。电子设备的信号生成电路可以生成具有目标频率的输出信号；电子设备的时间调节电路可以基于具有目标频率的输出信号对该电子设备的时钟信号进行同步调节操作，从而使电子设备的网络时间同步的精度更高。
例如，时间同步系统60中的每个电子设备都可以为根据上述任一实施例所述的电子设置，从而时间同步系统60中的每个电子设备都可以基于具有目标频率的输出信号调节其时钟信号，以使时间同步系统60中的多个电子设备达到时间同步。由于输出信号的目标频率大于原始频率源输出的输入信号的初始频率，由此，时间同步系统60中的多个电子设备的时间同步精度高，各个电子设备工作的一致性、协调性更好。
例如，如图11所示，在一些示例中，时间同步系统60包括两个电子设备，且分别为第一电子设备61和第二电子设备62。第一电子设备61可以位于客户端，第二电子设备62可以位于服务器端。如图12所示，第一电子设备61被配置在第一时间戳发送第一网络报文至第二电子设备62。第一网络报文附带有该第一电子设备61在第一时间戳的时间信息。在第一时间戳，第一电子设备61上是时间为T1，从而第一网络报文包括该时间T1，第二电子设备62上的时间为T1+d1，d1为第一电子设备61和第二电子设备62之间的同步时间误差，由于第一电子设备61和第二电子设备62之间的位置差异，第二电子设备62在第二时间戳接收第一网络报文。在第二时间戳，第二电子设备62上的时间为T2，此时，第一电子设备61上是时间为T2-d1。经过第二电子设备62的内部系统的时间延迟，第二电子设备62在第三时间戳输出第二网络报文至第一电子设备61。第二网络报文附带有该第二电子设备62在第二时间戳的时间信息、第二电子设备62在第三时间戳的时间信号和第一网络报文所包括的第一电子设备61在第一时间戳的时间信息。在第三时间 戳，第二电子设备62上是时间为T3，第一电子设备61上的时间为T3-d1。由此，第二网络报文包括时间T1、时间T2和时间T3。第一电子设备61在第四时间戳接受第二网络报文。在第四时间戳，第一电子设备61上是时间为T4，第二电子设备62上的时间为T4+d1。然后，第一电子设备61可以并根据时间T1、T2、T3和T4计算得到第一电子设备61和第二电子设备62之间的时间偏差，从而调节第一电子设备61的时钟信号，以得到第一电子设备61的同步时钟信号。该第一电子设备61的同步时钟信号表示其与第二电子设备62同步的时钟信号，即该同步时钟信号与第二电子设备62的时钟信号同步。
例如，第一电子设备61的同步时钟信号的精度与第一电子设备61的信号生成电路输出的输出信号的目标频率的值正相关，当目标频率越高，则第一电子设备61的同步时钟信号的精度越高。例如，若目标频率为100HZ时，第一电子设备61的同步时钟信号的时间粒度(即同步精度)可以为0.01s。
例如，d2可以表示网络报文在第一电子设备61和第二电子设备62之间传输所消耗的单向平均延迟时间，d2可以表示为：
Figure PCTCN2019082926-appb-000004
例如，如图12所示，d21(下面表示为第一传输延迟时间)可以表示第一网络报文从第一电子设备61传输至第二电子设备62的过程中的传输延迟时间，d22(下面表示为第二传输延迟时间)可以表示第二网络报文从第二电子设备62传输至第一电子设备61的过程中的传输延迟时间，则
d21+d22＝2·d2
同步时间误差d1可以表示为：
Figure PCTCN2019082926-appb-000005
当第一传输延迟时间d21和第二传输延迟时间d22相同时，即d21＝d22＝d2，则同步时间误差d1可以表示为：
Figure PCTCN2019082926-appb-000006
也就是说，第一电子设备61的时间与第二电子设备62的时间相差 [(T2-T1)+(T3-T4)]/2。例如，在一个示例中，时间T1为10:00:00，时间T2为11:00:01，时间T3为11:00:02，时间T4为10:00:03，则单向传输网络报文的时间d2＝(3-1)/2＝1秒，即单向传输延迟为1秒，同步时间误差d1＝(1:00:01+00:59:59)/2＝1小时，即需要修正的时间误差为1小时。
需要说明的是，第一传输延迟时间d21和第二传输延迟时间d22也可能不相同，即d21与d22不相等。网络时间同步NTP协议可以包括客户端/服务端模式、对等体模式、广播模式、组播模式等，在不同工作模式下，电子设备的时间同步方式不相同，本公开对此不作限制。例如，在上述示例中，时间T3是11:00:02，如果需要强制将第一电子设备61的时间更新为第二电子设备62时间，则可以直接将第一电子设备61的时间T4更新为T3+d2(1s)即可，也就是说，在第四时间戳，第一电子设备61的时钟信号为11:00:03，第二电子设备62的时钟信号为11:00:03，也就是说，第一电子设备61的时钟信号与第二电子设备62的时钟信号同步。
例如，第一电子设备61需要调节其时钟信号，以与第二电子设备62达到时间同步。第一电子设备61需要调节的时间误差为d1＝[(T2-T1)+(T3-T4)]/2。由此，当第一电子设备61中的信号生成电路生成的输出信号的目标频率f TAF-DPS满足关系式：d1>1/f TAF-DPS，第一电子设备61则可以较好地修正该时间误差，从而第一电子设备61可以较好地实现与第二电子设备62之间的时间同步。
例如，在一个示例中，若d1为0.07s，当第一电子设备61中的信号生成电路生成的输出信号的目标频率f TAF-DPS为100Hz时，则第一电子设备61的输出信号的时间粒度为0.01s，且由于d1>1/f TAF-DPS，由此第一电子设备61可以修正其与第二电子设备62之间的时间误差，且修正的时间为0.07s，从而第一电子设备61和第二电子设备62的时间完全同步；而当目标频率f TAF-DPS为200Hz时，虽然d1>1/f TAF-DPS，但第一电子设备61的输出信号的时间粒度为0.02s，第一电子设备61无法完全修正其与第二电子设备62之间的时间误差，第一电子设备61可以修正的时间为0.06s，此时，第一电子设备61与第二电子设备62之间的修正后的时间误差为0.01s。若第一电子设备61与第二电子设备62之间的时间误差阈值为0.02s，修正后的时间误差小于时间误差阈值，则修正后的第一电子设备61的时钟信号满足时间同步系统的时间同步 需求。
图13示出了本公开至少一实施例提供的一种时间同步方法的示意性流程图。本公开至少一实施例提供的时间同步方法可以应用于本公开任一实施例所述的时间同步装置中。
例如，如图13所示，时间同步方法可以包括以下步骤：
S11：生成频率控制字；
S12：根据频率控制字和输入信号，生成并输出具有目标频率的输出信号；
S13：基于具有目标频率的输出信号对电子设备的时钟信号进行同步调节。
本公开实施例提供的时间同步方法可以合成目标频率足够大的输出信号，即输出信号的频率粒度较高，从而使各个电子设备获得更精准的同步时钟，各个电子设备在网络系统中的工作协调性和一致性更好。
例如，步骤S11可以包括：通过参数获取电路检测晶振漂移的影响参数；根据晶振漂移的影响参数生成频率控制字；输出频率控制字至信号调节电路。
例如，步骤S12可以包括：接收具有初始频率的输入信号，基于具有初始频率的输入信号，生成并输出基准时间单位；根据频率控制字和基准时间单位生成并输出具有目标频率的输出信号。
例如，具有目标频率的输出信号可以由TAF-DPS合成器生成。
需要说明的是，步骤S11和步骤S12可以由本公开任一实施例所述的时间同步装置中的信号生成电路来实现，步骤S13可以由本公开任一实施例所述的时间同步装置中的时间调节电路来实现，在此不再赘述类似的操作或步骤。
例如，在步骤S13中，对电子设备的时钟信号进行同步调节后，可以得到电子设备与时间同步系统中的其余的电子设备的同步时钟信号，且同步时钟信号的精度与电子设备生成的输出信号的目标频率的值正相关。
例如，在一些示例中，时间同步系统可以包括第一电子设备和第二电子设备。时间同步方法可以包括以下步骤：
S21：在第一时间戳，第一电子设备向第二电子设备发送第一网络报文，此时，第一电子设备上的时间为T1，所述第一网络报文包括时间T1；
S22：在第二时间戳，第二电子设备接收第一网络报文，此时，第二电子设备上的时间为T2；
S23：在第三时间戳，第二电子设备向第一电子设备发送第二网络报文，此时，第二电子设备上的时间为T3，所述第二网络报文包括时间T1、时间T2和时间T3；
S24：在第四时间戳，第一电子设备接收第二网络报文，此时，第一电子设备上的时间为T4；
S25：根据时间T1、T2、T3和T4，计算第一电子设备与第二电子设备的同步时间误差；
S26：基于第一电子设备生成的具有目标频率的输出信号对第一电子设备的时钟信号进行同步调节操作，以消除同步时间误差。
例如，在步骤S26中，若第一电子设备生成的输出信号的目标频率为f，而第一电子设备与第二电子设备之间的同步时间误差为ΔT，且ΔT>1/f，则第一电子设备可以较好地修正该同步时间误差，以使第一电子设备与第二电子设备的时间达到同步。
例如，步骤S26可以包括步骤S11-S13。
值得注意的是，图13所示的时间同步方法可以由本公开任一实施例所述的时间同步系统来实现，在此不再赘述类似的操作或步骤。
对于本公开，还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种用于电子设备的时间同步装置，包括：信号生成电路和时间调节电路，
    其中，所述信号生成电路包括：
    控制电路，被配置为生成频率控制字；以及
    信号调节电路，被配置为接收具有初始频率的输入信号和所述频率控制字，并根据所述频率控制字和所述输入信号生成并输出具有目标频率的输出信号，
    所述时间调节电路被配置为基于具有所述目标频率的输出信号对所述电子设备的时钟信号进行同步调节操作。
  2. 根据权利要求1所述的时间同步装置，其中，所述控制电路被配置为根据晶振漂移的影响参数生成所述频率控制字。
  3. 根据权利要求2所述的时间同步装置，其中，所述信号生成电路还包括参数获取电路，所述参数获取电路被配置为获取所述影响参数。
  4. 根据权利要求3所述的时间同步装置，其中，所述晶振漂移的影响参数包括温度参数，所述参数获取电路包括温度检测子电路；
    所述温度检测子电路被配置为检测所述温度参数。
  5. 根据权利要求4所述的时间同步装置，其中，所述温度检测子电路包括温度检测器和第一计数器，
    所述温度检测器被配置为检测环境温度，所述温度参数包括所述环境温度，
    所述第一计数器被配置为根据所述环境温度和参考温度记录频率变化量。
  6. 根据权利要求5所述的时间同步装置，其中，所述控制电路被配置为基于下式根据所述环境温度生成所述频率控制字：
    Figure PCTCN2019082926-appb-100001
    其中，F N表示所述频率控制字，F TO表示与所述参考温度对应的参考频率控制字，f Δ表示基准时间单位的频率，以及
    Δf＝r·ΔT n+p·ΔT n-1+...+d·ΔT+g
    其中，Δf表示所述频率变化量，r、p、d和g为常数，ΔT表示所述环境温度和所述参考温度的差值，ΔT＝T1-T2，T1表示所述环境温度，T2表示所述参考温度，n为正整数。
  7. 根据权利要求3所述的时间同步装置，其中，所述晶振漂移的影响参数包括老化参数，所述参数获取电路包括老化读取子电路；
    所述老化读取子电路被配置为读取晶振源的所述老化参数。
  8. 根据权利要求7所述的时间同步装置，其中，所述老化读取子电路包括老化读取元件和第二计数器，
    所述老化读取元件被配置为读取所述晶振源的老化速率，以及读取与所述老化速率相对应的参考时间，所述老化参数包括所述老化速率和所述参考时间，
    所述第二计数器被配置为记录所述参考时间的数量。
  9. 根据权利要求8所述的时间同步装置，其中，所述控制电路被配置为基于下式根据所述老化速率生成所述频率控制字：
    F N＝F AO·(1+γ)
    其中，F N表示所述频率控制字，F AO表示参考频率控制字，γ表示所述老化参数的乘积，其中，γ＝ν·t，ν表示所述老化速率，t表示所述参考时间的数量，且t为自然数。
  10. 根据权利要求1-9任一所述的时间同步装置，其中，所述信号调节电路包括基准时间单位生成子电路和频率调节子电路，
    基准时间单位生成子电路被配置为接收具有所述初始频率的所述输入信号，并根据所述初始频率生成并输出基准时间单位；以及
    频率调节子电路被配置为根据所述频率控制字和所述基准时间单位生成并输出具有所述目标频率的所述输出信号。
  11. 根据权利要求10所述的时间同步装置，其中，所述基准时间单位生成子电路包括：
    压控振荡器，被配置为以预定振荡频率振荡；
    第一锁相环回路电路，被配置为将所述压控振荡器的输出频率锁定为基准输出频率；
    K个输出端，被配置为输出K个相位均匀间隔的输出信号，其中，K为 大于1的正整数，
    其中，所述基准输出频率表示为f d，所述基准时间单位是所述K个输出端输出的任意两个相邻的输出信号之间的时间跨度，所述基准时间单位表示为△，并且△＝1/(K·f d)。
  12. 根据权利要求10所述的时间同步装置，其中，所述基准时间单位生成子电路包括：压控延迟器、第二锁相环回路电路和K个输出端，
    所述压控延迟器包括一个或者多个级联的延时单元，且被配置为根据所述输入信号和所述第二锁相环回路电路的输出信号产生延时信号；
    所述第二锁相环回路电路被配置为根据所述输入信号和所述延时信号将所述压控延迟器的输出频率锁定为基准输出频率；
    所述K个输出端，被配置为输出K个相位均匀间隔的输出信号，其中，K为大于1的正整数，
    其中，所述基准输出频率表示为f d，所述基准时间单位是所述K个输出端输出的任意两个相邻的输出信号之间的时间跨度，所述基准时间单位表示为△，并且△＝1/(K·f d)。
  13. 根据权利要求11或12所述的时间同步装置，其中，所述频率调节子电路被配置为基于下式根据所述频率控制字和所述基准时间单位确定所述目标频率：
    f TAF-DPS＝1/(F·△)＝(K·f d)/F
    其中，f TAF-DPS表示所述目标频率，F表示所述频率控制字。
  14. 根据权利要求11-13任一项所述的时间同步装置，其中，所述频率调节子电路包括时间平均频率直接周期合成器。
  15. 一种电子设备，包括根据权利要求1-14任一所述的时间同步装置。
  16. 根据权利要求15所述的电子设备，还包括频率源，
    其中，所述频率源被配置为提供具有所述初始频率的输入信号。
  17. 一种时间同步系统，包括：多个电子设备，
    其中，所述多个电子设备中的至少一个为根据权利要求15或16所述的电子设备。
  18. 一种时间同步方法，应用于根据权利要求1-14任一项所述的时间同步装置，所述时间同步方法包括：
    生成频率控制字；
    根据所述频率控制字和所述输入信号，生成并输出具有所述目标频率的输出信号；以及
    基于具有所述目标频率的输出信号对所述电子设备的时钟信号进行同步调节操作。
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