WO2019237748A1 - 像素电路及其驱动方法、显示装置 - Google Patents

像素电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2019237748A1
WO2019237748A1 PCT/CN2019/073218 CN2019073218W WO2019237748A1 WO 2019237748 A1 WO2019237748 A1 WO 2019237748A1 CN 2019073218 W CN2019073218 W CN 2019073218W WO 2019237748 A1 WO2019237748 A1 WO 2019237748A1
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Prior art keywords
light
control signal
emitting
circuit
driving
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PCT/CN2019/073218
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English (en)
French (fr)
Inventor
陈亮
王磊
刘冬妮
肖丽
玄明花
陈小川
杨盛际
卢鹏程
赵德涛
丛宁
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2019546841A priority Critical patent/JP7419069B2/ja
Priority to EP19755798.6A priority patent/EP3813052A4/en
Priority to US16/484,621 priority patent/US11450270B2/en
Publication of WO2019237748A1 publication Critical patent/WO2019237748A1/zh
Priority to JP2024000333A priority patent/JP2024028385A/ja

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0804—Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
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    • G—PHYSICS
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    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
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    • G09G2330/021—Power management, e.g. power saving

Definitions

  • Embodiments of the present disclosure relate to a pixel circuit, a driving method thereof, and a display device.
  • AMOLED Active Matrix Light Emitting Diode
  • a display panel generally includes a plurality of pixel units arranged in an array, and each pixel unit includes a light emitting unit and a single pixel compensation circuit connected to the light emitting unit.
  • the pixel compensation circuit can avoid the problem that there is a difference in the magnitude of the current flowing through the light-emitting unit due to the threshold voltage of the driving transistor that drives the light-emitting unit, thereby ensuring the uniformity of the display brightness of the display panel.
  • the pixel compensation circuit occupies a larger area of the circuit board, which is not conducive to the realization of a narrow-frame display panel.
  • At least one embodiment of the present disclosure provides a pixel circuit.
  • the pixel circuit includes a plurality of sets of pixel compensation circuits arranged in an array.
  • Each set of pixel compensation circuits includes K rows of pixel compensation circuits, where K is an integer greater than 1, and each The row pixel compensation circuit includes at least one pixel compensation circuit;
  • Each of the pixel compensation circuits is configured to allow connection with a group of light emitting units in operation, and each group of the light emitting units includes M light emitting units located in a same column, where M is an integer greater than 1;
  • the pixel circuit further includes a plurality of sets of light emitting control signal terminals corresponding to the plurality of sets of pixel compensation circuits, each group of light emitting control signal terminals including M light emitting control signal terminals, and each pixel in each group of pixel compensation circuits compensates
  • the circuits are connected to M light-emitting control signal terminals of a corresponding group of light-emitting control signal terminals;
  • Each of the M light-emitting control signal terminals connected to each of the pixel compensation circuits corresponds to one of the M light-emitting units connected to the pixel compensation circuit, and each of the light-emitting control signal terminals is used to pass through the pixel compensation circuit connected to To drive the corresponding light-emitting unit to emit light.
  • the pixel circuit further includes a plurality of total light emission control signal terminals corresponding to the plurality of sets of pixel compensation circuits, each of the total light emission control signal terminals and each of the corresponding set of pixel compensation circuits. Pixel compensation circuits are connected.
  • the M light-emitting units in the same column in each group of light-emitting units are adjacent to each other.
  • the K-row pixel compensation circuits in each group of pixel compensation circuits are adjacent to each other.
  • K 2.
  • the m-th light-emitting control signal terminal of the M light-emitting control signal terminals connected to each of the pixel compensation circuits corresponds to the m-th light-emitting unit of the M light-emitting units connected to the pixel compensation circuit.
  • M is a positive integer not greater than M.
  • each of the pixel compensation circuits includes a reset sub-circuit, a first light-emitting control sub-circuit, and M second light-emitting control sub-circuits;
  • the reset sub-circuit is connected to a reset signal terminal and a reset power supply terminal, respectively, and the reset sub-circuit is connected to the first light-emitting control sub-circuit at a first node, and the reset sub-circuit is configured to respond to A reset signal from the reset signal terminal, inputting a reset power signal from the reset power terminal to the first node;
  • the first light-emitting control sub-circuit is connected to the total light-emitting control signal terminal, power source terminal, data signal terminal, and driving power terminal, and the first light-emitting control sub-circuit is connected to the M second light-emitting control sub-circuits.
  • the first light-emitting control sub-circuit Connected to the second node, the first light-emitting control sub-circuit is configured to respond to the potential of the first node, a total light-emitting control signal from the total light-emitting control signal terminal, a power signal from a power source terminal, and from the driver.
  • a driving power signal at a power terminal inputting a data signal from the data signal terminal to the second node;
  • Each of the second light-emitting control sub-circuits is respectively connected to a light-emitting control signal terminal and a light-emitting unit of a corresponding set of light-emitting control signal terminals, and each of the second light-emitting control sub-circuits is configured to respond to The light-emitting control signal provided by the connected light-emitting control signal terminal drives the light-emitting unit connected to it to emit light.
  • each of the second light emission control sub-circuits includes: a first transistor
  • a gate of the first transistor is connected to a light-emitting control signal terminal, a first pole of the first transistor is connected to the second node, and a second pole of the first transistor is connected to a light-emitting unit.
  • the reset sub-circuit includes: a second transistor
  • a gate of the second transistor is connected to the reset signal terminal, a first pole of the second transistor is connected to a reset power terminal, and a second pole of the second transistor is connected to the first node;
  • the first light emission control sub-circuit includes: a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a storage capacitor;
  • a gate of the third transistor is connected to the driving power terminal, a first pole of the third transistor is connected to the data signal terminal, and a second pole of the third transistor is connected to a third node;
  • the gate of the fourth transistor is connected to the total light emission control signal terminal, the first pole of the fourth transistor is connected to the third node, and the second electrode of the fourth transistor is connected to the power terminal. ;
  • a gate of the fifth transistor is connected to the first node, a first pole of the fifth transistor is connected to the third node, and a second pole of the fifth transistor is connected to the second node;
  • a gate of the sixth transistor is connected to the driving power terminal, a first pole of the sixth transistor is connected to the first node, and a second pole of the sixth transistor is connected to the second node;
  • One end of the storage capacitor is connected to the power supply terminal, and the other end of the storage capacitor is connected to the first node.
  • At least one embodiment of the present disclosure provides a driving method of a pixel circuit, which is applied to the pixel circuit as described above, the method includes: driving the pixel circuit through M driving subframes, each of the driving subframes Including multiple driving stages, the number of driving stages included in each of the driving subframes is equal to the number of groups of pixel compensation circuits included in the pixel circuit and the number of groups of light emission control signal ends, and the multiple driving stages are equal to One-to-one correspondence of multiple groups of light-emitting control signal ends;
  • the driving the pixel circuit by M driving sub-frames includes: in a light-emitting sub-phase of each of the driving phases, one target light-emitting control of the M light-emitting control signal terminals included in a corresponding set of light-emitting control signal terminals.
  • the potential of the target light emission control signal provided by the signal terminal is an effective potential, and the potential of the light emission control signal provided by other light emission control signal terminals except the target light emission control signal terminal is an invalid potential, and is connected to the target light emission control signal terminal.
  • a group of pixel compensation circuits under the control of the target light emission control signal drives a light emitting unit corresponding to the target light emission control signal terminal to emit light.
  • the pixel circuit further includes a plurality of total light emission control signal terminals corresponding to the plurality of sets of pixel compensation circuits, each of the total light emission control signal terminals and each of the corresponding set of pixel compensation circuits.
  • the driving of the pixel circuit by M driving sub-frames includes: a total light-emission control corresponding to a group of pixel compensation circuits connected to the target light-emission control signal end in each light-emitting sub-phase of the driving phase.
  • the potential of the total emission control signal provided by the signal terminal is an effective potential.
  • each group of light-emitting units includes two light-emitting units located in the same column and adjacent to each other, and each group of light-emitting control signal terminals includes two light-emitting control signal terminals; and the driving of the pixel circuit through M driving sub-frames includes: Driving the pixel circuit through two driving subframes;
  • the driving the pixel circuit through two driving subframes includes:
  • the potential of the light-emitting control signal provided by one of the light-emitting control signal terminals corresponding to the driving phase is an effective potential
  • the potential of the lighting control signal provided by the other lighting control signal terminal is an invalid potential
  • the potential of the light-emitting control signal provided by the other light-emitting control signal terminal in a set of light-emitting control signal terminals corresponding to the driving phase is
  • the effective potential is a potential of a lighting control signal provided by one lighting control signal terminal other than the other lighting control signal terminal as an invalid potential.
  • each of the pixel compensation circuits includes a reset sub-circuit, a first light-emitting control sub-circuit, and M second light-emitting control sub-circuits; each of the driving stages further includes: Reset sub-phase and K compensation sub-phases;
  • the driving the pixel circuit through the M driving subframes further includes:
  • a potential of a reset signal provided by a reset signal terminal of the first row of pixel compensation circuits is an effective potential
  • the reset sub-circuit inputs a reset power signal from a reset power terminal to the first node
  • the potential of the driving power signal provided by the driving power terminal connected to the pixel compensation circuit in the k-th row is an effective potential, so
  • the potential of the total light-emission control signal provided by the total light-emission control signal terminal connected to the group of pixel compensation circuits is an inactive potential, and the first light-emission control sub-circuit of each pixel compensation circuit in the k-th pixel compensation circuit responds to the Driving the power signal, the potential of the first node, and the power signal provided by the power terminal to input a data signal from the data signal terminal to the second node, where k is a positive integer not greater than K;
  • the potentials of the total light-emitting control signals connected to the group of pixel compensation circuits are effective potentials.
  • M second light-emitting control sub-circuits of each pixel compensation circuit In response to the target light emission control signal, the second light emission control sub-circuit connected to the target light emission control signal terminal drives the light emitting unit connected to the light emission unit to emit light.
  • At least one embodiment of the present disclosure provides a display device including the pixel circuit described above and a plurality of groups of light emitting units, each group of the light emitting units including M light emitting units, where M is an integer greater than 1. ;
  • Each pixel compensation circuit in the pixel circuit is connected to a group of the light emitting units.
  • FIG. 1 is a schematic structural diagram of a pixel circuit provided by at least one embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of another pixel circuit provided by at least one embodiment of the present disclosure.
  • FIG. 3 is a schematic structural diagram of a pixel compensation circuit provided by at least one embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of another pixel compensation circuit provided by at least one embodiment of the present disclosure.
  • FIG. 5 is a flowchart of a driving method of a pixel circuit provided by at least one embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of dividing a frame scanning time into two driving subframes according to at least one embodiment of the present disclosure
  • FIG. 7 is a timing diagram of a driving process of a pixel circuit provided by at least one embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a display device provided by at least one embodiment of the present disclosure.
  • the transistors used in all the embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics.
  • the transistors used in the embodiments of the present disclosure are mainly switching transistors. Since the source and drain of the switching transistor used here are symmetrical, the source and drain of the switching transistor are interchangeable.
  • the source is referred to as a first stage, and the drain is referred to as a second stage.
  • the middle end of the transistor is specified as the gate, the signal input end is the source, and the signal output end is the drain.
  • the switching transistor used in the embodiment of the present disclosure may include any one of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low level and turned off when the gate is at a high level
  • the N-type switching transistor is turned on when the gate is high and turned off when the gate is low.
  • the “effective potential” mentioned in the present disclosure refers to a potential that makes the switching transistor on, and the “invalid potential” mentioned in the present disclosure refers to a potential that makes the switching transistor off.
  • an OLED display device generally includes a plurality of pixel units arranged in an array, and each pixel unit may include a corresponding light-emitting driving circuit, for example.
  • the threshold voltage of the driving transistor in each light-emitting driving circuit may be different due to a manufacturing process, and the threshold voltage of the driving transistor may have a drift phenomenon due to, for example, the influence of temperature change. Therefore, the difference in the threshold voltage of each driving transistor may cause poor display (such as uneven display), so it is necessary to compensate the threshold voltage.
  • the off state due to the existence of leakage current, it may cause display failure.
  • the industry also provides other light-emitting drive circuits with compensation functions on the basis of the basic light-emitting drive circuits of 2T1C (that is, two transistors and one capacitor).
  • the compensation function can be implemented by voltage compensation, current compensation, or hybrid compensation.
  • the pixel circuit of the compensation function may be, for example, 4T1C or 4T2C, which is not described in detail here.
  • FIG. 1 is a schematic structural diagram of a pixel circuit provided by at least one embodiment of the present disclosure.
  • the pixel circuit may include: a plurality of groups of pixel compensation circuits 01 arranged in an array, and each group of pixel compensation circuits 01 may include The K-line pixel compensation circuit 011, K is an integer greater than 1, and each row of the pixel compensation circuit includes at least one pixel compensation circuit 011.
  • FIG. 1 shows only one pixel compensation circuit 011 in each row of pixel compensation circuits.
  • each row of pixel compensation circuits may include multiple pixel compensation circuits 011.
  • each pixel compensation circuit 011 is configured to allow connection with a group of light-emitting units 02 in operation.
  • Each group of light-emitting units 02 may include M light-emitting units 021 located in the same column, where M is greater than 1. Integer.
  • the pixel circuit may further include a plurality of sets of light-emitting control signal terminals 03 corresponding to the plurality of sets of pixel compensation circuits 01, each group of light-emitting control signal terminals 03 may include M light-emitting control signal terminals EM, and each group of pixel compensation circuits Each pixel compensation circuit 011 in 01 may be connected to a corresponding set of M light-emitting control signal terminals EM in a corresponding set of light-emitting control signal terminals 03.
  • each pixel compensation circuit 011 may be connected to two light emission control signal terminals EM of the group of light emission control signal terminals 03. That is, each light-emitting control signal terminal EM in each group of light-emitting control signal terminals 03 can be connected to each group of pixel compensation circuits 01 (each group of pixel compensation circuits 01 can include K-line pixel compensation circuits, where K is an integer greater than 1)
  • Each of the pixel compensation circuits 011 is connected.
  • the number of signal terminals required to be set in the pixel circuit is reduced, and the area occupied by the pixel compensation circuit is reduced.
  • Each of the M light-emitting control signal terminals EM connected to each pixel compensation circuit 011 corresponds to the M light-emitting units 021 connected to the pixel compensation circuit 011, and each light-emitting control signal terminal EM can be used to pass the pixel compensation circuit connected to it.
  • the pixel circuit provided in at least one embodiment of the present disclosure may include M driving sub-frames when driving the light-emitting unit 021 to emit light, and each driving sub-frame may include a plurality of driving stages corresponding to the plurality of sets of light-emitting control signal terminals 03 one-to-one. .
  • each driving phase a group of light-emitting control signal terminals 03 corresponding to the driving phase in a plurality of groups of light-emitting control signal terminals 03 are in a working state, and there is only one target light-emitting control signal terminal in the group of light-emitting control signal terminals 03.
  • the potential of the light-emitting control signal provided is an effective potential, and the potential of the light-emitting control signal provided by each light-emitting control signal terminal except the one target light-emitting control signal terminal is an invalid potential. That is, in each driving stage of each driving sub-frame, among a group of pixel compensation circuits 01 connected to the group of light-emitting control signal terminals 03 in the working state, each pixel compensation circuit 011 is connected to M lights. Of the units 021, only the light-emitting unit 021 corresponding to the target light-emitting control signal terminal can emit light under the driving of the target light-emitting control signal.
  • the potential of the light-emitting control signal provided by the first light-emitting control signal terminal EM may be an effective potential, that is, the first light-emitting control signal terminal EM is the target light-emitting control signal terminal.
  • the light-emitting unit 021 corresponding to the EM emits light.
  • the potential of the lighting control signal provided by the second lighting control signal terminal EM in the set of lighting control signal terminals 03 corresponding to the driving phase may be an effective potential, that is, the first
  • the two light emission control signal terminals EM are target light emission control signal terminals.
  • the light emitting unit 021 corresponding to the second light emission control signal terminal EM emits light.
  • the pixel circuit provided by some embodiments of the present disclosure includes multiple pixel compensation circuits, and since each pixel compensation circuit can be connected to M light-emitting units located in the same column, that is, one pixel compensation circuit can be used for The M light-emitting units are driven, so the number of pixel compensation circuits to be set can be reduced. Further, because of the M light-emitting control signal terminals included in each group of light-emitting control signal terminals, each light-emitting control signal terminal can be connected to a group of pixel compensation circuits (that is, K-line pixel compensation circuits), thereby reducing the required setting. The number of signal terminals further reduces the area occupied by the pixel circuit on the circuit board, which is more conducive to the realization of a narrow-frame display panel.
  • FIG. 2 is a schematic structural diagram of another pixel circuit provided by at least one embodiment of the present disclosure.
  • the pixel circuit may further include a plurality of total light emission control signal terminals corresponding to the plurality of sets of pixel compensation circuits 01 one-to-one.
  • each total light emission control signal end EMC may be connected to each pixel compensation circuit 011 in a corresponding set of pixel compensation circuits 01.
  • one total light emission control signal end EMC may be connected to two rows of pixel compensation circuits 011 in a group of pixel compensation circuits 01.
  • the total light emission control signal terminal EMC can drive a group of light emitting units 02 connected to the pixel compensation circuit 011 to emit light through each pixel compensation circuit 011 connected to the pixel compensation circuit 011.
  • each total light emission control signal end EMC may be connected to each pixel compensation circuit 011 in a corresponding set of pixel compensation circuits 01 (that is, K-line pixel compensation circuits), and since each The pixel compensation circuit 011 can be connected to a group of light-emitting units 02 (each group of light-emitting units 02 can include M light-emitting units 021 located in the same column), so the one total light-emitting control signal terminal EMC can pass through the group of pixel compensation circuits 01 Each of the pixel compensation circuits 011 drives M ⁇ K rows of light-emitting units to emit light.
  • a total light emitting control signal terminal EMC drives a row of light emitting units through a row of pixel compensation circuits 011 connected to it, further reducing the number of signal terminals required in the pixel circuit, thereby reducing the area occupied by the pixel circuit.
  • each group of light-emitting units 02 includes two light-emitting units 021 located in the same column, and a group of pixel compensation circuits 01 includes two rows of pixel compensation circuits 011, a light-emitting control signal end EMC can pass a group of The pixel compensation circuit 01 drives the four rows of light-emitting units 021 to operate.
  • one light emitting control signal terminal EM can control two rows of light emitting units; Compared with the related art, one light-emitting control signal terminal EM controls a row of light-emitting units, and the setting of the light-emitting control signal terminal EM is reduced by a half.
  • one total light emission control signal terminal EMC can control four rows of light-emitting units; compared to one related art, the total light emission control signal terminal EMC controls one or two lines of light-emitting units, which effectively reduces the required setting. The number of total light emission control signal ends EMC.
  • each group of the light-emitting units 02 may include M light-emitting units 021 located in the same column and adjacent to each other. Adjacent M light-emitting units 021 share a pixel compensation circuit 011, which can minimize the trace length between the light-emitting unit 021 and the pixel compensation circuit 011, which can reduce the wiring cost of the display panel and simplify the manufacturing process of the display panel.
  • M 2
  • a pixel compensation circuit 011 common to the two light-emitting units 021 may be provided in the two light-emitting units 021. Between, which can further reduce wiring costs.
  • each group of pixel compensation circuits 01 may include adjacent K rows of pixel compensation circuits.
  • the pixel compensation circuits 01 located in adjacent rows as a group, it is possible to prevent the light emission control signal terminal EM from connecting the pixel compensation circuits 01 across the rows, thereby reducing wiring costs.
  • each group of pixel compensation circuits 01 may further include two adjacent rows of pixel compensation circuits 011.
  • each Each light-emitting control signal terminal EM is only connected to two rows of pixel compensation circuits 011, that is, one control signal terminal EM only needs to control the work of two rows of light-emitting units 021 at the same time, so as to reduce the area occupied by the pixel compensation circuit while avoiding display The display effect of the panel affects.
  • the m-th light-emitting control signal terminal of the M light-emitting control signal terminals connected to each pixel compensation circuit corresponds to the m-th light-emitting unit of the M light-emitting units connected thereto, m Is a positive integer not greater than M.
  • the first light-emitting control signal terminal EM of each group of light-emitting control signal terminals 03 may sequentially output a light-emitting control signal of an effective potential.
  • the first light-emitting control signal terminal EM in each group of light-emitting control signal terminal 03 corresponds to the first light-emitting unit 021 of the two light-emitting units 021 connected to the pixel compensation circuit 011 connected to the light-emitting control signal terminal EM, therefore The first light-emitting control signal terminal EM in each group of light-emitting control signal terminals 03 can sequentially drive the light-emitting units 021 of odd-numbered rows to emit light row by row through the pixel compensation circuit 011 connected thereto, thereby achieving the light-emitting unit 021.
  • the line spacing is driven in an orderly manner.
  • FIG. 3 is a schematic structural diagram of a pixel compensation circuit provided by at least one embodiment of the present disclosure.
  • each pixel compensation circuit 011 may include a reset sub-circuit 10, a first light-emitting control sub-circuit 20, and M Second emission control sub-circuit 30.
  • reset sub-circuit 10 a reset sub-circuit 10
  • first light-emitting control sub-circuit 20 a first light-emitting control sub-circuit 20
  • M Second emission control sub-circuit 30 For example, two second light emission control sub-circuits 30 are shown in FIG.
  • the reset sub-circuit 10 may be connected to a reset signal terminal RST, a reset power terminal Vint, and a first node P1, respectively.
  • the reset sub-circuit 10 may be configured to respond to a reset signal from the reset signal terminal RST to the first node.
  • a node P1 inputs a reset power signal from the reset power terminal Vint.
  • the reset sub-circuit 10 may input a reset power signal from the reset power terminal Vint to the first node P1, and the potential of the reset power signal may be Effective potential.
  • the first light-emitting control sub-circuit 20 may be connected to a first node P1, a total light-emitting control signal terminal EMC, a power terminal ELVDD, a data signal terminal D, a driving power terminal G, and a second node P2, respectively.
  • the light emission control sub-circuit 20 may be configured to respond to the potential of the first node P1, the total light emission control signal from the total light emission control signal terminal EMC, the power signal from the power terminal ELVDD, and the driving power signal from the driving power terminal G to the first
  • the two node P2 inputs a data signal from the data signal terminal D.
  • the first light-emitting control sub-circuit 20 may input a data signal from the data signal terminal D to the second node P2.
  • the pixel compensation circuits located in the same row may be connected to the same driving power terminal G. Since each pixel compensation circuit may be connected to M light-emitting units located in the same column, one driving power terminal G is M rows of light-emitting units can be driven to work by a row of pixel compensation circuits. Compared with the related art, one driving power terminal G can only drive one row of light-emitting units, the number of driving power terminals G required in the pixel circuit provided by some embodiments of the present disclosure is small, and the occupied area of the pixel circuit is small.
  • each second light-emitting control sub-circuit 30 may be respectively connected to a second node P2, one light-emitting control signal terminal EM and a light-emitting unit 021 of a corresponding group of light-emitting control signal terminals, and each second light-emitting control The sub-circuit 30 may be configured to drive a light-emitting unit 021 connected to the light-emitting unit 021 to emit light in response to a light-emitting control signal provided from a light-emitting control signal terminal EM connected to the sub-circuit 30.
  • the second light emission control sub-circuit 30 may drive the light emitting unit 021 corresponding to the light emission control signal terminal EM to emit light. .
  • FIG. 4 is a schematic structural diagram of another pixel compensation circuit provided by at least one embodiment of the present disclosure. As shown in FIG. 4, each of the second light emission control sub-circuits 30 may include a first transistor M1.
  • each pixel compensation circuit 011 is connected to two light-emitting units 021 located in the same column.
  • the one pixel compensation circuit may include two first transistors M1, each The gate of the first transistor M1 may be connected to a light-emitting control signal terminal EM, the first pole of the first transistor M1 may be connected to the second node P2, and the second pole of the first transistor M1 may be connected to a light-emitting unit 021.
  • the other end of each light-emitting unit 021 may also be connected to a low-level power supply terminal ELVSS.
  • the light-emitting unit may be an organic light-emitting diode (OLED) or an AMOLED.
  • the reset sub-circuit 10 may include a second transistor M2.
  • the gate of the second transistor M2 may be connected to the reset signal terminal RST, the first pole of the second transistor M2 may be connected to the reset power terminal Vint, and the second pole of the second transistor M2 may be connected to the first node P1.
  • the first light emission control sub-circuit 20 may include a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a storage capacitor C.
  • a gate of the third transistor M3 may be connected to a driving power terminal G, a first pole of the third transistor M3 may be connected to a data signal terminal D, and a second pole of the third transistor M3 may be connected to a third Node P3 is connected.
  • the gate of the fourth transistor M4 may be connected to the total light emission control signal terminal EMC, the first pole of the fourth transistor M4 may be connected to the third node P3, and the second pole of the fourth transistor M4 may be connected to the power supply terminal ELVDD.
  • the gate of the fifth transistor M5 may be connected to the first node P1, the first pole of the fifth transistor M5 may be connected to the third node P3, and the second pole of the fifth transistor M5 may be connected to the second node P2.
  • the gate of the sixth transistor M6 may be connected to the driving power terminal G, the first pole of the sixth transistor M6 may be connected to the first node P1, and the second pole of the sixth transistor M6 may be connected to the second node P2.
  • One end of the storage capacitor C may be connected to the power supply terminal ELVDD, and the other end may be connected to the first node P1.
  • a pixel compensation circuit is used to drive multiple light-emitting units to reduce the number of pixel compensation circuits to be set, thereby reducing the area occupied by the pixel compensation circuit.
  • each light emission control signal terminal and each total light emission control signal terminal are connected to each pixel compensation circuit in a group of pixel compensation circuits (ie, K-line pixel compensation circuits), reducing pixels. The number of signal terminals required for the circuit. Therefore, the pixel circuit provided by some embodiments of the present disclosure occupies a small area, which can effectively improve the PPI of the display panel.
  • the pixel compensation circuit may also have other structures such as 6T1C or 9T1C.
  • the pixel compensation circuit is not limited in this embodiment of the present disclosure.
  • each transistor in each of the above embodiments, description is made by taking each transistor as a P-type transistor and the effective potential as a low potential as an example.
  • each transistor may also be an N-type transistor.
  • the effective potential is a high potential.
  • the pixel circuit provided by some embodiments of the present disclosure includes multiple pixel compensation circuits, and since each pixel compensation circuit can be connected to M light-emitting units located in the same column, that is, one pixel compensation circuit can be used for The M light-emitting units are driven, so the number of pixel compensation circuits to be set can be reduced. Further, because of the M light-emitting control signal terminals included in each group of light-emitting control signal terminals, each light-emitting control signal terminal can be connected to a group of pixel compensation circuits (that is, K-line pixel compensation circuits), thereby reducing the required setting. The number of signal terminals further reduces the area occupied by the pixel circuit on the circuit board, which is more conducive to the realization of a narrow-frame display panel.
  • At least one embodiment of the present disclosure provides a method for driving a pixel circuit.
  • the method may be applied to the pixel circuit shown in FIG. 1.
  • the method may include: driving the pixel circuit through M driving subframes.
  • the number of driving subframes included in the driving method is equal to the number of light emitting units connected to each pixel compensation circuit.
  • the M driving subframes correspond to the M light-emitting units connected to each pixel compensation circuit one by one.
  • the M light-emitting units connected to each pixel compensation circuit correspond to the driving subframe.
  • the corresponding one light-emitting unit emits light, and the other M-1 light-emitting units do not emit light.
  • Each driving sub-frame may include multiple driving stages, and the number of driving stages included in each driving sub-frame may be equal to the number of groups of pixel compensation circuits included in the pixel circuit and the number of groups of the light emitting control signal end.
  • Each driving phase corresponds to a plurality of sets of light-emitting control signal terminals.
  • Driving the pixel circuit through the M driving sub-frames may include: in a light-emitting sub-phase of each driving phase, one of the M light-emitting control signal terminals included in a corresponding set of light-emitting control signal terminals includes a target provided by the light-emitting control signal terminal.
  • the potential of the light-emitting control signal is an effective potential.
  • the potential of the light-emitting control signal provided by the other light-emitting control signal terminals except the target light-emitting control signal terminal is an invalid potential.
  • a group of pixel compensation circuits connected to the target light-emitting control signal terminal can be at the target. Under the control of the light emission control signal, the corresponding light emitting unit is driven to emit light. That is, in each driving stage included in each driving subframe, only one light emitting unit in a group of light emitting units connected to each pixel compensation circuit emits light.
  • the other light-emitting control signal terminals other than the target light-emitting control signal terminal refer to M-1 light-emitting control signal terminals other than one target light-emitting control signal terminal of the corresponding group of light-emitting control signal terminals, and the multiple Among the group of light emission control signal terminals, the other group of light emission control signal terminals other than the corresponding group of light emission control signal terminals.
  • the method for driving a pixel circuit is because a set of pixel compensation circuits (i.e., K-line pixel compensation circuits) connected to a target control signal end in a light-emitting sub-stage of each driving stage. )
  • the corresponding light emitting unit can be driven to emit light under the control of the target light emission control signal end. Therefore, the number of signal terminals to be set is reduced, the area of the circuit board occupied by the pixel circuit is further reduced, and the realization of the narrow-frame display panel is more favorable.
  • the pixel circuit may further include a plurality of total light emission control signal terminals EMC corresponding to the one-to-one group of the pixel compensation circuits 01, and each of the total light emission control signal terminals EMC may correspond to a corresponding one of the pixel compensation circuits 01.
  • Each pixel compensation circuit 011 is connected.
  • driving the pixel circuit by the M driving sub-frames may further include: in a light-emitting sub-phase of each driving phase, a total light-emitting control signal terminal corresponding to a group of pixel compensation circuits connected to the target light-emitting control signal terminal is provided The potential of the total light emission control signal is the effective potential.
  • each group of light emitting units may include two adjacent light emitting units located in the same column, and each group of light emitting control signal terminals may include two light emitting control signal terminals.
  • driving the pixel circuit by the M driving subframes may include: driving the pixel circuit by the two driving subframes.
  • Driving a pixel circuit through two driving subframes may include:
  • the potential of the light-emitting control signal provided by one light-emitting control signal terminal of a set of light-emitting control signal terminals corresponding to the driving phase may be an effective potential.
  • the potential of the light-emitting control signal provided by a light-emitting control signal terminal may be an invalid potential;
  • the potential of the light-emitting control signal provided by another light-emitting control signal terminal of a set of light-emitting control signal terminals corresponding to the driving phase may be an effective potential
  • the potential of the lighting control signal provided by one lighting control signal terminal other than the other lighting control signal terminal may be an invalid potential.
  • each group of pixel compensation circuits may include adjacent K rows of pixel compensation circuits.
  • each light-emitting sub-phase in the K-row pixel compensation circuit, one light-emitting unit connected to each pixel compensation circuit emits light.
  • each pixel compensation circuit may include a reset sub-circuit 10, a first light-emitting control sub-circuit 20, and M second light-emitting control sub-circuits 30.
  • each driving stage may further include a reset sub-stage and K compensation sub-stages located before the light-emitting sub-stage.
  • FIG. 5 is a flowchart of a driving method of a pixel circuit provided by at least one embodiment of the present disclosure. As shown in FIG. 5, the method may include:
  • Step 501 In the reset sub-phase, among a group of pixel compensation circuits connected to a set of light-emitting control signal terminals corresponding to the driving phase, the potential of the reset signal provided by the reset signal terminal of the first row of pixel compensation circuits is an effective potential, In response to the reset signal, the reset sub-circuit inputs a reset power signal from the reset power terminal to the first node.
  • the potentials of the total light emission control signals provided by the total light emission control signal terminals connected to each group of pixel compensation circuits are all inactive potentials.
  • Step 502 In the k-th compensation sub-phase of the K compensation sub-phases, in the group of pixel compensation circuits, the potential of the driving power signal provided by the driving power terminal connected to the k-th row pixel compensation circuit is an effective potential, and the group The potential of the total light-emission control signal provided by the total light-emission control signal terminal connected to the pixel compensation circuit is an invalid potential.
  • the first light-emission control sub-circuit of each pixel compensation circuit in the k-th pixel compensation circuit responds to the driving power signal and the first node. And the power signal provided by the power terminal, input a data signal from the data signal terminal to the second node, and k is a positive integer not greater than K.
  • Step 503 In the light-emitting sub-phase, the potential of the total light-emitting control signal connected to the group of pixel compensation circuits is an effective potential.
  • the M second light-emitting control sub-circuits of each pixel compensation circuit are connected to the target.
  • the second light-emitting control sub-circuit connected to the light-emitting control signal terminal drives the light-emitting unit connected thereto to emit light in response to the target light-emitting control signal.
  • the pixel circuit shown in FIG. 2 (that is, M and K are both 2) is taken as an example, and the pixel compensation circuit shown in FIG. 4 is taken as an example, and each transistor in the pixel compensation circuit is P Type transistor, which details the driving principle of the pixel circuit provided by some embodiments of the present disclosure.
  • the pixel circuit can scan the light-emitting units in the display panel in a frame of 1F.
  • the time is divided into two driving subframes SF1 and SF2.
  • the pixel circuit may drive the odd-numbered rows of light-emitting units in the display panel to emit light row by row, that is, in the first driving sub-frame SF1, the pixel circuit may sequentially drive the first In the second driving sub-frame SF2, the pixel circuit can drive the even-numbered rows of the light-emitting units in the display panel to emit light one by one, that is, In the second driving sub-frame SF2, the pixel circuit can sequentially drive the light-emitting units of the second, fourth, and sixth rows to the even-numbered rows of the last row in the display panel to emit light.
  • the first driving subframe SF1 may include a plurality of driving phases, and an i-th of the plurality of driving phases (i is a positive integer not greater than the number of driving phases included in each driving subframe)
  • the i-th group of light-emitting control signal terminals corresponding to the i-th driving stage Qi can drive the i-th group of pixel compensation circuits to operate.
  • the first-row pixel compensation circuit is the n-th row pixel compensation circuit in the display panel, as shown in FIG.
  • the drive power terminal G (n-1) connected to the pixel compensation circuit of the n-th row of pixel compensation circuits in the display panel (that is, the n-1th row) is used as the n-th
  • the reset signal terminal of the row pixel compensation circuit provides a reset signal at an effective potential.
  • the second transistor M2 of each pixel compensation circuit in the pixel compensation circuit in the nth row of the display panel is turned on, and the reset power supply terminal Vint inputs a reset power signal at an effective potential to the first node P1 through the second transistor M2.
  • This reset stage T1 can reset the pixel compensation circuit in the n-th row.
  • the fifth transistor M5 of each pixel compensation circuit in the pixel compensation circuit of the nth row in the display panel is turned on.
  • each driving stage may include two compensation sub-stages T2 and T3.
  • the first-line pixel compensation circuit in the i-th group of pixel compensation circuits (that is, the n-th pixel compensation circuit in the display panel)
  • the potential of the driving power signal provided by the connected driving power terminal G (n) is an effective potential.
  • the third transistor M3 of each pixel compensation circuit in the pixel compensation circuit of the nth row in the display panel is turned on, and the data signal terminal D passes
  • the third transistor M3 and the fifth transistor M5 input a data signal D (n) to the second node P2, and store the data signal and a threshold voltage of the fifth transistor M5 in the storage capacitor C.
  • the first-line pixel compensation circuit in the i-th group of pixel compensation circuits (that is, the n-th pixel compensation circuit in the display panel) is connected
  • the driving power terminal G (n) can also be used as the reset signal terminal of the second row of pixel compensation circuits in the i-th group of pixel compensation circuits (ie, the n + 1th row of pixel compensation circuits in the display panel).
  • the +1 row pixel compensation circuit provides a reset signal at an effective potential.
  • the second transistor M2 of each pixel compensation circuit in the pixel compensation circuit in the n + 1th row of the display panel is turned on, and the reset power supply terminal Vint can input a reset power signal at a valid potential to the first node P1 through the second transistor M2. , So as to reset the pixel compensation circuit of the n + 1th row. That is, the first compensation sub-stage T2 can also be used as a reset sub-stage of the pixel compensation circuit in the (n + 1) th row.
  • the pixel compensation circuit of the second row in the i-th group of pixel compensation circuits (that is, the pixel compensation circuit of the n + 1th row in the display panel) is connected
  • the potential of the driving power signal provided by the driving power terminal G (n + 1) is the effective potential.
  • the third transistor M3 of each pixel compensation circuit in the pixel compensation circuit in the n + 1th row of the display panel is turned on, and because of this,
  • the fifth transistor M5 is also turned on, the data signal terminal D inputs a data signal D (n + 1) to the second node P2 through the third transistor M3 and the fifth transistor M5, and the data signal and the threshold value of the fifth transistor M5
  • the voltage is stored in a storage capacitor C.
  • the first row of pixel compensation circuits and the second row of pixel compensation circuits in the i-th group of pixel compensation circuits ( That is, the potential of the total light emission control signal provided by the total light emission control signal end EMC connected to the nth row pixel compensation circuit and the n + 1th row pixel compensation circuit in the display panel is an invalid potential.
  • the fourth transistor M4 of each pixel compensation circuit in the row pixel compensation circuit, and the fourth transistor M4 of each pixel compensation circuit in the n + 1th row pixel compensation circuit in the display panel are turned off.
  • the total light-emission control signal terminal EMC connected to each pixel compensation circuit in the i-th group of pixel compensation circuits provides the total The potential of the light emission control signal jumps to an effective potential, the fourth transistor M4 of each pixel compensation circuit in the n-th row pixel compensation circuit in the display panel, and the n + 1-th row pixel compensation circuit in the display panel.
  • the fourth transistor M4 of each pixel compensation circuit is turned on.
  • the power terminal ELVDD can input a power signal to the second node P2 through the fourth transistor M4 and the fifth transistor M5.
  • the potential of the light-emitting control signal provided by the first light-emitting control signal terminal EM (n_1) in the i-th group of light-emitting control signal terminals is an effective potential.
  • the pixel compensation circuits in the nth and n + 1th rows of the display panel In each pixel compensation circuit, the first transistor M1 corresponding to the first light-emitting control signal terminal EM (n_1) is turned on, and the second node P2 can drive the light-emitting unit connected to the first transistor M1 to emit light through the first transistor M1.
  • the light-emitting unit corresponding to the first light-emitting control signal terminal EM (n_1) emits light.
  • the first light-emitting unit connected to each pixel compensation circuit in the n-th row pixel compensation circuit in the display panel and the n + 1th in the display panel can emit light simultaneously.
  • a set of pixel compensation circuits when a set of pixel compensation circuits includes two rows of pixel compensation circuits, only one compensation sub-phase needs to be added in each driving phase. Accordingly, the duration of the light-emitting sub-phase in each driving phase is reduced.
  • each driving stage has a compensation sub-phase of 1H
  • the light-emitting time of 1H is correspondingly reduced.
  • the reduced duration of 1H of the light-emitting sub-phase has a negative effect on the display effect of the display panel. The impact is negligible.
  • a light-emitting control signal provided by a second light-emitting control signal terminal EM (n_2) of the i-th group of light-emitting control signal terminals in a light-emitting sub-phase of the i-th driving phase Qi of the second driving sub-frame SF2, a light-emitting control signal provided by a second light-emitting control signal terminal EM (n_2) of the i-th group of light-emitting control signal terminals.
  • the potential of is the effective potential, and the potential of the light-emitting control signal provided by the first light-emitting control signal terminal EM (n_1) of the i-th group of light-emitting control signal terminals jumps to an invalid potential.
  • the first transistor M1 corresponding to the second light emission control signal terminal EM (n_2) in each of the pixel compensation circuits in the nth and n + 1th rows of the pixel compensation circuit in the display panel is turned on, and the second node P2
  • the light emitting unit connected to the first transistor M1 can be driven to emit light by the first transistor M1. That is, a light-emitting unit corresponding to the second light-emitting control signal terminal EM (n_2) in a group of light-emitting units connected to each pixel compensation circuit in the n-th and n + 1-th pixel compensation circuits in the display panel. Glow.
  • the second light-emitting unit connected to each pixel compensation circuit in the n-th row pixel compensation circuit in the display panel and the n + 1th in the display panel can emit light simultaneously.
  • each transistor in each of the above embodiments, description is made by taking each transistor as a P-type transistor and the effective potential as a low potential as an example.
  • each transistor can also be an N-type transistor.
  • the effective potential can be a high potential.
  • the method for driving a pixel circuit is because a set of pixel compensation circuits (i.e., K-line pixel compensation circuits) connected to a target control signal end in a light-emitting sub-stage of each driving stage. ) Under the control of the target light emission control signal end, the corresponding light emitting unit can be controlled to emit light. Therefore, the number of signal terminals to be set is reduced, the area of the circuit board occupied by the pixel circuit is further reduced, and the realization of the narrow-frame display panel is more favorable.
  • a set of pixel compensation circuits i.e., K-line pixel compensation circuits
  • the corresponding light emitting unit Under the control of the target light emission control signal end, the corresponding light emitting unit can be controlled to emit light. Therefore, the number of signal terminals to be set is reduced, the area of the circuit board occupied by the pixel circuit is further reduced, and the realization of the narrow-frame display panel is more favorable.
  • the display device may include a pixel circuit as shown in FIG. 1 to FIG. 4 and a plurality of groups of light emitting units. Each group of light emitting units includes M light emitting units, and M Is an integer greater than 1. Each pixel compensation circuit in the pixel circuit is connected to a group of light emitting units.
  • the display device may be any product or component having a display function such as a MicroLED display substrate, a liquid crystal panel, an electronic paper, an AMOLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display device 800 includes a pixel circuit 801 and a plurality of groups of light-emitting units 802, wherein the pixel circuit 801 may be any one of the pixel circuits described above, and the light-emitting unit 802 may be any of the above-mentioned pixels.
  • a light emitting unit may be any of the above-mentioned pixels.

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  • Electroluminescent Light Sources (AREA)

Abstract

一种像素电路(801)及其驱动方法、显示装置(800)，像素电路(801)包括多个像素补偿电路(011)，且由于每个像素补偿电路(011)可以与位于同一列的M个发光单元(021, 802)连接，也即是一个像素补偿电路(011)可以用于驱动M个发光单元(021, 802)，因此可以减少所需设置的像素补偿电路(011)的个数；进一步的，由于每组发光控制信号端(03)包括的M个发光控制信号端(EM)中，每个发光控制信号端(EM)可以与一组像素补偿电路(011)连接，因此减少了所需设置的信号端的个数，进一步减少了像素电路(801)占用电路板的面积，更加有利于窄边框显示面板的实现。

Description

像素电路及其驱动方法、显示装置
相关申请的交叉引用
本申请要求于2018年6月13日递交的第201810607789.5号中国专利申请的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种像素电路及其驱动方法、显示装置。
背景技术
有源矩阵发光二极管(Active Matrix Organic Light Emitting Diode，AMOLED)是一种可以自主发光的电流型发光器件，因其响应速度快、刷新频率高和低功耗等特点越来越多地被应用于高性能显示面板中。
相关技术中，显示面板一般包括多个阵列排布的像素单元，每个像素单元包括发光单元及与该发光单元连接的像素补偿单路。该像素补偿电路可以避免由于驱动发光单元的驱动晶体管的阈值电压发生漂移，而造成流经发光单元的电流大小存在差异的问题，从而可以保证显示面板显示亮度的均一性。
当显示面板中的像素单元的个数较多时，像素补偿电路的个数则会较多，像素补偿电路占用电路板的面积较大，不利于窄边框显示面板的实现。
发明内容
本公开的至少一个实施例提供了一种像素电路，所述像素电路包括：阵列排布的多组像素补偿电路，每组像素补偿电路包括K行像素补偿电路，K为大于1的整数，每行像素补偿电路包括至少一个像素补偿电路；
每个所述像素补偿电路配置为在操作中允许与一组发光单元连接，每组所述发光单元包括位于同一列的M个发光单元，M为大于1的整数；
所述像素电路还包括与所述多组像素补偿电路一一对应的多组发光控制信号端，每组发光控制信号端包括M个发光控制信号端，每组像素补偿电路 中的每个像素补偿电路均与对应的一组发光控制信号端中的M个发光控制信号端连接；
每个所述像素补偿电路所连接的M个发光控制信号端与所述像素补偿电路连接的M个发光单元一一对应，每个所述发光控制信号端用于通过其所连接的像素补偿电路，驱动对应的发光单元发光。
可选的，所述像素电路还包括与所述多组像素补偿电路一一对应的多个总发光控制信号端，每个所述总发光控制信号端与对应的一组像素补偿电路中的每个像素补偿电路连接。
可选的，每组发光单元中位于同一列的所述M个发光单元彼此相邻。
可选的，M＝2。
可选的，每组像素补偿电路中的所述K行像素补偿电路彼此相邻。
可选的，K＝2。
可选的，每个所述像素补偿电路所连接的M个发光控制信号端中的第m个发光控制信号端，与该像素补偿电路所连接的M个发光单元中的第m个发光单元对应，m为不大于M的正整数。
可选的，每个所述像素补偿电路包括：复位子电路、第一发光控制子电路以及M个第二发光控制子电路；
所述复位子电路分别与复位信号端和复位电源端连接，并且所述复位子电路与所述第一发光控制子电路连接于第一节点处，所述复位子电路用于响应于来自所述复位信号端的复位信号，向所述第一节点输入来自所述复位电源端的复位电源信号；
所述第一发光控制子电路分别与所述总发光控制信号端、电源端、数据信号端和驱动电源端连接，并且所述第一发光控制子电路与所述M个第二发光控制子电路连接于第二节点处，所述第一发光控制子电路用于响应于所述第一节点的电位、来自所述总发光控制信号端的总发光控制信号、来自电源端的电源信号以及来自所述驱动电源端的驱动电源信号，向所述第二节点输入来自所述数据信号端的数据信号；
每个所述第二发光控制子电路分别与对应的一组发光控制信号端中的一个发光控制信号端以及一个发光单元连接，每个所述第二发光控制子电路用于响应于来自其所连接的发光控制信号端提供的发光控制信号，驱动其所连 接的发光单元发光。
可选的，每个所述第二发光控制子电路包括：第一晶体管；
所述第一晶体管的栅极与一个发光控制信号端连接，所述第一晶体管的第一极与所述第二节点连接，所述第一晶体管的第二极与一个发光单元连接。
可选的，所述复位子电路包括：第二晶体管；
所述第二晶体管的栅极与所述复位信号端连接，所述第二晶体管的第一极与复位电源端连接，所述第二晶体管的第二极与所述第一节点连接；
所述第一发光控制子电路包括：第三晶体管、第四晶体管、第五晶体管、第六晶体管和存储电容；
所述第三晶体管的栅极与所述驱动电源端连接，所述第三晶体管的第一极与所述数据信号端连接，所述第三晶体管的第二极与第三节点连接；
所述第四晶体管的栅极与所述总发光控制信号端连接，所述第四晶体管的第一极与所述第三节点连接，所述第四晶体管的第二极与所述电源端连接；
所述第五晶体管的栅极与所述第一节点连接，所述第五晶体管的第一极与所述第三节点连接，所述第五晶体管的第二极与所述第二节点连接；
所述第六晶体管的栅极与所述驱动电源端连接，所述第六晶体管的第一极与所述第一节点连接，所述第六晶体管的第二极与所述第二节点连接；
所述存储电容的一端与所述电源端连接，所述存储电容的另一端与所述第一节点连接。
本公开的至少一个实施例提供了一种像素电路的驱动方法，应用于如上所述的像素电路，所述方法包括：通过M个驱动子帧驱动所述像素电路，每个所述驱动子帧包括多个驱动阶段，每个所述驱动子帧包括的驱动阶段的个数与所述像素电路包括的像素补偿电路的组数以及发光控制信号端的组数相等，且所述多个驱动阶段与多组发光控制信号端一一对应；
所述通过M个驱动子帧驱动所述像素电路包括：在每个所述驱动阶段的发光子阶段中，对应的一组发光控制信号端包括的M个发光控制信号端中的一个目标发光控制信号端提供的目标发光控制信号的电位为有效电位，除所述目标发光控制信号端之外的其他发光控制信号端提供的发光控制信号的电位为无效电位，与所述目标发光控制信号端连接的一组像素补偿电路在所述目标发光控制信号的控制下，驱动与所述目标发光控制信号端对应的发光单 元发光。
可选的，所述像素电路还包括与所述多组像素补偿电路一一对应的多个总发光控制信号端，每个所述总发光控制信号端与对应的一组像素补偿电路中的每个像素补偿电路连接；
所述通过M个驱动子帧驱动所述像素电路包括：在每个所述驱动阶段的发光子阶段中，与所述目标发光控制信号端连接的一组像素补偿电路所对应的一个总发光控制信号端提供的总发光控制信号的电位为有效电位。
可选的，每组发光单元包括位于同一列且相邻的两个发光单元，每组发光控制信号端包括两个发光控制信号端；所述通过M个驱动子帧驱动所述像素电路包括：通过两个驱动子帧驱动所述像素电路；
所述通过两个驱动子帧驱动所述像素电路包括：
在第一个驱动子帧的每个所述驱动阶段的发光子阶段中，与所述驱动阶段对应的一组发光控制信号端中的一个发光控制信号端提供的发光控制信号的电位为有效电位，另一个发光控制信号端提供的发光控制信号的电位为无效电位；
在第二个驱动子帧的每个所述驱动阶段的发光子阶段中，与所述驱动阶段对应的一组发光控制信号端中所述另一个发光控制信号端提供的发光控制信号的电位为有效电位，除所述另一个发光控制信号端之外的一个发光控制信号端提供的发光控制信号的电位为无效电位。
可选的，每个所述像素补偿电路包括：复位子电路、第一发光控制子电路以及M个第二发光控制子电路；每个所述驱动阶段还包括：位于所述发光子阶段之前的重置子阶段和K个补偿子阶段；
所述通过M个驱动子帧驱动所述像素电路还包括：
在所述重置子阶段中，所述驱动阶段对应的一组发光控制信号端所连接的一组像素补偿电路中，第一行像素补偿电路的复位信号端提供的复位信号的电位为有效电位，所述复位子电路响应于所述复位信号，向第一节点输入来自复位电源端的复位电源信号；
在所述K个补偿子阶段的第k个补偿子阶段中，所述一组像素补偿电路中，第k行像素补偿电路所连接的驱动电源端提供的驱动电源信号的电位为有效电位，所述一组像素补偿电路连接的总发光控制信号端提供的总发光控 制信号的电位为无效电位，所述第k行像素补偿电路中每个像素补偿电路的第一发光控制子电路响应于所述驱动电源信号、所述第一节点的电位以及电源端提供的电源信号，向第二节点输入来自数据信号端的数据信号，k为不大于K的正整数；
在所述发光子阶段中，所述一组像素补偿电路连接的总发光控制信号的电位为有效电位，所述一组像素补偿电路中，每个像素补偿电路的M个第二发光控制子电路中与所述目标发光控制信号端连接的第二发光控制子电路响应于所述目标发光控制信号，驱动其所连接的发光单元发光。
本公开的至少一个实施例提供了一种显示装置，所述显示装置包括：如上所述的像素电路以及多组发光单元，每组所述发光单元包括M个发光单元，M为大于1的整数；
所述像素电路中的每个像素补偿电路与一组所述发光单元连接。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1是本公开至少一个实施例提供的一种像素电路的结构示意图；
图2是本公开至少一个实施例提供的另一种像素电路的结构示意图；
图3是本公开至少一个实施例提供的一种像素补偿电路的结构示意图；
图4是本公开至少一个实施例提供的另一种像素补偿电路的结构示意图；
图5是本公开至少一个实施例提供的一种像素电路的驱动方法的流程图；
图6是本公开至少一个实施例提供的一种将一帧扫描时间划分为两个驱动子帧的示意图；
图7是本公开至少一个实施例提供的一种像素电路的驱动过程的时序图；
图8是本公开至少一个实施例提供的显示装置的结构示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件，根据在电路中的作用本公开的实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开实施例中，将其中源极称为第一级，漏极称为第二级。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。此外，本公开实施例所采用的开关晶体管可以包括P型开关晶体管和N型开关晶体管中的任一种，其中，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型开关晶体管在栅极为高电平时导通，在栅极为低电平时截止。
本公开中提到的“有效电位”指的是使得开关晶体管导通的电位，以及本公开中提到的“无效电位”指的是使得开关晶体管截止的电位。
例如，OLED显示装置通常包括多个按阵列排布的像素单元，每个像素单元例如可以包括相应的发光驱动电路。在OLED显示装置中，各个发光驱动电路中的驱动晶体管的阈值电压由于制备工艺可能存在差异，而且由于例如温度变化的影响，驱动晶体管的阈值电压可能会产生漂移现象。因此，各 个驱动晶体管的阈值电压的不同可能会导致显示不良(例如显示不均匀)，所以就需要对阈值电压进行补偿。同时在处于关态时，由于漏电流的存在，也可能会导致显示不良。因此，业界还在2T1C(即两个晶体管和一个电容)的基本发光驱动电路的基础上提供了其他具有补偿功能的发光驱动电路，补偿功能可以通过电压补偿、电流补偿或混合补偿来实现，具有补偿功能的像素电路例如可以为4T1C或4T2C等，这里不再详述。
图1是本公开至少一个实施例提供的一种像素电路的结构示意图，如图1所示，该像素电路可以包括：阵列排布的多组像素补偿电路01，每组像素补偿电路01可以包括K行像素补偿电路011，K为大于1的整数，每行像素补偿电路包括至少一个像素补偿电路011。
示例的，在图1所示的像素电路中，每组像素补偿电路01包括两行像素补偿电路011，即K＝2。图1中仅示出了每行像素补偿电路中的一个像素补偿电路011，实际每行像素补偿电路可以包括多个像素补偿电路011。
在本公开一些实施例中，每个像素补偿电路011配置为在操作中允许与一组发光单元02连接，每组发光单元02可以包括位于同一列的M个发光单元021，M为大于1的整数。示例的，在图1所示的像素电路中，每个像素补偿电路011可以与位于同一列的两个发光单元021连接，即M＝2。
进一步的，该像素电路还可以包括与多组像素补偿电路01一一对应的多组发光控制信号端03，每组发光控制信号端03可以包括M个发光控制信号端EM，每组像素补偿电路01中的每个像素补偿电路011可以均与对应的一组发光控制信号端03中的M个发光控制信号端EM连接。
示例的，如图1所示，该每组发光控制信号端03可以包括两个发光控制信号端EM，即M＝2。且每个像素补偿电路011可以均与该一组发光控制信号端03中的两个发光控制信号端EM连接。也即是每组发光控制信号端03中的每个发光控制信号端EM可以均与每组像素补偿电路01(每组像素补偿电路01可以包括K行像素补偿电路，K为大于1的整数)中的每个像素补偿电路011连接。相对于相关技术中一个发光控制信号端EM连接一个像素补偿电路011，减少了像素电路中所需设置的信号端的个数，减少了像素补偿电路所占的面积。
每个像素补偿电路011所连接的M个发光控制信号端EM与像素补偿电 路011连接的M个发光单元021一一对应，每个发光控制信号端EM可以用于通过其所连接的像素补偿电路011，驱动对应的发光单元021发光。也即是，在本公开一些实施例中，一个发光控制信号端EM可以通过其连接的每个像素补偿电路011，驱动该像素补偿电路011连接的一组发光单元中，与该发光控制信号端EM对应的发光单元021发光。
本公开至少一个实施例提供的像素电路在驱动发光单元021发光时，可以包括M个驱动子帧，每个驱动子帧可以包括与该多组发光控制信号端03一一对应的多个驱动阶段。在每个驱动阶段中，多组发光控制信号端03中与该驱动阶段对应的一组发光控制信号端03处于工作状态，在该一组发光控制信号端03中仅有一个目标发光控制信号端提供的发光控制信号的电位为有效电位，除该一个目标发光控制信号端之外的其他每个发光控制信号端提供的发光控制信号的电位均为无效电位。也即是在每个驱动子帧的每个驱动阶段中，与该处于工作状态的一组发光控制信号端03连接的一组像素补偿电路01中，每个像素补偿电路011连接的M个发光单元021中，只有与该目标发光控制信号端对应的发光单元021可以在该目标发光控制信号的驱动下发光。
例如，假设像素电路驱动发光单元发光时包括两个驱动子帧(即M＝2)，则在第一个驱动子帧的某个驱动阶段中，与该驱动阶段对应的一组发光控制信号端03中，第一个发光控制信号端EM提供的发光控制信号的电位可以为有效电位，即第一个发光控制信号端EM为目标发光控制信号端，此时与该第一个发光控制信号端EM对应的发光单元021发光。在第二个驱动子帧的该驱动阶段中，与该驱动阶段对应的一组发光控制信号端03中，第二个发光控制信号端EM提供的发光控制信号的电位可以为有效电位，即第二个发光控制信号端EM为目标发光控制信号端，此时与该第二个发光控制信号端EM对应的发光单元021发光。
综上所述，本公开一些实施例提供的像素电路包括多个像素补偿电路，并且由于每个像素补偿电路可以与位于同一列的M个发光单元连接，也即是一个像素补偿电路可以用于驱动M个发光单元，因此可以减少所需设置的像素补偿电路的个数。进一步的，由于每组发光控制信号端包括的M个发光控制信号端中，每个发光控制信号端可以与一组像素补偿电路(即K行像素补 偿电路)连接，因此减少了所需设置的信号端的个数，进一步减少了像素电路占用电路板的面积，更加有利于窄边框显示面板的实现。
图2是本公开至少一个实施例提供的另一种像素电路的结构示意图，如图2所示，该像素电路还可以包括与多组像素补偿电路01一一对应的多个总发光控制信号端EMc，每个总发光控制信号端EMc可以与对应的一组像素补偿电路01中的每个像素补偿电路011连接。示例的，如图2所示，一个总发光控制信号端EMc可以与一组像素补偿电路01中的两行像素补偿电路011均连接。
该总发光控制信号端EMc可以通过其所连接的每个像素补偿电路011，驱动该像素补偿电路011所连接的一组发光单元02发光。
在本公开一些实施例中，由于每个总发光控制信号端EMc可以与对应的一组像素补偿电路01(即K行像素补偿电路)中的每个像素补偿电路011连接，且又由于每个像素补偿电路011可以与一组发光单元02(每组发光单元02可以包括位于同一列的M个发光单元021)连接，因此该一个总发光控制信号端EMc即可以通过该一组像素补偿电路01中的每个像素补偿电路011驱动M×K行发光单元发光。相对于相关技术中一个总发光控制信号端EMc通过其连接的一行像素补偿电路011驱动一行发光单元，进一步减少了像素电路中所需设置的信号端的个数，进而减小了像素电路占用的面积。
示例的，参考图2，假设每组发光单元02包括位于同一列的两个发光单元021，一组像素补偿电路01包括两行像素补偿电路011，则一个发光控制信号端EMc即可以通过一组像素补偿电路01驱动四行发光单元021工作。
参考图1和图2，假设每个像素补偿电路011均与位于同一列的两个发光单元021连接，则在本公开一些实施例中，一个发光控制信号端EM可以控制两行发光单元；相比相关技术中一个发光控制信号端EM控制一行发光单元，减少了二分之一数量的发光控制信号端EM的设置。并且，本公开一些实施例中的一个总发光控制信号端EMc可以控制四行发光单元；相比相关技术中一个总发光控制信号端EMc控制一行或者两行发光单元，有效减少了所需设置的总发光控制信号端EMc的数量。
可选的，该每组发光单元02可以包括位于同一列且相邻的M个发光单元021。相邻的M个发光单元021共用一个像素补偿电路011，可以尽量减 小发光单元021与像素补偿电路011之间的走线长度，可以减少显示面板的布线成本，简化显示面板的制造工艺。
可选的，该每组发光单元02可以包括位于同一列且相邻的两个发光单元021，即M＝2。当每组发光单元02中仅包括两个相邻的发光单元021时，如图1和图2所示，该两个发光单元021所共用的像素补偿电路011可以设置在该两个发光单元021之间，从而可以进一步减小布线成本。
可选的，该每组像素补偿电路01可以包括相邻的K行像素补偿电路。通过将位于相邻行的像素补偿电路01作为一组，可以避免发光控制信号端EM跨行连接像素补偿电路01，从而可以减小布线成本。
可选的，参考图1和图2，该每组像素补偿电路01还可以包括相邻的两行像素补偿电路011，通过将位于相邻两行的像素补偿电路011作为一组，可以使得每个发光控制信号端EM仅与两行像素补偿电路011连接，也即是一个控制信号端EM仅需要同时控制两行发光单元021工作，使得在减小像素补偿电路占用面积的同时，避免对显示面板的显示效果造成影响。
在本公开一些实施例中，每个像素补偿电路所连接的M个发光控制信号端中的第m个发光控制信号端，与其所连接的M个发光单元中的第m个发光单元对应，m为不大于M的正整数。通过使得每个像素补偿电路011连接的发光控制信号端EM，与该像素补偿电路011连接的发光单元021对应，可以使得各组发光控制信号端03可以通过像素补偿电路011等行距有序驱动各行发光单元021发光，显示面板的显示效果较好。
示例的，假设包括两个驱动子帧。在第一个驱动子帧中，各组发光控制信号端03中的第一个发光控制信号端EM可以依次输出有效电位的发光控制信号。由于每组发光控制信号端03中的第一个发光控制信号端EM，与该发光控制信号端EM连接的像素补偿电路011连接的两个发光单元021中的第一个发光单元021对应，因此，该各组发光控制信号端03中的第一个发光控制信号端EM可以通过其所连接的像素补偿电路011，依次驱动奇数行的发光单元021逐行发光，由此实现了对发光单元021的等行距有序驱动。
图3是本公开至少一个实施例提供的一种像素补偿电路的结构示意图，如图3所示，每个像素补偿电路011可以包括：复位子电路10、第一发光控制子电路20以及M个第二发光控制子电路30。例如，图3中示出了两个第 二发光控制子电路30。
参考图3，该复位子电路10可以分别与复位信号端RST、复位电源端Vint以及第一节点P1连接，该复位子电路10可以用于响应于来自该复位信号端RST的复位信号，向第一节点P1输入来自复位电源端Vint的复位电源信号。
示例的，当该复位信号端RST提供的复位信号的电位为有效电位时，该复位子电路10可以向第一节点P1输入来自复位电源端Vint的复位电源信号，该复位电源信号的电位可以为有效电位。
参考图3，该第一发光控制子电路20可以分别与第一节点P1、总发光控制信号端EMc、电源端ELVDD、数据信号端D、驱动电源端G和第二节点P2连接，该第一发光控制子电路20可以用于响应于第一节点P1的电位、来自总发光控制信号端EMc的总发光控制信号、来自电源端ELVDD的电源信号以及来自驱动电源端G的驱动电源信号，向第二节点P2输入来自数据信号端D的数据信号。
示例的，当该驱动电源端G提供的驱动电源信号的电位为有效电位，总发光控制信号端EMc提供的总发光控制信号的电位为无效电位，第一节点P1的电位为有效电位，电源端ELVDD提供的电源信号的电位为无效电位时，该第一发光控制子电路20可以向第二节点P2输入来自数据信号端D的数据信号。
在本公开一些实施例中，位于同一行的像素补偿电路可以与同一个驱动电源端G连接，由于每个像素补偿电路可以与位于同一列的M个发光单元连接，因此一个驱动电源端G即可以通过一行像素补偿电路驱动M行发光单元工作。相对于相关技术中一个驱动电源端G仅能驱动一行发光单元，本公开一些实施例提供的像素电路中所需设置的驱动电源端G的个数较少，该像素电路的占用面积较小。
参考图3，每个第二发光控制子电路30可以分别与第二节点P2、对应的一组发光控制信号端中的一个发光控制信号端EM以及一个发光单元021连接，每个第二发光控制子电路30可以用于响应于来自其所连接的发光控制信号端EM提供的发光控制信号，驱动其所连接的发光单元021发光。
示例的，当图3中的一个发光控制信号端EM提供的发光控制信号的电 位为有效电位时，该第二发光控制子电路30中可以驱动与该发光控制信号端EM对应的发光单元021发光。
图4是本公开至少一个实施例提供的另一种像素补偿电路的结构示意图，如图4所示，该每个第二发光控制子电路30可以包括：第一晶体管M1。
示例的，假设如图1所示，每个像素补偿电路011与位于同一列的两个发光单元021连接，则参考图4，该一个像素补偿电路可以包括两个第一晶体管M1，该每个第一晶体管M1的栅极可以与一个发光控制信号端EM连接，第一晶体管M1的第一极可以与第二节点P2连接，第一晶体管M1的第二极与一个发光单元021连接。且参考图4，每个发光单元021的另一端还可以与低电平电源端ELVSS连接。该发光单元可以为有机发光二极管(Organic Light-Emitting Diode，OLED)或AMOLED。
可选的，参考图4，该复位子电路10可以包括：第二晶体管M2。
该第二晶体管M2的栅极可以与复位信号端RST连接，该第二晶体管M2的第一极可以与复位电源端Vint连接，该第二晶体管M2的第二极可以与第一节点P1连接。
可选的，参考图4，该第一发光控制子电路20可以包括：第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6和存储电容C。
参考图4，该第三晶体管M3的栅极可以与驱动电源端G连接，该第三晶体管M3的第一极可以与数据信号端D连接，该第三晶体管M3的第二极可以与第三节点P3连接。
第四晶体管M4的栅极可以与总发光控制信号端EMc连接，第四晶体管M4的第一极可以与第三节点P3连接，第四晶体管M4的第二极可以与电源端ELVDD连接。
第五晶体管M5的栅极可以与第一节点P1连接，第五晶体管M5的第一极可以与第三节点P3连接，第五晶体管M5的第二极可以与第二节点P2连接。
第六晶体管M6的栅极可以与驱动电源端G连接，第六晶体管M6的第一极可以与第一节点P1连接，第六晶体管M6的第二极可以与第二节点P2连接。
存储电容C的一端可以与电源端ELVDD连接，另一端可以与第一节点 P1连接。
由于像素补偿电路的面积与显示面板单位尺寸内的屏幕分辨率(Pixels Per inch，PPI)成负相关，也即是像素补偿电路的面积越大，显示面板的PPI越低。本公开一些实施例通过采用一个像素补偿电路驱动多个发光单元工作，减少了所需设置的像素补偿电路的个数，进而减小了像素补偿电路占用的面积。并且，本公开一些实施例中，每个发光控制信号端和每个总发光控制信号端均与一组像素补偿电路(即K行像素补偿电路)中的每个像素补偿电路连接，减少了像素电路所需设置的信号端的个数。因此本公开一些实施例提供的像素电路占用面积较小，可以有效提高显示面板的PPI。
需要说明的是，在本公开一些实施例中，该像素补偿电路除了可以为图4所示的7T1C(即七个晶体管和一个电容器)的结构之外，也可以为6T1C或者9T1C等其他结构的像素补偿电路，本公开实施例对此不做限定。
还需要说明的是，在上述各实施例中，均是以各个晶体管为P型晶体管，且有效电位为低电位为例进行的说明。当然，各个晶体管还可以采用N型晶体管，当各个晶体管均采用N型晶体管时，该有效电位为高电位。
综上所述，本公开一些实施例提供的像素电路包括多个像素补偿电路，并且由于每个像素补偿电路可以与位于同一列的M个发光单元连接，也即是一个像素补偿电路可以用于驱动M个发光单元，因此可以减少所需设置的像素补偿电路的个数。进一步的，由于每组发光控制信号端包括的M个发光控制信号端中，每个发光控制信号端可以与一组像素补偿电路(即K行像素补偿电路)连接，因此减少了所需设置的信号端的个数，进一步减少了像素电路占用电路板的面积，更加有利于窄边框显示面板的实现。
本公开至少一个实施例提供了一种像素电路的驱动方法，该方法可以应用于图1所示的像素电路中，该方法可以包括：通过M个驱动子帧驱动像素电路。该驱动方法包括的驱动子帧的个数与每个像素补偿电路连接的发光单元的个数相等。并且，该M个驱动子帧与每个像素补偿电路连接的M个发光单元一一对应，在每个驱动子帧中，每个像素补偿电路连接的M个发光单元中，与该驱动子帧对应的一个发光单元发光，其他M-1个发光单元不发光。
其中，每个驱动子帧可以包括多个驱动阶段，每个驱动子帧包括的驱动阶段的个数可以与像素电路包括的像素补偿电路的组数以及发光控制信号端 的组数相等，并且该多个驱动阶段与多组发光控制信号端一一对应。
通过M个驱动子帧驱动像素电路可包括：在每个驱动阶段的发光子阶段中，对应的一组发光控制信号端包括的M个发光控制信号端中的一个目标发光控制信号端提供的目标发光控制信号的电位为有效电位，除目标发光控制信号端之外的其他发光控制信号端提供的发光控制信号的电位为无效电位，与目标发光控制信号端连接的一组像素补偿电路可以在目标发光控制信号的控制下，驱动对应的发光单元发光。也即是，在每个驱动子帧包括的每个驱动阶段中，每个像素补偿电路所连接的一组发光单元中，仅有一个发光单元发光。
其中，除目标发光控制信号端之外的其他发光控制信号端是指该对应的一组发光控制信号端中除一个目标发光控制信号端之外的M-1个发光控制信号端，以及该多组发光控制信号端中，除该对应的一组发光控制信号端之外的其他组发光控制信号端。
综上所述，本公开至少一个实施例提供的像素电路的驱动方法，由于在每个驱动阶段的发光子阶段中，与目标控制信号端连接的一组像素补偿电路(即K行像素补偿电路)可以在该目标发光控制信号端的控制下，驱动对应的发光单元发光。因此减少了所需设置的信号端的个数，进一步减少了像素电路占用电路板的面积，更加有利于窄边框显示面板的实现。
参考图2，该像素电路还可以包括与多组像素补偿电路01一一对应的多个总发光控制信号端EMc，每个总发光控制信号端EMc可以与对应的一组像素补偿电路01中的每个像素补偿电路011连接。
相应的，通过M个驱动子帧驱动像素电路还可包括：在每个驱动阶段的发光子阶段中，与目标发光控制信号端连接的一组像素补偿电路所对应的一个总发光控制信号端提供的总发光控制信号的电位为有效电位。
可选的，每组发光单元可以包括位于同一列且相邻的两个发光单元，每组发光控制信号端可以包括两个发光控制信号端。相应的，通过M个驱动子帧驱动像素电路即可以包括：通过两个驱动子帧驱动像素电路。
通过两个驱动子帧驱动像素电路可包括：
在第一个驱动子帧的每个驱动阶段的发光子阶段中，与该驱动阶段对应的一组发光控制信号端中的一个发光控制信号端提供的发光控制信号的电位 可以为有效电位，另一个发光控制信号端提供的发光控制信号的电位即可以为无效电位；以及
在第二个驱动子帧的每个驱动阶段的发光子阶段中，与该驱动阶段对应的一组发光控制信号端中的另一个发光控制信号端提供的发光控制信号的电位可以为有效电位，除另一个发光控制信号端之外的一个发光控制信号端提供的发光控制信号的电位即可以为无效电位。
可选的，每组像素补偿电路可以包括相邻的K行像素补偿电路。相应的，在每个发光子阶段中，K行像素补偿电路中，每个像素补偿电路连接的一个发光单元发光。
参考图4，每个像素补偿电路可以包括：复位子电路10、第一发光控制子电路20以及M个第二发光控制子电路30。相应的，每个驱动阶段还可以包括：位于发光子阶段之前的重置子阶段和K个补偿子阶段。
图5是本公开至少一个实施例提供的一种像素电路的驱动方法流程图，如图5所示，该方法可以包括：
步骤501、在重置子阶段中，驱动阶段对应的一组发光控制信号端所连接的一组像素补偿电路中，第一行像素补偿电路的复位信号端提供的复位信号的电位为有效电位，复位子电路响应于复位信号，向第一节点输入来自复位电源端的复位电源信号。
并且，在重置子阶段中，每组像素补偿电路连接的总发光控制信号端的提供的总发光控制信号的电位均为无效电位。
步骤502、在K个补偿子阶段的第k个补偿子阶段中，该组像素补偿电路中，第k行像素补偿电路所连接的驱动电源端提供的驱动电源信号的电位为有效电位，该组像素补偿电路连接的总发光控制信号端提供的总发光控制信号的电位为无效电位，第k行像素补偿电路中每个像素补偿电路的第一发光控制子电路响应于驱动电源信号、第一节点的电位以及电源端提供的电源信号，向第二节点输入来自数据信号端的数据信号，k为不大于K的正整数。
示例的，假设每组像素补偿电路包括两行像素补偿电路，则每个驱动阶段可以包括两个补偿子阶段，即K＝2。
步骤503、在发光子阶段中，该组像素补偿电路连接的总发光控制信号的电位为有效电位，该组像素补偿电路中，每个像素补偿电路的M个第二发 光控制子电路中与目标发光控制信号端连接的第二发光控制子电路响应于目标发光控制信号，驱动其所连接的发光单元发光。
在本公开一些实施例中，以图2所示的像素电路(即M和K均为2)为例，并以图4所示的像素补偿电路为例，且像素补偿电路中各个晶体管为P型晶体管，详细介绍本公开一些实施例提供的像素电路的驱动原理。
由于该像素电路中每个像素补偿电路连接的一组发光单元包括两个发光单元，即M＝2，因此如图6所示，可以将像素电路对显示面板中的发光单元进行一帧1F扫描的时间划分为两个驱动子帧SF1和SF2。参考图6，在第一个驱动子帧SF1中，像素电路可以逐行驱动显示面板中的奇数行发光单元发光，也即是在第一个驱动子帧SF1中，像素电路可以依次驱动第一行、第三行、第五行至显示面板中最后一行奇数行的发光单元发光；在第二个驱动子帧SF2中，像素电路可以逐行驱动显示面板中的偶数行发光单元发光，也即是在第二个驱动子帧SF2中，像素电路可以依次驱动第二行、第四行、第六行至显示面板中最后一行偶数行的发光单元发光。
参考图7，该第一个驱动子帧SF1可以包括多个驱动阶段，在该多个驱动阶段的第i个(i为不大于每个驱动子帧包括的驱动阶段的个数的正整数)驱动阶段Qi中，与该第i个驱动阶段Qi对应的第i组发光控制信号端可以驱动第i组像素补偿电路工作。假设该第i组像素补偿电路包括的两行像素补偿电路中，第一行像素补偿电路为显示面板中的第n行像素补偿电路，则如图7所示，在该第i个驱动阶段Qi的重置子阶段T1中，显示面板中第n行像素补偿电路的前一行像素补偿电路(也即是第n-1行)所连接的的驱动电源端G(n-1)作为该第n行像素补偿电路的复位信号端提供处于有效电位的复位信号。显示面板中第n行像素补偿电路中每个像素补偿电路的第二晶体管M2开启，复位电源端Vint通过该第二晶体管M2向第一节点P1输入位于有效电位的复位电源信号。该重置阶段T1可以实现对第n行像素补偿电路的复位。并且，在该重置子阶段T1中，显示面板中第n行像素补偿电路中每个像素补偿电路的第五晶体管M5开启。
由于一组像素补偿电路01包括两行像素补偿电路011，即K＝2，则在第一个驱动子帧SF1中，每个驱动阶段可以包括两个补偿子阶段T2和T3。参考图7，在该第i个驱动阶段Qi的第一个补偿子阶段T2中，该第i组像素补 偿电路中的第一行像素补偿电路(即显示面板中的第n行像素补偿电路)所连接的驱动电源端G(n)提供的驱动电源信号的电位为有效电位，该显示面板中的第n行像素补偿电路中每个像素补偿电路的第三晶体管M3开启，数据信号端D通过该第三晶体管M3和第五晶体管M5向第二节点P2输入数据信号D(n)，并且将数据信号和第五晶体管M5的阈值电压储存在存储电容C中。
同时，在该第i个驱动阶段Qi的第一个补偿子阶段T2中，该第i组像素补偿电路中的第一行像素补偿电路(即显示面板中的第n行像素补偿电路)所连接的驱动电源端G(n)还可以作为该第i组像素补偿电路中的第二行像素补偿电路(即显示面板中的第n+1行像素补偿电路)的复位信号端，为该第n+1行像素补偿电路提供处于有效电位的复位信号。该显示面板中的第n+1行像素补偿电路中每个像素补偿电路的第二晶体管M2开启，复位电源端Vint可以通过该第二晶体管M2向第一节点P1输入处于有效电位的复位电源信号，从而实现对该第n+1行像素补偿电路复位。也即是该第一个补偿子阶段T2也可以作为第n+1行像素补偿电路的重置子阶段。
在该第i个驱动阶段Qi的第二个补偿子阶段T3中，该第i组像素补偿电路中的第二行像素补偿电路(即显示面板中的第n+1行像素补偿电路)所连接的驱动电源端G(n+1)提供的驱动电源信号的电位为有效电位，该显示面板中的第n+1行像素补偿电路中每个像素补偿电路的第三晶体管M3开启，且由于此时第五晶体管M5也是开启的，数据信号端D通过该第三晶体管M3和第五晶体管M5向第二节点P2输入数据信号D(n+1)，并且将数据信号和第五晶体管M5的阈值电压存储在存储电容C中。
并且，在该重置子阶段T1以及该两个补偿子阶段T2和T3的每个补偿子阶段中，该第i组像素补偿电路中的第一行像素补偿电路和第二行像素补偿电路(即显示面板中的第n行像素补偿电路和第n+1行像素补偿电路)所连接的总发光控制信号端EMc提供的总发光控制信号的电位均为无效电位，该显示面板中的第n行像素补偿电路中的每个像素补偿电路的第四晶体管M4，以及该显示面板中的第n+1行像素补偿电路中的每个像素补偿电路的第四晶体管M4均关闭。
进一步的，在第一个驱动子帧SF1的第i个驱动阶段Qi的发光子阶段 T4中，第i组像素补偿电路中的每个像素补偿电路所连接的总发光控制信号端EMc提供的总发光控制信号的电位跳变为有效电位，该显示面板中的第n行像素补偿电路中的每个像素补偿电路的第四晶体管M4，以及该显示面板中的第n+1行像素补偿电路中的每个像素补偿电路的第四晶体管M4均开启。电源端ELVDD可以通过该第四晶体管M4和第五晶体管M5输入电源信号至第二节点P2。第i组发光控制信号端中的第一个发光控制信号端EM(n_1)提供的发光控制信号的电位为有效电位，该显示面板中的第n行和第n+1行像素补偿电路中的每个像素补偿电路中与该第一个发光控制信号端EM(n_1)对应的第一晶体管M1开启，第二节点P2可以通过第一晶体管M1驱动与该第一晶体管M1连接的发光单元发光。即显示面板中第n行和第n+1行像素补偿电路中的每个像素补偿电路所连接的一组发光单元中，与该第一个发光控制信号端EM(n_1)对应的发光单元发光。例如在该第i个驱动阶段Qi的发光子阶段中，该显示面板中的第n行像素补偿电路中每个像素补偿电路所连接的第一个发光单元和该显示面板中的第n+1行像素补偿电路中每个像素补偿电路所连接的第一个发光单元可以同时发光。
在本公开一些实施例中，当一组像素补偿电路包括两行像素补偿电路时，每个驱动阶段中仅需增加一个补偿子阶段，相应的，每个驱动阶段中发光子阶段的持续时长减少一个补偿子阶段的持续时长。其中，每个驱动阶段中的每个子阶段的持续时长可以为1H，1H是指像素电路扫描一行发光单元所需的时长，且该1H满足：1H＝1/(f×S)，f为帧频，S为显示面板中包括的发光单元的总行数。由于每个驱动阶段多了1H的补偿子阶段，因此也就相应的减少1H的发光时长，但是由于显示面板包括多行发光单元，因此发光子阶段减少的1H的持续时长对显示面板显示效果的影响可以忽略不计。
参考图7，在第二个驱动子帧SF2的第i个驱动阶段Qi的发光子阶段中，第i组发光控制信号端中的第二个发光控制信号端EM(n_2)提供的发光控制信号的电位为有效电位，而该第i组发光控制信号端中的第一个发光控制信号端EM(n_1)提供的发光控制信号的电位则跳变为无效电位。该显示面板中的第n行和第n+1行像素补偿电路中的每个像素补偿电路中与该第二个发光控制信号端EM(n_2)对应的第一晶体管M1开启，第二节点P2可以通过第一晶体管M1驱动与该第一晶体管M1连接的发光单元发光。即显示 面板中的第n行和第n+1行像素补偿电路中的每个像素补偿电路所连接的一组发光单元中，与该第二个发光控制信号端EM(n_2)对应的发光单元发光。例如在该第i个驱动阶段Qi的发光子阶段中，该显示面板中的第n行像素补偿电路中每个像素补偿电路所连接的第二个发光单元和该显示面板中的第n+1行像素补偿电路中每个像素补偿电路所连接的第二个发光单元可以同时发光。
还需要说明的是，在上述各实施例中，均是以各个晶体管为P型晶体管，且有效电位为低电位为例进行的说明。当然，各个晶体管还可以采用N型晶体管，当各个晶体管均采用N型晶体管时，该有效电位可以为高电位。
综上所述，本公开至少一个实施例提供的像素电路的驱动方法，由于在每个驱动阶段的发光子阶段中，与目标控制信号端连接的一组像素补偿电路(即K行像素补偿电路)可以在该目标发光控制信号端的控制下，控制对应的发光单元发光。因此减少了所需设置的信号端的个数，进一步减少了像素电路占用电路板的面积，更加有利于窄边框显示面板的实现。
另外，本公开至少一个实施例还提供一种显示装置，该显示装置可以包括如图1至图4所示的像素电路以及多组发光单元，该每组发光单元包括M个发光单元，且M为大于1的整数。该像素电路中的每个像素补偿电路与一组发光单元连接。该显示装置可以为：MicroLED显示基板、液晶面板、电子纸、AMOLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
如图8所示，根据本公开至少一个实施例的显示装置800包括像素电路801和多组发光单元802，其中像素电路801可以是上述的任一像素电路，以及发光单元802可以是上述的任一发光单元。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的像素电路和显示装置的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。

Claims (15)

  1. 一种像素电路，包括：阵列排布的多组像素补偿电路，每组像素补偿电路包括K行像素补偿电路，K为大于1的整数，每行像素补偿电路包括至少一个像素补偿电路；
    每个所述像素补偿电路配置为在操作中允许与一组发光单元连接，每组所述发光单元包括位于同一列的M个发光单元，M为大于1的整数；
    所述像素电路还包括与所述多组像素补偿电路一一对应的多组发光控制信号端，每组所述发光控制信号端包括M个发光控制信号端，每组所述像素补偿电路中的每个像素补偿电路均与对应的一组所述发光控制信号端中的M个发光控制信号端连接；
    每个所述像素补偿电路所连接的M个发光控制信号端与所述像素补偿电路连接的M个发光单元一一对应，每个所述发光控制信号端用于通过其所连接的像素补偿电路，驱动对应的发光单元发光。
  2. 根据权利要求1所述的像素电路，其中，
    所述像素电路还包括与所述多组像素补偿电路一一对应的多个总发光控制信号端，每个所述总发光控制信号端与对应的一组像素补偿电路中的每个像素补偿电路连接。
  3. 根据权利要求1或2所述的像素电路，其中，
    每组发光单元中位于同一列的所述M个发光单元彼此相邻。
  4. 根据权利要求3所述的像素电路，其中，
    M＝2。
  5. 根据权利要求1至4任一所述的像素电路，其中，
    每组像素补偿电路中的所述K行像素补偿电路彼此相邻。
  6. 根据权利要求5所述的像素电路，其中，
    K＝2。
  7. 根据权利要求1至6任一所述的像素电路，其中，
    每个所述像素补偿电路所连接的M个发光控制信号端中的第m个发光控制信号端，与所述像素补偿电路所连接的M个发光单元中的第m个发光单元对应，m为不大于M的正整数。
  8. 根据权利要求2至7任一所述的像素电路，其中，每个所述像素补偿电路包括：复位子电路、第一发光控制子电路以及M个第二发光控制子电路；
    所述复位子电路分别与复位信号端和复位电源端连接，并且所述复位子电路与所述第一发光控制子电路连接于第一节点处，所述复位子电路用于响应于来自所述复位信号端的复位信号，向所述第一节点输入来自所述复位电源端的复位电源信号；
    所述第一发光控制子电路分别与所述总发光控制信号端、电源端、数据信号端和驱动电源端连接，并且所述第一发光控制子电路与所述M个第二发光控制子电路连接于第二节点处，所述第一发光控制子电路用于响应于所述第一节点的电位、来自所述总发光控制信号端的总发光控制信号、来自电源端的电源信号以及来自所述驱动电源端的驱动电源信号，向所述第二节点输入来自所述数据信号端的数据信号；
    每个所述第二发光控制子电路分别与对应的一组发光控制信号端中的一个发光控制信号端以及一个发光单元连接，每个所述第二发光控制子电路用于响应于来自其所连接的发光控制信号端提供的发光控制信号，驱动其所连接的发光单元发光。
  9. 根据权利要求8所述的像素电路，其中，每个所述第二发光控制子电路包括：第一晶体管；
    所述第一晶体管的栅极与一个发光控制信号端连接，所述第一晶体管的第一极与所述第二节点连接，所述第一晶体管的第二极与一个发光单元连接。
  10. 根据权利要求8或9所述的像素电路，其中，所述复位子电路包括： 第二晶体管；
    所述第二晶体管的栅极与所述复位信号端连接，所述第二晶体管的第一极与复位电源端连接，所述第二晶体管的第二极与所述第一节点连接；
    所述第一发光控制子电路包括：第三晶体管、第四晶体管、第五晶体管、第六晶体管和存储电容；
    所述第三晶体管的栅极与所述驱动电源端连接，所述第三晶体管的第一极与所述数据信号端连接，所述第三晶体管的第二极与第三节点连接；
    所述第四晶体管的栅极与所述总发光控制信号端连接，所述第四晶体管的第一极与所述第三节点连接，所述第四晶体管的第二极与所述电源端连接；
    所述第五晶体管的栅极与所述第一节点连接，所述第五晶体管的第一极与所述第三节点连接，所述第五晶体管的第二极与所述第二节点连接；
    所述第六晶体管的栅极与所述驱动电源端连接，所述第六晶体管的第一极与所述第一节点连接，所述第六晶体管的第二极与所述第二节点连接；
    所述存储电容的一端与所述电源端连接，所述存储电容的另一端与所述第一节点连接。
  11. 一种像素电路的驱动方法，应用于如权利要求1至10任一所述的像素电路，所述方法包括：通过M个驱动子帧驱动所述像素电路，每个所述驱动子帧包括多个驱动阶段，每个所述驱动子帧包括的驱动阶段的个数与所述像素电路包括的像素补偿电路的组数以及发光控制信号端的组数相等，且所述多个驱动阶段与多组发光控制信号端一一对应，
    所述通过M个驱动子帧驱动所述像素电路包括：在每个所述驱动阶段的发光子阶段中，对应的一组发光控制信号端包括的M个发光控制信号端中的一个目标发光控制信号端提供的目标发光控制信号的电位为有效电位，除所述目标发光控制信号端之外的其他发光控制信号端提供的发光控制信号的电位为无效电位，与所述目标发光控制信号端连接的一组像素补偿电路在所述目标发光控制信号的控制下，驱动与所述目标发光控制信号端对应的发光单元发光。
  12. 根据权利要求11所述的方法，其中，所述像素电路还包括与所述多 组像素补偿电路一一对应的多个总发光控制信号端，每个所述总发光控制信号端与对应的一组像素补偿电路中的每个像素补偿电路连接；
    所述通过M个驱动子帧驱动所述像素电路还包括：在每个所述驱动阶段的发光子阶段中，与所述目标发光控制信号端连接的一组像素补偿电路所对应的一个总发光控制信号端提供的总发光控制信号的电位为有效电位。
  13. 根据权利要求11或12所述的方法，其中，每组发光单元包括位于同一列且相邻的两个发光单元，每组发光控制信号端包括两个发光控制信号端；
    所述通过M个驱动子帧驱动所述像素电路包括：通过两个驱动子帧驱动所述像素电路；以及
    所述通过两个驱动子帧驱动所述像素电路包括：
    在第一个驱动子帧的每个所述驱动阶段的发光子阶段中，与所述驱动阶段对应的一组发光控制信号端中的一个发光控制信号端提供的发光控制信号的电位为有效电位，另一个发光控制信号端提供的发光控制信号的电位为无效电位；
    在第二个驱动子帧的每个所述驱动阶段的发光子阶段中，与所述驱动阶段对应的一组发光控制信号端中所述另一个发光控制信号端提供的发光控制信号的电位为有效电位，除所述另一个发光控制信号端之外的一个发光控制信号端提供的发光控制信号的电位为无效电位。
  14. 根据权利要求12或13所述的方法，其中，每个所述像素补偿电路包括：复位子电路、第一发光控制子电路以及M个第二发光控制子电路；每个所述驱动阶段还包括：位于所述发光子阶段之前的重置子阶段和K个补偿子阶段；
    所述通过M个驱动子帧驱动所述像素电路还包括：
    在所述重置子阶段中，所述驱动阶段对应的一组发光控制信号端所连接的一组像素补偿电路中，第一行像素补偿电路的复位信号端提供的复位信号的电位为有效电位，所述复位子电路响应于所述复位信 号，向第一节点输入来自复位电源端的复位电源信号；
    在所述K个补偿子阶段的第k个补偿子阶段中，所述一组像素补偿电路中，第k行像素补偿电路所连接的驱动电源端提供的驱动电源信号的电位为有效电位，所述一组像素补偿电路连接的总发光控制信号端提供的总发光控制信号的电位为无效电位，所述第k行像素补偿电路中每个像素补偿电路的第一发光控制子电路响应于所述驱动电源信号、所述第一节点的电位以及电源端提供的电源信号，向第二节点输入来自数据信号端的数据信号，k为不大于K的正整数；
    在所述发光子阶段中，所述一组像素补偿电路连接的总发光控制信号的电位为有效电位，所述一组像素补偿电路中，每个像素补偿电路的M个第二发光控制子电路中与所述目标发光控制信号端连接的第二发光控制子电路响应于所述目标发光控制信号，驱动其所连接的发光单元发光。
  15. 一种显示装置，包括：
    如权利要求1至10任一所述的像素电路；以及
    多组发光单元，每组所述发光单元包括M个发光单元，M为大于1的整数，
    其中，所述像素电路中的每个像素补偿电路与一组所述发光单元连接。
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