WO2019114400A1 - 显示面板的亮度调节方法、显示面板及其驱动方法 - Google Patents

显示面板的亮度调节方法、显示面板及其驱动方法 Download PDF

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Publication number
WO2019114400A1
WO2019114400A1 PCT/CN2018/110281 CN2018110281W WO2019114400A1 WO 2019114400 A1 WO2019114400 A1 WO 2019114400A1 CN 2018110281 W CN2018110281 W CN 2018110281W WO 2019114400 A1 WO2019114400 A1 WO 2019114400A1
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Prior art keywords
display area
display
display panel
signal
pulse width
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PCT/CN2018/110281
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English (en)
French (fr)
Inventor
喻勇
兰传艳
申丽霞
常小幻
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP18857380.2A priority Critical patent/EP3726516A4/en
Priority to US16/336,706 priority patent/US11417271B2/en
Publication of WO2019114400A1 publication Critical patent/WO2019114400A1/zh

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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
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    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
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    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
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    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0213—Addressing of scan or signal lines controlling the sequence of the scanning lines with respect to the patterns to be displayed, e.g. to save power
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0218—Addressing of scan or signal lines with collection of electrodes in groups for n-dimensional addressing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/067—Special waveforms for scanning, where no circuit details of the gate driver are given
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
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    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0686—Adjustment of display parameters with two or more screen areas displaying information with different brightness or colours

Definitions

  • Embodiments of the present disclosure relate to a brightness adjustment method of a display panel, a display panel, and a method of driving the same.
  • Electroluminescent elements have been increasingly used in display panels as a current-type light-emitting device. Due to the self-luminous property, the electroluminescent display panel does not require a backlight, and has the advantages of high contrast, thin thickness, wide viewing angle, fast reaction speed, flexibility, simple structure and simple process. Therefore, the electroluminescent display panel gradually becomes The next generation of mainstream display panels.
  • the organic light emitting diode (OLED) display panel realizes the display function through the OLED array, and is an electroluminescent display panel which is widely used.
  • At least one embodiment of the present disclosure provides a brightness adjustment method of a display panel.
  • the display panel includes a display area, and the brightness adjustment method includes: determining a target pulse width of a gate signal input to the display area based on a data write time determined for the display area; adjusting a pulse width of the gate signal Up to the target pulse width to bring the display area to a corresponding target brightness.
  • the display panel includes a plurality of display areas, each of which has a data write time
  • the brightness adjustment method further includes: determining the Data writing time of each display area, wherein determining the data writing time of each of the display areas comprises: acquiring initial brightness corresponding to each of the display areas; according to the initial brightness and each of the The target brightness corresponding to the display area is determined, and the data writing time corresponding to each display area is determined.
  • the display panel includes a plurality of display areas and power lines for supplying power voltages to the plurality of display areas, and each display area corresponds to a data writing time
  • the brightness adjusting method further comprising: determining a data writing time of each of the display areas, wherein determining the data writing time of each of the display areas comprises: acquiring the plurality of display area edges An arrangement order of the voltage drop directions of the power lines; determining a data write time corresponding to each of the display areas according to the arrangement order and the number of the plurality of display areas.
  • the plurality of data writing times corresponding to the plurality of display areas are sequentially decreased along the voltage drop direction of the power line.
  • the display panel further includes a gate driving circuit, and adjusting a pulse width of the gate signal to the target pulse width includes: writing based on the data The input time adjusts a pulse width of an input signal of the gate driving circuit; and adjusts a pulse width of the gate signal to the target pulse width according to a pulse width of an input signal of the adjusted gate driving circuit.
  • an input signal of the gate driving circuit includes at least one input sub-signal.
  • the display panel includes a plurality of pixel units, the plurality of pixel units are arranged in a plurality of rows and columns, and the display regions each include at least one row.
  • the pixel unit includes a plurality of pixel units, the plurality of pixel units are arranged in a plurality of rows and columns, and the display regions each include at least one row.
  • each pixel unit includes a light emitting element, a driving circuit, and a storage capacitor
  • the driving circuit is configured to control a driving current flowing through the light emitting element
  • the storage capacitor is coupled to the control terminal of the drive circuit to store a data voltage signal applied to the control terminal, the data write time being less than a charge time for charging the storage capacitor to bring it to a saturated state.
  • the display panel is an organic light emitting diode display panel.
  • At least one embodiment of the present disclosure also provides a display panel including: a display area, a brightness adjustment circuit, and a gate drive circuit.
  • the brightness adjustment circuit is configured to: adjust a pulse width of an input signal of the gate driving circuit based on a data writing time determined for the display area; the gate driving circuit is configured to: according to the adjusted Describe the pulse width of the input signal, and output a gate signal to the display area to bring the display area to a corresponding target brightness.
  • the display panel includes a plurality of display areas
  • the brightness adjustment circuit includes a memory and a processor
  • each display area corresponds to a data write time
  • the memory is Configuring to acquire and store initial brightness corresponding to each display area
  • the processor is configured to determine, according to the initial brightness and target brightness corresponding to each display area, that each display area corresponds to The data is written to the time.
  • the display panel includes a plurality of display areas and a power supply line for supplying a power supply voltage to the plurality of display areas
  • the brightness adjustment circuit includes a memory and a processor.
  • Each display area corresponds to a data write time
  • the memory is configured to acquire and store an arrangement order of the plurality of display areas along a voltage drop direction of the power line and a quantity of the plurality of display areas
  • the processor is configured to determine a data write time corresponding to each of the display regions according to the arrangement order and the number of the plurality of display regions.
  • a plurality of data writing times corresponding to the plurality of display areas are sequentially decreased along a voltage drop direction of the power line.
  • an input signal of the gate driving circuit includes at least one input sub-signal.
  • an output end of the brightness adjustment circuit is connected to an input end of the gate driving circuit, and the brightness adjustment circuit is configured to be determined based on the display area.
  • the data write time adjusts a pulse width of the at least one input sub-signal; and the adjusted at least one input sub-signal is output to the input end of the gate drive circuit through the output end.
  • At least one embodiment of the present disclosure also provides a display panel including: a display area and a gate driving circuit.
  • the display area includes a plurality of pixel units, the gate driving circuit is configured to provide a gate signal having a target pulse width to the pixel unit; the pixel unit is configured to receive the gate signal and be gated by the gate
  • the signal controls illumination to bring the display area to a corresponding target brightness.
  • the target pulse width is obtained based on a data write time determined for the display area to adjust a pulse width of a gate signal input to the display area.
  • At least one embodiment of the present disclosure further provides a driving method applied to a display panel provided by an embodiment of the present disclosure, including: a data writing phase and a display phase.
  • the pixel unit includes a light emitting element, a driving circuit, and a storage capacitor. Writing, in the data writing phase, a target data voltage signal to the storage capacitor under control of the gate signal; in the display phase, the driving circuit drives the light emitting device to emit light according to the target data voltage signal So that the display area reaches a corresponding target brightness.
  • FIG. 1 is a flowchart of a method for adjusting brightness of a display panel according to an embodiment of the present disclosure
  • 2A is a schematic structural view of a 2T1C pixel circuit
  • 2B is a schematic structural diagram of a pixel circuit having a compensation function
  • 3 is a signal timing diagram of a pixel circuit having a compensation function
  • FIG. 5 is a schematic diagram of light emission brightness of an OLED display panel according to an embodiment of the present disclosure.
  • FIG. 6 is a flowchart of determining a data write time in a brightness adjustment method according to an embodiment of the present disclosure
  • FIG. 7 is a flowchart of determining a data write time in another brightness adjustment method according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a waveform of a gate signal before adjustment and a waveform of a gate signal after adjustment according to an embodiment of the present disclosure
  • FIG. 9 is a flowchart of adjusting a gate signal in a brightness adjustment method according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural view of a gate driving circuit
  • 11 is a signal timing diagram of a gate driving circuit
  • FIG. 12 is a schematic structural diagram of a sub-circuit of a gate driving circuit
  • FIG. 13 is a block diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 14 is a block diagram of another display panel according to an embodiment of the present disclosure.
  • FIG. 15 is a schematic flowchart of a driving method of a display panel according to an embodiment of the present disclosure.
  • the organic light emitting diode (OLED) display panel is divided into an active OLED (AMOLED) display panel and a passive OLED (PMOLED) display panel.
  • the pixel circuit of the AMOLED display panel may include a selection transistor, a driving transistor, and a storage capacitor. The selection transistor is turned on/off by the scan signal, thereby charging a voltage corresponding to the display data to the storage capacitor, thereby controlling the conduction degree of the driving transistor by the data voltage stored by the storage capacitor, thereby controlling the current flowing through the OLED, and adjusting The brightness of the OLED.
  • the AMOLED display panel can include an internal power supply circuit to provide a constant voltage (eg, a first supply voltage). Since the power supply line of the internal power supply circuit has a certain resistance value, an IR drop is generated along the extending direction of the power supply line (ie, the wiring direction of the power supply line), that is, the voltage drop direction along the power supply line, first The power supply voltage will change and the first supply voltage will be different at different locations on the power line. The difference in the first power supply voltage causes a difference in brightness of the display panel, resulting in a lower brightness uniformity of the display panel. On the other hand, the difference in device performance due to the manufacturing process of the display panel also affects the brightness uniformity of the display panel, thereby affecting the display quality.
  • a constant voltage eg, a first supply voltage
  • At least one embodiment of the present disclosure provides a brightness adjustment method of a display panel, a display panel, and a driving method thereof.
  • the brightness adjustment method can solve the problem of uneven brightness caused by factors such as voltage drop of the internal power supply circuit and difference in device performance, improve brightness uniformity of the display panel, and improve display quality.
  • FIG. 1 is a flowchart of a method for adjusting brightness of a display panel according to an embodiment of the present disclosure. Referring to FIG. 1 , the method for adjusting brightness includes:
  • S11 determining a target pulse width of a gate signal input to the display area based on a data writing time determined for the display area;
  • the display panel may be an organic light emitting diode (OLED) display panel and includes a display area.
  • the display area includes a plurality of pixel units, each of which includes a pixel circuit and a light emitting element (eg, an OLED).
  • the pixel circuit can include a drive circuit and a storage capacitor.
  • the drive circuit is configured to control a drive current flowing through the light emitting element, the storage capacitor being coupled to the control terminal of the drive circuit to store a data voltage signal applied to the control terminal of the drive circuit.
  • the pixel circuit receives the gate signal and the data voltage signal and writes the data voltage signal to the storage capacitor within the effective pulse width of the gate signal.
  • the data write time may be the time at which the data voltage signal is written to the storage capacitor, and the data write time is determined by the pulse width of the gate signal.
  • the basic pixel circuit can be a 2T1C pixel circuit that utilizes two TFTs (thin film transistors) and one storage capacitor Cs to achieve the basic function of driving OLED illumination.
  • 2A is a schematic structural view of a 2T1C pixel circuit. Referring to FIG. 2A, the pixel circuit includes a first transistor T1, a driving transistor N0 (ie, a driving circuit), and a storage capacitor Cs.
  • the gate of the first transistor T1 is connected to the gate line to receive the first gate signal Sn, the source is connected to the data line to receive the data voltage signal Vdata, the drain is connected to the gate of the driving transistor N0; the source of the driving transistor N0 Connected to the first power terminal Vdd (eg, high voltage terminal), the drain is connected to the anode terminal of the OLED; one end of the storage capacitor Cs is connected to the drain of the first transistor T1 and the gate of the driving transistor N0, and the other end is connected to the driving The source of the transistor N0 and the first power terminal Vdd; the cathode end of the OLED is connected to the second power terminal Vss (for example, the low voltage terminal), and the second power terminal Vss is, for example, a ground terminal.
  • Vdd high voltage terminal
  • the data voltage Vdata fed through the data line by the data driving circuit charges the storage capacitor Cs via the first transistor T1, thereby storing the data voltage Vdata in The storage capacitor Cs, and the stored data voltage Vdata controls the degree of conduction of the driving transistor N0, thereby controlling the magnitude of the current flowing through the driving transistor N0 to drive the OLED to emit light, that is, the current determines the luminance of the OLED.
  • the first transistor T1 may be an N-type transistor
  • the driving transistor N0 may be a P-type transistor
  • the first transistor T1 may also be a P-type transistor, as long as the polarity of the first gate signal Sn that is turned on or off is controlled to be changed accordingly.
  • the driving transistor N0 can also be an N-type transistor, which is not limited in the embodiment of the present disclosure.
  • the pixel circuit may also include other circuit structures having compensation functions.
  • the compensation function can be realized by voltage compensation, current compensation or hybrid compensation, and the pixel circuit with compensation function can be, for example, 4T1C or 4T2C.
  • a pixel circuit having a compensation function includes a data write circuit, a compensation circuit, a drive circuit, and a memory circuit.
  • the driving circuit includes a driving transistor, and the storage circuit includes a storage capacitor.
  • the data write circuit and the compensation circuit cooperate to write the data voltage signal and the threshold voltage of the drive transistor to the gate of the drive transistor and store through the memory circuit.
  • the pixel circuit includes a driving transistor N0, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a storage capacitor Cs.
  • the drive transistor N0 is used to supply current to the OLEDs connected thereto.
  • the driving transistor N0, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all P-type transistors.
  • the driving transistor N0, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may also be N-type transistors, which are not limited in the embodiments of the present disclosure.
  • the source of the third transistor T3 is connected to the gate of the driving transistor N0
  • the drain of the third transistor T3 is connected to the drain of the driving transistor N0
  • the gate of the third transistor T3 receives the first gate signal Sn.
  • the first gate signal Sn When the first gate signal Sn is active, the first transistor T1, the driving transistor N0, and the third transistor T3 are turned on, and thus the data voltage signal Vdata charges the storage capacitor Cs through the first transistor T1, the driving transistor N0, and the third transistor T3. .
  • the threshold voltage of the driving transistor N0 is recorded, that is, the voltage value carrying the data voltage signal Vdata and the threshold voltage of the driving transistor N0 is stored by the storage capacitor Cs. Therefore, in the process in which the driving transistor N0 drives the OLED to emit light, its threshold voltage is compensated.
  • the structure of the pixel circuit having the compensation function is not limited thereto, and may be any applicable structure.
  • FIG. 3 is a signal timing diagram of the pixel circuit shown in FIG. 2B.
  • the first gate signal Sn is a scan signal applied to the current scan line
  • the second gate signal Sn-1 is a scan signal applied to a previous scan line adjacent to the current scan line.
  • En is the illumination control signal.
  • the second transistor T2 is turned on, and the storage capacitor Cs is discharged, thereby initializing the storage capacitor Cs.
  • the first transistor T1, the driving transistor N0 and the third transistor T3 are turned on, thereby charging the storage capacitor Cs to store the data voltage signal Vdata and the threshold voltage Vth of the driving transistor N0, that is, the storage capacitor Cs is stored.
  • the voltage is Vdata+Vth.
  • the fourth transistor T4, the driving transistor N0, and the fifth transistor T5 are turned on, so that the driving transistor N0 supplies an illuminating current to the OLED according to the voltage stored in the storage capacitor Cs, and the OLED emits light corresponding to the illuminating current. .
  • the process of writing the data voltage signal Vdata is essentially a process of charging the storage capacitor Cs.
  • the data write time may be a time at which the data voltage signal Vdata charges the storage capacitor Cs via the first transistor T1.
  • the amount of charge in the storage capacitor is related to the charging time.
  • the type of storage capacitor is not limited. According to the preparation process, an organic dielectric capacitor, an inorganic dielectric capacitor, an electrolytic capacitor or an air dielectric capacitor may be selected, or other suitable capacitors may be used.
  • Figure 4 is a graph showing the relationship between the amount of charge of the storage capacitor and the charging time.
  • the abscissa is the charging time t
  • the ordinate is the amount of charge Q
  • the amount of charge corresponding to the data voltage signal Vdata is the target amount of charge Q3.
  • the amount of charge Q increases, and the closer the amount of charge Q is to the target amount of charge Q3, the closer the capacitance of the capacitor (ie, the voltage difference across the capacitor) is to the data voltage signal Vdata.
  • the charge amount Q is positively correlated with the charging time t.
  • the first charging time t1 corresponds to the first amount of charge Q1
  • the second charging time t2 corresponds to the second amount of charge Q2, and when t2>t1, then Q2>Q1.
  • the capacitor storage voltage is positively correlated with the charge amount Q.
  • the capacitor storage voltage corresponding to the first charge amount Q1 is U1
  • the capacitance storage voltage corresponding to the second charge amount Q2 is U2, and when Q2>Q1, U2>U1.
  • the charging time of the storage capacitor affects the amount of charge, thereby affecting the voltage difference across the storage capacitor, thereby affecting the current flowing through the OLED, and ultimately affecting the luminance of the OLED.
  • the charging time of the storage capacitor is equivalent to the data writing time, and the data writing time is determined by the pulse width of the gate signal input to the pixel circuit. The wider the pulse width of the gate signal, the longer the data write time. Therefore, by adjusting the pulse width of the gate signal, the charging time of the storage capacitor can be adjusted, thereby adjusting the capacitance storage voltage, and thus the brightness of the OLED of the pixel unit can be controlled.
  • FIG. 5 is a schematic diagram of a light-emitting luminance of an OLED display panel according to an embodiment of the present disclosure
  • FIG. 6 is a flowchart of determining a data write time in a brightness adjustment method according to an embodiment of the present disclosure. A method for determining a data write time according to an embodiment of the present disclosure is described in detail below with reference to FIG. 5 and FIG.
  • the display panel includes a plurality of display areas and power lines for supplying power voltages to the plurality of display areas, each of the display areas corresponding to a data writing time, and the plurality of display areas corresponding to A plurality of data write times, and the plurality of data write times are in one-to-one correspondence with the plurality of display areas, that is, one display area corresponds to only one data write time. If the display panel includes W display areas, the W display areas correspond to W data write times, and the first display area corresponds to the first data write time, and the second display area corresponds to the second data write time. And so on, the Wth display area corresponds to the Wth data write time.
  • the brightness adjustment method further includes determining a data write time of each display area.
  • the operation of determining the data write time of each display area may include:
  • Step S201 obtaining an arrangement order of a plurality of display areas along a voltage drop direction of the power line
  • Step S202 determining a data writing time corresponding to each display area according to the arrangement order and the number of the plurality of display areas.
  • the first power supply terminal Vdd supplies power to each pixel unit through an internal power supply circuit provided on the display panel. Since the power supply line in the internal power supply circuit has a certain resistance value, a voltage drop occurs along the extending direction of the power supply line (for example, the wiring direction of the power supply line, that is, the voltage drop direction of the power supply line), that is, each display area is received.
  • the first power supply voltages outputted by the first power supply terminal Vdd are different from each other, for example, sequentially decreasing along the voltage drop direction of the power supply line. The difference in the first power supply voltage may cause a difference in brightness of each display area of the display panel, resulting in poor uniformity of brightness of the display panel.
  • a rectangular display panel in a first direction, may be divided into seven display areas along its length direction (ie, first display area 1, second display area 2, third display area 3, The fourth display area 4, the fifth display area 5, the sixth display area 6, and the seventh display area 7).
  • the power supply line in the internal power supply circuit is routed along the direction from the seventh display area 7 to the first display area 1 (ie, the first direction), that is, the voltage drop direction of the power supply line is along the seventh display area 7
  • the data voltage signals Vdata input to the respective display areas may be the same.
  • the number in the circle shown in FIG. 5 indicates the actual light-emitting brightness of the circle area.
  • the light-emitting brightness of the display panel is from the seventh display area. 7 to the first display area 1 is sequentially lowered, the seventh display area 7 has the highest light emission luminance, and the first display area 1 has the smallest light emission luminance.
  • each display area may be a rectangle. However, it is not limited thereto, and each display area may be other rules or irregular shapes.
  • the first power supply voltages received by the first to seventh display regions 1 to 7 may be V11, V12, . . . V16 and V17, respectively. Since there is a voltage drop along the extending direction of the power line, the first power voltage received by each display area is sequentially decreased along the first direction, that is, V17>V16> ⁇ >V12>V11. According to the current equation flowing through the OLED, when the data voltage signal Vdata input to each display region is the same, when the value of the first power supply voltage is changed, the obtained current is different.
  • the scanning order of each display area is not limited, and scanning may be performed in a direction from the seventh display area 7 to the first display area 1 (ie, a first direction), or may be displayed in a display from the first display area 1 to the seventh display area
  • the direction of the region 7 i.e., the opposite direction of the first direction is scanned, which is not limited by the embodiment of the present disclosure.
  • step S201 the order of arrangement of the plurality of display areas along the power supply line voltage drop direction is first acquired, that is, the arrangement order is the seventh display area 7, the sixth display area 6, ... up to the first display area 1. Then, according to the above-described arrangement order and the number of the plurality of display areas (for example, 7), a plurality of data writing times (for example, 7 pieces of data writing time) corresponding to the respective display areas are respectively determined.
  • the data writing time corresponding to the seventh display area 7 is determined according to the arrangement order and the number of the plurality of display areas; and then, corresponding to the sixth display area 6 is determined according to the arrangement order and the number of the plurality of display areas
  • the data writing time, and so on, finally, the data writing time corresponding to the first display area 1 is determined according to the arrangement order and the number of the plurality of display areas, thereby determining a plurality of data writing times.
  • the data writing time of the seventh display area 7 is the longest, and the data writing time of the first display area 1 is the shortest. From the seventh display area 7 to the first display area 1, the data writing time of each display area is sequentially decreased. That is, the data writing time of each display area is sequentially decreased along the voltage drop direction of the power line.
  • each data write time is not limited and can be determined according to actual needs.
  • the data writing time of each display area may be 10% or 20% smaller than the data writing time of the adjacent previous display area or other applicable ratio (for example, the data writing of the sixth display area 6)
  • the entry time is 10% smaller than the data write time of the seventh display area 7
  • the data write time of the fifth display area 5 is 10% smaller than the data write time of the sixth display area 6, and so on.
  • the plurality of display areas may be divided into one group, whereby the display panel may include a plurality of display area groups.
  • the plurality of display area groups are sorted, and according to the arrangement order, the data writing time corresponding to each display area group may be 5% smaller than the data writing time corresponding to the adjacent previous display area group or other applicable ratio.
  • the seventh display area 7 and the sixth display area 6 are divided into a first display area group, and the fifth display area 5 to the first display area 1 are divided into second display area groups, so that data of the second display area group is made.
  • the write time is 5% less than the data write time of the first display area group.
  • the target pulse width of the gate signal input to each display region is determined according to the plurality of data write times determined as described above, and the pulse width of the gate signal is adjusted to the target pulse width. For example, determining a target pulse width of the gate signal input to the first display region 1 according to a data writing time corresponding to the first display region 1; determining input to the second display according to a data writing time corresponding to the second display region 2 The target pulse width of the gate signal of region 2; and so on.
  • a schematic diagram of the waveform of the gate signal before adjustment and the waveform of the gate signal after adjustment is shown in FIG. Referring to Fig. 8, the waveforms shown in the figure are combined waveforms of waveforms input to respective display areas.
  • GO is the gate signal waveform before adjustment, and the pulse width of the gate signal of each display area is the same, both are t0.
  • the pulse widths of the front gate signals may be the same or different.
  • the pulse width of the gate signal can be pre-processed according to the empirical value before the adjustment, so that the pulse width of the adjustment front gate signal is different.
  • GO' is the adjusted gate signal waveform, that is, the gate signal waveform having the target pulse width, and the target pulse width of each gate display signal is different. For example, from the seventh display area 7 to the first display area 1, the target pulse width of the gate signal is successively decreased, that is, t02 ⁇ t01 ⁇ t0.
  • the pixel circuit charges the storage capacitor according to the target pulse width of the gate signal. Therefore, when the data voltage signals Vdata are the same, from the seventh display area 7 to the first display area 1, the capacitance storage voltages corresponding to the respective display areas are sequentially decreased.
  • the power line in the internal power supply circuit may affect the brightness uniformity of the display panel, the difference in device performance caused by the manufacturing process of the display panel, such as the difference in performance of the TFT or the storage capacitor in the pixel circuit, or the electromagnetic interference received by the display panel during operation. Etc. also affects brightness uniformity.
  • the factor affecting the brightness uniformity may be any factor, and the embodiment of the present disclosure does not limit this.
  • FIG. 7 is a flowchart of determining a data write time in another brightness adjustment method according to an embodiment of the present disclosure. Another method for determining data write time according to an embodiment of the present disclosure is described in detail below with reference to FIG. 5 and FIG.
  • the display panel includes a plurality of display areas, each display area corresponding to a data write time, the plurality of display areas corresponding to a plurality of data write times, and a plurality of data writes
  • the time corresponds to a plurality of display areas, that is, one display area corresponds to only one data write time.
  • the brightness adjustment method further includes determining a data write time of each display area.
  • the operation of determining the data write time of each display area may include:
  • Step S101 acquiring initial brightness corresponding to each display area
  • Step S102 determining a data writing time corresponding to each display area according to the initial brightness and the target brightness corresponding to each display area.
  • a plurality of display areas are in one-to-one correspondence with a plurality of initial brightnesses, that is, one display area corresponds to only one initial brightness.
  • the plurality of display areas are in one-to-one correspondence with the plurality of target brightnesses, that is, one display area corresponds to only one target brightness.
  • the display panel includes W display areas
  • the W display areas correspond to W initial brightnesses
  • the first display area corresponds to the first initial brightness
  • the second display area corresponds to the second initial brightness
  • the Wth The display area corresponds to the Wth initial brightness
  • the W display areas correspond to W target brightnesses
  • the first display area corresponds to the first target brightness
  • the second display area corresponds to the second target brightness
  • the Wth The display area corresponds to the Wth target brightness.
  • the display panel includes a first display area and a second display area, and the brightness of the first display area is smaller than the brightness of the second display area.
  • the brightness of the first display area may also be greater than or equal to the brightness of the second display area.
  • step S101 includes: inputting the same data voltage signal Vdata to the first display area and the second display area; detecting actual light-emitting brightness of the first display area and the second display area to obtain the first display The first initial brightness corresponding to the area 1 and the second initial brightness corresponding to the second display area 2.
  • the brightness of the first display area 1 is smaller than the brightness of the second display area 2, that is, the first initial brightness is smaller than the second initial brightness.
  • step S102 includes: obtaining a first target brightness corresponding to the first display area 1 and a second target brightness corresponding to the second display area 2 according to the data voltage signal Vdata; according to the first initial brightness, the second initial brightness, The first target brightness and the second target brightness determine a first data write time corresponding to the first display area 1 and a second data write time corresponding to the second display area 2.
  • the same data voltage signal Vdata is input to the first display area and the second display area, and the first target brightness and the second target brightness are the same.
  • the first data write time is less than the second data write time. It should be noted that the quantitative relationship between the first data write time and the second data write time is not limited and may be determined according to actual needs.
  • the pulse width of the gate signal is adjusted to the target pulse width according to the first data write time and the second data write time.
  • the target pulse width of the gate signal corresponds to the data write time, so that the target pulse width of the gate signal corresponding to the first display region 1 is smaller than the target pulse width of the gate signal corresponding to the second display region 2.
  • the pixel circuit charges the storage capacitor according to the target pulse width of the gate signal. Therefore, when the data voltage signal Vdata is the same, the capacitance storage voltage corresponding to the first display area 1 is smaller than the capacitance storage voltage corresponding to the second display area 2.
  • the data voltage signal Vdata voltage is 4V
  • the threshold voltage Vth of the driving transistor N0 is 2V. Due to IR DROP, assuming that the first power supply voltage V12 at the second display area 2 in FIG. 5 is 4.5V, the first power supply voltage V11 of the first display area 1 is 4.3V.
  • the capacitance storage voltage corresponding to the first display area 1 is Vdata1-Vth
  • the capacitance storage voltage corresponding to the second display area 2 is Vdata2-Vth.
  • the brightness of the second display area 2 is greater than the brightness of the first display area 1.
  • the capacitance storage voltage corresponding to the first display area 1 is Vdata1'-Vth
  • the capacitance storage voltage corresponding to the second display area 2 is Vdata2'-Vth.
  • Vdata1'-Vth is smaller than Vdata2'-Vth, so that the Vgs1 and Vgs2 gaps are reduced or become equal.
  • Vdata1'-Vth is 1.8V
  • Vdata2'-Vth is 2V
  • ie Vgs1 Vgs2
  • the brightness adjustment method of the embodiment of the present disclosure can improve the brightness uniformity of the display panel by gradually adjusting the data writing time of different areas.
  • the capacitor storage voltage corresponding to the first display area 1 is smaller than that of the second display area 2, regardless of factors such as the voltage drop of the power supply line in the internal power supply circuit and/or the difference in device characteristics caused by the display panel manufacturing process.
  • the capacitor stores the voltage, so the brightness of the first display area 1 should be greater than the brightness of the second display area 2.
  • the influence of the voltage drop of the power supply line in the internal power supply circuit and/or the difference in device characteristics caused by the manufacturing process of the display panel on the display brightness and the influence of the capacitance storage voltage on the display brightness can cancel each other, for example,
  • the brightness of the first display area 1 and the second display area 2 are the same or similar, and the purpose of improving brightness uniformity is achieved.
  • the shape and size of the first display area 1 and the second display area 2 may be the same.
  • the first display area 1 and the second display area 2 are each in the shape of, for example, a rectangle or a trapezoid.
  • the first display area 1 may include N rows of pixel units, and the second display area 2 also includes N rows of pixel units. N is a positive integer greater than zero.
  • the embodiment of the present disclosure is not limited thereto, and the shapes and/or sizes of the first display area 1 and the second display area 2 may also be different.
  • the first display area 1 may include N rows of pixel units, and the second display area 2 It may include M rows of pixel units, N and M are not the same, and N and M are both positive integers greater than zero. The embodiments of the present disclosure do not limit this.
  • the data write time (eg, the first data write time, the second data write time) of each display area needs to be less than the charging time for charging the storage capacitor in the pixel circuit to bring it to a saturated state.
  • the display area shown in FIG. 5 is only schematic, and the display area on the display panel can be divided into various required shapes and quantities according to actual design requirements, which is not limited in the embodiment of the present disclosure.
  • FIG. 9 is a flowchart of adjusting a gate signal in a brightness adjustment method according to an embodiment of the present disclosure.
  • adjusting the pulse width of the gate signal to the target pulse width in the brightness adjustment method may include:
  • Step S301 adjusting a pulse width of an input signal of the gate driving circuit based on a data writing time
  • Step S302 adjusting the pulse width of the gate signal to the target pulse width according to the pulse width of the input signal of the adjusted gate driving circuit.
  • the gate signal input to the pixel circuit may be provided by a gate driving circuit that outputs a gate signal to the pixel circuit to control the pixel unit for display.
  • the input signal to the gate drive circuit can be provided by a gate driver.
  • the input signal of the gate drive circuit includes at least one input sub-signal. In the step S301, any one of the input sub-signals may be adjusted, and the plurality of input sub-signals may be adjusted at the same time, which is not limited by the embodiment of the present disclosure.
  • FIG. 10 is a schematic structural view of a gate driving circuit.
  • the gate drive circuit includes a plurality of cascaded sub-circuits.
  • the gate driving circuit includes, for example, a first sub-circuit SR1, a second sub-circuit SR2, a third sub-circuit SR3, and a fourth sub-circuit SR4.
  • the number of sub-circuits is not limited to four, and may be any number. The number of sub-circuits can be determined according to the number of rows of pixel cells.
  • the input signal includes a plurality of input sub-signals such as a clock signal, an on signal GSTV, a high level signal VGH (not shown), and a low level signal VGL (not shown).
  • the clock signal may include a first clock signal CK and a second clock signal CB as needed to provide a clock to the sub-circuit. According to the circuit configuration, the clock signal is not limited to two, and may be one or more.
  • the high level signal VGH and the low level signal VGL are used to provide a constant voltage signal to the gate drive circuit.
  • each sub-circuit can receive a high level signal VGH and a low level signal VGL, and can also receive a plurality of high level signals VGH and a plurality of low level signals VGL, and can also not receive a high level.
  • the signal VGH and/or the low level signal VGL are not limited by the embodiments of the present disclosure.
  • the turn-on signal GSTV is input to the first sub-circuit SR1.
  • the turn-on signal GSTV can be, for example, one or more.
  • the output of the brightness adjustment circuit is coupled to the input of the gate drive circuit.
  • a plurality of input sub-signals eg, the turn-on signal GSTV, the first clock signal CK, and the second clock signal CB
  • the brightness adjustment circuit may be configured to adjust the time based on the data write determined for the display area
  • the pulse width of each of the input sub-signals; and the adjusted plurality of input sub-signals are output to the input end of the gate driving circuit through the output end.
  • the turn-on signal GSTV, the first clock signal CK, and the second clock signal CB are adjusted via the brightness adjustment circuit to obtain an on signal GSTV', a first clock signal CK', and a second clock signal CB'.
  • the turn-on signal GSTV', the first clock signal CK', and the second clock signal CB' may be input to the gate driving circuit to control the gate driving circuit output gate signal (eg, the gate signal may include the first gate shown in FIG. Signal GO1', second gate signal GO2', third gate signal GO3', fourth gate signal GO4').
  • the plurality of input sub-signals may include the first partial input sub-signal and the second partial input sub-signal, and the first partial input sub-signal may also be directly transmitted to the gate driving circuit, that is, the brightness adjusting circuit may only adjust multiple The second part of the input sub-signal inputs the sub-signal.
  • the first gate signal GO1', the second gate signal GO2', the third gate signal GO3', and the fourth gate signal GO4' are the first sub-circuit SR1, the second sub-circuit SR2, the third sub-circuit SR3, and the first The four sub-circuit SR4 outputs a line scan signal to the corresponding pixel unit.
  • the gate signals output by each sub-circuit are respectively used as the reset signals of the adjacent previous sub-circuits and the input signals of the adjacent next sub-circuits.
  • the second gate signal GO2' may serve as a reset signal of the first sub-circuit SR1 and an input signal of the third sub-circuit SR3
  • the third gate signal GO3' may serve as a reset signal of the second sub-circuit SR2 and the fourth sub-circuit SR4 Input signal.
  • Fig. 11 is a timing chart of signals of the gate driving circuit shown in Fig. 10.
  • the gate driving circuit may receive the turn-on signal GSTV', the first clock signal CK', and the second clock signal CB', and output a plurality of gate signals (eg, the first gate signal GO1', the second Gate signal GO2', third gate signal GO3', fourth gate signal GO4').
  • the first sub-circuit SR1 After receiving the turn-on signal GSTV', the first sub-circuit SR1 outputs a first gate signal GO1' when the corresponding first clock signal CK' is at a low level, and the first gate signal GO1' is, for example, a low-level square wave.
  • the first gate signal GO1' is output to the corresponding pixel unit to cause it to perform a data write operation.
  • the first gate signal GO1' is also transmitted as an input signal to the second sub-circuit SR2.
  • the corresponding gate signal is output when the corresponding clock signal is low.
  • the gate signal is output to a corresponding pixel unit to cause a data write operation.
  • the gate signal is also transmitted as an input signal to the next adjacent sub-circuit, and is also transmitted as a reset signal to the adjacent previous sub-circuit. This is done until the end of the output of the fourth sub-circuit SR4.
  • the turn-on signal GSTV, the first clock signal CK, and the second clock signal CB are input sub-signals before being adjusted by the brightness adjustment circuit, the turn-on signal GSTV', the first clock signal CK', and the second clock signal CB.
  • the first gate signal GO1, the second gate signal GO2, the third gate signal GO3, and the fourth gate signal GO4 are gate signals obtained according to the turn-on signal GSTV, the first clock signal CK, and the second clock signal CB, as shown in FIG.
  • the pulse width of the first gate signal GO1, the pulse width of the second gate signal GO2, the pulse width of the third gate signal GO3, and the pulse width of the fourth gate signal GO4 are all the same, the first gate signal GO1', the second gate signal
  • the GO2', the third gate signal GO3', and the fourth gate signal GO4' are gate signals obtained according to the turn-on signal GSTV', the first clock signal CK', and the second clock signal CB'.
  • the pulse widths of at least some of the gate signals of the first gate signal GO1', the second gate signal GO2', the third gate signal GO3', and the fourth gate signal GO4' are different. As shown in FIG.
  • the pulse width of the first gate signal GO1', the pulse width of the second gate signal GO2', the pulse width of the third gate signal GO3', and the pulse width of the fourth gate signal GO4' are different, and The pulse width of the first gate signal GO1' is greater than the pulse width of the second gate signal GO2', the pulse width of the second gate signal GO2' is greater than the pulse width of the third gate signal GO3', and the pulse width of the third gate signal GO3' is greater than The pulse width of the fourth gate signal GO4'.
  • each sub-circuit in the gate drive circuit turns off the output of the previous sub-circuit when it begins to output, even if the previous sub-circuit does not output a gate signal. That is, when the second sub-circuit SR2 performs output, the first sub-circuit SR1 turns off its output; when the third sub-circuit SR3 performs output, the second sub-circuit SR2 turns off its output.
  • each sub-circuit can realize the function of a shift register, and the gate drive circuit can realize sequential output of a plurality of gate signals.
  • the number of input signals and output gate signals of the gate driving circuit is not limited to the number described above, and may be any number, which may be determined according to actual needs.
  • the input sub-signal of the gate driving circuit may be an on signal GSTV, a first clock signal CK, a second clock signal CB, and the like.
  • the pulse width of the turn-on signal GSTV, the first clock signal CK or the second clock signal CB affects the pulse width of the gate signal. Therefore, the pulse width of the turn-on signal GSTV, the first clock signal CK or the second clock signal CB can be adjusted to achieve the purpose of adjusting the pulse width of the gate signal.
  • the input signal described in step S301 shown in FIG. 9 may include one or more of an on signal GSTV, a first clock signal CK, and a second clock signal CB. It should be noted that the input signal may also be other input signals of the gate driving circuit, which is not limited in the embodiment of the present disclosure.
  • the pulse width of the input sub-signal of the gate driving circuit is positively correlated with the pulse width of the gate signal output by the gate driving circuit, that is, the wider the pulse width of the input sub-signal of the gate driving circuit, the more the pulse width of the gate signal is. width.
  • the pulse width of the at least one input sub-signal may be increased, and the gate driving circuit receives the at least one input sub-signal and outputs The gate signal having the target pulse width, that is, the target pulse width of the adjusted gate signal is larger than the pulse width of the gate signal before the adjustment.
  • the pulse width of the at least one input sub-signal can be reduced, and the gate driving circuit receives the at least one input sub-signal. And outputting the gate signal having the target pulse width, that is, the target pulse width of the adjusted gate signal is smaller than the pulse width of the gate signal before the adjustment.
  • FIG. 12 is a circuit diagram showing the structure of the first sub-circuit SR1 in the gate driving circuit shown in FIG. It should be noted that the first sub-circuit SR1 generates and outputs the first gate signal GO1' according to the adjusted input sub-signal.
  • the first sub-circuit SR1 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a bypass capacitor C1.
  • the first electrode of the sixth transistor T6 is connected to the second clock signal CB', and the second electrode is connected to the first electrode of the seventh transistor T7 and outputs the first gate signal GO1'.
  • the gate of the sixth transistor T6 is connected to the first electrode of the eighth transistor T8 and the second electrode of the ninth transistor T9.
  • the second electrode of the seventh transistor T7 is connected to the second electrode of the eighth transistor T8 and the high level signal VGH.
  • the gate of the seventh transistor T7 is connected to the gate of the eighth transistor T8, and the gate of the seventh transistor T7 and the gate of the eighth transistor T8 each receive the second gate signal GO2'.
  • the first pole of the ninth transistor T9 is connected to its gate and receives the turn-on signal GSTV'.
  • One end of the bypass capacitor C1 is connected to the gate of the sixth transistor T6, and the other end is connected to the second electrode of the sixth transistor T6.
  • the ninth transistor T9 and the sixth transistor T6 are turned on, so the first gate signal GO1' is the second clock signal CB', that is, when the second clock signal CB When 'low', the first gate signal GO1' also outputs a low level.
  • the pulse width of the second clock signal CB' may be the pulse width of the first gate signal GO1'.
  • each of the above transistors is symmetrical, the source and the drain thereof can be interchanged.
  • the first pole can be a source or a drain, and the second pole can be a drain or a source.
  • each of the above transistors is a P-type transistor.
  • each of the above transistors is not limited to a P-type transistor, and may be an N-type transistor as long as the polarity of the control voltage signal of the gate of the transistor is changed.
  • the structure of the first sub-circuit SR1 is not limited to the structure described above, and the first sub-circuit SR1 may be any structure, and may also include more or fewer transistors and/or capacitors, such as the first sub-circuit. SR1 may also include sub-circuits for implementing pull-up node control, pull-down node control, noise reduction, and the like. Similarly, the remaining sub-circuits in the gate driving circuit (for example, the second sub-circuit SR2, the third sub-circuit SR3, and the fourth sub-circuit SR4) may be the structures described above, or may be any suitable structure, the present disclosure. The embodiment does not limit this.
  • FIG. 13 is a block diagram of a display panel according to an embodiment of the present disclosure.
  • the display panel 100 includes a display area 110, a brightness adjustment circuit 120, and a gate drive circuit 130.
  • the display panel can solve the problem of uneven brightness caused by factors such as voltage drop of the internal power supply circuit and difference in device performance, improve brightness uniformity of the display panel, and improve display quality.
  • the brightness adjustment circuit 120 and the gate drive circuit 130 are electrically connected, and are configured to adjust the pulse width of the input signal of the gate drive circuit 130 based on the data write time determined for the display area 110.
  • the output end of the brightness adjustment circuit 120 is electrically connected to the input end of the gate drive circuit 130, and the brightness adjustment circuit 120 can output the input signal of the adjusted gate drive circuit 130 to the gate drive circuit 130 through its output end. Input.
  • the brightness adjustment circuit 120 can include a memory and a processor configured to adjust a pulse width of an input signal of the gate drive circuit based on a data write time determined for the display area.
  • the memory can also store first computer program instructions, the processor being configured to execute the first computer program instructions to perform an operation based on a pulse width of an input signal of the time-stamped gate drive circuit for data determined for the display area.
  • the memory when the display panel includes a plurality of display areas and power lines for supplying power voltages to the plurality of display areas, each display area corresponding to a data write time, the memory is configured to acquire and store a plurality of The arrangement order of the display areas along the voltage drop direction of the power supply line and the number of the plurality of display areas; the processor is configured to determine the data write time corresponding to each display area according to the arrangement order and the number of the plurality of display areas.
  • the memory can also store second computer program instructions, the processor being configured to execute the second computer program instructions to perform an operation of determining a data write time corresponding to each display area according to an arrangement order and a number of display areas.
  • a plurality of data write times corresponding to a plurality of display areas are sequentially decreased in the direction of voltage drop of the power supply line.
  • each display area corresponds to a data write time.
  • the memory is configured to acquire and store an initial brightness corresponding to each display area; the processor is configured to determine a data write time corresponding to each display area based on the initial brightness and the target brightness corresponding to each display area.
  • the memory may further store third computer program instructions, the processor being configured to execute the third computer program instructions to perform determining a data write time corresponding to each display area according to an initial brightness and a target brightness corresponding to each display area Operation.
  • determining the data write time may refer to the related description of the method shown in FIG. 6 or FIG. 7 , and determining the data write time may also be determined according to other applicable methods. Embodiments of the present disclosure There is no limit to this.
  • the input signal of the gate driving circuit 130 may include one or more of the turn-on signal GSTV, the first clock signal CK, and the second clock signal CB, and may also be other applicable signals, and embodiments of the present disclosure No restrictions.
  • the brightness adjustment circuit is configured to: adjust a pulse width of the at least one input sub-signal based on a data write time determined for the display area; and output the adjusted at least one input sub-signal to the input of the gate drive circuit through the output end end.
  • the brightness adjustment circuit may further include an output sub-circuit including an output, and after the processor performs an operation of adjusting a pulse width of the at least one input sub-signal based on a data write time determined for the display area, the output sub-circuit may receive and The adjusted at least one input sub-signal is output to an input of the gate drive circuit.
  • the gate driving circuit 130 is configured to adjust the pulse width of the gate signal according to the pulse width of the adjusted input signal to obtain a gate signal having a target pulse width.
  • the gate signal having the target pulse width is output to the display area 110 to bring the display area 110 to the corresponding target brightness.
  • the display area 110 includes a plurality of pixel units, and the plurality of pixel units are arranged in a plurality of rows and columns.
  • a plurality of pixel units of each display area 110 receive a gate signal having a target pulse width output from the gate driving circuit 130, and emit light of a corresponding brightness, thereby causing each display area 110 to reach a corresponding target brightness.
  • the display panel may include more or less circuits, and the connection relationship between the respective circuits is not limited, and may be determined according to actual needs.
  • the specific configuration of each circuit is not limited, and may be composed of an analog device according to the circuit principle, a digital chip, or other suitable manner.
  • circuits in the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the solution. A person skilled in the art can use different methods to implement the described functions for each particular application, but such implementation should not be considered to be beyond the scope of the present disclosure.
  • FIG. 14 is a block diagram of another display panel according to an embodiment of the present disclosure.
  • the display panel 200 includes a gate driving circuit 230 and a display area 210.
  • the display panel can solve the problem of uneven brightness, improve the brightness uniformity of the display panel, improve the display quality, and does not affect the structure of the existing display panel, and is easy to implement.
  • display area 210 includes a plurality of pixel units 240.
  • the gate driving circuit 230 is configured to supply the pixel unit 240 with a gate signal having a target pulse width.
  • the pixel unit 240 is configured to receive the gate signal having the target pulse width and control the illumination by the gate signal having the target pulse width to bring the display region 210 to the corresponding target luminance.
  • the target pulse width is obtained based on the data write time determined for the display area 210 to adjust the pulse width of the gate signal input to the display area 210.
  • the display panel 200 is controlled by a display driving chip, and the display driving chip includes an adjustment module (eg, an adjustment circuit) that can adjust a pulse width of an input signal of the gate driving circuit 230, thereby causing a gate
  • the pole drive circuit 230 outputs a gate signal having a target pulse width.
  • the display panel 200 is electrically coupled to a dedicated adjustment device that adjusts the pulse width of the input signal of the gate drive circuit 230 such that the gate drive circuit 230 outputs a gate signal having a target pulse width. .
  • the specific manner of adjusting the pulse width of the gate signal is not limited, and may be determined according to actual needs.
  • At least one embodiment of the present disclosure further provides a driving method applied to a display panel provided by an embodiment of the present disclosure.
  • the driving method includes a data writing phase and a display phase.
  • the display panel includes at least one display area. Each display area includes a plurality of pixel units including a light emitting element, a driving circuit, and a storage capacitor.
  • FIG. 15 is a schematic flowchart of a driving method applied to a display panel according to any of the above-mentioned embodiments.
  • a driving method of a display panel provided by an embodiment of the present disclosure includes the following steps:
  • Step S500 in the data writing phase, writing a target data voltage signal to the storage capacitor under the control of the gate signal;
  • Step S550 In the display stage, the driving circuit drives the light emitting element to emit light according to the target data voltage signal, so that the display area reaches the corresponding target brightness.
  • the gate signal has a target pulse width.
  • the data voltage signal written to the storage capacitor is determined by the pulse width of the gate signal, that is, the target data voltage signal corresponds to the target pulse width.
  • the target pulse width is obtained based on the data write time determined for the display area of the display panel to adjust the pulse width of the gate signal input to the display area.
  • the driving method of the display panel may further include a reset phase, a compensation phase, a reset phase, and the like, which are not specifically limited in the embodiments of the present disclosure.

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Abstract

一种显示面板的亮度调节方法、显示面板及其驱动方法。显示面板（100）包括显示区域（200）。亮度调节方法包括：基于为显示区域确定的数据写入时间确定输入至显示区域的栅信号的目标脉冲宽度（S11）；调节栅信号的脉冲宽度至所述目标脉冲宽度，以使显示区域达到对应的目标亮度（S12）。

Description

显示面板的亮度调节方法、显示面板及其驱动方法
本申请要求于2017年12月15日递交的中国专利申请第201711353495.6号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种显示面板的亮度调节方法、显示面板及其驱动方法。
背景技术
电致发光元件作为一种电流型发光器件已越来越多地被应用于显示面板中。由于具备自发光特性，电致发光显示面板不需要背光源，且具有对比度高、厚度薄、视角广、反应速度快、可弯曲、构造及制程简单等优点，因此，电致发光显示面板逐渐成为下一代主流显示面板。有机发光二极管(OLED)显示面板通过OLED阵列实现显示功能，是应用较为广泛的一种电致发光显示面板。
发明内容
本公开至少一个实施例提供一种显示面板的亮度调节方法。所述显示面板包括显示区域，所述亮度调节方法包括：基于为所述显示区域确定的数据写入时间确定输入至所述显示区域的栅信号的目标脉冲宽度；调节所述栅信号的脉冲宽度至所述目标脉冲宽度，以使所述显示区域达到对应的目标亮度。
例如，在本公开一实施例提供的显示面板的亮度调节方法中，所述显示面板包括多个显示区域，每个显示区域对应有数据写入时间，所述亮度调节方法还包括：确定所述每个显示区域的数据写入时间，其中，确定所述每个显示区域的数据写入时间包括：获取与所述每个显示区域对应的初始亮度；根据所述初始亮度和与所述每个显示区域对应的目标亮度，确定所述每个显示区域对应的数据写入时间。
例如，在本公开一实施例提供的显示面板的亮度调节方法中，所述显示面板包括多个显示区域和用于向所述多个显示区域提供电源电压的电源线，每个 显示区域对应有数据写入时间，所述亮度调节方法还包括：确定所述每个显示区域的数据写入时间，其中，确定所述每个显示区域的数据写入时间包括：获取所述多个显示区域沿所述电源线的压降方向的排列顺序；根据所述排列顺序和所述多个显示区域的数量，确定所述每个显示区域对应的数据写入时间。
例如，在本公开一实施例提供的显示面板的亮度调节方法中，与所述多个显示区域对应的多个数据写入时间沿所述电源线的压降方向依次递减。
例如，在本公开一实施例提供的显示面板的亮度调节方法中，所述显示面板还包括栅极驱动电路，调节所述栅信号的脉冲宽度至所述目标脉冲宽度包括：基于所述数据写入时间调节所述栅极驱动电路的输入信号的脉冲宽度；根据调节后的所述栅极驱动电路的输入信号的脉冲宽度，调节所述栅信号的脉冲宽度至所述目标脉冲宽度。
例如，在本公开一实施例提供的显示面板的亮度调节方法中，所述栅极驱动电路的输入信号包括至少一个输入子信号。
例如，在本公开一实施例提供的显示面板的亮度调节方法中，所述显示面板包括多个像素单元，所述多个像素单元排列为多行多列，所述显示区域每个包括至少一行所述像素单元。
例如，在本公开一实施例提供的显示面板的亮度调节方法中，每个像素单元包括发光元件、驱动电路和存储电容，所述驱动电路被配置为控制流过所述发光元件的驱动电流，所述存储电容与所述驱动电路的控制端相连，以存储施加至所述控制端的数据电压信号，所述数据写入时间小于对所述存储电容充电以使其达到饱和状态的充电时间。
例如，在本公开一实施例提供的显示面板的亮度调节方法中，所述显示面板为有机发光二极管显示面板。
本公开至少一个实施例还提供一种显示面板，包括：显示区域、亮度调节电路和栅极驱动电路。所述亮度调节电路被配置为：基于为所述显示区域确定的数据写入时间调节所述栅极驱动电路的输入信号的脉冲宽度；所述栅极驱动电路被配置为：根据调节后的所述输入信号的脉冲宽度，输出栅信号至所述显示区域，以使所述显示区域达到对应的目标亮度。
例如，在本公开一实施例提供的显示面板中，所述显示面板包括多个显示区域，所述亮度调节电路包括存储器和处理器，每个显示区域对应有数据写入时间，所述存储器被配置为获取并存储与所述每个显示区域对应的初始亮度； 所述处理器被配置为根据所述初始亮度和与所述每个显示区域对应的目标亮度，确定所述每个显示区域对应的数据写入时间。
例如，在本公开一实施例提供的显示面板中，所述显示面板包括多个显示区域和用于向所述多个显示区域提供电源电压的电源线，所述亮度调节电路包括存储器和处理器，每个显示区域对应有数据写入时间，所述存储器被配置为获取并存储所述多个显示区域沿所述电源线的压降方向的排列顺序和所述多个显示区域的数量；所述处理器被配置为根据所述排列顺序和所述多个显示区域的数量，确定所述每个显示区域对应的数据写入时间。
例如，在本公开一实施例提供的显示面板中，与所述多个显示区域对应的多个数据写入时间沿所述电源线的压降方向依次递减。
例如，在本公开一实施例提供的显示面板中，所述栅极驱动电路的输入信号包括至少一个输入子信号。
例如，在本公开一实施例提供的显示面板中，所述亮度调节电路的输出端连接所述栅极驱动电路的输入端，所述亮度调节电路被配置为：基于为所述显示区域确定的数据写入时间调节所述至少一个输入子信号的脉冲宽度；并将调节后的所述至少一个输入子信号通过所述输出端输出至所述栅极驱动电路的输入端。
本公开至少一个实施例还提供一种显示面板，包括：显示区域和栅极驱动电路。所述显示区域包括多个像素单元，所述栅极驱动电路被配置为向所述像素单元提供具有目标脉冲宽度的栅信号；所述像素单元被配置为接收所述栅信号并由所述栅信号控制发光，以使所述显示区域达到对应的目标亮度。所述目标脉冲宽度是基于为所述显示区域确定的数据写入时间调节输入至所述显示区域的栅信号的脉冲宽度而获得的。
本公开至少一个实施例还提供一种应用于本公开一实施例提供的显示面板的驱动方法，包括：数据写入阶段和显示阶段。所述像素单元包括发光元件、驱动电路和存储电容。在所述数据写入阶段，在所述栅信号控制下向所述存储电容写入目标数据电压信号；在所述显示阶段，所述驱动电路根据所述目标数据电压信号驱动所述发光元件发光，以使所述显示区域达到对应的目标亮度。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简 单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开一实施例提供一种显示面板的亮度调节方法的流程图；
图2A为一种2T1C像素电路的结构示意图；
图2B为一种具有补偿功能的像素电路的结构示意图；
图3为一种具有补偿功能的像素电路的信号时序图；
图4为存储电容的电荷量与充电时间的关系曲线；
图5为本公开一实施例提供的一种OLED显示面板的发光亮度示意图；
图6为本公开一实施例提供的一种亮度调节方法中确定数据写入时间的流程图；
图7为本公开一实施例提供的另一种亮度调节方法中确定数据写入时间的流程图；
图8为本公开一实施例提供的调节前的栅信号波形和调节后的栅信号波形示意图；
图9为本公开一实施例提供的一种亮度调节方法中调节栅信号的流程图；
图10为一种栅极驱动电路的结构示意图；
图11为一种栅极驱动电路的信号时序图；
图12为一种栅极驱动电路的子电路的结构示意图；
图13为本公开一实施例提供的一种显示面板的框图；
图14为本公开一实施例提供的另一种显示面板的框图；以及
图15为本公开一实施例提供的一种显示面板的驱动方法的示意性流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的 组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
根据驱动方式的不同，有机发光二极管(OLED)显示面板分为主动式OLED(AMOLED)显示面板和被动式OLED(PMOLED)显示面板。AMOLED显示面板的像素电路可以包括选择晶体管、驱动晶体管和存储电容。通过扫描信号打开/关闭选择晶体管，从而将与显示数据相应的电压充电至存储电容，由此通过存储电容存储的数据电压来控制驱动晶体管的导通程度，从而控制流经OLED的电流大小，调节OLED的发光亮度。
AMOLED显示面板可以包括内部供电电路，用以提供恒定电压(例如，第一电源电压)。由于内部供电电路的电源线具有一定的电阻值，因此沿着电源线的延伸方向(即电源线的布线方向)会产生压降(IR drop)，即沿着电源线的压降方向，第一电源电压会发生变化，电源线不同位置的第一电源电压有所不同。第一电源电压的差异会导致显示面板的亮度差异，从而导致显示面板的亮度均一性较低。另一方面，由于显示面板制作工艺导致的器件性能差异，也会影响显示面板的亮度均一性，从而影响显示质量。
本公开至少一个实施例提供一种显示面板的亮度调节方法、显示面板及其驱动方法。该亮度调节方法可以解决由于内部供电电路的压降和器件性能差异等因素导致的亮度不均匀的问题，提高显示面板的亮度均一性，改善显示质量。
下面，将参考附图详细地说明本公开的实施例。应当注意的是，不同的附图中相同的附图标记将用于指代已描述的相同的元件。
本公开至少一实施例提供一种显示面板的亮度调节方法。图1为本公开一实施例提供一种显示面板的亮度调节方法的流程图，参考图1，该亮度调节方法包括：
S11：基于为显示区域确定的数据写入时间确定输入至显示区域的栅信号的目标脉冲宽度；
S12：调节栅信号的脉冲宽度至目标脉冲宽度，以使显示区域达到对应的 目标亮度。
例如，显示面板可以为有机发光二极管(OLED)显示面板，且包括显示区域。显示区域包括多个像素单元，每个像素单元包括像素电路和发光元件(例如，OLED)。像素电路可以包括驱动电路和存储电容。驱动电路被配置为控制流过发光元件的驱动电流，存储电容与驱动电路的控制端相连，以存储施加至驱动电路的控制端的数据电压信号。像素电路接收栅信号和数据电压信号，并在栅信号的有效脉冲宽度内将数据电压信号写入至存储电容。数据写入时间可以为将数据电压信号写入存储电容的时间，且数据写入时间由栅信号的脉冲宽度决定。
例如，在一些实施例中，基本的像素电路可以为2T1C像素电路，即利用两个TFT(薄膜晶体管)和一个存储电容Cs来实现驱动OLED发光的基本功能。图2A为一种2T1C像素电路的结构示意图。参考图2A，该像素电路包括第一晶体管T1、驱动晶体管N0(即驱动电路)以及存储电容Cs。例如，第一晶体管T1的栅极连接栅线以接收第一栅信号Sn，源极连接到数据线以接收数据电压信号Vdata，漏极连接到驱动晶体管N0的栅极；驱动晶体管N0的源极连接到第一电源端Vdd(例如，高压端)，漏极连接到OLED的阳极端；存储电容Cs的一端连接到第一晶体管T1的漏极以及驱动晶体管N0的栅极，另一端连接到驱动晶体管N0的源极以及第一电源端Vdd；OLED的阴极端连接到第二电源端Vss(例如，低压端)，第二电源端Vss例如为接地端。当通过栅线施加第一栅信号Sn以开启第一晶体管T1时，数据驱动电路通过数据线送入的数据电压Vdata将经由第一晶体管T1对存储电容Cs充电，由此将数据电压Vdata存储在存储电容Cs中，且此存储的数据电压Vdata控制驱动晶体管N0的导通程度，由此控制流过驱动晶体管N0以驱动OLED发光的电流大小，即此电流决定该OLED的发光亮度。
例如，第一晶体管T1可以为N型晶体管，驱动晶体管N0可以为P型晶体管。当然，第一晶体管T1也可以为P型晶体管，只要控制其导通或截止的第一栅信号Sn的极性进行相应地改变即可。同样地，驱动晶体管N0也可以为N型晶体管，本公开的实施例对此不作限制。
例如，像素电路还可以包括其他具有补偿功能的电路结构。补偿功能可以通过电压补偿、电流补偿或混合补偿来实现，具有补偿功能的像素电路例如可以为4T1C或4T2C等。例如，具有补偿功能的像素电路包括数据写入电路、 补偿电路、驱动电路和存储电路。驱动电路包括驱动晶体管，存储电路包括存储电容。在具有补偿功能的像素电路中，数据写入电路和补偿电路配合将数据电压信号以及驱动晶体管的阈值电压写入到驱动晶体管的控制极且通过存储电路存储。
图2B为一种具有补偿功能的像素电路的结构示意图。参考图2B，该像素电路包括驱动晶体管N0、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5和存储电容Cs。驱动晶体管N0用于给与其相连的OLED提供电流。该像素电路中，驱动晶体管N0、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4和第五晶体管T5都为P型晶体管。当然，驱动晶体管N0、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4和第五晶体管T5也可以为N型晶体管，本公开的实施例对此不作限制。第三晶体管T3的源极与驱动晶体管N0的栅极连接，第三晶体管T3的漏极与驱动晶体管N0的漏极连接，第三晶体管T3的栅极接收第一栅信号Sn。当第一栅信号Sn有效时，第一晶体管T1、驱动晶体管N0和第三晶体管T3导通，因此数据电压信号Vdata通过第一晶体管T1、驱动晶体管N0和第三晶体管T3对存储电容Cs进行充电。通过这种电路结构，驱动晶体管N0的阈值电压被记录，即携带有数据电压信号Vdata以及驱动晶体管N0的阈值电压的电压值被存储电容Cs存储。因此在驱动晶体管N0驱动OLED发光的过程中，其阈值电压得到补偿。流经OLED的电流可以表示为：I＝1/2K(Vdata-Vdd) 2，其中，K为预定的常数。当然，具有补偿功能的像素电路的结构不局限于此，可以为任意适用的结构。
图3为图2B所示的像素电路的信号时序图。参考图3，第一栅信号Sn为施加到当前扫描线上的扫描信号，第二栅信号Sn-1为施加到与当前扫描线相邻的前一扫描线上的扫描信号。En为发光控制信号。在t11周期内，第二晶体管T2导通，存储电容Cs放电，从而初始化存储电容Cs。在t12周期内，第一晶体管T1、驱动晶体管N0和第三晶体管T3导通，从而对存储电容Cs进行充电，以存储数据电压信号Vdata以及驱动晶体管N0的阈值电压Vth，即存储电容Cs存储的电压为Vdata+Vth。在t13周期内，第四晶体管T4、驱动晶体管N0和第五晶体管T5导通，从而驱动晶体管N0根据存储在存储电容Cs中的电压给OLED提供发光电流，OLED发出与发光电流相对应亮度的光。
根据对图2A和图2B所示的像素电路的分析可知，数据电压信号Vdata 写入的过程实质上是对存储电容Cs充电的过程。数据写入时间可以为数据电压信号Vdata经由第一晶体管T1对存储电容Cs进行充电的时间。对存储电容进行充电时，存储电容的电荷量的多少与充电时间有关。当然，存储电容的种类不受限制，根据制备工艺可以选择有机介质电容、无机介质电容、电解电容或空气介质电容，也可以是其他适用的电容。
图4为存储电容的电荷量与充电时间的关系曲线。参考图4，横坐标为充电时间t，纵坐标为电荷量Q，数据电压信号Vdata对应的电荷量为目标电荷量Q3。随着充电时间t的增大，电荷量Q会随之增大，电荷量Q也越接近目标电荷量Q3，电容存储电压(即电容两端的电压差)也越接近数据电压信号Vdata。电荷量Q与充电时间t正相关，例如，第一充电时间t1对应第一电荷量Q1，第二充电时间t2对应第二电荷量Q2，当t2>t1时，则Q2>Q1。电容存储电压与电荷量Q正相关，例如，第一电荷量Q1对应的电容存储电压为U1，第二电荷量Q2对应的电容存储电压为U2，当Q2>Q1时，则U2>U1。
在像素电路中，存储电容的充电时间会影响电荷量，从而影响存储电容两端的电压差，进而影响流经OLED的电流，最终影响OLED的发光亮度。存储电容的充电时间相当于数据写入时间，而数据写入时间由输入到像素电路的栅信号的脉冲宽度决定。栅信号的脉冲宽度越宽，则数据写入时间越长。因此，通过调节栅信号的脉冲宽度，即可调节存储电容的充电时间，从而调节电容存储电压，进而可以控制像素单元的OLED的发光亮度。
图5为本公开一实施例提供的一种OLED显示面板的发光亮度示意图；图6为本公开一实施例提供的一种亮度调节方法中确定数据写入时间的流程图。下面参考图5和图6详细描述本公开一实施例提供的一种确定数据写入时间的方法。
参考图5和图6，在一个示例中，显示面板包括多个显示区域和用于向多个显示区域提供电源电压的电源线，每个显示区域对应有数据写入时间，多个显示区域对应多个数据写入时间，且多个数据写入时间与多个显示区域一一对应，即一个显示区域仅对应一个数据写入时间。若显示面板包括W个显示区域，W个显示区域对应W个数据写入时间，且第一个显示区域对应第一个数据写入时间，第二个显示区域对应第二个数据写入时间，依次类推，第W个显示区域对应第W个数据写入时间。
例如，亮度调节方法还包括：确定每个显示区域的数据写入时间。参考图 6，确定每个显示区域的数据写入时间包括的操作可以包括：
步骤S201，获取多个显示区域沿电源线的压降方向的排列顺序；
步骤S202，根据排列顺序和多个显示区域的数量，确定每个显示区域对应的数据写入时间。
参考图2A，第一电源端Vdd通过设置在显示面板上的内部供电电路给每个像素单元供电。由于内部供电电路中的电源线具有一定的电阻值，因此沿着电源线的延伸方向(例如，电源线的布线方向，即电源线的压降方向)会产生压降，即每个显示区域接收到的第一电源端Vdd输出的第一电源电压彼此不同，例如，沿着电源线的压降方向依次减小。第一电源电压的差异会导致显示面板各显示区域的亮度差异，从而导致显示面板的亮度均一性较差。
参考图5，在一个示例中，沿第一方向，长方形的显示面板沿其长度方向可以被划分为七个显示区域(即第一显示区域1、第二显示区域2、第三显示区域3、第四显示区域4、第五显示区域5、第六显示区域6和第七显示区域7)。内部供电电路中的电源线沿着由第七显示区域7到第一显示区域1的方向(即第一方向)布线，也就是说，电源线的压降方向为沿着由第七显示区域7到第一显示区域1的方向，即第一方向。输入到各个显示区域的数据电压信号Vdata可以相同，例如，图5所示的圆圈中的数字表示该圆圈区域的实际发光亮度，由实际发光亮度可知，该显示面板的发光亮度从第七显示区域7到第一显示区域1依次降低，第七显示区域7的发光亮度最大，第一显示区域1的发光亮度最小。
例如，每个显示区域的形状可以为矩形。但不限于此，每个显示区域还可以为其他规则或不规则的形状。
例如，第一显示区域1到第七显示区域7接收到的第一电源电压可以分别为V11、V12、···V16和V17。由于沿着电源线的延伸方向存在压降，各显示区域接收到的第一电源电压沿着第一方向依次递减，即V17>V16>···>V12>V11。根据上述的流经OLED的电流公式可知，在输入每个显示区域的数据电压信号Vdata相同时，当第一电源电压的值改变，则所得到的电流不同。例如，对于特定的数据电压信号Vdata，第一电源电压越小，则流经OLED的电流也越小，从而从第七显示区域7到第一显示区域1，流经OLED的发光电流依次递减，即显示面板的亮度不均匀且亮度沿着电源线延伸的方向依次降低。如图5所示，各个显示区域的亮度从第七显示区域7到第一 显示区域1依次降低。
例如，各个显示区域的扫描顺序不受限制，可以按照从第七显示区域7到第一显示区域1的方向(即第一方向)进行扫描，也可以按照从第一显示区域1到第七显示区域7的方向(即第一方向的相反方向)进行扫描，本公开的实施例对此不作限制。
例如，在步骤S201中，首先获取多个显示区域沿电源线压降方向的排列顺序，即排列顺序为第七显示区域7、第六显示区域6……直至第一显示区域1。然后根据上述排列顺序和多个显示区域的数量(例如，7)，分别确定与各个显示区域对应的多个数据写入时间(例如，7份数据写入时间)。例如，首先，根据排列顺序和多个显示区域的数量，确定与第七显示区域7对应的数据写入时间；然后，根据排列顺序和多个显示区域的数量，确定与第六显示区域6对应的数据写入时间，依次类推，最后，根据排列顺序和多个显示区域的数量，确定与第一显示区域1对应的数据写入时间，由此，确定多个数据写入时间。例如第七显示区域7的数据写入时间最长，第一显示区域1的数据写入时间最短，从第七显示区域7至第一显示区域1，各个显示区域的数据写入时间依次递减，即各个显示区域的数据写入时间沿电源线的压降方向依次递减。
各个数据写入时间之间的定量关系不受限制，可以根据实际需求确定。例如，按照排列顺序，每个显示区域的数据写入时间可以比相邻前一个显示区域的数据写入时间小10％或20％或其他适用的比例(例如，第六显示区域6的数据写入时间比第七显示区域7的数据写入时间小10％，第五显示区域5的数据写入时间比第六显示区域6的数据写入时间小10％，以此类推)。
又例如，多个显示区域可以被划分为一组，由此，显示面板可以包括多个显示区域组。对多个显示区域组进行排序，按照排列顺序，每个显示区域组对应的数据写入时间可以比相邻前一个显示区域组对应的数据写入时间小5％或其他适用的比例。例如，将第七显示区域7和第六显示区域6划分为第一显示区域组，将第五显示区域5至第一显示区域1划分为第二显示区域组，使第二显示区域组的数据写入时间比第一显示区域组的数据写入时间小5％。通过分组的方式，可以在亮度均一性要求不高的情况下简化调节过程。
根据上述确定的多个数据写入时间确定输入至各个显示区域的栅信号的目标脉冲宽度，调节栅信号的脉冲宽度至目标脉冲宽度。例如，根据与第一显示区域1对应的数据写入时间确定输入至第一显示区域1的栅信号的目标脉冲 宽度；根据与第二显示区域2对应的数据写入时间确定输入至第二显示区域2的栅信号的目标脉冲宽度；以此类推。调节前的栅信号波形和调节后的栅信号波形示意图如图8所示。参考图8，图中所示的波形为输入到各个显示区域的波形的组合波形。GO为调节前的栅信号波形，每个显示区域的栅信号的脉冲宽度均相同，都为t0。当然，本公开的实施例不限于此，调节前栅信号的脉冲宽度可以相同，也可以不同。例如，在调节前可以根据经验值对栅信号的脉冲宽度进行预先处理，从而使调节前栅信号的脉冲宽度不相同。GO'为调节后的栅信号波形，即具有目标脉冲宽度的栅信号波形，每个显示区域的栅信号的目标脉冲宽度各不相同。例如，从第七显示区域7至第一显示区域1，栅信号的目标脉冲宽度依次递减，即t02<t01<t0。
像素电路根据栅信号的目标脉冲宽度对存储电容进行充电。因此，在数据电压信号Vdata相同时，从第七显示区域7至第一显示区域1，各个显示区域对应的电容存储电压依次递减。
不仅内部供电电路中的电源线会影响显示面板的亮度均一性，显示面板制造工艺导致的器件性能差异例如像素电路中的TFT或存储电容的性能差异等，或者显示面板工作时的受到的电磁干扰等也会影响亮度均一性。影响亮度均一性的因素可以为任意因素，本公开的实施例对此不作限制。
图7为本公开一实施例提供的另一种亮度调节方法中确定数据写入时间的流程图。下面参考图5和图7详细描述本公开一实施例提供的另一种确定数据写入时间的方法。
参考图5和图7，在另一个示例中，显示面板包括多个显示区域，每个显示区域对应有数据写入时间，多个显示区域对应多个数据写入时间，且多个数据写入时间与多个显示区域一一对应，即一个显示区域仅对应一个数据写入时间。关于多个数据写入时间的说明可以参考上面对图6所示的实施例中的相关描述，在此不再赘述。
例如，亮度调节方法还包括：确定每个显示区域的数据写入时间。参考图7，确定每个显示区域的数据写入时间的操作可以包括：
步骤S101，获取与每个显示区域对应的初始亮度；
步骤S102，根据初始亮度和与每个显示区域对应的目标亮度，确定每个显示区域对应的数据写入时间。
例如，多个显示区域与多个初始亮度一一对应，即一个显示区域仅对应一 个初始亮度。多个显示区域与多个目标亮度一一对应，即一个显示区域仅对应一个目标亮度。若显示面板包括W个显示区域，W个显示区域对应W个初始亮度，且第一个显示区域对应第一个初始亮度，第二个显示区域对应第二个初始亮度，依次类推，第W个显示区域对应第W个初始亮度；W个显示区域对应W个目标亮度，且第一个显示区域对应第一个目标亮度，第二个显示区域对应第二个目标亮度，依次类推，第W个显示区域对应第W个目标亮度。
在下面的描述中，显示面板包括第一显示区域和第二显示区域，且第一显示区域的亮度小于第二显示区域的亮度。但不限于此，第一显示区域的亮度也可以大于或等于第二显示区域的亮度。
例如，在一个示例中，步骤S101包括：对第一显示区域和第二显示区域输入相同的数据电压信号Vdata；检测第一显示区域和第二显示区域的实际发光亮度，以获得与第一显示区域1对应的第一初始亮度和与第二显示区域2对应的第二初始亮度。
例如，由于内部供电电路中的电源线的压降和/或显示面板制造工艺导致的器件特性差异等因素的影响。如图5所示，在输入每个显示区域的数据电压信号Vdata相同时，第一显示区域1的亮度小于第二显示区域2的亮度，也就是说，第一初始亮度小于第二初始亮度。
例如，步骤S102包括：根据数据电压信号Vdata可以得到与第一显示区域1对应的第一目标亮度和与第二显示区域2对应的第二目标亮度；根据第一初始亮度、第二初始亮度、第一目标亮度和第二目标亮度，确定与第一显示区域1对应的第一数据写入时间和与第二显示区域2对应的第二数据写入时间。
例如，对第一显示区域和第二显示区域输入相同的数据电压信号Vdata，第一目标亮度和第二目标亮度相同。
例如，第一数据写入时间小于第二数据写入时间。需要说明的是，第一数据写入时间和第二数据写入时间的定量关系不受限制，可以根据实际需求确定。
例如，根据第一数据写入时间和第二数据写入时间调节栅信号的脉冲宽度至目标脉冲宽度。栅信号的目标脉冲宽度与数据写入时间相对应，从而第一显示区域1对应的栅信号的目标脉冲宽度小于第二显示区域2对应的栅信号的目标脉冲宽度。像素电路根据栅信号的目标脉冲宽度对存储电容进行充电。因此，在数据电压信号Vdata相同时，第一显示区域1对应的电容存储电压小于第二 显示区域2对应的电容存储电压。
例如，参考图2B，当第一电源端Vdd输出的第一电源电压固定为4.6V，数据电压信号Vdata电压为4V，驱动晶体管N0的阈值电压Vth为2V时。由于IR DROP，假设图5中第二显示区域2处的第一电源电压V12为4.5V，第一显示区域1的第一电源电压V11为4.3V。第一显示区域1对应的电容存储电压为Vdata1-Vth，第二显示区域2对应的电容存储电压为Vdata2-Vth，在没有经过本公开实施例提供的亮度调节方法进行处理时，Vdata1-Vth和Vdata2-Vth相等。例如，在一个示例中，Vdata1-Vth和Vdata2-Vth均为2V，此时，Vgs1＝Vdata1-Vth-V11＝-2.3V，而Vgs2＝-2.5V。由此，第二显示区域2的亮度大于第一显示区域1的亮度。但经过本公开实施例提供的亮度调节方法进行处理后，此时，第一显示区域1对应的电容存储电压为Vdata1'-Vth，第二显示区域2对应的电容存储电压为Vdata2'-Vth，由于第一数据写入时间小于第二数据写入时间，因此Vdata1'-Vth小于Vdata2'-Vth，从而Vgs1和Vgs2差距会减小或者变得相等。例如，在一个示例中，Vdata1'-Vth为1.8V，Vdata2'-Vth为2V，从而Vgs1＝Vdata1'-Vth-V11＝-2.5V，Vgs2＝Vdata2'-Vth-V12＝-2.5V，即Vgs1＝Vgs2，从而第一显示区域1和第二显示区域2的亮度相同。以此类推，显示面板上的其余各显示区域的数据写入时间也可以相应调整，以使各显示区域的亮度相同。从而，本公开实施例的亮度调节方法可以通过逐步调整不同区域的数据写入时间，提高显示面板的亮度均一性。
在不考虑内部供电电路中的电源线的压降和/或显示面板制造工艺导致的器件特性差异等因素的影响时，由于第一显示区域1对应的电容存储电压小于第二显示区域2对应的电容存储电压，因此第一显示区域1的亮度应当大于第二显示区域2的亮度。在实际显示时，内部供电电路中的电源线的压降和/或显示面板制造工艺导致的器件特性差异等因素对显示亮度的影响与电容存储电压对显示亮度的影响例如可以互相抵消，从而使第一显示区域1和第二显示区域2的亮度相同或相近，达到提高亮度均一性的目的。
例如，第一显示区域1和第二显示区域2的形状和大小可以相同。第一显示区域1和第二显示区域2例如均为矩形、梯形等形状。第一显示区域1可以包括N行像素单元，且第二显示区域2也包括N行像素单元。N为大于0的正整数。本公开的实施例不限于此，第一显示区域1和第二显示区域2的形状和/或大小也可以不相同，例如，第一显示区域1可以包括N行像素单元，第 二显示区域2可以包括M行像素单元，N与M不相同，且N与M均为大于0的正整数。本公开的实施例对此不作限制。
例如，各显示区域的数据写入时间(例如，第一数据写入时间、第二数据写入时间)需要小于对像素电路中的存储电容充电以使其达到饱和状态的充电时间。
需要说明的是，图5所示的显示区域仅是示意性的，根据实际设计需求，显示面板上的显示区域可以被划分为各种需要的形状和数量，本公开实施例对此不作限制。
图9为本公开一实施例提供的一种亮度调节方法中调节栅信号的流程图。参考图9，在一个示例中，亮度调节方法中调节栅信号的脉冲宽度至目标脉冲宽度可以包括：
步骤S301，基于数据写入时间调节栅极驱动电路的输入信号的脉冲宽度；
步骤S302，根据调节后的栅极驱动电路的输入信号的脉冲宽度，调节栅信号的脉冲宽度至目标脉冲宽度。
例如，输入到像素电路中的栅信号可以由栅极驱动电路提供，栅极驱动电路将栅信号输出给像素电路以控制像素单元进行显示。栅极驱动电路的输入信号可以由栅极驱动器提供。例如，栅极驱动电路的输入信号包括至少一个输入子信号。在步骤S301中，可以调节任意一个输入子信号，也可以同时调节多个输入子信号，本公开的实施例对此不作限制。
图10为一种栅极驱动电路的结构示意图。栅极驱动电路包括多个级联的子电路。参考图10，栅极驱动电路例如包括第一子电路SR1、第二子电路SR2、第三子电路SR3和第四子电路SR4。当然，子电路的个数不局限于4个，可以为任意个数。子电路的个数可以根据像素单元的行数确定。
输入信号包括时钟信号、开启信号GSTV、高电平信号VGH(图中未示出)和低电平信号VGL(图中未示出)等多个输入子信号。时钟信号根据需要可以包括第一时钟信号CK和第二时钟信号CB，用以为子电路提供时钟。根据电路结构，时钟信号不局限于两个，可以为一个或多个。高电平信号VGH和低电平信号VGL用于为栅极驱动电路提供恒压信号。根据实际设计需求，每个子电路可以接收一个高电平信号VGH和一个低电平信号VGL，也可以接收多个高电平信号VGH和多个低电平信号VGL，还可以不接收高电平信号VGH和/或低电平信号VGL，本公开的实施例对此不作限制。开启信号GSTV输入 到第一子电路SR1。开启信号GSTV例如可以为一个或多个。
例如，如图10所示，亮度调节电路的输出端连接栅极驱动电路的输入端。多个输入子信号(例如，开启信号GSTV、第一时钟信号CK和第二时钟信号CB)可以被传输至亮度调节电路，亮度调节电路可以用于基于为显示区域确定的数据写入时间调节多个输入子信号中每个的脉冲宽度；并将调节后的多个输入子信号通过输出端输出至栅极驱动电路的输入端。例如，开启信号GSTV、第一时钟信号CK和第二时钟信号CB经由亮度调节电路调节后得到开启信号GSTV'、第一时钟信号CK'和第二时钟信号CB'。开启信号GSTV'、第一时钟信号CK'和第二时钟信号CB'可以被输入至栅极驱动电路以控制栅极驱动电路输出栅信号(例如，栅信号可以包括图10所示的第一栅信号GO1'、第二栅信号GO2'、第三栅信号GO3'、第四栅信号GO4')。
需要说明的是，多个输入子信号可以包括第一部分输入子信号和第二部分输入子信号，第一部分输入子信号也可以直接被传输至栅极驱动电路，即亮度调节电路可以仅调节多个输入子信号中的第二部分输入子信号。
例如，第一栅信号GO1'、第二栅信号GO2'、第三栅信号GO3'、第四栅信号GO4'分别是第一子电路SR1、第二子电路SR2、第三子电路SR3、第四子电路SR4输出给相应的像素单元的行扫描信号。并且，除了第一子电路SR1和第四子电路SR4外，每一个子电路输出的栅信号还分别作为相邻上一个子电路的复位信号和相邻下一个子电路的输入信号。例如，第二栅信号GO2'可以作为第一子电路SR1的复位信号和第三子电路SR3的输入信号，第三栅信号GO3'可以作为第二子电路SR2的复位信号和第四子电路SR4的输入信号。
图11为图10所示的栅极驱动电路的信号时序图。参考图10和图11，栅极驱动电路可以接收开启信号GSTV'、第一时钟信号CK'和第二时钟信号CB'，并输出多个栅信号(例如，第一栅信号GO1'、第二栅信号GO2'、第三栅信号GO3'、第四栅信号GO4')。第一子电路SR1接收到开启信号GSTV'后，在对应的第一时钟信号CK'为低电平时，输出第一栅信号GO1'，第一栅信号GO1'例如为低电平方波。第一栅信号GO1'输出到对应的像素单元以使其进行数据写入操作。第一栅信号GO1'还作为输入信号被传输至第二子电路SR2。
从第二子电路SR2开始，后续子电路接收到前一个子电路提供的输入信号后，在各自对应的时钟信号为低电平时，输出相应的栅信号。该栅信号输出到对应的像素单元以使其进行数据写入操作。另外，栅信号也作为输入信号被传 输至相邻下一个子电路，还作为复位信号被传输至相邻上一个子电路。如此直至第四子电路SR4输出结束为止。
例如，参考图11，开启信号GSTV、第一时钟信号CK和第二时钟信号CB为通过亮度调节电路调节前的输入子信号，开启信号GSTV'、第一时钟信号CK'和第二时钟信号CB'为通过亮度调节电路调节后的输入子信号。第一栅信号GO1、第二栅信号GO2、第三栅信号GO3、第四栅信号GO4为根据开启信号GSTV、第一时钟信号CK和第二时钟信号CB得到的栅信号，如图11所示，第一栅信号GO1的脉冲宽度、第二栅信号GO2的脉冲宽度、第三栅信号GO3的脉冲宽度、第四栅信号GO4的脉冲宽度均相同，第一栅信号GO1'、第二栅信号GO2'、第三栅信号GO3'、第四栅信号GO4'为根据开启信号GSTV'、第一时钟信号CK'和第二时钟信号CB'得到的栅信号。第一栅信号GO1'、第二栅信号GO2'、第三栅信号GO3'、第四栅信号GO4'中至少部分栅信号的脉冲宽度不相同。如图11所示，第一栅信号GO1'的脉冲宽度、第二栅信号GO2'的脉冲宽度、第三栅信号GO3'的脉冲宽度、第四栅信号GO4'的脉冲宽度各不相同，且第一栅信号GO1'的脉冲宽度大于第二栅信号GO2'的脉冲宽度，第二栅信号GO2'的脉冲宽度大于第三栅信号GO3'的脉冲宽度，第三栅信号GO3'的脉冲宽度大于第四栅信号GO4'的脉冲宽度。
例如，栅极驱动电路中的每个子电路会在其开始输出时，关闭上一个子电路的输出，即使上一个子电路不输出栅信号。也就是说，第二子电路SR2进行输出时，第一子电路SR1关闭其输出；第三子电路SR3进行输出时，则第二子电路SR2关闭其输出。由此，各个子电路即可实现移位寄存器的功能，栅极驱动电路可以实现多个栅信号的顺序输出。当然，栅极驱动电路的输入信号和输出的栅信号的个数不局限于上文中描述的个数，可以为任意个数，可以根据实际需求确定。
例如，栅极驱动电路的输入子信号可以为开启信号GSTV、第一时钟信号CK和第二时钟信号CB等。开启信号GSTV、第一时钟信号CK或第二时钟信号CB的脉冲宽度都会影响栅信号的脉冲宽度。因此，调节开启信号GSTV、第一时钟信号CK或第二时钟信号CB的脉冲宽度，都可以达到调节栅信号的脉冲宽度的目的。例如，图9所示的步骤S301中描述的输入信号可以包括开启信号GSTV、第一时钟信号CK和第二时钟信号CB之中的一个或多个。需要说明的是，输入信号也可以为栅极驱动电路的其他输入信号，本公开的实施 例对此不作限制。
例如，栅极驱动电路的输入子信号的脉冲宽度与栅极驱动电路输出的栅信号的脉冲宽度正相关，即栅极驱动电路的输入子信号的脉冲宽度越宽，则栅信号的脉冲宽度越宽。例如，在一个示例中，若需要使栅信号的目标脉冲宽度大于调节前的脉冲宽度，则可以增大至少一个输入子信号的脉冲宽度，栅极驱动电路接收该至少一个输入子信号，并输出具有目标脉冲宽度的栅信号，即调节后的栅信号的目标脉冲宽度大于调节前的栅信号的脉冲宽度。又例如，在另一个示例中，若需要使栅信号的目标脉冲宽度小于调节前的脉冲宽度，则可以减小至少一个输入子信号的脉冲宽度，栅极驱动电路接收该至少一个输入子信号，并输出具有目标脉冲宽度的栅信号，即调节后的栅信号的目标脉冲宽度小于调节前的栅信号的脉冲宽度。
下面以第一子电路SR1为例详细描述栅极驱动电路中的每个子电路的工作原理。图12为图10所示的栅极驱动电路中的第一子电路SR1的电路结构示意图。需要说明的是，第一子电路SR1根据调节后的输入子信号生成并输出第一栅信号GO1'。参考图12，第一子电路SR1包括第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9和旁路电容C1。例如，第六晶体管T6的第一极连接第二时钟信号CB'，第二极连接第七晶体管T7的第一极并输出第一栅信号GO1'。第六晶体管T6的栅极连接第八晶体管T8的第一极以及第九晶体管T9的第二极。第七晶体管T7的第二极连接第八晶体管T8的第二极以及高电平信号VGH。第七晶体管T7的栅极连接第八晶体管T8的栅极，第七晶体管T7的栅极和第八晶体管T8的栅极均接收第二栅信号GO2'。第九晶体管T9的第一极和其栅极相连，并接收开启信号GSTV'。旁路电容C1的一端连接第六晶体管T6的栅极，另一端连接第六晶体管T6的第二极。
该电路工作时，当开启信号GSTV'为低电平，则第九晶体管T9和第六晶体管T6导通，因此第一栅信号GO1'为第二时钟信号CB'，即当第二时钟信号CB'为低电平时，则第一栅信号GO1'也输出低电平。从而，第二时钟信号CB'的脉冲宽度可以为第一栅信号GO1'的脉冲宽度。当第二栅信号GO2'为低电平时，第七晶体管T7和第八晶体管T8导通，因此高电平信号VGH被写入第六晶体管T6的栅极和第一极，从而实现对第六晶体管T6进行复位。
由于上述各个晶体管的源极、漏极是对称的，所以其源极、漏极可以互换。第一极可以为源极或者漏极，第二极可以为漏极或者源极。例如，上述各个晶 体管为P型晶体管。当然，上述各个晶体管不限于P型晶体管，也可以为N型晶体管，只要改变晶体管的栅极的控制电压信号的极性即可。
需要说明的是，第一子电路SR1的结构不局限于上面描述的结构，第一子电路SR1可以为任意结构，也可以包括更多或更少的晶体管和/或电容，例如第一子电路SR1还可以包括用于实现上拉节点控制、下拉节点控制、降噪等功能的子电路等。同样地，栅极驱动电路中的其余子电路(例如，第二子电路SR2、第三子电路SR3和第四子电路SR4)可以为上面描述的结构，也可以为任意适用的结构，本公开的实施例对此不作限制。
本公开至少一个实施例还提供一种显示面板。图13为本公开一实施例提供的一种显示面板的框图。参考图13，该显示面板100包括显示区域110、亮度调节电路120和栅极驱动电路130。该显示面板可以解决由于内部供电电路的压降和器件性能差异等因素导致的亮度不均匀的问题，提高显示面板的亮度均一性，改善显示质量。
例如，亮度调节电路120和栅极驱动电路130电连接，且被配置为基于为显示区域110确定的数据写入时间调节栅极驱动电路130的输入信号的脉冲宽度。例如，亮度调节电路120的输出端和栅极驱动电路130的输入端电连接，且亮度调节电路120可以通过其输出端将调节后的栅极驱动电路130的输入信号输出至栅极驱动电路130的输入端。
例如，亮度调节电路120可以包括存储器和处理器，处理器被配置为基于为显示区域确定的数据写入时间调节栅极驱动电路的输入信号的脉冲宽度。例如，存储器还可以存储第一计算机程序指令，处理器被配置运行该第一计算机程序指令以执行基于为显示区域确定的数据写入时间调节栅极驱动电路的输入信号的脉冲宽度的操作。
例如，在一些示例中，当显示面板包括多个显示区域和用于向多个显示区域提供电源电压的电源线，每个显示区域对应有数据写入时间，存储器被配置为获取并存储多个显示区域沿电源线的压降方向的排列顺序和多个显示区域的数量；处理器被配置为根据排列顺序和多个显示区域的数量，确定每个显示区域对应的数据写入时间。例如，存储器还可以存储第二计算机程序指令，处理器被配置运行该第二计算机程序指令以执行根据排列顺序和多个显示区域的数量，确定每个显示区域对应的数据写入时间的操作。
例如，与多个显示区域对应的多个数据写入时间沿电源线的压降方向依次 递减。
又例如，在另一些示例中，当显示面板包括多个显示区域时，每个显示区域对应有数据写入时间。存储器被配置为获取并存储与每个显示区域对应的初始亮度；处理器被配置为根据初始亮度和与每个显示区域对应的目标亮度，确定每个显示区域对应的数据写入时间。例如，存储器还可以存储第三计算机程序指令，处理器被配置运行该第三计算机程序指令以执行根据初始亮度和与每个显示区域对应的目标亮度，确定每个显示区域对应的数据写入时间的操作。
需要说明的是，确定数据写入时间的方法的具体操作过程可以参考图6或图7所示的方法的相关说明，确定数据写入时间也可以根据其他适用的方法确定，本公开的实施例对此不作限制。
例如，栅极驱动电路130的输入信号可以包括开启信号GSTV、第一时钟信号CK和第二时钟信号CB之中的一个或多个，也可以为其他适用的信号，本公开的实施例对此不作限制。例如，亮度调节电路被配置为：基于为显示区域确定的数据写入时间调节至少一个输入子信号的脉冲宽度；并将调节后的至少一个输入子信号通过输出端输出至栅极驱动电路的输入端。亮度调节电路还可以包括输出子电路，输出子电路包括输出端，当处理器执行基于为显示区域确定的数据写入时间调节至少一个输入子信号的脉冲宽度的操作后，输出子电路可以接收并将调节后的至少一个输入子信号输出至栅极驱动电路的输入端。
例如，栅极驱动电路130被配置为根据调节后的输入信号的脉冲宽度，调节栅信号的脉冲宽度，以获得具有目标脉冲宽度的栅信号。该具有目标脉冲宽度的栅信号被输出至显示区域110，以使显示区域110达到对应的目标亮度。
例如，显示区域110包括多个像素单元，多个像素单元排列为多行多列。每个显示区域110的多个像素单元接收栅极驱动电路130输出的具有目标脉冲宽度的栅信号，并发出相应亮度的光，从而使每个显示区域110达到对应的目标亮度。
本公开的实施例中，显示面板可以包括更多或更少的电路，并且各个电路之间的连接关系不受限制，可以根据实际需求而定。各个电路的具体构成方式不受限制，可以根据电路原理由模拟器件构成，也可以由数字芯片构成，或者以其他适用的方式构成。
此外，本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例中的各电路，能够以电子硬件、或者计算机软件和电子硬件的结合来 实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本公开的范围。
本公开至少一个实施例还提供一种显示面板。图14为本公开一实施例提供的另一种显示面板的框图。参考图14，该显示面板200包括栅极驱动电路230和显示区域210。该显示面板可以解决亮度不均匀的问题，提高显示面板的亮度均一性，改善显示质量，并且不影响现有显示面板的结构，易于实现。
例如，显示区域210包括多个像素单元240。栅极驱动电路230被配置为向像素单元240提供具有目标脉冲宽度的栅信号。像素单元240被配置为接收该具有目标脉冲宽度的栅信号并由该具有目标脉冲宽度的栅信号控制发光，以使显示区域210达到对应的目标亮度。目标脉冲宽度是基于为显示区域210确定的数据写入时间调节输入至显示区域210的栅信号的脉冲宽度而获得的。
例如，在一个示例中，显示面板200由显示驱动芯片控制，显示驱动芯片中包括调节模块(例如，调节电路)，该调节模块可调节栅极驱动电路230的输入信号的脉冲宽度，从而使栅极驱动电路230输出具有目标脉冲宽度的栅信号。例如，在另一个示例中，显示面板200与专用调节装置电连接，专用调节装置可调节栅极驱动电路230的输入信号的脉冲宽度，从而使栅极驱动电路230输出具有目标脉冲宽度的栅信号。
需要说明的是，本公开的各实施例中，调节栅信号的脉冲宽度的具体方式不受限制，可以根据实际需求确定。
本公开至少一个实施例还提供一种应用于本公开一实施例提供的显示面板的驱动方法。该驱动方法包括数据写入阶段和显示阶段。该显示面板包括至少一个显示区域。每个显示区域包括多个像素单元，像素单元包括发光元件、驱动电路和存储电容。
图15为本公开一实施例提供的一种应用于上述任一项所述的显示面板的驱动方法的示意性流程图。参考图15，本公开实施例提供的显示面板的驱动方法包括以下步骤：
步骤S500：在数据写入阶段，在栅信号控制下向存储电容写入目标数据电压信号；
步骤S550：在显示阶段，驱动电路根据目标数据电压信号驱动发光元件发光，以使显示区域达到对应的目标亮度。
例如，在步骤S500中，栅信号具有目标脉冲宽度。
向存储电容写入的数据电压信号由栅信号的脉冲宽度决定，即目标数据电压信号与目标脉冲宽度相对应。目标脉冲宽度是基于为显示面板的显示区域确定的数据写入时间调节输入至显示区域的栅信号的脉冲宽度而获得的。需要说明的是，关于栅信号的具体说明可以参考上述关于显示面板的亮度调节方法的实施例中的相关描述，在此不再赘述。
需要说明的是，根据实际电路设计，显示面板的驱动方法还可以包括复位阶段、补偿阶段和重置阶段等，本公开的实施例对此不作具体限定。
有以下几点需要说明：
(1)本公开实施例附图只涉及到本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种显示面板的亮度调节方法，其中，所述显示面板包括显示区域，
    所述亮度调节方法包括：
    基于为所述显示区域确定的数据写入时间确定输入至所述显示区域的栅信号的目标脉冲宽度；
    调节所述栅信号的脉冲宽度至所述目标脉冲宽度，以使所述显示区域达到对应的目标亮度。
  2. 根据权利要求1所述的显示面板的亮度调节方法，其中，所述显示面板包括多个显示区域，每个显示区域对应有数据写入时间，
    所述亮度调节方法还包括：确定所述每个显示区域的数据写入时间，
    其中，确定所述每个显示区域的数据写入时间包括：
    获取与所述每个显示区域对应的初始亮度；
    根据所述初始亮度和与所述每个显示区域对应的目标亮度，确定所述每个显示区域对应的数据写入时间。
  3. 根据权利要求1所述的显示面板的亮度调节方法，其中，所述显示面板包括多个显示区域和用于向所述多个显示区域提供电源电压的电源线，每个显示区域对应有数据写入时间，
    所述亮度调节方法还包括：确定所述每个显示区域的数据写入时间，
    其中，确定所述每个显示区域的数据写入时间包括：
    获取所述多个显示区域沿所述电源线的压降方向的排列顺序；
    根据所述排列顺序和所述多个显示区域的数量，确定所述每个显示区域对应的数据写入时间。
  4. 根据权利要求3所述的显示面板的亮度调节方法，其中，与所述多个显示区域对应的多个数据写入时间沿所述电源线的压降方向依次递减。
  5. 根据权利要求1-4任一项所述的显示面板的亮度调节方法，其中，所述显示面板还包括栅极驱动电路，
    调节所述栅信号的脉冲宽度至所述目标脉冲宽度包括：
    基于所述数据写入时间调节所述栅极驱动电路的输入信号的脉冲宽度；
    根据调节后的所述栅极驱动电路的输入信号的脉冲宽度，调节所述栅信号的脉冲宽度至所述目标脉冲宽度。
  6. 根据权利要求5所述的显示面板的亮度调节方法，其中，所述栅极驱动电路的输入信号包括至少一个输入子信号。
  7. 根据权利要求1-6任一项所述的显示面板的亮度调节方法，其中，所述显示面板包括多个像素单元，所述多个像素单元排列为多行多列，所述显示区域每个包括至少一行所述像素单元。
  8. 根据权利要求7所述的显示面板的亮度调节方法，其中，每个像素单元包括发光元件、驱动电路和存储电容，
    所述驱动电路被配置为控制流过所述发光元件的驱动电流，所述存储电容与所述驱动电路的控制端相连，以存储施加至所述控制端的数据电压信号，
    所述数据写入时间小于对所述存储电容充电以使其达到饱和状态的充电时间。
  9. 根据权利要求1-8任一项所述的显示面板的亮度调节方法，其中，所述显示面板为有机发光二极管显示面板。
  10. 一种显示面板，包括：显示区域、亮度调节电路和栅极驱动电路，
    其中，所述亮度调节电路被配置为：基于为所述显示区域确定的数据写入时间调节所述栅极驱动电路的输入信号的脉冲宽度；
    所述栅极驱动电路被配置为：根据调节后的所述输入信号的脉冲宽度，输出栅信号至所述显示区域，以使所述显示区域达到对应的目标亮度。
  11. 根据权利要求10所述的显示面板，其中，所述显示面板包括多个显示区域，所述亮度调节电路包括存储器和处理器，每个显示区域对应有数据写入时间，
    所述存储器被配置为获取并存储与所述每个显示区域对应的初始亮度；
    所述处理器被配置为根据所述初始亮度和与所述每个显示区域对应的目标亮度，确定所述每个显示区域对应的数据写入时间。
  12. 根据权利要求10所述的显示面板，其中，所述显示面板包括多个显示区域和用于向所述多个显示区域提供电源电压的电源线，所述亮度调节电路包括存储器和处理器，每个显示区域对应有数据写入时间，
    所述存储器被配置为获取并存储所述多个显示区域沿所述电源线的压降方向的排列顺序和所述多个显示区域的数量；
    所述处理器被配置为根据所述排列顺序和所述多个显示区域的数量，确定所述每个显示区域对应的数据写入时间。
  13. 根据权利要求12所述的显示面板，其中，与所述多个显示区域对应的多个数据写入时间沿所述电源线的压降方向依次递减。
  14. 根据权利要求10-13任一项所述的显示面板，其中，所述栅极驱动电路的输入信号包括至少一个输入子信号。
  15. 根据权利要求14所述的显示面板，其中，所述亮度调节电路的输出端连接所述栅极驱动电路的输入端，
    所述亮度调节电路被配置为：基于为所述显示区域确定的数据写入时间调节所述至少一个输入子信号的脉冲宽度；并将调节后的所述至少一个输入子信号通过所述输出端输出至所述栅极驱动电路的输入端。
  16. 一种显示面板，包括：显示区域和栅极驱动电路，
    其中，所述显示区域包括多个像素单元，
    所述栅极驱动电路被配置为向所述像素单元提供具有目标脉冲宽度的栅信号；
    所述像素单元被配置为接收所述栅信号并由所述栅信号控制发光，以使所述显示区域达到对应的目标亮度；
    其中，所述目标脉冲宽度是基于为所述显示区域确定的数据写入时间调节输入至所述显示区域的栅信号的脉冲宽度而获得的。
  17. 一种应用于权利要求16所述的显示面板的驱动方法，包括：数据写入阶段和显示阶段，
    其中，所述像素单元包括发光元件、驱动电路和存储电容，
    在所述数据写入阶段，在所述栅信号控制下向所述存储电容写入目标数据电压信号；
    在所述显示阶段，所述驱动电路根据所述目标数据电压信号驱动所述发光元件发光，以使所述显示区域达到对应的目标亮度。
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