WO2019207404A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2019207404A1
WO2019207404A1 PCT/IB2019/053066 IB2019053066W WO2019207404A1 WO 2019207404 A1 WO2019207404 A1 WO 2019207404A1 IB 2019053066 W IB2019053066 W IB 2019053066W WO 2019207404 A1 WO2019207404 A1 WO 2019207404A1
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Prior art keywords
wiring
potential
circuit
terminal
memory cell
Prior art date
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Ceased
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PCT/IB2019/053066
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English (en)
French (fr)
Japanese (ja)
Inventor
池田隆之
山本朗央
勝井秀一
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to US17/050,359 priority Critical patent/US12118333B2/en
Priority to JP2020515309A priority patent/JP7337782B2/ja
Publication of WO2019207404A1 publication Critical patent/WO2019207404A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/048—Activation functions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0499—Feedforward networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G06N3/09—Supervised learning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D87/00—Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate

Definitions

  • One embodiment of the present invention relates to a semiconductor device.
  • one embodiment of the present invention relates to a method for operating a semiconductor device.
  • one embodiment of the present invention is not limited to the above technical field.
  • the technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method.
  • one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, the technical field of one embodiment of the present invention disclosed in this specification more specifically includes a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, an imaging device, a memory device, a processor, an electronic device, A system, a driving method thereof, a manufacturing method thereof, or an inspection method thereof can be given as an example.
  • the artificial neural network is an information processing system that uses a neural network as a model. It is expected that a computer with higher performance than a conventional Neumann computer can be realized by using an artificial neural network. In recent years, various studies for constructing an artificial neural network on an electronic circuit have been advanced.
  • Patent Document 1 discloses an invention in which weight data necessary for calculation of an artificial neural network is held by a memory device using a transistor having an oxide semiconductor in a channel formation region.
  • oxide semiconductor for example, not only single-component metal oxides such as indium oxide and zinc oxide but also multi-component metal oxides are known.
  • IGZO In—Ga—Zn oxide
  • Non-Patent Document 1 and Non-Patent Document 2 also disclose a technique for manufacturing a transistor using an oxide semiconductor having a CAAC structure. Furthermore, it is shown in Non-Patent Document 4 and Non-Patent Document 5 that even an oxide semiconductor having lower crystallinity than the CAAC structure and the nc structure has a minute crystal.
  • Patent Document 2 discloses an invention in which a transistor including IGZO in an active layer is used for a pixel circuit of a display device.
  • connection strength between a plurality of first neurons in the first layer and one of the second neurons in the second layer is stored, and a plurality of layers in the first layer are stored. It is necessary to realize a product-sum operation circuit that multiplies the outputs of the first neurons and their corresponding coupling strengths and adds them. That is, it is necessary to mount a memory for holding the coupling strength, a multiplication circuit and an addition circuit for executing a product-sum operation, and the like on the semiconductor device.
  • the memory needs to have a specification capable of storing multi-bit information.
  • the multiplier circuit and the adder circuit Therefore, it is necessary to have a specification that can handle multi-bit operations. That is, in order to construct a hierarchical artificial neural network with a digital circuit, a large-scale memory, a large-scale multiplier circuit, and a large-scale adder circuit are required, which increases the chip area of the digital circuit.
  • the analog circuit does not need to be configured as a large-scale arithmetic circuit as the digital circuit.
  • the chip area can be made smaller.
  • an operation result is output in a hierarchical artificial neural network having an existing connection strength (sometimes referred to as a weight coefficient, weight data, etc.), and a new connection strength is based on the operation result.
  • the existing bond strength stored in the memory is updated to the new bond strength.
  • the calculation result is output again in the hierarchical artificial neural network having the new connection strength, the connection strength based on the calculation result is calculated, and the connection strength of the memory is updated. That is, each time an operation is performed, it is necessary to rewrite the coupling strength of the memory. Therefore, it may take a long time to perform learning on the hierarchical artificial neural network.
  • problems of one embodiment of the present invention are not limited to the problems listed above.
  • the problems listed above do not disturb the existence of other problems.
  • Other issues are issues not mentioned in this section, which are described in the following description. Problems not mentioned in this item can be derived from descriptions of the specification or drawings by those skilled in the art, and can be appropriately extracted from these descriptions.
  • one embodiment of the present invention solves at least one of the above-described problems and other problems. Note that one embodiment of the present invention does not have to solve all of the problems listed above and other problems.
  • One embodiment of the present invention includes first to third circuits, first to third memory cells, and first to fifth wirings, and the first circuit includes the first wiring through the first wiring.
  • the memory cell and the second circuit are electrically connected.
  • the first circuit is electrically connected to the second memory cell via a fourth wiring.
  • the first circuit is electrically connected to the second circuit.
  • the second circuit is electrically connected to the third circuit, and the third circuit is connected to the first memory cell, the second memory cell, and the second memory cell via the second wiring.
  • the third circuit is electrically connected to the first memory cell and the third memory cell through the third wiring, and the third circuit has an input terminal,
  • Each of the first to third memory cells has a holding node, and the first memory cell has a holding node of the first memory cell in accordance with a change in the potential of the second wiring.
  • a function of changing the potential of the first memory cell a function of changing the potential of the holding node of the first memory cell in accordance with the change of the potential of the third wiring, and a current corresponding to the potential of the holding node of the first memory cell.
  • a function of flowing between one memory cell and the first wiring, and the second memory cell has a function of changing the potential of the holding node of the second memory cell in accordance with the change of the potential of the second wiring.
  • the second memory cell has a function of causing a current corresponding to the potential of the holding node of the second memory cell to flow between the second memory cell and the fourth wiring.
  • the third memory cell responds to a change in the potential of the third wiring.
  • One circuit responds to the current flowing through the fourth wiring and the current flowing through the fifth wiring.
  • the second circuit generates a first potential corresponding to the first current flowing between the first wiring and the second circuit, and generates a first potential corresponding to the third circuit.
  • the second potential is input to the input terminal of the third circuit, and the third circuit has the first potential, the second potential, the potential of the second wiring, Is a semiconductor device having a function of changing the potential of the third wiring by being input to the third circuit.
  • One embodiment of the present invention is a semiconductor device in which the third circuit includes an integration circuit and the output terminal of the integration circuit is electrically connected to the third wiring in the configuration of the above (1).
  • the second circuit includes a comparator and a resistance element, and one of the inverting input terminal and the non-inverting input terminal of the comparator is The semiconductor device is electrically connected to the resistance element and the first wiring, and the output terminal of the comparator is electrically connected to the third circuit.
  • the holding node of the first memory cell holds a potential corresponding to the first data
  • the potential of the second wiring The amount of change is a potential difference according to the second data
  • the first current is a current according to the product of the first data and the second data
  • the second potential is a potential according to the teacher data.
  • the amount of change in potential of the third wiring is a potential difference according to the update data.
  • One embodiment of the present invention is the above structure (4), in which a plurality of first memory cells, a plurality of second memory cells, a plurality of third memory cells, a plurality of third circuits, and a plurality of second circuits are provided.
  • Each of the plurality of first memory cells is electrically connected to the first wiring, and each of the plurality of second memory cells is connected to the fourth wiring.
  • Each of the plurality of third memory cells is electrically connected to the fifth wiring, and each of the plurality of third circuits is connected to the plurality of second memory via one of the plurality of second wirings.
  • One memory cell and one of the plurality of second memory cells are electrically connected, and each of the plurality of third circuits is connected to the plurality of first memory cells via one of the plurality of third wirings. And one of a plurality of third memory cells are electrically connected to each other, and a holding node of the plurality of first memory cells A potential corresponding to the plurality of first data is held in each, a potential difference corresponding to the plurality of second data is input to each of the plurality of second wirings, and the first current is the plurality of first data. And a plurality of second data, and the plurality of third circuits output potential differences corresponding to the plurality of update data to the plurality of third wirings, respectively.
  • each of the first to third memory cells includes a first transistor, a second transistor, a first capacitor
  • the first terminal of the first transistor is the gate of the second transistor, the first terminal of the first capacitor, and the second capacitor.
  • the second terminal of the first capacitor is electrically connected to the second wiring, and the second terminal of the second capacitor is electrically connected to the third wiring.
  • the first terminal of the second transistor is electrically connected to the first wiring, and in the second memory cell, the first terminal of the second transistor is electrically connected to the fourth wiring.
  • the first terminal of the second transistor It is electrically connected to the fifth wiring, a semiconductor device.
  • One embodiment of the present invention includes first to third circuits, first memory cells, and first to third wirings, and the first circuit includes the first memory cells through the first wirings.
  • the second circuit is electrically connected to the third circuit, and the third circuit is electrically connected to the first memory cell through the second wiring.
  • the third circuit is electrically connected to the first memory cell through the third wiring, the third circuit has an input terminal, the first memory cell has a holding node, and the first memory The cell has a function of changing the potential of the holding node of the first memory cell according to the change in the potential of the second wiring, and the potential of the holding node of the first memory cell according to the change of the potential of the third wiring.
  • the first circuit has a function of supplying a current to the first wiring
  • the second circuit has a first potential corresponding to the first current flowing between the first wiring and the second circuit.
  • the second potential is input to the input terminal of the third circuit
  • the third circuit has the first potential and the second potential.
  • the potential of the second wiring are input to the third circuit, thereby changing the potential of the third wiring in accordance with the first potential, the second potential, and the potential of the second wiring. It is a semiconductor device.
  • One embodiment of the present invention is the semiconductor device in the structure of (7), in which the third circuit includes an integration circuit, and the output terminal of the integration circuit is electrically connected to the third wiring.
  • the second circuit includes a comparator, a resistance element, and a first switch, and the comparator has an inverting input terminal or a non-inverting terminal.
  • One of the input terminals is electrically connected to the resistance element, and one of the inverting input terminal or the non-inverting input terminal of the comparator is electrically connected to the first wiring via the first switch, and the output terminal of the comparator Is a semiconductor device electrically connected to the third circuit.
  • the first circuit includes a first constant current circuit, a second constant current circuit, and a current sink circuit.
  • the first constant current circuit has a function of supplying a current to the current sink circuit or supplying a current to the first wiring
  • the second constant current circuit has a function of supplying a current to the first wiring.
  • the current sink circuit is a semiconductor device having a function of sucking current from the first constant current circuit or sucking current from the first wiring.
  • the first constant current circuit holds the first holding potential at the holding node of the first memory cell, and receives the first initial potential from the second wiring.
  • the second constant current circuit has a function of generating, as a constant current, a second current that flows from the first circuit to the first wiring when the second initial potential is input from the third wiring.
  • the first holding potential is held at the holding node, the third potential is input from the second wiring, and the second initial potential is input from the third wiring, the third current flowing from the first circuit to the first wiring
  • the current sink circuit has a function of generating a current as a constant current.
  • the current sink circuit holds the first holding potential at the holding node of the first memory cell, receives the third potential from the second wiring, and outputs the second potential from the third wiring.
  • the first current flowing from the first constant current circuit when the initial potential is input The first constant current circuit has a function of sucking current as a constant current, and the second holding potential is held in the holding node of the first memory cell, the first initial potential is input from the second wiring, and the third wiring
  • the fourth current flowing from the first circuit to the first wiring is generated as a constant current, and the first memory cell serves as a holding node of the first memory cell.
  • the third potential is input from the second wiring
  • the second initial potential is input from the third wiring
  • the second holding potential, the third potential, and the second initial potential are set.
  • the first circuit holds the second holding potential at the holding node of the first memory cell;
  • the third current is a difference current between the sum and the fifth current, and the third circuit sets the second initial potential of the third wiring as the first potential, the second potential, and the first initial potential and the third potential of the second wiring.
  • the difference between the first holding potential and the second holding potential is a potential difference according to the first data, and the difference between the first initial potential and the third potential.
  • the first current is a current according to the product of the first data and the second data
  • the second potential is a potential according to the teacher data
  • the difference between the second initial potential and the fourth potential is a semiconductor device that is a potential difference according to the update data.
  • One embodiment of the present invention is the above structure (12), including a plurality of first memory cells, a plurality of third circuits, a plurality of second wirings, and a plurality of third wirings.
  • Each of the first memory cells is electrically connected to the first wiring
  • each of the plurality of third circuits is electrically connected to one of the plurality of first memory cells via one of the plurality of second wirings.
  • Each of the plurality of third circuits is electrically connected to one of the plurality of first memory cells via one of the plurality of third wirings, and each of the holding nodes of the plurality of first memory cells.
  • the potential difference corresponding to the plurality of first data is held, the potential difference corresponding to the plurality of second data is applied to each of the plurality of second wirings, and the first current is the same as that of the plurality of first data.
  • Current corresponding to the product sum of the plurality of second data and each of the plurality of third circuits For each of the third wirings, and outputs a potential difference corresponding to the plurality of update data, which is a semiconductor device.
  • the first memory cell includes a first transistor, a second transistor, a first capacitor, and a second capacitor.
  • the first terminal of the first transistor is electrically connected to the gate of the second transistor, the first terminal of the first capacitor element, and the first terminal of the second capacitor element.
  • the second terminal of the capacitive element is electrically connected to the second wiring, the second terminal of the second capacitive element is electrically connected to the third wiring, and the first terminal of the second transistor is the first wiring.
  • the semiconductor device is electrically connected to the semiconductor device.
  • each channel formation region of the first transistor and the second transistor includes a metal oxide, and the first to third circuits Each is a semiconductor device configured as a unipolar circuit.
  • One embodiment of the present invention includes first to third circuits, first memory cells, and first to third wirings, and the first circuit includes the first memory cells through the first wirings.
  • the second circuit is electrically connected to the third circuit, and the third circuit is electrically connected to the first memory cell through the second wiring.
  • the third circuit is electrically connected to the first memory cell via the third wiring, and the first circuit has a first constant current circuit, a second constant current circuit, and a current sink circuit.
  • the third circuit has an input terminal, and the first memory cell is a method for operating a semiconductor device having a holding node.
  • the semiconductor device has first to fourth periods.
  • the first memory The first holding potential is held at the holding node of the cell, and the first initial potential from the second wiring and the second initial potential from the third wiring are stored in the first memory cell.
  • a potential corresponding to the first holding potential, the first initial potential, and the second initial potential flows between the first memory cell and the first wiring, and the current flows from the first circuit.
  • the second current flowing in the first wiring is generated as a constant current by the first constant current circuit.
  • the first holding potential is held in the holding node of the first memory cell, and the first memory cell Are inputted with the third potential from the second wiring and the second initial potential from the third wiring, and the first holding potential and the third potential between the first memory cell and the first wiring.
  • a third current flowing from the first circuit to the first wiring is generated as a constant current by the second constant current circuit and flows from the first constant current circuit.
  • Two currents are sucked out as a constant current by the current sink circuit, and in the third period, the first memory A second holding potential is held in the holding node of the cell, and a first initial potential from the second wiring and a second initial potential from the third wiring are input to the first memory cell, and the first memory A current corresponding to the second holding potential, the first initial potential, and the second initial potential flows between the cell and the first wiring, and the fourth current flowing from the first circuit to the first wiring is: Generated as a constant current by the first constant current circuit, and in the fourth period, the second holding potential is held in the holding node of the first memory cell, and the third potential from the second wiring is held in the first memory cell.
  • the second initial potential from the third wiring are input according to the second holding potential, the third potential, and the second initial potential between the first memory cell and the first wiring.
  • the fifth current flows, the sum of the fourth current and the fifth current supplied to the first wiring, and the second current drawn from the first wiring.
  • the first current flows between the second circuit and the first wiring, so that the first potential corresponding to the first current is generated by the second circuit.
  • the second potential is input to the input terminal of the third circuit, the first potential, the second potential, the first initial potential and the third potential of the second wiring. Is input to the third circuit, and the second initial potential of the third wiring is changed to the first potential, the second potential, the first initial potential, and the third potential by the third circuit. This is a method for operating a semiconductor device that varies to a fourth potential corresponding to the potential difference between the two.
  • One embodiment of the present invention is the operation method of (16), in which the third circuit includes an integration circuit, and the output terminal of the integration circuit is electrically connected to the third wiring. Is the method.
  • One embodiment of the present invention is the operation method according to (16) or (17), in which the second circuit includes a comparator, a resistance element, and a first switch, and the inverting input terminal of the comparator One of the inverting input terminals is electrically connected to the resistance element, and one of the inverting input terminal of the comparator or the non-inverting input terminal is electrically connected to the first wiring via the first switch, and the output of the comparator
  • the terminal is an operation method of the semiconductor device which is electrically connected to the third circuit.
  • the difference between the first holding potential and the second holding potential is a potential difference corresponding to the first data.
  • the difference between the initial potential and the third potential is a potential difference according to the second data
  • the first current is a current according to the product of the first data and the second data
  • the second potential is This is a method of operating a semiconductor device, which is a potential according to teacher data
  • a difference between the second initial potential and the fourth potential is a potential difference according to update data.
  • One embodiment of the present invention is the operation method according to (19), including a plurality of first memory cells, a plurality of third circuits, a plurality of second wirings, and a plurality of third wirings.
  • Each of the first memory cells is electrically connected to the first wiring
  • each of the plurality of third circuits is electrically connected to one of the plurality of first memory cells via one of the plurality of second wirings.
  • Each of the plurality of third circuits is electrically connected to one of the plurality of first memory cells via one of the plurality of third wirings, and each of the holding nodes of the plurality of first memory cells.
  • a potential difference corresponding to the plurality of first data is held in each of the plurality of second wirings, and a potential difference corresponding to the plurality of second data is applied to each of the plurality of second wirings.
  • a current corresponding to the product sum of the plurality of second data, and each of the plurality of third circuits For each of a plurality of third wirings, and outputs a potential difference corresponding to the plurality of update data, an operation method of a semiconductor device.
  • One embodiment of the present invention is the operation method according to any one of the above (16) to (20), in which the first memory cell includes a first transistor, a second transistor, a first capacitor, and a second capacitor. And the first terminal of the first transistor is electrically connected to the gate of the second transistor, the first terminal of the first capacitor, and the first terminal of the second capacitor, The second terminal of the one capacitive element is electrically connected to the second wiring, the second terminal of the second capacitive element is electrically connected to the third wiring, and the first terminal of the second transistor is the first wiring.
  • An operation method of a semiconductor device which is electrically connected to wiring.
  • the channel formation regions of the first transistor and the second transistor each include a metal oxide, and each of the first to third circuits is a single unit.
  • a semiconductor device refers to a device using semiconductor characteristics, such as a circuit including a semiconductor element (a transistor, a diode, a photodiode, or the like), a device including the circuit, or the like. In addition, it refers to all devices that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including the integrated circuit, and an electronic component in which the chip is housed in a package are examples of the semiconductor device.
  • a memory device, a display device, a light-emitting device, a lighting device, an electronic device, and the like are themselves semiconductor devices and may include a semiconductor device.
  • X and Y are connected, X and Y are electrically connected, and X and Y are functionally connected. And the case where X and Y are directly connected are disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or text, and things other than the connection relation shown in the figure or text are also disclosed in the figure or text.
  • X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
  • an element for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display, etc.
  • the switch has a function of controlling on / off. That is, the switch is in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether or not to pass a current.
  • a circuit for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc.
  • Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes signal potential level, etc.), voltage source, current source, switching Circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.)
  • One or more can be connected between them.
  • a circuit for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc.
  • Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power
  • X and Y, the source (or the first terminal) and the drain (or the second terminal) of the transistor are electrically connected to each other, and X and the source (or the first terminal of the transistor). 1 ”, the drain of the transistor (or the second terminal, and the like) and the Y are connected in this order.” Or “the source (or the first terminal, etc.) of the transistor is electrically connected to X, the drain (or the second terminal, etc.) of the transistor is electrically connected to Y, and X, the source of the transistor ( Or the first terminal or the like, the drain of the transistor (or the second terminal, or the like) and Y are electrically connected in this order.
  • X is electrically connected to Y through the source (or the first terminal) and the drain (or the second terminal) of the transistor, and X is the source of the transistor (or the first terminal). Terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order.
  • the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor are separated. Apart from that, the technical scope can be determined.
  • these expression methods are examples, and are not limited to these expression methods.
  • X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
  • the term “electrically connected” in this specification includes in its category such a case where one conductive film has functions of a plurality of components.
  • a transistor has three terminals called a gate, a source, and a drain.
  • the gate is a control terminal that controls the conduction state of the transistor.
  • Two terminals functioning as a source or a drain are input / output terminals of the transistor.
  • One of the two input / output terminals serves as a source and the other serves as a drain depending on the conductivity type (n-channel type and p-channel type) of the transistor and the potential applied to the three terminals of the transistor.
  • the terms source and drain can be paraphrased.
  • a node can be restated as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, or the like depending on a circuit configuration, a device structure, or the like. Further, a terminal, a wiring, or the like can be referred to as a node.
  • Voltage is a potential difference from a reference potential.
  • the reference potential is a ground potential (ground potential)
  • “voltage” can be rephrased as “potential”.
  • the ground potential does not necessarily mean 0V. Note that the potential is relative, and the potential applied to the wiring or the like may be changed depending on the reference potential.
  • “current” is defined as a charge transfer phenomenon (electric conduction) associated with the movement of a positive charged body, but the description “electric conduction of a positive charged body” In other words, “negatively charged electric conduction occurs in the opposite direction”. Therefore, in this specification and the like, “current” refers to a charge movement phenomenon (electric conduction) accompanying the movement of carriers unless otherwise specified. Examples of the carrier here include electrons, holes, anions, cations, complex ions, and the like, and the carriers differ depending on the system in which current flows (for example, semiconductor, metal, electrolyte, vacuum, etc.). In general, the “current direction” in a wiring or the like is a direction in which positive carriers move, and is expressed as a positive current amount.
  • the direction in which the negative carriers move is opposite to the direction of the current, and is expressed by a negative current amount. Therefore, in this specification and the like, when there is no notice about the positive / negative of the current (or the direction of the current), a description such as “current flows from element A to element B” is “current flows from element B to element A” or the like In other words. In addition, a description such as “current is input to element A” can be restated as “current is output from element A” or the like.
  • the ordinal numbers “first”, “second”, and “third” are given to avoid confusion between components. Therefore, the number of components is not limited. Further, the order of the components is not limited. For example, a component referred to as “first” in one of the embodiments (or examples) of this specification and the like may be referred to as “second” in the other embodiments (or examples) or in the claims. It may be a component referred to. Further, for example, a component referred to as “first” in one embodiment (or example) of the present specification may be omitted in another embodiment or in the claims.
  • the terms “upper” and “lower” do not limit that the positional relationship between the constituent elements is directly above or directly below and in direct contact with each other.
  • the expression “electrode B on the insulating layer A” does not require the electrode B to be formed in direct contact with the insulating layer A, and another configuration between the insulating layer A and the electrode B. Do not exclude things that contain elements.
  • conductive layer may be changed to the term “conductive film”.
  • insulating film may be changed to the term “insulating layer”.
  • the term “conductive layer” or “conductive film” may be changed to the term “conductor” in some cases.
  • the terms “insulating layer” and “insulating film” may be changed to the term “insulator”.
  • Electrode and “wiring” do not functionally limit these components.
  • an “electrode” may be used as part of a “wiring” and vice versa.
  • the terms “electrode” and “wiring” include a case where a plurality of “electrodes” and “wirings” are integrally formed.
  • wiring in this specification and the like, terms such as “wiring”, “signal line”, and “power supply line” can be interchanged with each other depending on circumstances or circumstances.
  • the term “wiring” may be changed to a term such as “power supply line”.
  • the reverse is also true, and there are cases where terms such as “signal line” and “power supply line” can be changed to the term “wiring”.
  • a term such as “power line” may be changed to a term such as “signal line”.
  • a term such as “signal line” may be changed to a term such as “power line”.
  • the term “potential” applied to the wiring may be changed to a term “signal” or the like depending on circumstances or circumstances. The reverse is also true, and a term such as “signal” may be changed to a term “potential”.
  • a semiconductor impurity means, for example, a component other than the main component constituting a semiconductor layer.
  • an element having a concentration of less than 0.1 atomic% is an impurity.
  • impurities for example, DOS (Density of States) may be formed in the semiconductor, carrier mobility may be reduced, and crystallinity may be reduced.
  • examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and components other than main components Examples include transition metals, and in particular, hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, and the like.
  • oxygen vacancies may be formed by mixing impurities such as hydrogen, for example.
  • impurities such as hydrogen, for example.
  • examples of impurities that change the characteristics of the semiconductor include group 1 elements, group 2 elements, group 13 elements, and group 15 elements excluding oxygen and hydrogen.
  • a switch refers to a switch that is in a conductive state (on state) or a non-conductive state (off state) and has a function of controlling whether or not to pass a current.
  • the switch refers to a switch having a function of selecting and switching a current flow path.
  • an electrical switch, a mechanical switch, or the like can be used. That is, the switch is not limited to a specific one as long as it can control the current.
  • Examples of electrical switches include transistors (eg, bipolar transistors, MOS transistors, etc.), diodes (eg, PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes. , Diode-connected transistors, etc.), or a logic circuit combining these.
  • transistors eg, bipolar transistors, MOS transistors, etc.
  • diodes eg, PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes. , Diode-connected transistors, etc.
  • the “conducting state” of the transistor means a state in which the source electrode and the drain electrode of the transistor can be regarded as being electrically short-circuited.
  • non-conducting state of a transistor refers to a state where the source electrode and the drain electrode of the transistor can be regarded as being electrically disconnected. Note that when a transistor is operated as a simple switch, the polarity (conductivity type) of the transistor is not particularly limited.
  • a mechanical switch is a switch using MEMS (micro electro mechanical system) technology such as a digital micromirror device (DMD).
  • MEMS micro electro mechanical system
  • DMD digital micromirror device
  • the switch has an electrode that can be moved mechanically, and operates by controlling conduction and non-conduction by moving the electrode.
  • a semiconductor device in which a hierarchical artificial neural network capable of learning is constructed can be provided.
  • a semiconductor device in which a weighting factor is updated in a short time can be provided.
  • a semiconductor device with low power consumption can be provided.
  • the effects of one embodiment of the present invention are not limited to the effects listed above.
  • the effects listed above do not preclude the existence of other effects.
  • the other effects are effects not mentioned in this item described in the following description. Effects not mentioned in this item can be derived from the description of the specification or drawings by those skilled in the art, and can be appropriately extracted from these descriptions.
  • one embodiment of the present invention has at least one of the effects listed above and other effects. Accordingly, one embodiment of the present invention may not have the above-described effects depending on circumstances.
  • FIG. 11 is a block diagram illustrating an example of a semiconductor device.
  • FIG. 6 is a circuit diagram illustrating an example of a memory cell included in a semiconductor device.
  • FIG. 11 is a block diagram illustrating an example of a current supply circuit included in a semiconductor device.
  • FIG. 6 is a circuit diagram illustrating an example of a current supply circuit included in a semiconductor device.
  • FIG. 10 is a circuit diagram illustrating an example of an activation function circuit included in a semiconductor device.
  • FIG. 6 is a circuit diagram illustrating an example of a circuit included in a semiconductor device.
  • FIG. 6 is a block diagram illustrating an example of a learning circuit included in a semiconductor device.
  • FIG. 3 is a circuit diagram illustrating an example of a part of a circuit included in a learning circuit.
  • FIG. 3 is a circuit diagram illustrating an example of a part of a circuit included in a learning circuit.
  • FIG. 6 is a circuit diagram illustrating an example of a current supply circuit included in a semiconductor device. 6 is a timing chart illustrating an operation example of a semiconductor device. 6 is a timing chart illustrating an operation example of a semiconductor device. 6 is a timing chart illustrating an operation example of a semiconductor device.
  • FIG. 10 is a cross-sectional view illustrating a structure example of a semiconductor device. FIG.
  • FIG. 10 is a cross-sectional view illustrating a structure example of a semiconductor device.
  • FIG. 10 is a cross-sectional view illustrating a structural example of a transistor.
  • 10A and 10B are a top view and a cross-sectional view illustrating a structure example of a transistor.
  • 10A and 10B are a top view and a cross-sectional view illustrating a structure example of a transistor.
  • 10A and 10B are a top view and a cross-sectional view illustrating a structure example of a transistor.
  • 10A and 10B are a top view and a cross-sectional view illustrating a structure example of a transistor.
  • 10A and 10B are a top view and a cross-sectional view illustrating a structure example of a transistor.
  • FIG. 10A and 10B are a top view and a perspective view illustrating a structural example of a transistor.
  • FIG. 10 is a cross-sectional view illustrating a structural example of a transistor.
  • the perspective view which shows an example of an electronic device.
  • the perspective view which shows an example of an electronic device.
  • the block diagram which shows the circuit used for calculation in an Example.
  • the distribution map which shows the classification
  • the graph which shows the frequency of an update.
  • an artificial neural network refers to all models that mimic biological neural networks.
  • a neural network has a configuration in which units simulating neurons are connected to each other via units simulating synapses.
  • the strength of synaptic connections can be changed by providing existing information to the neural network. In this way, the process of giving existing information to the neural network and determining the coupling strength is sometimes called “learning”.
  • new information can be output based on the connection strength by giving some information to the neural network that has been “learned” (the connection strength is determined).
  • the connection strength is determined.
  • a process of outputting new information based on given information and connection strength may be referred to as “inference” or “cognition”.
  • Examples of neural network models include a hop field type and a hierarchical type.
  • a neural network having a multilayer structure is referred to as “deep neural network” (DNN), and machine learning by the deep neural network is referred to as “deep learning”.
  • DNN deep neural network
  • a metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors, and the like. For example, when a metal oxide is used for an active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, in the case where a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide is abbreviated as a metal oxide semiconductor (metal oxide semiconductor). It can be called OS. In addition, in the case of describing an OS FET or an OS transistor, it can be restated as a transistor including a metal oxide or an oxide semiconductor.
  • metal oxide semiconductor metal oxide semiconductor
  • metal oxides having nitrogen may be collectively referred to as metal oxides.
  • a metal oxide containing nitrogen may be referred to as a metal oxynitride.
  • the content (or part of the content) described in one embodiment (or example) may be another content (or part of content) described in the embodiment (or the example).
  • at least one of the contents described in one or a plurality of other embodiments (or one or a plurality of other examples) may be a part of the contents) Alternatively, replacement can be performed.
  • FIG. 1 shows a configuration example of the arithmetic circuit 100.
  • An arithmetic circuit 100 shown in FIG. 1 is a circuit that performs a product-sum operation of first data held in a memory cell, which will be described later, and second data input to the memory cell. It is a circuit that outputs the value of the corresponding activation function.
  • the first data and the second data can be analog data or multi-value data (discrete data).
  • the arithmetic circuit 100 shown in FIG. 1 includes a current supply circuit IS, a circuit WDD, a circuit WLD, a circuit VLD, an activation function circuit ACTV, a learning circuit LEC, and a memory cell array MCA.
  • the memory cell array MCA includes a memory cell AM [1], a memory cell AM [2], a memory cell AMxr [1], a memory cell AMxr [2], a memory cell AMwr [1], and a memory cell AMwr [2]. ].
  • the memory cell AM [1] and the memory cell AM [2] have a function of holding the first data, and the memory cell AMxr [1] and the memory cell AMxr [2] perform a product-sum operation. It has a function of holding first reference data that is necessary.
  • the memory cell AMwr [1] and the memory cell AMwr [2] have a function of holding second reference data necessary for performing a product-sum operation.
  • the memory cell array MCA also functions as a nonvolatile local memory. For this reason, by providing a memory unit for storing data in a circuit that performs calculation, it is possible to read out data necessary for the calculation from the outside of the calculation circuit 100 and transmit the data to the calculation circuit one by one during calculation. Can do.
  • the reference data can also be analog data or multi-valued data (discrete data), like the first data and the second data.
  • the memory cell array MCA in FIG. 1 has a configuration in which memory cells are arranged in a matrix of 2 rows and 3 columns. However, the memory cell array MCA has memory cells arranged in a matrix of 3 rows or more and 4 columns or more. It is good also as a structure. In addition, when performing multiplication instead of product-sum operation, the memory cell array MCA may have a configuration in which three memory cells are arranged in a matrix in the row direction and one or more in the column direction.
  • the memory cell AM [1], the memory cell AM [2], the memory cell AMxr [1], the memory cell AMxr [2], the memory cell AMwr [1], and the memory cell AMwr [2] have the same circuit configuration. It can be. Therefore, in this specification and the like, unless otherwise specified, the memory cell AM [1], the memory cell AM [2], the memory cell AMxr [1], the memory cell AMxr [2], the memory cell AMwr [1], and The memory cell AMwr [2] may be collectively referred to as a memory cell AM.
  • the memory cell AM has terminals m1 to m5 as shown in FIG.
  • the memory cell AM can be configured as shown in FIG. 2A, for example.
  • the memory cell AM includes a transistor Tr1, a transistor Tr2, a capacitor C1, and a capacitor C2.
  • the transistor Tr1 is preferably an OS transistor.
  • the channel formation region of the transistor Tr1 is more preferably an oxide containing at least one of indium, element M (element M includes aluminum, gallium, yttrium, tin, and the like) and zinc.
  • the transistor Tr1 particularly preferably has the structure of the transistor described in Embodiment 3.
  • an OS transistor is used as the transistor Tr1
  • leakage current of the transistor Tr1 can be suppressed, so that a product-sum operation circuit with high calculation accuracy may be realized.
  • an OS transistor as the transistor Tr1
  • a leakage current from the holding node to the write word line can be extremely reduced when the transistor Tr1 is in a non-conductive state. That is, since the refresh operation of the potential of the holding node can be reduced, the power consumption of the product-sum operation circuit can be reduced.
  • the transistor Tr2 can be manufactured at the same time as the transistor Tr1 by using an OS transistor, the manufacturing process of the arithmetic circuit may be shortened.
  • the transistor Tr2 may be a transistor in which the channel formation region includes silicon such as amorphous silicon or polycrystalline silicon instead of oxide (hereinafter referred to as Si FET, Si transistor, or the like).
  • the first terminal of the transistor Tr1 is electrically connected to the gate of the transistor Tr2, the first terminal of the capacitor C1, and the first terminal of the capacitor C2.
  • the first terminal of the transistor Tr2 is electrically connected to the wiring VR0.
  • the wiring VR0 is a wiring for allowing a current to flow between the first terminal and the second terminal of the transistor Tr2. Therefore, the wiring VR0 functions as a wiring for applying a predetermined potential.
  • the potential provided by the wiring VR0 can be a ground potential or a potential lower than the ground potential.
  • the second terminal of the transistor Tr1 is electrically connected to the terminal m1
  • the second terminal of the transistor Tr2 is electrically connected to the terminal m2
  • the gate of the transistor Tr1 is connected to the terminal m3. Electrically connected.
  • the second terminal of the capacitive element C1 is electrically connected to the terminal m4, and the second terminal of the capacitive element C2 is electrically connected to the terminal m5.
  • a connection point of the first terminal of the transistor Tr1, the gate of the transistor Tr2, the first terminal of the capacitor C1, and the first terminal of the capacitor C2 serves as a holding node of the memory cell AM, and FIG. ) Shows a node NM.
  • node NM signal of a specific memory cell
  • the node NM of the memory cell AM [1] when the node NM of the memory cell AM [1] is indicated, it is described as the node NM (AM [1]).
  • the node NM AMxr [2]
  • the node NM AMxr [2]
  • the structure of the memory cell AM included in the memory cell array MCA of the arithmetic circuit 100 is not limited to the structure illustrated in FIG.
  • the configuration of the memory cell AM can be selected according to the situation and / or the configuration of the electrical connection can be changed.
  • the transistor Tr1 and the transistor Tr2 included in the memory cell AM illustrated in FIG. 2A may have a back gate.
  • FIG. 2B shows a structure of the memory cell AM in which the transistors Tr1 and Tr2 have back gates.
  • the back gate of the transistor Tr1 is electrically connected to the gate of the transistor Tr1
  • the back gate of the transistor Tr2 is electrically connected to the gate of the transistor Tr2.
  • the connection configuration will be described.
  • the terminal m1 is electrically connected to the wiring WD
  • the terminal m2 is electrically connected to the wiring BL
  • the terminal m3 is electrically connected to the wiring WL [1].
  • the terminal m4 is electrically connected to the wiring VL [1]
  • the terminal m5 is electrically connected to the wiring HW [1].
  • the terminal m1 is electrically connected to the wiring WD
  • the terminal m2 is electrically connected to the wiring BL
  • the terminal m3 is electrically connected to the wiring WL [2].
  • the terminal m4 is electrically connected to the wiring VL [2]
  • the terminal m5 is electrically connected to the wiring HW [2].
  • the terminal m1 is electrically connected to the wiring WDxr
  • the terminal m2 is electrically connected to the wiring BLxr
  • the terminal m3 is electrically connected to the wiring WL [1].
  • the terminal m4 is electrically connected to the wiring VL [1]
  • the terminal m5 is electrically connected to the wiring GNDL.
  • the terminal m1 is electrically connected to the wiring WDxr
  • the terminal m2 is electrically connected to the wiring BLxr
  • the terminal m3 is electrically connected to the wiring WL [2].
  • the terminal m4 is electrically connected to the wiring VL [2]
  • the terminal m5 is electrically connected to the wiring GNDL.
  • the terminal m1 is electrically connected to the wiring WDwr
  • the terminal m2 is electrically connected to the wiring BLwr
  • the terminal m3 is electrically connected to the wiring WL [1].
  • the terminal m4 is electrically connected to the wiring GNDL
  • the terminal m5 is electrically connected to the wiring HW [1].
  • the terminal m1 is electrically connected to the wiring WDwr
  • the terminal m2 is electrically connected to the wiring BLwr
  • the terminal m3 is electrically connected to the wiring WL [2].
  • the terminal m4 is electrically connected to the wiring GNDL
  • the terminal m5 is electrically connected to the wiring HW [2].
  • the wiring GNDL is a wiring for applying a ground potential GND to an electrical connection destination of the wiring GNDL. Therefore, the ground potential GND is lower than the high power supply potential VDD.
  • the current supply circuit IS has a terminal co, a terminal coxr, and a terminal cowr.
  • the terminal co is electrically connected to the wiring BL
  • the terminal coxr is electrically connected to the wiring BLxr
  • the terminal cowr is electrically connected to the wiring BLwr.
  • the current supply circuit IS has a function of supplying current to the wiring BL, the wiring BLxr, and the wiring BLwr. In such herein, the current flowing from the terminal co wiring BL marked I C, the current flowing from the terminal coxr wiring BLxr marked I CXR, and the current flowing from the terminal cowr wiring BLwr wrote and I CWR.
  • the current supply circuit IS is shown as having, for example, a bias circuit CS and a current mirror circuit CM. Details of a configuration example of the current supply circuit IS in this case are shown in FIG.
  • the current supply circuit IS illustrated in FIG. 3A includes a circuit CS1, a circuit CSx, and a circuit CSw as the bias circuit CS, and includes a circuit CMx and a circuit CMw as the current mirror circuit CM. .
  • the circuit CS1 is a circuit having a terminal d1, a terminal d2, a terminal dx, a terminal dw, and a plurality of constant current sources. Inside the circuit CS1, each of the terminal d1, the terminal d2, the terminal dx, and the terminal dw is electrically connected to a different constant current source.
  • the terminal d1 is electrically connected to the wiring OL [1]
  • the terminal dx is electrically connected to the wiring OLxr
  • the terminal d2 is electrically connected to the wiring OL [2]
  • the terminal dw is Are electrically connected to the wiring OLwr.
  • circuit CS1 outputs the current I d1 from terminal d1, and outputs a current I dx from the terminal dx, and outputs a current I d2 from the terminal d2, and outputs a current I dw from the terminal dw Shall.
  • the circuit CMx is a current mirror circuit for sucking out a current corresponding to the potential of the wiring OLxr from the wiring OL [1] and the wiring OLxr.
  • the circuit CMx may be a current mirror circuit that supplies a current corresponding to the potential of the wiring OLxr to the wiring OL [1] and the wiring OLxr.
  • the circuit CSx is a current sink circuit that samples the potential of the wiring OL [1] and sucks a current corresponding to the potential from the wiring OL [1]. In this configuration example, it is assumed that the current ICSx is sucked from the wiring OL [1]. However, depending on the circuit configuration, the circuit CSx may be a current source circuit that samples the potential of the wiring OL [1] and supplies a current corresponding to the potential. The circuit CSx may be a circuit that performs both supply of current and suction of current to the wiring OL [1]. Further, the current supply circuit IS illustrated in FIG. 3A may exclude the circuit CSx depending on the situation.
  • the circuit CSw is a current sink circuit that samples the potential of the wiring OL [2] and sucks a current corresponding to the potential from the wiring OL [2]. In this configuration example, it is assumed that the current ICSw is sucked from the wiring OL [2]. However, depending on the circuit configuration, the circuit CSw may be a current source circuit that samples the potential of the wiring OL [2] and supplies a current corresponding to the potential. The circuit CSw may be a circuit that performs both supply of current and suction of current to the wiring OL [2]. Further, the current supply circuit IS illustrated in FIG. 3A may exclude the circuit CSw depending on the situation.
  • FIG. 3B is a configuration example of the current supply circuit IS in which the circuit CSx and the circuit CSw are combined as the circuit CSxw.
  • the circuit CSxw is a current sink circuit that samples the potential of the wiring OL [1] and draws out the current ICSxw corresponding to the potential from the wiring OL [1].
  • the circuit CSxw may be a current source circuit that samples the potential of the wiring OL [1] and supplies a current corresponding to the potential.
  • the circuit CSxw may be a circuit that performs both supply of current and suction of current to the wiring OL [1].
  • the current supply circuit IS illustrated in FIG. 3B may exclude the circuit CSxw depending on the situation.
  • FIG. 4 shows an example of a circuit diagram of the current supply circuit IS shown in FIG.
  • the circuit CS1 includes transistors M1 to M4, the circuit CMx includes transistors M5 and M6, the circuit CMw includes transistors M7 and M8, and the circuit CSx includes the transistor M9.
  • the transistor CS11 includes the transistor M11 and the capacitor CD1, and the circuit CSw includes the transistors M12 to M14 and the capacitor CD2.
  • the transistors M1 to M14 are n-channel transistors. Therefore, the current supply circuit IS can be configured as a unipolar circuit.
  • the transistors M1 to M14 are preferably OS transistors, like the transistors Tr1 and Tr2.
  • OS transistor the description of the transistor Tr1 is referred to.
  • the transistors M1 to M14 may be Si transistors.
  • the first terminals of the transistors M1 to M4 are electrically connected to the wiring OL [1], the wiring OLxr, the wiring OL [2], and the wiring OLwr, and the respective gates of the transistors M1 to M4.
  • the second terminals of the transistors M1 to M4 are electrically connected to the wiring VDDL.
  • each of the transistors M1 to M4 has a back gate, and the back gates of the transistors M1 to M4 are electrically connected to the wirings BGL1 to BGL4.
  • the wiring VDDL is a wiring for applying a high power supply potential VDD to an electrical connection destination of the wiring VDDL.
  • each of the transistors M1 to M4 has a gate-source voltage of 0 V, a high-level potential is applied to each of the wirings BGL1 to BGL4, so that each of the transistors M1 to M4 has a source-drain voltage.
  • a current can be passed through.
  • the circuit CS1 illustrated in FIG. 4 can be a circuit that supplies a constant current to each of the wiring OL [1], the wiring OLxr, the wiring OL [2], and the wiring OLwr by this operation. Note that the currents I d1 , I d2 , I dx , and I dw in FIG. 4 do not have to be equal.
  • the sum of I d1 and I d2 is greater than each of I dx and I dw. Larger is preferred. Therefore, the sizes of the transistors M1 to M4 may be different from each other. Alternatively, the wiring VDDL connected to the second terminals of the transistors M1 to M4 may be wirings to which different high power supply potentials are applied.
  • the first terminal of the transistor M5 is electrically connected to the wiring OL [1]
  • the first terminal of the transistor M6 is electrically connected to the wiring OLxr
  • each of the transistors M5 and M6 has a first terminal.
  • the two terminals are electrically connected to the wiring VSSL
  • the gate of the transistor M5 is electrically connected to the gate of the transistor M6 and the wiring OLxr.
  • the first terminal of the transistor M7 is electrically connected to the wiring OL [2]
  • the first terminal of the transistor M8 is electrically connected to the wiring OLwr
  • each of the transistors M7 and M8 has a first terminal.
  • the two terminals are electrically connected to the wiring VSSL
  • the gate of the transistor M7 is electrically connected to the gate of the transistor M8 and the wiring OLwr.
  • the wiring VSSL is a wiring for applying a low power supply potential VSS to an electrical connection destination of the wiring VSSL. Therefore, the low power supply potential VSS is lower than the high power supply potential VDD.
  • the low power supply potential VSS is preferably set to the ground potential GND or a potential lower than the ground potential.
  • the circuit CMx shown in FIG. 4 refers to the potential of the first terminal of the transistor M6, that is, the potential of the wiring OLxr, and sinks a current I CMxr corresponding to the potential from the wiring OL [1] and the wiring OLxr. Functions as a circuit.
  • the circuit CMw shown in FIG. 4 refers to the potential of the first terminal of the transistor M8, that is, the potential of the wiring OLwr, and sucks the current I CMwr corresponding to the potential from the wiring OL [2] and the wiring OLwr. Functions as a current mirror circuit.
  • the first terminal of the transistor M9 is electrically connected to the first terminal of the transistor M10 and the wiring OL [1], and the gate of the transistor M9 is connected to the second terminal of the transistor M10 and the transistor M11.
  • the gate of the transistor M9 is connected to the second terminal of the transistor M10 and the transistor M11.
  • Each of the second terminal of the transistor M9, the second terminal of the transistor M11, and the second terminal of the capacitor CD1 is electrically connected to the wiring VSSL.
  • the gate of the transistor M10 is electrically connected to the wiring OSP1, and the gate of the transistor M11 is electrically connected to the wiring ORP1.
  • the first terminal of the transistor M12 is electrically connected to the first terminal of the transistor M13 and the wiring OL [2].
  • the gate of the transistor M12 is connected to the second terminal of the transistor M13 and the transistor M14. Are electrically connected to the first terminal of the capacitor element CD2 and the first terminal of the capacitive element CD2.
  • Each of the second terminal of the transistor M13, the second terminal of the transistor M14, and the second terminal of the capacitor CD2 is electrically connected to the wiring VSSL.
  • the gate of the transistor M13 is electrically connected to the wiring OSP2, and the gate of the transistor M14 is electrically connected to the wiring ORP2.
  • the circuit CSx illustrated in FIG. 4 functions as a current sink circuit that samples the potential of the wiring OL [1] and sucks the current ICSx corresponding to the potential from the wiring OL [1].
  • the circuit CSx first applies a low-level potential to the wiring OSP1, turns off the transistor M10, applies a high-level potential to the wiring ORP1, and turns on the transistor M11. The potential held at one terminal is set to VSS. Next, a low-level potential is applied to the wiring ORP1, the transistor M11 is turned off, a high-level potential is applied to the wiring OSP1, and the transistor M10 is turned on, whereby the potential of the wiring OL [1], Alternatively, the vicinity of the potential is held at the first terminal of the capacitor CD1.
  • the wiring OL [1] is connected between the source and the drain of the transistor M9.
  • the current ICSx can be sucked out.
  • the circuit CSw illustrated in FIG. 4 functions as a current sink circuit that samples the potential of the wiring OL [2] and sucks the current ICSw corresponding to the potential from the wiring OL [2].
  • the operation of the circuit CSw is by replacing the wiring OSP1 and the wiring ORP1 with the wiring OSP2 and the wiring ORP2, respectively replacing the transistors M9 to M11 with the transistors M12 to M14, and replacing the capacitor CD1 with the capacitor CD2. It can be regarded as the operation of the circuit CSx.
  • the current ICSw can be sucked from the wiring OL [2] through the source and drain of the transistor M12.
  • Circuit WDD, Circuit WLD, Circuit VLD ⁇ Circuit WDD, Circuit WLD, Circuit VLD.
  • the circuit WDD is electrically connected to the wiring WD, the wiring WDxr, and the wiring WDwr.
  • the circuit WDD has a function of transmitting first data to be stored in each memory cell AM included in the memory cell array MCA.
  • the circuit WLD is electrically connected to the wiring WL [1] and the wiring WL [2].
  • the circuit WLD has a function of selecting a memory cell AM to which the data is written. .
  • the circuit VLD is electrically connected to the wiring VL [1] and the wiring VL [2].
  • the circuit VLD has a function of applying a potential corresponding to the second data to the second terminal of each capacitor C1 included in the memory cell array MCA.
  • the circuit VLD also has a function of transmitting a potential corresponding to the second data to a learning circuit LEC described later.
  • the activation function circuit ACTV has a terminal ai, a terminal afb, and a terminal ao.
  • the terminal ai is electrically connected to the wiring BL
  • the terminal afb is electrically connected to a terminal gi4 of a learning circuit LEC described later.
  • I ⁇ a current flowing from the wiring BL electrically connected to the memory cell array MCA to the terminal ai.
  • the terminal ao is electrically connected to the wiring OPL, and the wiring OPL can function as a wiring for outputting the result of the arithmetic circuit 100 to the outside.
  • the activation function circuit ACTV is a circuit that generates a potential according to a current input from the wiring BL to the terminal ai or a change in the current, and performs an operation on the potential according to a predefined function. It is.
  • a sigmoid function, a tanh function, a softmax function, a ReLU (Rectified Linear Unit) function, a threshold function, and the like can be used. These functions are applied as activation functions in a neural network.
  • the output result of the activation function circuit ACTV is output to the terminal afb and the terminal ao. Since the terminal afb and the terminal gi4 are electrically connected, the output result of the activation function circuit ACTV is input to the learning circuit LEC. In this specification and the like, the output result is referred to as operation result data.
  • FIG. 5A shows a configuration example of the activation function circuit ACTV.
  • the activation function circuit ACTV in FIG. 5A is a circuit having a function of generating a potential according to an input current, and includes a comparator CMP, a constant voltage source VC1, a constant voltage source VC2, and a resistance element. R1 and a switch SWA.
  • the + side input terminal of the comparator CMP is electrically connected to the first terminal of the switch SWA and the first terminal of the resistance element R1, and the ⁇ side input terminal of the comparator CMP is connected to the positive terminal of the constant voltage source VC2.
  • the output terminal of the comparator CMP is electrically connected to the terminal afb and the terminal ao.
  • the negative terminal of the constant voltage source VC2 is electrically connected to the wiring GNDL
  • the second terminal of the resistor element R1 is electrically connected to the positive terminal of the constant voltage source VC1
  • the negative terminal of the constant voltage source VC1 is connected to the wiring
  • the second terminal of the switch SWA is electrically connected to the terminal ai.
  • the wiring SWAL is electrically connected to the activation function circuit ACTV shown in FIG.
  • the wiring SWAL is a wiring for switching the switch SWA between an on state and an off state.
  • the activation function circuit ACTV in FIG. 5A when the input impedance of the comparator CMP is sufficiently higher than that of the resistance element R1 and a current is input from the terminal ai, the current flows through the resistance element R1. At this time, a voltage is generated between the first terminal and the second terminal of the resistance element R1. In particular, the potential of the first terminal of the resistance element R1 is determined by the magnitude of the current. That is, the input potential to the + side input terminal of the comparator CMP is determined by the current input from the terminal ai.
  • the constant voltage source VC1 and the constant voltage source VC2 are constant voltage sources that output the same voltage.
  • the positive electrode potential of the constant voltage source VC2 is the reference potential input to the negative input terminal of the comparator CMP. Therefore, the comparator CMP compares the input potential to the + side input terminal and the reference potential to the ⁇ side input terminal, and outputs a potential according to the comparison result from the output terminal.
  • the potential output from the output terminal of the comparator CMP can be a binary potential, that is, one of a low level potential and a high level potential.
  • a differential amplifier may be used instead as the comparator CMP included in the activation function circuit ACTV here. In this case, the potential output from the differential amplifier is an analog value.
  • the potential output from the output terminal of the comparator CMP is output to the terminal ao and the terminal afb as operation result data.
  • the operation result data is input to the learning circuit LEC.
  • the switch SWA may be set to a non-conductive state between the terminal ai and the + side input terminal of the comparator CMP. With such a configuration, a potential corresponding to the current input to the terminal ai can be output at a predetermined timing.
  • the switch SWA may not be provided, and instead of applying the power supply potential for driving the comparator CMP to the comparator CMP, the activation function circuit ACTV may not be driven.
  • FIG. 5B shows a configuration example of another activation function circuit ACTV, which is different from FIG.
  • An activation function circuit ACTV in FIG. 5A is a circuit having a function of generating a potential in accordance with a change in input current, and includes transistors Tr6 to Tr8, a capacitor element Cactv, and a resistor element R2. , A comparator CMP, and a constant voltage source VC3. Note that in FIG. 5B, the transistors Tr6 to Tr8 are n-channel transistors.
  • the transistors Tr6 to Tr8 are preferably OS transistors, like the transistors Tr1 and Tr2.
  • OS transistor the description of the transistor Tr1 is referred to.
  • the transistors Tr6 to Tr8 may be Si transistors.
  • the terminal ai is electrically connected to the first terminal of the capacitive element Cactv and the first terminal of the resistive element R1.
  • the second terminal of the capacitive element Cactv is electrically connected to the first terminal of the transistor Tr6 and the gate of the transistor Tr7.
  • the first terminal of the transistor Tr7 is electrically connected to the first terminal of the transistor Tr8 and the + side input terminal of the comparator CMP. Note that an electrical connection point between the first terminal of the capacitor element Cactv, the first terminal of the resistor element R1, and the terminal a i is a node Na, the second terminal of the capacitor element Cactv, and the first terminal of the transistor Tr6
  • the electrical connection point between the transistor Tr7 and the gate is the node Nb.
  • the second terminal of the resistance element R2 is electrically connected to the wiring VrefL.
  • the second terminal of the transistor Tr6 is electrically connected to the wiring VaL, and the gate of the transistor Tr7 is electrically connected to the wiring RST.
  • a second terminal of the transistor Tr7 is electrically connected to the wiring VDDL.
  • a second terminal of the transistor Tr8 is electrically connected to the wiring VSSL, and a gate of the transistor Tr8 is electrically connected to the wiring VbL.
  • the transistor Tr7, the transistor Tr8, the wiring VDDL, the wiring VSSL, and the wiring VbL constitute a source follower circuit.
  • a first current (hereinafter referred to as a first current) flows from the terminal ai
  • the resistance element R2 and the wiring VrefL cause the node Na to respond to the first current and the resistance of the resistance element R1.
  • a potential is applied.
  • the transistor Tr6 is turned on to apply the potential Va to the node Nb. Thereafter, the transistor Tr6 is turned off.
  • a second current (hereinafter referred to as a second current) flows from the terminal ai, similarly to when the first current flows, the resistance element R2 and the wiring VrefL cause the node Na.
  • the resistance element R2 and the wiring VrefL cause the node Na.
  • the potential of the node Nb also changes due to capacitive coupling when the potential of the node Na changes.
  • the change in the potential of the node Na is ⁇ V Na and the capacitive coupling coefficient is K
  • the potential of the node Nb is Va + K ⁇ ⁇ V Na .
  • the potential Va + K ⁇ ⁇ V Na -V th is output from the wiring OL.
  • the potential Va and the threshold voltage V th it is possible to enter a potential K ⁇ [Delta] V Na against the comparator CMP + side input terminal.
  • the capacitive coupling coefficient K is a constant determined by the gate capacitance of the transistor Tr7, the wiring material around the node Nb, the parasitic resistance, and the like.
  • the potential change amount ⁇ V Na is determined according to the change amount from the first current to the second current, the resistance value of the resistance element R1, and the potential Vref. Therefore, since each of the capacitive coupling coefficient K, the resistance value of the resistance element R1, and the potential Vref can be a constant, the potential K ⁇ ⁇ V Na input to the positive side input terminal of the comparator CMP is It depends on the amount of change from the first current to the second current.
  • the constant voltage source VC3 is a constant voltage source, and the positive potential of the constant voltage source VC3 is a reference potential input to the negative side input terminal of the comparator CMP. Therefore, the comparator CMP compares the input potential K ⁇ ⁇ V Na to the + side input terminal with the reference potential to the ⁇ side input terminal, and outputs a potential corresponding to the comparison result from the output terminal. .
  • the potential output from the output terminal of the comparator CMP can be a binary potential, that is, one of a low level potential and a high level potential.
  • the voltage between the positive electrode and the negative electrode of the constant voltage source VC3 can be appropriately determined according to the capacitive coupling coefficient K, the resistance value of the resistance element R1, and the potential Vref.
  • the potential output from the output terminal of the comparator CMP is output to the terminal ao and the terminal afb as operation result data.
  • the operation result data is input to the learning circuit LEC.
  • the comparator CMP shown in FIGS. 5A and 5B can be configured as a unipolar circuit.
  • the comparator CMP configured as a unipolar circuit can be the circuit of FIG.
  • the comparator CMP illustrated in FIG. 5C includes a differential amplifier DIAa, a differential amplifier DIAb, a circuit LAT, a capacitor element CE1, a capacitor element CE2, and switches SWB1 to SWB6.
  • the circuit LAT has a terminal ILP and a terminal ILN.
  • the terminal INP corresponds to the + side input terminal of the comparator CMP
  • the terminal INN corresponds to the ⁇ side input terminal of the comparator CMP
  • the terminal OLP corresponds to the + side output terminal of the comparator CMP.
  • the terminal OLP corresponds to the output terminal of the comparator CMP illustrated in FIGS. 5A and 5B, the terminal OLP is electrically connected to the terminal ao and the terminal afb.
  • the comparator CMP shown in FIG. 5C also shows a terminal OLN corresponding to the negative output terminal of the comparator CMP as a circuit for performing differential output, but the activation function shown in FIGS.
  • the terminal OLN is not electrically connected to an element, a wiring, a circuit, or the like.
  • the non-inverting input terminal of the differential amplifier DIAa is electrically connected to one of the two pairs of terminals of the switch SWB1 and one of the two pairs of terminals of the switch SWB3.
  • the inverting input terminal of the differential amplifier DIAa is One of the two pairs of terminals of the switch SWB2 and one of the two pairs of terminals of the switch SWB4 are electrically connected, and the non-inverting output terminal of the differential amplifier DIAa is one of the two pairs of electrodes of the capacitive element CE1.
  • the inverting output terminal of the differential amplifier DIAb is electrically connected to one of the two pairs of electrodes of the capacitive element CE1.
  • the non-inverting input terminal of the differential amplifier DIAb is electrically connected to one of the two pairs of terminals of the switch SWB5 and the other of the two pairs of terminals of the capacitive element CE1, and the inverting input terminal of the differential amplifier DIAb is , And electrically connected to one of the two pairs of terminals of the switch SWB6 and the other of the two pairs of terminals of the capacitive element CE2, and the non-inverting output terminal of the differential amplifier DIAb is electrically connected to the terminal ILP of the circuit LAT.
  • the inverting output terminal of the differential amplifier DIAb is electrically connected to the terminal ILN of the circuit LAT.
  • the other of the two pairs of terminals of the switch SWB1 is electrically connected to the terminal INP, and the other of the two pairs of terminals of the switch SWB2 is electrically connected to the terminal INN.
  • the other of the two pairs of terminals of each of the switches SWB3 to SWB6 is electrically connected to the wiring CREF.
  • Each control terminal of the switch SWB1 and the switch SWB2 is electrically connected to the wiring STB.
  • the control terminals of the switches SWB3 to SWB6 are electrically connected to the wiring ST.
  • the switches SWB1 to SWB6 can be n-channel transistors.
  • the control terminals of the switches SWB1 to SWB6 are gates of the transistors.
  • the wiring CREF is a wiring for supplying a comparison potential to the comparator CMP. Therefore, although not illustrated in FIG. 5C, the comparison potential supplied to the wiring CREF can be a potential supplied to the terminal INN. Note that the comparison potential applied to the wiring CREF may be a potential applied to the terminal INP depending on the configuration of the activation function circuit ACTV.
  • the differential amplifier DIAa and the differential amplifier DIAb When the differential amplifier DIAa and the differential amplifier DIAb are unipolar circuits, the differential amplifier DIAa and the differential amplifier DIAb can be the circuit shown in FIG.
  • the differential amplifier DIAa and the differential amplifier DIAb illustrated in FIG. 6A include transistors A1 to A10 that are n-channel transistors, and capacitors B1 to B4.
  • the differential amplifier DIAa and the differential amplifier DIAb have an inverting input terminal in, a non-inverting input terminal ip, and a non-inverting output terminal op.
  • the differential amplifier DIAa and the differential amplifier DIAb illustrated in FIG. 6A include a wiring VDDL, a wiring VSSL, a wiring VBCS, a wiring VBIS, a wiring SCO, a wiring SCOB, and a wiring ST. Electrically connected.
  • the transistors A1 to A10 are preferably OS transistors like the transistors Tr1 and Tr2. For the OS transistor, the description of the transistor Tr1 is referred to.
  • the transistors A1 to A10 may be Si transistors.
  • the wiring VDDL is a wiring for applying a high power supply potential to the differential amplifier DIAa and the differential amplifier DIAb
  • the wiring VSSL is a wiring for applying a low power supply potential to the differential amplifier DIAa and the differential amplifier DIAb.
  • the wiring VBCS is a wiring for applying a first constant potential to one of a gate of a predetermined transistor and two pairs of terminals of a predetermined capacitive element.
  • the wiring VBIS is a wiring for applying a second constant potential to one of a gate of a predetermined transistor and two pairs of terminals of a predetermined capacitor.
  • the wiring ST, the wiring SCO, and the wiring SCOB are wirings for applying a potential to the gate of a transistor used as a switching element, thereby switching between conduction and non-conduction of the transistor.
  • the transistors used as the switching element are a transistor A1, a transistor A3, a transistor A7, a transistor A8, and a transistor A9.
  • the circuit LAT samples and holds the potential input to the terminal ILP and the terminal ILN, a latch circuit, a circuit that retains the potential amplified by the latch circuit, and a buffer circuit for outputting the potential Have.
  • the circuit LAT can be a circuit illustrated in FIG.
  • a circuit LAT illustrated in FIG. 6B includes transistors A11 to A30 which are n-channel transistors, and capacitors B5 to B10.
  • the circuit LAT is electrically connected to the wiring VDDL, the wiring VSSL, the wiring VBCS, the wiring ST, the wiring STB, the wiring LT, the wiring LTB, and the wiring SH.
  • the transistors A11 to A30 are preferably OS transistors like the transistors Tr1 and Tr2. For the OS transistor, the description of the transistor Tr1 is referred to.
  • the transistors A11 to A30 may be Si transistors.
  • a high level potential is applied to the wiring ST, and a low level potential is applied to the wiring STB.
  • the switches SWB1 and SWB2 are turned off, and the switches SWB3 to SWB6 are turned on.
  • the differential amplifier DIAa and the differential amplifier DIAb illustrated in FIG. 6A the transistors A1 and A3 are turned on, the gates of the transistors A2 and A4, the capacitors B1 and B2, respectively.
  • a potential from the wiring VBCS is applied to one of the two pairs of electrodes. Further, in the circuit LAT illustrated in FIG.
  • the transistor A11 and the transistor A13 are turned on, and each of the gates of the transistor A12 and the transistor A14 and one of the two pairs of electrodes of the capacitor B5 and the capacitor B6 are connected.
  • a potential from the wiring VBCS is applied.
  • a high level potential is applied to the wiring SCO, and a high level potential is applied to the wiring SCOB. Accordingly, in the differential amplifier DIAa and the differential amplifier DIAb illustrated in FIG. 6A, the transistors A7 to A9 are turned on, and in particular, each of the gate of the transistor A10, the capacitive element B3, and the capacitive element B4. A potential from the wiring VBIS is applied to one of the pair of electrodes.
  • the comparison potential from the wiring CREF is applied to the non-inverting input terminal ip and the inverting input terminal in of each of the differential amplifier DIAa and the differential amplifier DIAb. Therefore, substantially the same potential is output from each of the non-inverting output terminal op and the inverting output terminal on of the differential amplifier DIAa.
  • the respective potentials at this time are defined as a first differential output potential and a second differential output potential. Similarly, substantially the same potential is output from each of the terminal op and the terminal on of the differential amplifier DIAb.
  • a high level potential is applied to each of the wiring LT and the wiring LTB. Accordingly, the transistors A15 to A18 are turned on, and the comparison potential from the wiring CREF is applied to one of the two pairs of electrodes of the capacitor B7 and the capacitor B8. Further, since the transistor A21 and the transistor A24 are turned on, the potentials of the first terminal and the second terminal of the transistor A21 are substantially equal. Note that since the low-level potential is applied to the wiring STB, the transistor A19 and the transistor A20 are off.
  • a low level potential is applied to the wiring ST, and a low level potential is applied to the wiring SCO.
  • the switches SWB3 to SWB6 are turned off.
  • the transistors A1, A3, and A9 are turned off, and in the circuit LAT in FIG. 6B, the transistors A11 and A13 are turned off. It becomes. Therefore, one potential of each of the two pairs of electrodes of the capacitive elements B1 to B6 is held.
  • a high level potential is applied to the wiring STB.
  • the respective potentials of the terminal INP and the terminal INN of the comparator CMP are input to the non-inverting input terminal ip and the inverting input terminal in of the differential amplifier DIAa.
  • a potential corresponding to the differential input is output from each of the non-inverting output terminal op and the inverting output terminal on of the differential amplifier DIAa.
  • a potential corresponding to each differential input is set as a third differential output potential and a fourth differential output potential.
  • the other potential of the two pairs of electrodes of the capacitive element CE1 is the third differential output potential.
  • the difference between the first differential output potential and the second differential output potential, and the other potential of the two pairs of electrodes of the capacitive element CE2 depends on the difference between the fourth differential output potential and the second differential output potential. fluctuate. For this reason, a potential changed from the comparison potential is input to each of the non-inverting input terminal ip and the inverting input terminal in of the differential amplifier DIAb, and from the non-inverting output terminal op and the inverting output terminal on of the differential amplifier DIAb. A differential output potential corresponding to the potential is output.
  • the differential output potential is input to the terminal ILP and the terminal ILN of the circuit LAT. Therefore, in the circuit LAT, the differential output potential is applied to one of the two pairs of electrodes of the capacitive element B7 and the capacitive element B8. Further, the low level potential is applied to the wiring LT at the timing when the high level potential is applied to the wiring STB. For this reason, the differential output potential is not applied to the first terminal and the second terminal of the transistor A21 via the transistor A17 and the transistor A18.
  • a high level potential is applied to the wiring LT and a low level potential is applied to the wiring LTB, whereby each of the capacitor B7 and the capacitor B8 is connected to each of the first terminal and the second terminal of the transistor A21.
  • the differential output potential held in one of the two pairs of electrodes is input.
  • the transistors A11 to A14, the transistors A22 to A24, the capacitor B5, and the capacitor B6 form a latch circuit. Accordingly, one of the differential output potentials input by the latch circuit changes to a high level potential, and the other changes to a low level potential.
  • the transistor A25 and the transistor A26 are turned on, and the high-level potential and the low-level potential that have fluctuated from each of the differential output potentials are connected to the capacitor B9. It is held on one of the two pairs of electrodes of the capacitive element B10.
  • the transistor A27 to the transistor A30 form a buffer circuit.
  • the high level potential is applied to the respective gates of the transistor A27 and the transistor A30 and the low level potential is applied to the respective gates of the transistor A28 and the transistor A29, the low level potential is output from the terminal OLP and the terminal OLN. Outputs a high level potential.
  • the high level potential is output from the terminal OLP.
  • a low level potential is output from the terminal OLN. Note that the high-level potential and the low-level potential input to the gates of the transistors A27 to A30 may be different from the high-level potential and the low-level potential output from the terminal OLP and the terminal OLN.
  • a low level potential is applied to the wiring SH to turn off the transistor A25 and the transistor A26, whereby the high level potential and the low level potential output from the latch circuit are changed to the capacitive element B9 and the capacitive element. It can be held on one of each of the two pairs of electrodes of B10. Thus, the input potential to the buffer circuit is held, so that the contents of the latch circuit can be initialized.
  • the unipolar circuit comparator CMP shown in FIGS. 5C and 6A and 6B can be applied.
  • an n-channel transistor is used, but a p-channel transistor is used instead, and each of the circuits shown in FIGS. 6A and 6B is used.
  • the configuration of the circuit diagram may be changed.
  • the polarity of all transistors included in the comparator CMP, the constant voltage source VC1, and the constant voltage source VC2 shown in FIG. 5A can be configured as a unipolar circuit.
  • the polarity of all the transistors included in the comparator CMP and the constant voltage source VC3 shown in FIG. 5B can be n-channel type, the activation function circuit ACTV shown in FIG. It can be configured as a polarity circuit.
  • the structure of the activation function circuit ACTV included in the arithmetic circuit 100 is not limited to the structure illustrated in FIGS.
  • the configuration of the activation function circuit ACTV included in the arithmetic circuit 100 can be changed as appropriate according to the content to be calculated.
  • the arithmetic circuit 100 may have a plurality of activation function circuits ACTV having different circuit configurations, and may select one desired circuit from the plurality of activation function circuits ACTV and perform an operation.
  • the learning circuit LEC is a circuit for updating the first data held in the memory cell AM.
  • the update amount of the first data is ⁇ w
  • ⁇ w can be expressed by the following equation (A1).
  • ⁇ is a constant representing the learning rate, and is a real number between 0 and 1.
  • the numerical value of the learning rate ⁇ is increased, the update amount per one time is increased, but the first data and the operation result data may be diverged by repeating the update.
  • the numerical value of the learning rate ⁇ is small, the first data and the calculation result data are likely to converge, but the number of updates necessary for convergence is increased.
  • the learning circuit LEC is a circuit that calculates the update amount ⁇ w by giving the first data w, the second data x, the teacher data t, and the calculation result data y.
  • the learning circuit LEC includes a terminal gi1, a terminal gi2 [1], a terminal gi2 [2], a terminal gi3, a terminal gi4, a terminal io [1], and a terminal io [2].
  • a terminal gi1 a terminal gi2 [1]
  • a terminal gi2 [2] a terminal gi3
  • a terminal gi4 a terminal io [1]
  • a terminal io [2] a terminal io [2].
  • the terminal gi1 is electrically connected to the wiring XL
  • the terminal gi2 [1] is electrically connected to the wiring VL [1]
  • the terminal gi2 [2] is electrically connected to the wiring VL [2].
  • the terminal gi3 is electrically connected to the wiring TL
  • the terminal gi4 is electrically connected to the terminal afb.
  • terminal io [1] is electrically connected to the wiring HW [1]
  • terminal io [2] is electrically connected to the wiring HW [2].
  • the wiring XL is a wiring for inputting input data to the learning circuit LEC
  • the wiring TL is a wiring for inputting teacher data to the learning circuit LEC.
  • the input data here is handled as reference data to be compared with the second data x.
  • the second data output from the circuit VLD is input to the terminal gi [1] via the wiring VL [1]. Similarly, the second data output from the circuit VLD is input to the terminal gi [2] through the wiring VL [2].
  • the learning circuit LEC receives the second data from the wiring VL [1], thereby inputting the second data, the input data input from the wiring XL, the teacher data input from the wiring TL, and the terminal gi4.
  • the update amount of the first data is generated using the operation result data and transmitted to the wiring HW [1].
  • the learning circuit LEC receives the second data from the wiring VL [2], thereby receiving the second data, the input data input from the wiring XL, the teacher data input from the wiring TL, and the terminal gi4.
  • An update amount of the first data is generated using the input calculation result data and transmitted to the wiring HW [2].
  • FIG. 7 shows a configuration example of the learning circuit LEC.
  • the learning circuit LEC shown in FIG. 7 includes an addition circuit ADA [1], an addition circuit ADA [2], an addition circuit ADB [1], an addition circuit ADB [2], a multiplication circuit MLT [1], and multiplication.
  • a circuit MLT [2], an integration circuit ITG [1], and an integration circuit ITG [2] are included.
  • Each of the integration circuit ITG [1] and the integration circuit ITG [2] has a terminal ii.
  • the output terminal of the multiplication circuit MLT [1] is electrically connected to the terminal ii of the integration circuit ITG [1]
  • the output terminal of the multiplication circuit MLT [1] is electrically connected to the terminal ii of the integration circuit ITG [2]. It is connected to the.
  • the adder circuit ADA [1] has a function of calculating a difference between the data input to the terminal gi1 and the data input to the terminal gi2 [1]. That is, the adder circuit ADA [1], to generate the input data x 0, which is input to the terminal gi1, a second data x that is input to the terminal GI2 [1], the data x 0 -x from. Further, the generated data x 0 -x is input to the multiplier circuit MLT [1].
  • the addition circuit ADB [1] has a function of taking a difference between the data input to the terminal gi3 and the data input to the terminal gi4. That is, the adder circuit ADB [1] generates data ty from the teacher data t input to the terminal gi3 and the operation result data y input to the terminal gi4. The generated data ty is input to the multiplication circuit MLT [1].
  • the multiplication circuit MLT [1] has a function of generating a product of data x 0 -x and data ty generated by the addition circuit ADA [1] and the addition circuit ADB [1], respectively. As a result, data ⁇ w is generated. The generated ⁇ w is input to the terminal ii of the integration circuit ITG [1].
  • the learning rate ⁇ can be applied to the product of the data x 0 -x and the data ty by adjusting the resistance value of the resistance element.
  • the method of operation of the learning rate ⁇ is not limited to the above.
  • ⁇ may be added to the calculation as an integration coefficient of the integration circuit ITG [1].
  • the learning rate ⁇ can be applied by adjusting the capacitance value of the capacitive element included in the integration circuit ITG [1].
  • the addition circuit ADA [1], the addition circuit ADB [1], and the multiplication circuit MLT [1] can calculate two sets of products by taking the difference between the two inputs as one set. For this reason, for example, a multiplication circuit called a Gilbert cell can be applied as the addition circuit ADA [1], the addition circuit ADB [1], and the multiplication circuit MLT [1].
  • the integration circuit ITG [1] is a circuit that outputs the sum of the input data ⁇ w and the total value of the update amounts input so far as update data ⁇ w.
  • the learning circuit LEC calculates the update amount ⁇ w by the addition circuit ADA [1], the addition circuit ADB [1], and the multiplication circuit MLT [1]. Then, the update data ⁇ w is generated by the integration circuit IGT [1] using the update amount ⁇ w and the total value of the update amounts calculated for each update until the previous time.
  • the output terminal of the integration circuit IGT [1] is electrically connected to the terminal io [1]. Since the terminal io [1] is electrically connected to the wiring HW [1], a potential V ⁇ w corresponding to the update data ⁇ w output from the integration circuit IGT [1] is applied to the wiring HW [1]. Is done.
  • the learning circuit LEC includes the adder circuit ADA [1], the adder circuit ADB [1], the multiplier circuit MLT [1], and the integrator circuit ITG [1].
  • the first data of the cell AM is updated, and the memory cell in the second row of the memory cell array MCA is updated by the addition circuit ADA [2], the addition circuit ADB [2], the multiplication circuit MLT [2], and the integration circuit ITG [2].
  • the first data of AM is updated. Therefore, when the memory cell array MCA has a configuration of three or more rows, an adder circuit, a multiplier circuit, a low-pass filter, and an integrator circuit may be provided in the learning circuit LEC as necessary.
  • the learning circuit LEC can be configured as a unipolar circuit having only n-channel transistors.
  • FIG. 8A illustrates the addition circuit ADA [1], the addition circuit ADB [1], the multiplication circuit MLT [1] (the addition circuit ADA [2], the addition circuit ADB [2], and the multiplication circuit MLT illustrated in FIG. It is the circuit diagram which showed the structural example of the Gilbert cell applicable to [2]).
  • an adder circuit ADA [1] an adder circuit ADB [1]
  • a multiplier circuit MLT [1] adder circuit ADA [2], adder circuit ADB [2], multiplier The circuit MLT [2]
  • the Gilbert cell of FIG. 8A is provided with chopper circuits CC1 to CC3 for two input differentials and output differentials, respectively.
  • Each of the chopper circuit CC1 to the chopper circuit CC3 includes a terminal cp1 to a terminal cp4, makes a conductive state between the terminal cp1 and one of the terminal cp3 or the terminal cp4, and the terminal cp2 and the terminal cp3 or It functions as a circuit that brings the other terminal cp4 into a conductive state.
  • FIG. 8B is a circuit diagram illustrating a configuration example of the chopper circuit CC that can be applied to the chopper circuits CC1 to CC3.
  • the Gilbert cell in FIG. 8A includes transistors Tr11 to Tr19.
  • the transistors Tr11 and Tr12 function as a first differential pair
  • the transistors Tr13 and Tr14 function as a second differential pair
  • the transistors Tr15 and Tr16 function as a third differential pair.
  • the transistors Tr11 to Tr19 are n-channel transistors.
  • the transistors Tr11 to Tr19 are preferably OS transistors, like the transistors Tr1 and Tr2.
  • OS transistor the description of the transistor Tr1 is referred to.
  • the transistors Tr11 to Tr19 may be Si transistors.
  • a first differential pair, via a chopper circuit CC1, the input data x 0, and the second data is input to the second differential pair, via a chopper circuit CC1, the input data x 0 and a Two data are input, and teacher data t and calculation result data y are input to the third differential pair via the chopper circuit CC2.
  • the terminal cp1 of the chopper circuit CC1 is electrically connected to the terminal gi1
  • the terminal cp2 of the chopper circuit CC1 is electrically connected to the terminal gi2 [1] (terminal gi2 [2])
  • the terminal cp1 of the chopper circuit CC2 Is electrically connected to the terminal gi3
  • the terminal cp2 of the chopper circuit CC2 is electrically connected to the terminal gi4.
  • the output of the Gilbert cell in FIG. 8A becomes the voltage of the terminal cp3 and the terminal cp4 of the chopper circuit CC3, and the difference voltage between the terminal cp3 and the terminal cp4 becomes a value corresponding to the result of addition and multiplication.
  • the first terminals of the transistors Tr17 and Tr18 are electrically connected to the wiring VDDL, and the gates of the transistors Tr17 and Tr18 are electrically connected to the wiring VGCR.
  • the transistor Tr17 and the transistor Tr18 function as a current source for inputting a current to the Gilbert cell.
  • the first terminal of the transistor Tr19 is electrically connected to the wiring VGCB, and the first terminal of the transistor Tr19 is electrically connected to the wiring GNDL.
  • the transistor Tr19 has a role of sucking current from the Gilbert cell.
  • the chopper circuit CC illustrated in FIG. 8B includes transistors Tr21 to Tr24 and terminals cp1 to cp4.
  • the wiring CLKL is a wiring for transmitting a clock signal
  • the wiring CLKLB is a wiring for transmitting an inverted signal of the clock signal sent to the wiring CLKL.
  • the transistors Tr21 to Tr24 are n-channel transistors.
  • the transistors Tr21 to Tr24 are preferably OS transistors, like the transistors Tr1 and Tr2.
  • OS transistor the description of the transistor Tr1 is referred to.
  • the transistors Tr21 to Tr24 may be Si transistors.
  • the potential of the wiring CLKL is switched between the high level potential and the low level potential at high speed, so that the offset cancellation can be performed for the error caused by the differential pair of the Gilbert cell.
  • the Gilbert cell of FIG. 8A and the chopper circuit of FIG. 8B do not have a p-channel transistor but only an n-channel transistor, the Gilbert cell of FIG.
  • the chopper circuit in FIG. 8B can be configured as a unipolar circuit.
  • FIG. 9A is a diagram showing an example of a circuit configuration applicable to the integration circuit ITG [1] (integration circuit ITG [2]) shown in FIG.
  • the integration circuit illustrated in FIG. 9A includes transistors Tr26 to Tr29, a capacitor CL1, a capacitor CL2, and a fully differential amplifier FDA. Note that in the integration circuit ITG [1] (integration circuit ITG [2]) illustrated in FIG. 9, the transistors Tr26 to Tr29 are n-channel transistors.
  • the transistors Tr26 to Tr29 are preferably OS transistors, like the transistors Tr1 and Tr2.
  • OS transistor the description of the transistor Tr1 is referred to.
  • the transistors Tr26 to Tr29 may be Si transistors.
  • the non-inverting input terminal of the fully differential amplifier FDA is electrically connected to the input terminal nt1, the first terminal of the transistor Tr28, and the capacitive element CL1, and the inverting input terminal of the fully differential amplifier FDA is the input terminal. It is electrically connected to nt2, the first terminal of the transistor Tr29, and the capacitor CL2.
  • the inverting output terminal of the fully differential amplifier FDA is electrically connected to the output terminal st1, the first terminal of the transistor Tr26, and the second terminal of the transistor Tr28, and the non-inverting output terminal of the fully differential amplifier FDA is The output terminal st2, the first terminal of the transistor Tr27, and the second terminal of the transistor Tr29 are electrically connected.
  • the second terminal of the capacitor CL1 is electrically connected to the first terminal of the transistor Tr27, and the second terminal of the capacitor CL2 is electrically connected to the second terminal of the transistor Tr27.
  • the output common-mode voltage input terminal is electrically connected to a wiring to which a ground potential is applied.
  • the gates of the transistors Tr26 and Tr27 are electrically connected to the wiring STL, and the gates of the transistors Tr28 and Tr29 are electrically connected to the wiring RSTL.
  • the integration circuit shown in FIG. 9A can be driven by applying a low level potential to the wiring RSTL and applying a high level potential to the wiring STL.
  • Each of the transistor Tr26 and the transistor Tr27 holds a potential at each of the second terminal of the capacitor CL1 and the second terminal of the capacitor CL2 when a high-level potential is applied to the wiring STL.
  • the potential held in each of the second terminal of the capacitor CL1 and the second terminal of the capacitor CL2 can be reset by applying a high-level potential to the wiring RSTL and a low-level potential to the wiring STL.
  • FIG. 9B shows a configuration example of the fully differential amplifier FDA. Note that in FIG. 9B, only circuits, circuit elements, wirings, and the like necessary for explanation are denoted by reference numerals.
  • the fully differential amplifier FDA in FIG. 9B includes a circuit CIRA, a circuit CIRB, and a circuit CIRC.
  • the fully differential amplifier FDA includes a terminal inn corresponding to an inverting input terminal, a terminal inp corresponding to a non-inverting input terminal, a terminal outn corresponding to an inverting output terminal, and a terminal outp corresponding to a non-inverting output terminal.
  • 9B includes a wiring VDDL, a wiring VSSL, a wiring VBCS, a wiring VBIS, a wiring VCOM, a wiring COMI, a wiring COMO, a wiring SCO, a wiring SCOB, and a wiring. Is electrically connected to the SET.
  • the wiring VDDL is a wiring for applying a high power supply potential to the fully differential amplifier FDA
  • the wiring VSSL is a wiring for applying a low power supply potential to the fully differential amplifier FDA.
  • the wiring VBCS is a wiring for applying a first constant potential to one of a gate of a predetermined transistor and two pairs of terminals of a predetermined capacitive element.
  • the wiring VBIS is a wiring for applying a second constant potential to one of a gate of a predetermined transistor and two pairs of terminals of a predetermined capacitor.
  • the wiring VCOM is a wiring corresponding to the output common-mode voltage input terminal of the fully differential amplifier FDA. As shown in FIG. 9A, the output common-mode voltage input terminal is electrically connected to the wiring GNDL that provides the ground potential, so that the wiring VCOM becomes the ground potential.
  • the wiring COMO is a wiring for outputting an intermediate potential of the differential output
  • the wiring COMI is a wiring for inputting the intermediate potential
  • the first constant potential is applied to one of the two pairs of terminals of the gates of the transistors X1 to X4 and the capacitive elements Y1 to Y4 by the wiring VBCS. Therefore, a current corresponding to the first constant potential flows from the wiring VDDL between the sources and drains of the transistors X1 to X4. After that, by applying a low level potential to the wiring SET, the first constant potential can be held in each of the capacitor elements Y1 to Y4.
  • the wiring SET when a high level potential is applied to the wiring SET, one of two pairs of terminals of the gates of the transistors X5 and X6 and the capacitors Y5 and Y6 for sucking current into the wiring VSSL of the circuit CIRC.
  • the second constant potential is applied from the wiring VBIS. Thereby, the transistors X5 and X6 suck the current corresponding to the second constant potential into the wiring VSSL. After that, by applying a low level potential to the wiring SET, the second constant potential can be held in the capacitive elements Y5 and Y6.
  • a high power supply potential is always applied to the gates of the transistors X7 and X8 for supplying current from the wiring VDDL, and the gate of the transistor X9 for discharging current to the wiring VSSL is always the first. 2 constant potential is applied.
  • the second terminal from the wiring VBIS is connected to one of the two terminals of the gate of the transistor X10 and the capacitor Y10 in the circuit CIRA for discharging current to the wiring VSSL.
  • a constant potential is applied.
  • the transistor X10 discharges a current corresponding to the second constant potential to the wiring VSSL.
  • the second constant potential is held in the capacitor Y10. Note that an inversion signal of a signal input to the wiring SCO is input to the wiring SCOB.
  • the circuit CIRA outputs a first output potential from the node NT1 as a differential output in accordance with each input potential, and from the node NT2.
  • a second output potential is output.
  • the potentials of the gates of the transistors X5 and X6 for discharging current to the wiring VSSL vary according to the first output potential and the second output potential due to capacitive coupling of the capacitive elements Y5 and Y6.
  • the circuit CIRC outputs the output potential of the fully differential amplifier FDA from the terminal outp and the terminal outn.
  • the wiring SCO since the wiring SCO has a low level potential, the wiring SCOB has a high level potential. Accordingly, the wiring COMO outputs an intermediate potential between the potential of the terminal outp and the potential of the terminal outn. Therefore, the intermediate potential is input to the wiring COMI.
  • the circuit CIRB outputs the third output potential from the node NT3 by the differential input of the ground potential of the wiring VCOM and the intermediate potential of the wiring COMI.
  • the potential of the gate of the transistor X10 for discharging current to the wiring VSSL varies according to the second output potential due to capacitive coupling of the capacitive element Y10.
  • the amount of current flowing through the transistor X10 changes. That is, common mode feedback in the fully differential amplifier FDA can be performed by the circuit CIRB generating the second output potential in response to the input of the intermediate potential from the wiring COMI and applying the second output potential to the circuit CIRA.
  • the fully differential amplifier FDA shown in FIG. 9B includes transistors X1 to X10 which are n-channel transistors.
  • a transistor without a reference sign is also an n-channel transistor. Therefore, the fully differential amplifier FDA shown in FIG. 9B is configured as a unipolar circuit. It is preferable that all the transistors included in the fully differential amplifier FDA are OS transistors like the transistors Tr1 and Tr2. For the OS transistor, the description of the transistor Tr1 is referred to. All or some of the transistors included in the fully differential amplifier FDA may be Si transistors.
  • the learning circuit LEC can be configured as a unipolar circuit using only n-channel transistors.
  • the current supply circuit IS of the arithmetic circuit 100 dealt with in the description of this operation example has the configuration shown in FIG.
  • the current supply circuit IS shown in FIG. 10 has a configuration in which the terminal d1 and the terminal d2 of the circuit CS1 are combined into the terminal d and the circuit CSx and the circuit CSw are excluded from the current supply circuit IS shown in FIG. It has become. Therefore, in the current supply circuit IS in FIG. 3A, the wiring OL [1] and the wiring OL [2] are combined as the wiring OL, and the current Id1 and the current Id2 are set as the current I d as the current flowing from the terminal d of the circuit CS1. The current is sucked out by the circuit CMx and the circuit CMw with respect to the current flowing through the wiring OL.
  • the arithmetic circuit 100 and acquires the operation result data from the change amount of the current I alpha, operation will be described for the update of the first data. Therefore, in this operation example, the activation function circuit ACTV is described by applying the activation function circuit ACTV shown in FIG.
  • FIG. 11 shows a timing chart of an operation example of the arithmetic circuit 100.
  • the timing chart in FIG. 11 illustrates the wiring WL [1], the wiring WL [2], the wiring WD, the wiring WDxr, the wiring WDwr, the node NM (AM [1]), and the node NM (AM [2] from time T01 to time T10.
  • a high level potential (indicated as High in FIG. 11) is applied to the wiring WL [1], and a low level potential (Low in FIG. 11) is applied to the wiring WL [2]. Is applied).
  • a potential V PR ⁇ V W [1] larger than the ground potential (indicated as GND in FIG. 11) is applied to the wiring WD, and a potential V PR larger than the ground potential is applied to the wiring WDxr.
  • a potential V PR ⁇ V W [1] larger than the ground potential is applied to the wiring WDwr.
  • each of the wiring VL [1], the wiring VL [2], the wiring HW [1], and the wiring HW [2] is referred to as a reference potential (referred to as REFP in FIG. 11. May be described as a potential).
  • the potential V W [1] is a potential corresponding to one of the plurality of first data.
  • the potential VPR is a potential corresponding to the reference data.
  • V th is the threshold voltage of the transistor Tr2.
  • IAMxr [1] When the current flowing from the wiring BLxr to the first terminal via the second terminal of the transistor Tr2 of the memory cell AMxr [1] is IAMxr [1], 0 , IAMxr [1], 0 is It can be expressed by a formula.
  • IAMwr [1] when the current flowing from the wiring BLwr to the first terminal via the second terminal of the transistor Tr2 of the memory cell AMwr [1] is IAMwr [1], 0 , IAMwr [1], 0 is It can be expressed by the following formula.
  • the low-level potential is continuously applied to the wiring WL [2] from before time T02. For this reason, the transistors Tr1 of the memory cell AM [2], the memory cell AMxr [2], and the memory cell AMwr [2] are in the off state before time T02.
  • an OS transistor to each transistor Tr1 of the memory cell AMwr [2] a leakage current flowing between the first terminal and the second terminal of the transistor Tr1 can be reduced. Can be held for a long time.
  • the ground potential is applied to the wiring WD, the wiring WDxr, and the wiring WDwr.
  • the transistors Tr1 of the memory cell AM [1], the memory cell AM [2], the memory cell AMxr [1], the memory cell AMxr [2], the memory cell AMwr [2], and the memory cell AMwr [2] Since the conductive state is established, application of potentials from the wiring WD, the wiring WDxr, and the wiring WDwr causes the memory cell AM [1], the memory cell AM [2], the memory cell AMxr [1], and the memory cell AMxr [2 ], The potential held in the respective nodes of the memory cell AMwr [2] and the memory cell AMwr [2] is not rewritten.
  • the potential V w [2] is a potential corresponding to one of a plurality of first data different from the potential V w [1] .
  • the memory cell AM [2] since the high level potential is applied to the gates of the transistors Tr1 of the memory cell AM [2], the memory cell AMxr [2], and the memory cell AMwr [2], the memory cell AM [2], the memory cell Each transistor Tr1 of AMxr [2] and the memory cell AMwr [2] is turned on. Therefore, in the memory cell AM [2], the wiring WD and the node NM (AM [2]) are in a conductive state, so that the potential of the node NM (AM [2]) is V PR ⁇ V W [2 ] .
  • the potential of the wiring WDxr and node NM (AMxr [2]) between the for is turned on, the node NM (AM [2]) is a V PR.
  • the potential of the node NM (AMwr [2]) is V PR ⁇ V W [2 ] .
  • a current flowing from the second terminal of the transistor Tr2 to the first terminal of each of the memory cell AM [2], the memory cell AMxr [2], and the memory cell AMwr [2] is considered.
  • the current flowing from the wiring BL to the first terminal through the second terminal of the transistor Tr2 of the memory cell AM [2] is IAM [2], 0 , IAM [2], 0 is expressed by the following equation: be able to.
  • IAMxr [2] When the current flowing from the wiring BLxr to the first terminal through the second terminal of the transistor Tr2 of the memory cell AMxr [2] is IAMxr [2], 0 , IAMxr [2], 0 is It can be expressed by a formula.
  • a current from the terminal coxr of the current supply circuit IS is supplied to the wiring BLxr.
  • the current can be described using a constant current I dx supplied from the circuit CS1 and a current drawn into the circuit CMx inside the current supply circuit IS.
  • ICMx ICMx , 0
  • the following equation is established according to Kirchhoff's law.
  • the wiring BLwr is supplied with current from the terminal cow of the current supply circuit IS.
  • the current can be described using the constant current I dw supplied from the circuit CS1 and the current drawn into the circuit CMw in the current supply circuit IS.
  • I CMw I CMw, 0
  • the following equation is established according to Kirchhoff's law.
  • the current from the terminal co of the current supply circuit IS is supplied to the wiring BL.
  • the current inside the current supply circuit IS can be described using a constant current I d supplied from the circuit CS1, a current wicked respective circuits CMx and circuit CMw, the.
  • I d supplied from the circuit CS1
  • CMx current wicked respective circuits CMx and circuit CMw
  • the relationship between the current flowing through the wiring OL and the wiring BL can be expressed by the following equation according to Kirchhoff's law.
  • V x [1] is a potential corresponding to one of the plurality of second data.
  • the increase in the potential of the gate of the transistor Tr2 is a potential obtained by multiplying the potential change of the wiring VL [1] by a capacitive coupling coefficient determined by the capacitor C1 and its peripheral circuit configuration.
  • the capacitive coupling coefficient can be calculated from the capacitance of the capacitive element C1, the capacitance of the capacitive element C2, the gate capacitance of the transistor Tr2, a parasitic capacitance, and the like.
  • the capacitive coupling coefficient by the capacitive element C1 is A C1 .
  • the potential V X [1] is applied to the second terminal of each of the capacitive elements C1 of the memory cell AM [1] and the memory cell AMxr [1], whereby the node The potentials of NM (AM [1]) and node NM (AMxr [1]) are increased by A C1 V X [1] , respectively.
  • IAMxr [1], 1 IAMxr [1], 1 is It can be expressed by a formula.
  • the current flowing from the wiring BLxr to the first terminal through the second terminal of the transistor Tr2 of the memory cell AMxr [1] is I AMxr [ 1], 1 ⁇ I AMxr [1], 0 ( indicated as ⁇ I AMxr [1] in FIG. 11).
  • a current from the terminal coxr of the current supply circuit IS is supplied to the wiring BLxr.
  • the current can be described using a constant current I dx supplied from the circuit CS1 and a current drawn into the circuit CMx inside the current supply circuit IS.
  • I CMx I CMx, 1
  • the following equation is established according to Kirchhoff's law.
  • a current from a terminal co of the current supply circuit IS is supplied to the wiring BL.
  • the current inside the current supply circuit IS can be described using a constant current I d supplied from the circuit CS1, a current wicked respective circuits CMx and circuit CMw, the.
  • I d supplied from the circuit CS1
  • CMx current wicked respective circuits CMx and circuit CMw
  • the relationship between the current flowing through the wiring OL and the wiring BL can be expressed by the following equation according to Kirchhoff's law.
  • ⁇ I ⁇ is referred to as a first differential current in the arithmetic circuit 100.
  • the first differential current ⁇ I ⁇ can be expressed as in the following equation using equations (B1) to (B13).
  • the potential V x [2] is a potential corresponding to one of a plurality of second data different from the potential V x [1] .
  • the memory cell AM [2] and the same applies to the change in the potential level of the storage node of the memory cell AMxr [2], explaining the capacitive coupling coefficients of each memory cell as A C1. Since the capacitive coupling coefficient is A C1 , the potential V X [2] is applied to the second terminals of the respective capacitive elements C1 of the memory cell AM [2] and the memory cell AMxr [2], whereby the node The potentials of NM (AM [2]) and node NM (AMxr [2]) are increased by A C1 V X [2] , respectively.
  • the current flowing from the wiring BL to the first terminal through the second terminal of the transistor Tr2 of the memory cell AM [2] is I AM [ 2], 1 ⁇ I AM [2], 0 (indicated as ⁇ I AM [2] in FIG. 11).
  • IAMxr [2] when the current flowing from the wiring BLxr to the first terminal via the second terminal of the transistor Tr2 of the memory cell AMxr [2] is IAMxr [2], 1 , IAMxr [2], 1 is It can be expressed by a formula.
  • the current flowing from the wiring BLxr to the first terminal through the second terminal of the transistor Tr2 of the memory cell AMxr [2] is I AMxr [ 2], 1 ⁇ I AMxr [2], 0 ( indicated as ⁇ I AMxr [2] in FIG. 11).
  • a current from the terminal coxr of the current supply circuit IS is supplied to the wiring BLxr.
  • the current can be described using a constant current I dx supplied from the circuit CS1 and a current drawn into the circuit CMx inside the current supply circuit IS.
  • ICMx constant current supplied from the circuit CS1
  • CMx current drawn into the circuit CMx inside the current supply circuit IS.
  • a current from a terminal co of the current supply circuit IS is supplied to the wiring BL.
  • the current inside the current supply circuit IS can be described using a constant current I d supplied from the circuit CS1, a current draft to the respective circuits CMx and circuit CMw, the.
  • I d supplied from the circuit CS1
  • CMx circuits CMx and circuit CMw
  • the relationship between the current flowing through the wiring OL and the wiring BL can be expressed by the following equation according to Kirchhoff's law. it can.
  • the first differential current ⁇ I ⁇ that is the difference between the two can be expressed as the following equation using equations (B1) to (B11) and equations (B15) to (E18).
  • VW [1] is applied to the wiring VL [1] from time T05 to time T06
  • VW [2] is applied to the wiring VL [2] from time T06 to time T07.
  • the potential applied to the wiring VL [1] and the wiring VL [2] may be lower than the reference potential REFP.
  • REFP a potential lower than the reference potential REFP
  • the potential of the holding node can be lowered by capacitive coupling.
  • the product of the first data and one of the second data having a negative value can be performed.
  • the wiring VL [2] the case of applying -V W [2] rather than V W [2]
  • the first differential current [Delta] I alpha following equation Can be expressed as
  • the memory cell array MCA having memory cells arranged in a matrix of 2 rows and 3 columns has been dealt with, but the same operation is performed for a memory cell array of 3 rows or more and 4 columns or more. be able to.
  • the arithmetic processing for the plurality of columns can be performed simultaneously. That is, by increasing the number of columns in the memory cell array, a semiconductor device that realizes high-speed arithmetic processing can be provided. Further, by increasing the number of rows, the number of terms to be added in the product-sum operation can be increased.
  • the first differential current ⁇ I ⁇ when the number of rows is increased can be expressed by the following equation.
  • the learning circuit LEC terminal gi1 input data x 0 is inputted
  • V X [1] is input as a plurality of second data to the terminal GI2 [1] of the learning circuit LEC
  • learning V X [2] is input as one of the plurality of second data to the terminal gi2 [2] of the circuit LEC
  • teacher data is input to the terminal gi3 of the learning circuit LEC.
  • the capacitor is connected via the terminal m5.
  • the potential ⁇ V ⁇ W [1] is applied to the second terminal of the element C2.
  • the potentials of the gates of the transistors Tr2 of the memory cell AM [1] and the memory cell AMwr [1] drop.
  • the wiring HW [1] is not electrically connected to the memory cell AMxr [1]
  • the gate of the transistor Tr2 in the memory cell AMxr [1] even when the potential of the wiring HW [1] changes. The potential of does not rise.
  • the increase in the potential of the gate of the transistor Tr2 is a potential obtained by multiplying the potential change of the wiring HW [1] by a capacitive coupling coefficient determined by the capacitor C2 and its peripheral circuit configuration.
  • the capacitive coupling coefficient can be calculated from the capacitance of the capacitive element C1, the capacitance of the capacitive element C2, the gate capacitance of the transistor Tr2, a parasitic capacitance, and the like. In this operation example, the capacitive coupling coefficient due to the capacitive element C2 as A C2, is described.
  • the capacitive coupling coefficient is A C2
  • the potential ⁇ V ⁇ W [1] is applied to the second terminals of the capacitive elements C2 of the memory cell AM [1] and the memory cell AMwr [1].
  • the potentials of the node NM (AM [1]) and the node NM (AMwr [1]) are decreased by A C2 V ⁇ W [1] , respectively.
  • the potential ⁇ V ⁇ W [ according to the update amount of the first data (potential V W [1] ) output from the terminal io [1] of the learning circuit LEC due to the capacitive coupling of the capacitive element C2 . 1] cannot be added to the respective potentials of the node NM (AM [1]) and the node NM (AMwr [1]) as they are. Therefore, the potential corresponding to the update amount of the first data (potential V W [1] ) output from the terminal io [1] of the learning circuit LEC is a potential that cancels the influence of capacitive coupling of the capacitive element C2.
  • IAMwr [1], 3 IAMwr [1], 3 is It can be expressed by a formula.
  • the current flowing from the wiring BLwr to the first terminal via the second terminal of the transistor Tr2 of the memory cell AMwr [1] is I AMxr [1], 0 ⁇ I AMxr [1], 3 (in FIG. 11, expressed as ⁇ I AMxr [1], ⁇ W ).
  • the wiring BLwr is supplied with current from the terminal cow of the current supply circuit IS.
  • the current can be in the internal current supply circuit IS, describes using a constant current I wx supplied from circuit CS1, a current that is wicked circuit CMw, the.
  • ICMw constant current supplied from circuit CS1
  • CMw wicked circuit
  • a current from a terminal co of the current supply circuit IS is supplied to the wiring BL.
  • the current inside the current supply circuit IS can be described using a constant current I d supplied from the circuit CS1, a current draft to the respective circuits CMx and circuit CMw, the.
  • I d supplied from the circuit CS1
  • CMx circuits CMx and circuit CMw
  • the relationship between the current flowing through the wiring OL and the wiring BL can be expressed by the following equation according to Kirchhoff's law.
  • ⁇ I ⁇ is referred to as a second differential current in the arithmetic circuit 100.
  • the second differential current ⁇ I ⁇ is expressed by the following equation using Equations (B1) to (B9), Equation (B11), Equations (B15) to (B17), and Equations (B22) to (B25). Can be expressed as follows.
  • the capacitor is connected via the terminal m5.
  • the potential ⁇ V ⁇ W [2] is applied to the second terminal of the element C2. Accordingly, the gate potentials of the transistors Tr2 of the memory cell AM [2] and the memory cell AMwr [2] are lowered. Note that since the wiring HW [2] is not electrically connected to the memory cell AMxr [2], the gate of the transistor Tr2 in the memory cell AMxr [2] even if the potential of the wiring HW [2] changes. The potential of does not rise.
  • the capacitive coupling coefficient is A C2
  • the potential ⁇ V ⁇ W [2] is applied to the second terminal of each of the capacitive elements C2 of the memory cell AM [2] and the memory cell AMwr [2].
  • the potentials of the node NM (AM [2]) and the node NM (AMwr [2]) are decreased by A C2 V ⁇ W [2] , respectively.
  • the current flowing from the wiring BL to the first terminal via the second terminal of the transistor Tr2 of the memory cell AM [2] is I AM [2], 1 ⁇ I AM [2], 3 (in FIG. 11, expressed as ⁇ I AM [2], ⁇ W ).
  • IAMwr [2] when the current flowing from the wiring BLwr to the first terminal via the second terminal of the transistor Tr2 of the memory cell AMwr [2] is IAMwr [2], 3 , IAMwr [2], 3 is It can be expressed by a formula.
  • the current flowing from the wiring BLwr to the first terminal via the second terminal of the transistor Tr2 of the memory cell AMwr [2] is I AMxr [2], 0 ⁇ I AMxr [2], 3 (in FIG. 11, expressed as ⁇ I AMxr [2], ⁇ W ).
  • the wiring BLwr is supplied with current from the terminal cow of the current supply circuit IS.
  • the current can be in the internal current supply circuit IS, describes using a constant current I wx supplied from circuit CS1, a current that is wicked circuit CMw, the.
  • I wx supplied from circuit CS1
  • CMw wicked circuit
  • a current from a terminal co of the current supply circuit IS is supplied to the wiring BL.
  • the current inside the current supply circuit IS can be described using a constant current I d supplied from the circuit CS1, a current draft to the respective circuits CMx and circuit CMw, the.
  • I d supplied from the circuit CS1
  • CMx circuits CMx and circuit CMw
  • the relationship between the current flowing through the wiring OL and the wiring BL can be expressed by the following equation according to Kirchhoff's law. it can.
  • the second differential current ⁇ I ⁇ that is the difference between the expressions (B1) to (B9), (B11), (B16), (B22), (B23), (B27) to (B29).
  • the second differential current ⁇ I ⁇ input to the terminal ai is in accordance with the potential V W corresponding to the updated plurality of first data and the plurality of second data.
  • the potential V X has a value corresponding to the sum of the product of. That is, when the second divided current ⁇ I ⁇ is input to the terminal ai of the activation function circuit ACTV, a product sum value of the first data and the second data is acquired, and an activation function corresponding to the value is obtained. Can be obtained.
  • the [Delta] W [1], replaced by -V ⁇ W [1] / a C2 , outputted from the terminal io [2] of the learning circuit LEC, according to the updated amount of the first data (potential V W [2]) potential the -V ⁇ W [2], may be replaced with -V ⁇ W [2] / a C2 . This corresponds to replacing the coefficient A C2 shown in equation (B31) to 1.
  • ⁇ V ⁇ W [1] is applied to the wiring HW [1] from time T08 to time T09
  • ⁇ V ⁇ W [2] is applied to the wiring HW [2] from time T09 to time T10 .
  • the potential applied to the wiring HW [1] and the wiring HW [2] may be higher than the reference potential REFP.
  • REFP reference potential
  • the potential of the holding node can be increased by capacitive coupling.
  • V ⁇ W [1] is applied to the wiring HW [1] instead of ⁇ V ⁇ W [1]
  • wiring HW [2] is between time T09 and time T10.
  • V ⁇ W [2] is applied instead of ⁇ V ⁇ W [2]
  • the second differential current ⁇ I ⁇ can be expressed as the following equation.
  • the first data is updated for the first time.
  • the operation result data is output every time the update is performed, and the learning circuit LEC It is necessary to output the total amount of updates.
  • the potential corresponding to the first update amount of the first data is ⁇ V ⁇ W, 1st, and the potential corresponding to the second update amount of the first data is ⁇ V.
  • V ⁇ w ⁇ V ⁇ W , 1st ⁇ V ⁇ W , 2nd .
  • the memory cell array MCA having memory cells arranged in a matrix of 2 rows and 3 columns is handled.
  • the operation is similarly performed for a memory cell array of 3 rows or more and 4 columns or more. be able to.
  • the second differential current ⁇ I ⁇ when the number of rows of the memory cell array MCA is increased can be expressed by the following equation.
  • the arithmetic circuit 100 described in this embodiment can be used for, for example, a hierarchical neural network. Specifically, when signals are given from all the neurons of the (K-1) layer (K is an integer of 2 or more) in the hierarchical neural network to one of the neurons of the K layer, By using the first data as the weighting factor and the second data as the intensity of the signal output from the (K-1) layer, the intensity and weight of the signal output from the (K-1) layer. The product sum of coefficients can be calculated. Further, the value of the activation function can be obtained by inputting the result of the product sum to the activation function circuit ACTV. The value of this activation function can be a signal input to one of the neurons of the Kth layer.
  • the difference between the intensity of the signal output from the neurons in the Kth layer and the teacher data is acquired, the update amount corresponding to the difference is calculated,
  • the weight coefficient between the (K-1) layer neurons and the Kth layer neurons may be changed by the update amount.
  • the intensity of the signal output from the K-th layer neuron is used as the operation result data, and the update amount ( ⁇ V ⁇ W [1] , ⁇ V ⁇ W [2] ) is calculated. Then, the weighting coefficient can be updated by changing the first data as the weighting coefficient by the amount of updating by capacitive coupling.
  • the update amount of the first data held in the node NM of the memory cell AM is updated to the wiring HW [1] or the wiring HW [2]. This is done by applying a potential according to the above. Therefore, it is not necessary to drive the circuit WDD and the circuit WLD to write the updated first data to the node NM of the memory cell AM. That is, since the driving frequency of the circuit WDD and the circuit WLD can be reduced, the power consumption of the arithmetic circuit 100 can be reduced.
  • the number of rows of memory cells having the same configuration as the memory cell AM [1] is the number of neurons in the previous layer.
  • the number of rows of the memory cell corresponds to the number of output signals of neurons in the previous layer input to the next layer.
  • the number of memory cells having the same configuration as the memory cell AM [1] is the number of neurons in the next layer.
  • the number of columns of the memory cell corresponds to the number of neuron output signals output from the next layer.
  • the number of rows and columns of the memory cell array MCA of the arithmetic circuit is determined by the number of neurons in the previous layer and the next layer, the number of rows and columns of the memory cell array are determined according to the neural network to be configured. Determine and design.
  • Embodiment 2 In this embodiment, a configuration example and an operation example of an arithmetic circuit different from those of the arithmetic circuit 100 described in Embodiment 1 will be described.
  • FIG. 12 shows a configuration example of the arithmetic circuit 200.
  • the arithmetic circuit 200 shown in FIG. 12 is similar to the arithmetic circuit 100 shown in FIG. 1 except that the memory cell AMxr [1], the memory cell AMxr [2], the memory cell AMwr [1], and the memory cell AMwr [2] ],
  • the current mirror circuit CM is removed from the current supply circuit IS.
  • the arithmetic circuit 100 has a configuration in which a current I ⁇ flows from the wiring BL to the terminal ai of the activation function circuit ACTV, but the arithmetic circuit 200 has a current I ⁇ from the terminal ai of the activation function circuit ACTV to the wiring BL.
  • a flowing configuration is used.
  • the memory cell AM [1] and the memory cell AM [2] included in the memory cell array MCA of the arithmetic circuit 200 illustrated in FIG. 12 are the memory cell AM [1] and the memory cell AM [2] described in Embodiment 1. It can be set as the same structure. Therefore, for the details of the memory cell AM [1] and the memory cell AM [2], the description of the arithmetic circuit 100 described in Embodiment 1 is referred to.
  • each of the circuit WDD, the circuit WLD, the circuit VLD, the activation function circuit ACTV, and the learning circuit LEC included in the arithmetic circuit 200 illustrated in FIG. 12 is the circuit WDD described in the first embodiment.
  • the circuit WLD, the circuit VLD, the activation function circuit ACTV, and the learning circuit LEC can have the same configuration. Therefore, the description of the arithmetic circuit 100 described in Embodiment 1 is referred to for the circuit WDD, the circuit WLD, the circuit VLD, the activation function circuit ACTV, and the learning circuit LEC.
  • a part of the configuration of the arithmetic circuit 200 can be the same as that of a part of the arithmetic circuit 100. Therefore, in the following description of the arithmetic circuit 200, the description of the arithmetic circuit 100 of Embodiment 1 will be given. The contents that overlap are omitted.
  • FIG. 13 shows a configuration example of a current supply circuit IS that does not have the current mirror circuit CM, which is different from FIGS. 3 (A), (B), and FIG.
  • the current supply circuit IS shown in FIG. 13 has a circuit CS2, a circuit CS3, a circuit CS4, and a switch SWC.
  • the switch SWC can be an n-channel transistor, for example.
  • the circuit CS2 includes transistors M22 to M24, a capacitor element CD3, a capacitor element CD4, and a terminal ct2, and the circuit CS3 includes transistors M27 to M29 and a capacitor.
  • the element CD7, the capacitor CD8, and the terminal ct3 are included, and the circuit CS4 includes the transistors M32 to M34, the capacitor CD11, the capacitor CD12, and the terminal ct4.
  • the transistors included in the current supply circuit IS shown in FIG. 13 are n-channel transistors. Therefore, the current supply circuit IS can be configured as a unipolar circuit.
  • the transistor included in the current supply circuit IS shown in FIG. 13 is preferably an OS transistor, like the transistors Tr1 and Tr2 described in the first embodiment.
  • OS transistor the description of the transistor Tr1 is referred to.
  • the transistor included in the current supply circuit IS shown in FIG. 13 may be a Si transistor.
  • Each of the circuit CS2 and the circuit CS3 is a constant current circuit that generates a current to be output to the terminal co.
  • the circuit CS2 has a function of generating a current ICS2 based on the potential held at the first terminal of the capacitive element CD3 and the first terminal of the capacitive element CD4.
  • the circuit CS3 includes the first element of the capacitive element CD7.
  • the terminal has a function of generating a current ICS3 based on the potential held at the terminal and the first terminal of the capacitor CD8.
  • Circuit CS4 from the sum of the current I CS2 and the current I CS3, a current sink circuit for suction the current based on the specific potential.
  • Circuit CS4 has a first terminal of the capacitor CD 11, and based on the potential held in the first terminal of the capacitor CD12, the source of the transistor M32 and the transistor M33 - through the drain and suction current I CS4 features
  • the first terminal of the transistor M22 is electrically connected to the wiring VDDL
  • the second terminal and the back gate of the transistor M22 are electrically connected to the first terminal of the transistor M23
  • the gate of the transistor M22 is Are electrically connected to the wiring SW2.
  • the second terminal and back gate of the transistor M23 are electrically connected to the second terminal of the capacitor CD4 and the terminal ct2, and the gate of the transistor M23 is connected to the first terminal of the transistor M24 and the capacitor CD3.
  • the second terminal of the transistor M24 is electrically connected to the wiring VBSL
  • the gate of the transistor M24 is electrically connected to the wiring SW3, and the second terminal of the capacitor CD3 is electrically connected to the wiring SW3B.
  • the first terminal of the transistor M27 is electrically connected to the wiring VDDL
  • the second terminal and the back gate of the transistor M27 are electrically connected to the first terminal of the transistor M28
  • the gate of the transistor M27 is Are electrically connected to the wiring SW4.
  • the second terminal and back gate of the transistor M28 are electrically connected to the second terminal of the capacitor CD8 and the terminal ct3, and the gate of the transistor M28 is connected to the first terminal of the transistor M29 and the capacitor CD7.
  • the second terminal of the transistor M29 is electrically connected to the wiring VBSL
  • the gate of the transistor M29 is electrically connected to the wiring SW5
  • the second terminal of the capacitor CD7 is electrically connected to the wiring SW5B.
  • the wiring VBSL is a wiring for applying an arbitrary potential to the electrical connection destination of the wiring VBSL. Note that the potential is preferably larger than the potential VSS.
  • the first terminal of the transistor M32 is electrically connected to the first terminal of the transistor M34 and the terminal ct4, and the second terminal of the transistor M32 is electrically connected to the first terminal of the transistor M33.
  • the gate of the transistor M32 is electrically connected to the wiring SW6.
  • the second terminal of the transistor M33 is electrically connected to the wiring VSSL, the back gate of the transistor M33 is electrically connected to the wiring VSSL, and the gate of the transistor M33 is connected to the second terminal of the transistor M34 and the capacitor.
  • the first terminal of the element CD11 and the first terminal of the capacitive element CD12 are electrically connected.
  • the gate of the transistor M34 is electrically connected to the wiring SW7
  • the second terminal of the capacitor CD11 is electrically connected to the wiring SW7B
  • the second terminal of the capacitor CD12 is electrically connected to the wiring VSSL. It is connected.
  • the first terminal of the switch SWC is electrically connected to the terminal ct2 and the terminal co, and the second terminal of the switch SWC is electrically connected to the terminal ct3 and the terminal ct4, and the switch SWC is turned off.
  • a control terminal for switching between the ON state and the ON state is electrically connected to the wiring SW1.
  • the wirings SW1 to SW7 are wirings to which one of a low level potential and a high level potential is applied.
  • the wiring SW3B is a wiring to which an inverted signal of the signal input to the wiring SW3 is input
  • the wiring SW5B is a wiring to which an inverted signal of the signal input to the wiring SW5 is input
  • the wiring SW7B Is a wiring to which an inverted signal of the signal input to the wiring SW7 is input.
  • the activation function circuit ACTV will be described by applying the activation function circuit ACTV shown in FIG.
  • FIG. 14 to 16 show timing charts of operation examples of the arithmetic circuit 200.
  • FIG. 14 to 16 illustrate the wiring WL [1], the wiring WL [2], the wiring WD, the node NM (AM [1]), the node NM (AM [2]), and the time NM from time T11 to time T38.
  • the wiring VL [1], the wiring VL [2], the wiring HW [1], the wiring HW [2], the wirings SW1 to SW7, the wiring SW3B, the wiring SW5B, the wiring SW7B, and the wiring SWAL are shown.
  • a variation in the size of AMall is shown.
  • the current I AMall indicates the total sum of currents flowing from the wiring BL to the respective terminals m2 of the memory cells AM [1] and AM [2] of the memory cell array MCA.
  • the timing chart of FIG. 14 shows an example of the operation of the arithmetic circuit 200 at times T11 to T20 and its vicinity
  • the timing chart of FIG. 15 shows the operation of the arithmetic circuit 200 at times T21 to T29 and its vicinity.
  • An operation example is shown
  • the timing chart of FIG. 16 shows an operation example of the arithmetic circuit 200 at time T30 to time T38 and in the vicinity thereof.
  • ⁇ From time T11 to time T12 a high-level potential is applied to the wiring WL [1], and a low-level potential is applied to the wiring WL [2].
  • a potential V Wa [1] larger than the ground potential is applied to the wiring WD.
  • each of the wiring VL [1], the wiring VL [2], the wiring HW [1], and the wiring HW [2] is referred to as a reference potential (referred to as REFP in FIGS. 14 to 16). Etc. may be described as an initial potential).
  • V W [1] V Wb [1] ⁇ V Wa [1]
  • V Wb [1] V Wb [1] .
  • V W [1] may be either a positive potential or a negative potential.
  • V th is the threshold voltage of the transistor Tr2.
  • the low-level potential is continuously applied to the wiring WL [2] from before time T12. For this reason, the transistor Tr1 of the memory cell AM [2] is in the off state before time T12.
  • the node NM (AM [1])
  • the transistors Tr1 of the memory cell AM [1] and the memory cell AM [2] are in the off state, the node NM (AM [1]), from time T12 to time T13, Each potential of the node NM (AM [2]) is held.
  • the ground potential is applied to the wiring WD. Since the transistors Tr1 of the memory cell AM [1] and the memory cell AM [2] are in an off state, application of a potential from the wiring WD causes the memory cell AM [1] and the memory cell AM [2] to be applied. The potentials held at the respective nodes are not rewritten.
  • V W [2] V Wb [2] ⁇ V Wa [2 ]
  • V W [2] is a potential corresponding to one of the plurality of first data, which is different from the potential V w [1].
  • V Wa [2] and V Wb [2] satisfying the above are defined.
  • V W [2] may be either a positive potential or a negative potential.
  • a current flowing from the second terminal of the transistor Tr2 of the memory cell AM [2] to the first terminal is considered.
  • the current flowing from the wiring BL to the first terminal through the second terminal of the transistor Tr2 of the memory cell AM [2] is IAM [2], 1
  • IAM [2], 1 is expressed by the following equation: be able to.
  • a low level potential is applied to the wiring SW1, a low level potential is applied to the wiring SW2, and a low level potential is applied to the wiring SW3. Then, a low level potential is applied to the wiring SW4, a low level potential is applied to the wiring SW5, a low level potential is applied to the wiring SW6, and a low level potential is applied to the wiring SW7. Further, a high level potential is applied to the wiring SW3B, a high level potential is applied to the wiring SW5B, and a high level potential is applied to the wiring SW7B. Therefore, in the circuit CS2, since the transistor M22 is off, no current flows from the wiring VDDL through the transistor M22.
  • the current supply circuit IS does not operate between time T11 and time T14.
  • ⁇ From time T14 to time T16 >> In the current supply circuit IS shown in FIG. 13, between time T14 and time T15, a high level potential is applied to the wiring SW1, a low level potential is applied to the wiring SW2, and a low level potential is applied to the wiring SW3.
  • a high level potential is applied to the wiring SW4, a high level potential is applied to the wiring SW5, a low level potential is applied to the wiring SW6, and a low level potential is applied to the wiring SW7.
  • a high level potential is applied to the wiring SW3B, a low level potential is applied to the wiring SW5B, and a high level potential is applied to the wiring SW7B.
  • the circuit CS2 since the transistor M22 is turned off, no current flows from the wiring VDDL to the terminal ct2 via the source and drain of the transistor M22. That is, the circuit CS2 does not output a constant current to the terminal ct2 between time T14 and time T15.
  • circuit CS4 since the transistor M32 is turned off, no current flows between the source and drain of the transistor M32. That is, the circuit CS4 does not suck out a constant current from the terminal ct4 between time T14 and time 15.
  • the transistor M27 is turned on and the transistor M29 is turned on.
  • an arbitrary potential is applied from the wiring VBSL to the first terminal of the capacitor CD7 and the first terminal of the capacitor CD8 through the source and drain of the transistor M29. Therefore, the circuit CS3 outputs a current corresponding to the potential from the wiring VDDL to the terminal ct3 via the source and drain of the transistors M27 and M28.
  • the current is described as I 1st .
  • the potential of the wiring VBSL is changed so as to satisfy the following expression.
  • the potential at this time is referred to as a first potential.
  • a low level potential is applied to the wiring SW5. Further, a high level potential is applied to the wiring SW5B. Note that the potential between the time T14 and the time T15 is continuously applied to each of the wirings SW1 to SW4, the wiring SW6, the wiring SW7, the wiring SW3B, and the wiring SW7B.
  • the transistor M29 since the low-level potential is applied to the wiring SW5 from time T15 to time T16, the transistor M29 is turned off, and the first terminal of the capacitor CD7 and the first terminal of the capacitor CD8 are connected. Holds the first potential. Further, since the high-level potential is applied to the wiring SW4, the transistor M27 is turned on, and the circuit CS3 outputs the current I 1st corresponding to the first potential to the terminal ct3.
  • V x [1] is a potential corresponding to one of the plurality of second data.
  • the increase in the potential of the gate of the transistor Tr2 is a potential obtained by multiplying the potential change of the wiring VL [1] by a capacitive coupling coefficient determined by the capacitor C1 and its peripheral circuit configuration.
  • the capacitive coupling coefficient can be calculated from the capacitance of the capacitive element C1, the capacitance of the capacitive element C2, the gate capacitance of the transistor Tr2, a parasitic capacitance, and the like.
  • the capacitive coupling coefficient by the capacitive element C1 is A C1 .
  • the capacitive coupling coefficient is AC1
  • the potential VX [1] is applied to the second terminal of the capacitive element C1 of the memory cell AM [1], so that the potential of the node NM (AM [1]) is , A C1 V X [1] rises.
  • a current flowing from the second terminal of the transistor Tr2 of the memory cell AM [1] to the first terminal is considered.
  • IAM [1], 2 IAM [1], 2 is expressed by the following equation. be able to.
  • the potential V x [2] is a potential corresponding to one of the plurality of second data, which is different from the potential V x [1] .
  • the change in the potential of the holding node of the memory cell AM [2] will be described with the capacity coupling coefficient of each memory cell being A C1 . Since the capacitive coupling coefficient is AC1 , the potential VX [2] is applied to the second terminal of the capacitive element C1 of the memory cell AM [2], so that the potential of the node NM (AM [2]) is , A C1 V X [2] rises.
  • the current flowing from the wiring BL to the first terminal through the second terminal of the transistor Tr2 of the memory cell AM [2] is I AM [ 2], 2 ⁇ I AM [2], 1 (indicated as ⁇ I AM [2], 2 in FIG. 14).
  • ⁇ From time T18 to time T21 >> In the current supply circuit IS shown in FIG. 13, between time T18 and time T19, a low level potential is applied to the wiring SW1, a high level potential is applied to the wiring SW2, and a high level potential is applied to the wiring SW3.
  • a high level potential is applied to the wiring SW4, a low level potential is applied to the wiring SW5, a high level potential is applied to the wiring SW6, and a high level potential is applied to the wiring SW7.
  • a low level potential is applied to the wiring SW3B, a high level potential is applied to the wiring SW5B, and a low level potential is applied to the wiring SW7B.
  • the potentials of the wiring SW4, the wiring SW5, and the wiring SW5B have not changed from time T15. Therefore, the first terminal of the capacitor CD7 and the first terminal of the capacitor CD8 of the circuit CS3 Subsequently, the first potential is maintained. Furthermore, since the transistor M27 is on, the circuit CS3 outputs I 1st to the terminal ct3.
  • the transistor M32 and the transistor M34 are in an on state, the first terminal of the transistor M33 and the gate of the transistor M33 are in a conductive state. That is, the transistor M33 has a diode connection configuration.
  • the switch SWC is in the OFF state, the current I 1st from the terminal ct3 of the circuit CS3 flows to the wiring VSSL via the terminal ct4 of the circuit CS4.
  • a potential corresponding to the current I 1st is held at the first terminal of the capacitive element CD11 and the first terminal of the capacitive element CD12. The potential at this time is referred to as a third potential.
  • the transistor M22 is turned on and the transistor M24 is turned on.
  • an arbitrary potential is applied from the wiring VBSL to the first terminal of the capacitor CD7 and the first terminal of the capacitor CD8 through the source and drain of the transistor M24. Therefore, the circuit CS2 outputs a current corresponding to the potential from the terminal ct2 from the wiring VDDL through the source and drain of each of the transistors M22 and M23.
  • the current is referred to as I 2nd .
  • the potential of the wiring VBSL is changed so as to satisfy the following expression.
  • the potential at this time is referred to as a second potential.
  • a low level potential is applied to the wiring SW3 and a low level potential is applied to the wiring SW7. Further, a high level potential is applied to the wiring SW3B, and a high level potential is applied to the wiring SW7B. Note that the potential between the time T18 and the time T19 is continuously applied to the wiring SW1, the wiring SW2, the wiring SW4 to the wiring SW6, and the wiring SW5B.
  • circuit CS2 In the circuit CS2, between the time T19 and the time T20, since the low-level potential is applied to the wiring SW3, the transistor M24 is turned off, and the first terminal of the capacitor CD3 and the first terminal of the capacitor CD4 are connected. Holds the second potential. Further, since the high level voltage is applied to the wiring SW3, the transistor M22 is turned on, circuit CS2 outputs a current I 2nd corresponding to the second potential to the terminal ct2.
  • the transistor M34 since the low-level potential is applied to the wiring SW7 from time T19 to time T20, the transistor M34 is turned off, and the first terminal of the capacitor CD11 and the first terminal of the capacitor CD12 are turned on. The terminal holds the third potential. Further, since the high-level potential is applied to the wiring SW6, the transistor M32 is turned on, and the circuit CS4 draws out the current I 1st corresponding to the third potential from the terminal ct4.
  • a low level potential is applied to the wiring SW2, and a low level potential is applied to the wiring SW6. Note that the potential between the time T20 and the time T21 is continuously applied to the wiring SW1, the wiring SW3 to the wiring SW5, the wiring SW7, the wiring SW3B, the wiring SW5B, and the wiring SW7B.
  • the transistor M22 since the low-level potential is applied to the wiring SW2 between the time T20 and the time T21, the transistor M22 is turned off, and the output of the current I 2nd to the terminal ct2 is not performed.
  • ⁇ From time T21 to time T22 a high level potential is applied to the wiring WL [1] and a low level potential is applied to the wiring WL [2].
  • a potential V Wb [1] larger than the ground potential is applied to the wiring WD.
  • a reference potential is applied to each of the wiring VL [1], the wiring VL [2], the wiring HW [1], and the wiring HW [2].
  • the current flowing from the wiring BL to the first terminal via the second terminal of the transistor Tr2 of the memory cell AM [1] changes IAM [1], 3- IAM [1], 2 (FIG. 15).
  • ⁇ I AM [1], 3 is used to indicate an increase in current.
  • ⁇ From time T23 to time T24 a low level potential is applied to the wiring WL [1] and a high level potential is applied to the wiring WL [2].
  • a potential V Wb [2] larger than the ground potential is applied to the wiring WD.
  • the reference potential is applied to the wiring VL [1], the wiring VL [2], the wiring HW [1], and the wiring HW [2] from time T22.
  • the current flowing from the wiring BL to the first terminal via the second terminal of the transistor Tr2 of the memory cell AM [2] changes IAM [2], 3- IAM [2], 2 (FIG. 15).
  • ⁇ I AM [2], 3 is used to indicate a decrease in current.
  • a high level potential is applied to the wiring SW1
  • a low level potential is applied to the wiring SW2
  • a low level potential is applied to the wiring SW3.
  • a high level potential is applied to the wiring SW4
  • a high level potential is applied to the wiring SW5
  • a low level potential is applied to the wiring SW6
  • a low level potential is applied to the wiring SW7.
  • a high level potential is applied to the wiring SW3B
  • a low level potential is applied to the wiring SW5B
  • a high level potential is applied to the wiring SW7B.
  • the transistor M22 is so turned off, the output of the current I 2nd to the terminal ct2 is not performed. Further, since the transistor M24 is turned off from time T20, the second potential is continuously held in the first terminal of the capacitor CD3 and the first terminal of the capacitor CD4.
  • the transistor M32 since the transistor M32 is turned off, the current I 1st is not sucked from the terminal ct4. In addition, since the transistor M34 is turned off from time T20, the third potential is continuously held in the first terminal of the capacitor CD11 and the first terminal of the capacitor CD12.
  • the transistor M27 is turned on and the transistor M29 is turned on.
  • an arbitrary potential is applied from the wiring VBSL to the first terminal of the capacitor CD7 and the first terminal of the capacitor CD8 through the source and drain of the transistor M29. Therefore, the circuit CS3 outputs a current corresponding to the potential from the wiring VDDL via the source and drain of each of the transistor M27 and the transistor M28.
  • the current is referred to as I 3rd .
  • the sum I C, 3 of the current flowing through the terminal m2 of the memory cell AM [1] and the memory cell AM [2] can be expressed by the following equation.
  • the potential of the wiring VBSL is changed so as to satisfy the following expression.
  • the potential at this time is referred to as a fourth potential.
  • a low level potential is applied to the wiring SW5 from time T25 to time T26. Further, a high level potential is applied to the wiring SW5B. Note that the potential between the time T24 and the time T25 is continuously applied to each of the wirings SW1 to SW4, the wiring SW6, the wiring SW7, the wiring SW3B, and the wiring SW7B.
  • the fourth potential is held in the first terminal of the capacitor CD7 and the first terminal of the capacitor CD8. Is done. Further, since the high-level potential is applied to the wiring SW4, the transistor M27 is turned on, and the circuit CS3 outputs the current I 3rd corresponding to the fourth potential to the terminal ct3.
  • the current flowing from the wiring BL to the first terminal through the second terminal of the transistor Tr2 of the memory cell AM [2] is I AM [ 2], 4 ⁇ I AM [2], 3 (in FIG. 15, expressed as ⁇ I AM [2], 4 ).
  • ⁇ From time T28 to time T30 >> In the current supply circuit IS shown in FIG. 13, between time T28 and time T29, a high level potential is applied to the wiring SW1, a high level potential is applied to the wiring SW2, and a low level potential is applied to the wiring SW3.
  • a high level potential is applied to the wiring SW4, a low level potential is applied to the wiring SW5, a high level potential is applied to the wiring SW6, and a low level potential is applied to the wiring SW7.
  • a high level potential is applied to the wiring SW3B, a high level potential is applied to the wiring SW5B, and a high level potential is applied to the wiring SW7B.
  • the circuit CS2 since the wiring SW2 is electrically connected to the gate of the transistor M22, the transistor M22 is turned on. Further, since the second potential is held at the first terminal of the capacitive element CD3 and the first terminal of the capacitive element CD4, the circuit CS2 outputs a current I 2nd corresponding to the second potential to the terminal ct2.
  • the circuit CS3 since the wiring SW4 is electrically connected to the gate of the transistor M27, the transistor M27 is turned on. Further, since the fourth potential is held at the first terminal of the capacitive element CD7 and the first terminal of the capacitive element CD8, the circuit CS3 outputs a current I 3rd corresponding to the fourth potential to the terminal ct3.
  • the circuit CS4 since the wiring SW6 is electrically connected to the gate of the transistor M32, the transistor M32 is turned on. Further, since the third potential is held at the first terminal of the capacitive element CD11 and the first terminal of the capacitive element CD12, the circuit CS4 sucks the current I 1st corresponding to the third potential from the terminal ct4.
  • I ⁇ flowing from the terminal a i is a value corresponding to the sum of the products of a plurality of first data potentials and a plurality of second data potentials.
  • I alpha output from the terminal ai activation function circuit ACTV activation acquired first data after update and the value of the sum of products of the second data, and corresponding to the value The value of the function can be obtained.
  • VW [1] is applied to the wiring VL [1] from time T16 to time T17 and from time T26 to time T27, and from time T17 to time T18 and from time T27.
  • VW [2] is applied to the wiring VL [2] until time T28, but the potential applied to the wiring VL [1] and the wiring VL [2] may be lower than the reference potential REFP.
  • REFP a potential lower than the reference potential REFP
  • the memory cell connected to the wiring VL [1] and / or the wiring VL [2] The potential of the holding node can be lowered by capacitive coupling. Thereby, in the product-sum operation, the product of the first data and one of the second data having a negative value can be performed.
  • the memory cell array MCA having memory cells arranged in a matrix of 2 rows and 1 column has been dealt with, but the same operation is performed for a memory cell array of 3 rows or more and 2 columns or more. be able to.
  • the arithmetic processing for the plurality of columns can be performed simultaneously. That is, by increasing the number of columns in the memory cell array, a semiconductor device that realizes high-speed arithmetic processing can be provided. Further, by increasing the number of rows, the number of terms to be added in the product-sum operation can be increased. When the number of lines is increased, I ⁇ can be expressed by the following equation.
  • the operation result data corresponding to the I alpha calculated in the period from time T28 to time T29 is output from the terminal afb. Then, the operation result data is input to the terminal gi4 of the learning circuit LEC. At this time, input data is input to the terminal gi1 of the learning circuit LEC, V X [1] is input as one of the second data to the terminal gi2 [1] of the learning circuit LEC, and the terminal of the learning circuit LEC the GI2 [2] is input V X [2] as a single second data, the teacher data is input to the learning circuit LEC terminal gi3.
  • ⁇ From time T30 to time T31 >> In the current supply circuit IS shown in FIG. 13, between time T30 and time T31, a low level potential is applied to the wiring SW1, a low level potential is applied to the wiring SW2, and a low level potential is applied to the wiring SW3.
  • a low level potential is applied to the wiring SW4, a low level potential is applied to the wiring SW5, a high level potential is applied to the wiring SW6, and a low level potential is applied to the wiring SW7.
  • a high level potential is applied to the wiring SW3B, a high level potential is applied to the wiring SW5B, and a high level potential is applied to the wiring SW7B.
  • the transistor M22 is turned off, so that the current 2nd is not output to the terminal ct2.
  • the transistor M24 is in an off state from time T20, the second potential is continuously held in the first terminal of the capacitor CD3 and the first terminal of the capacitor CD4.
  • the transistor M27 is turned off, the output of the current I 3rd to the terminal ct3 is not performed. Further, since the transistor M29 is turned off from time T25, the fourth potential is continuously held in the first terminal of the capacitor CD7 and the first terminal of the capacitor CD8.
  • the transistor M32 since the transistor M32 is turned off, the current I 1st is not sucked from the terminal ct4. In addition, since the transistor M34 is turned off from time T20, the third potential is continuously held in the first terminal of the capacitor CD11 and the first terminal of the capacitor CD12.
  • the potential V ⁇ W [1 ] is applied to the second terminal of the capacitor C2 through the terminal m5. ] Is applied, and the potential of the gate of the transistor Tr2 varies.
  • the amount of change in the potential of the gate of the transistor Tr2 is a potential obtained by multiplying the potential change of the wiring HW [1] by a capacitive coupling coefficient determined by the capacitor C2 and its peripheral circuit configuration.
  • the capacitive coupling coefficient can be calculated from the capacitance of the capacitive element C1, the capacitance of the capacitive element C2, the gate capacitance of the transistor Tr2, a parasitic capacitance, and the like.
  • the capacitive coupling coefficient by the capacitive element C2 is A C2
  • the amount of change in the potential of the gate of the transistor Tr2 is A C2 V ⁇ W [1] .
  • the potential corresponding to the update amount of the first data (potential V W [1] ) output from the terminal io [1] of the learning circuit LEC is a potential that cancels the influence of capacitive coupling of the capacitive element C2.
  • the reference potential is applied to the wiring VL [1] from time T31 to time T32.
  • the potential of the gate of the transistor Tr2 of the memory cell AM [1] is between time T30 and time T31. Reduced compared to potential.
  • the potential of the node NM is the sum of V Wb [1] and A C2 V ⁇ W [1] .
  • the current flowing from the wiring BL to the first terminal via the second terminal of the transistor Tr2 of the memory cell AM [1] changes IAM [1], 5- IAM [1], 4 (FIG. 16).
  • ⁇ I AM [1], 5 is used to indicate a decrease in current.
  • the potential V ⁇ W [2 ] is applied to the second terminal of the capacitor C2 through the terminal m5. ] Is applied.
  • the change in the potential of the holding node of the memory cell AM [2] will be described with the capacity coupling coefficient of each memory cell being AC2 . Due to the capacitive coupling coefficient with A C2, to the second terminal of the capacitor C2 of the memory cell AM [2], by the potential V [Delta] W [2] is applied, the potential of the node NM (AM [2]) , A C2 V ⁇ W [2] changes.
  • the first data (potential V W [ the potential corresponding to 2]) of the update amount of the total sum (update data), may be V ⁇ W [2] / a C2 .
  • the reference potential is applied to the wiring VL [2] between time T32 and time T33.
  • the potential of the gate of the transistor Tr2 of the memory cell AM [2] is between time T31 and time T32. Reduced compared to potential.
  • the potential of the node NM is the sum of V Wb [2] and A C2 V ⁇ W [2] .
  • the current flowing from the wiring BL to the first terminal via the second terminal of the transistor Tr2 of the memory cell AM [2] changes IAM [2], 5- IAM [2], 4 (FIG. 16).
  • ⁇ I AM [2], 5 is used to indicate a decrease in current.
  • ⁇ From time T33 to time T35 >> In the current supply circuit IS shown in FIG. 13, between time T33 and time T34, a high level potential is applied to the wiring SW1, a low level potential is applied to the wiring SW2, and a low level potential is applied to the wiring SW3.
  • a high level potential is applied to the wiring SW4, a high level potential is applied to the wiring SW5, a low level potential is applied to the wiring SW6, and a low level potential is applied to the wiring SW7.
  • a high level potential is applied to the wiring SW3B, a low level potential is applied to the wiring SW5B, and a high level potential is applied to the wiring SW7B.
  • the transistor M22 is so turned off, the output of the current I 2nd to the terminal ct2 is not performed. Further, since the transistor M24 is turned off from time T20, the second potential is continuously held in the first terminal of the capacitor CD3 and the first terminal of the capacitor CD4.
  • the transistor M27 is turned on and the transistor M29 is turned on.
  • an arbitrary potential is applied from the wiring VBSL to the first terminal of the capacitor CD7 and the first terminal of the capacitor CD8 through the source and drain of the transistor M29. Therefore, the circuit CS3 outputs a current corresponding to the potential from the wiring VDDL via the source and drain of each of the transistor M27 and the transistor M28.
  • the current is referred to as I 5th .
  • the sum I C, 5 of the current flowing through the terminal m2 of the memory cell AM [1] and the memory cell AM [2] can be expressed by the following equation.
  • the potential of the wiring VBSL is changed so as to satisfy the following expression.
  • the potential at this time is referred to as a fifth potential.
  • time T34 and time T35 a low level potential is applied to the wiring SW5. Further, a high level potential is applied to the wiring SW5B. Note that the potential between time T33 and time T34 is continuously applied to each of the wirings SW1 to SW4, wiring SW6, wiring SW7, wiring SW3B, and wiring SW7B.
  • the circuit CS3 since the low level potential is applied to the wiring SW5 from time T35 to time T36, the fifth potential is held in the first terminal of the capacitor CD7 and the first terminal of the capacitor CD8. Is done. Further, since the high-level potential is applied to the wiring SW4, the transistor M27 is turned on, and the circuit CS3 outputs I 5th .
  • the current flowing from the wiring BL to the first terminal through the second terminal of the transistor Tr2 of the memory cell AM [2] is I AM [ 2], 6 ⁇ I AM [2], 6 (indicated as ⁇ I AM [2], 6 in FIG. 14).
  • a high level potential is applied to the wiring SW1
  • a high level potential is applied to the wiring SW2
  • a low level potential is applied to the wiring SW3.
  • a high level potential is applied to the wiring SW4
  • a low level potential is applied to the wiring SW5
  • a high level potential is applied to the wiring SW6
  • a low level potential is applied to the wiring SW7.
  • a high level potential is applied to the wiring SW3B
  • a high level potential is applied to the wiring SW5B
  • a high level potential is applied to the wiring SW7B.
  • the circuit CS2 since the wiring SW2 is electrically connected to the gate of the transistor M22, the transistor M22 is turned on. Further, since the second potential is held at the first terminal of the capacitive element CD3 and the first terminal of the capacitive element CD4, the circuit CS2 outputs a current I 2nd corresponding to the second potential to the terminal ct2.
  • the circuit CS3 since the wiring SW4 is electrically connected to the gate of the transistor M27, the transistor M27 is turned on. Further, since the fifth potential is held at the first terminal of the capacitive element CD7 and the first terminal of the capacitive element CD8, the circuit CS3 outputs the current I 5th corresponding to the fifth potential to the terminal ct3.
  • the circuit CS4 since the wiring SW6 is electrically connected to the gate of the transistor M32, the transistor M32 is turned on. Further, since the second potential is held at the first terminal of the capacitive element CD11 and the first terminal of the capacitive element CD12, the circuit CS4 sucks the current I 1st corresponding to the third potential from the terminal ct4.
  • the current ⁇ I ⁇ flowing from the terminal ai is a value corresponding to the sum of the products of the updated potential according to the plurality of first data and the potential according to the plurality of second data. It becomes.
  • activation acquires the first data after updating the value of the sum of products of the second data, and corresponding to the value The value of the function can be obtained.
  • the first data is updated for the first time.
  • the operation result data is output every time the update is performed, and the learning circuit LEC It is necessary to output the total amount of updates.
  • the potential corresponding to the first update amount of the first data is V ⁇ W, 1st
  • the potential corresponding to the second update amount of the first data is V ⁇ W
  • V ⁇ w potential corresponding to the update amount of the sum of the first data from the learning circuit LEC terminal io [1] (or terminal io [2]) (the potential V W [1]) (updated data)
  • V ⁇ w V ⁇ W, 1st + V ⁇ W, 2nd .
  • the memory cell array MCA having memory cells arranged in a matrix of 2 rows and 1 column has been dealt with, but the same operation is performed for a memory cell array of 3 rows or more and 2 columns or more. be able to.
  • the I beta when increasing the number of rows of the memory cell array MCA can be expressed by the following equation.
  • the arithmetic circuit 200 described in this embodiment can be used for a hierarchical neural network, like the arithmetic circuit 100.
  • the number of rows of memory cells having the same configuration as the memory cell AM [1] is the number of neurons in the previous layer.
  • the number of rows of the memory cell corresponds to the number of output signals of neurons in the previous layer input to the next layer.
  • the number of memory cells having the same configuration as the memory cell AM [1] is the number of neurons in the next layer.
  • the number of columns of the memory cell corresponds to the number of neuron output signals output from the next layer.
  • the number of rows and columns of the memory cell array MCA of the arithmetic circuit is determined by the number of neurons in the previous layer and the next layer, the number of rows and columns of the memory cell array are determined according to the neural network to be configured. Determine and design.
  • the update of the first data held in the node NM of the memory cell AM is performed on the wiring HW [1] or the wiring HW [2]. This is done by applying a potential according to the above. Therefore, it is not necessary to drive the circuit WDD and the circuit WLD to write the updated first data to the node NM of the memory cell AM. That is, since the driving frequency of the circuit WDD and the circuit WLD can be reduced, the power consumption of the arithmetic circuit 200 can be reduced.
  • the arithmetic circuit 200 does not include the memory cell AM that holds the first reference data and the second reference data, as compared with the arithmetic circuit 100 described in the first embodiment. Can be reduced.
  • the structure of the arithmetic circuit 200 is not limited to the structure described in this embodiment.
  • the configuration of the arithmetic circuit 200 circuit elements can be selected and / or the configuration of electrical connection can be changed depending on the situation.
  • the arithmetic circuit 200 operates in accordance with fluctuations in potentials of the wirings SW1 to SW7, the wiring SW3B, the wiring SW5B, and the wiring SW7B.
  • An operation example of this embodiment (timing charts in FIGS. 14 to 16). Therefore, the wiring SW4 and the wiring SW6 can be the same wiring, the wiring SW5 and the wiring SW7 can be the same wiring, and the wiring SW5B and the wiring SW7B can be the same wiring.
  • the number of wirings provided in the arithmetic circuit 200 can be reduced, so that the circuit area of the arithmetic circuit 200 can be reduced.
  • a semiconductor device illustrated in FIG. 17 includes a transistor 300, a transistor 500, and a capacitor 600.
  • 19A is a cross-sectional view of the transistor 500 in the channel length direction
  • FIG. 19B is a cross-sectional view of the transistor 500 in the channel width direction
  • FIG. 19C is a cross-sectional view of the transistor 300 in the channel width direction.
  • the transistor 500 is a transistor (OS transistor) having a metal oxide in a channel formation region. Since the transistor 500 has a small off-state current, the transistor 500 can hold the first data for a long time by using the transistor 500 for the transistor Tr1 of the semiconductor device, particularly the memory cell MC. That is, since the frequency of the refresh operation is low or the refresh operation is not required, the power consumption of the semiconductor device can be reduced.
  • OS transistor transistor having a metal oxide in a channel formation region. Since the transistor 500 has a small off-state current, the transistor 500 can hold the first data for a long time by using the transistor 500 for the transistor Tr1 of the semiconductor device, particularly the memory cell MC. That is, since the frequency of the refresh operation is low or the refresh operation is not required, the power consumption of the semiconductor device can be reduced.
  • the semiconductor device described in this embodiment includes a transistor 300, a transistor 500, and a capacitor 600 as illustrated in FIG.
  • the transistor 500 is provided above the transistor 300
  • the capacitor 600 is provided above the transistor 300 and the transistor 500.
  • the transistor 300 includes a conductor 316, an insulator 315, a semiconductor region 313 including a part of the substrate 311, a low resistance region 314a functioning as a source region or a drain region, and a low resistance region 314b. . Note that the transistor 300 can be used as the transistor Tr2 in the above embodiment.
  • the transistor 300 as illustrated in FIG. 19C, the upper surface of the semiconductor region 313 and the side surface in the channel width direction are covered with the conductor 316 with the insulator 315 interposed therebetween.
  • the transistor 300 is of the Fin type, an effective channel width is increased, whereby the on-state characteristics of the transistor 300 can be improved.
  • the contribution of the electric field of the gate electrode can be increased, off characteristics of the transistor 300 can be improved.
  • the transistor 300 may be either a p-channel type or an n-channel type.
  • the transistor Tr2 transistor 300
  • the potential applied to the wiring VR0 is a high level potential
  • the memory cell MC It is preferable that a current is output from the terminal m1. Further, when the configuration of the memory cell MC is changed as described above, the configuration of the current supply circuit IS also needs to be changed.
  • the region in which the channel of the semiconductor region 313 is formed, the region in the vicinity thereof, the low resistance region 314a that serves as the source region or the drain region, the low resistance region 314b, and the like preferably include a semiconductor such as a silicon-based semiconductor. It preferably contains crystalline silicon. Alternatively, a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like may be used. A structure using silicon in which effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be employed. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.
  • HEMT High Electron Mobility Transistor
  • the low-resistance region 314a and the low-resistance region 314b provide an n-type conductivity element such as arsenic or phosphorus, or p-type conductivity such as boron, in addition to the semiconductor material used for the semiconductor region 313. Containing elements.
  • the conductor 316 functioning as a gate electrode includes a semiconductor material such as silicon, a metal material, an alloy containing an element imparting n-type conductivity such as arsenic or phosphorus, or an element imparting p-type conductivity such as boron.
  • a conductive material such as a material or a metal oxide material can be used.
  • the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and tungsten is particularly preferable from the viewpoint of heat resistance.
  • the transistor 300 illustrated in FIGS. 17A and 17B is an example and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.
  • the transistor 300 may have a structure similar to that of the transistor 500 including an oxide semiconductor. Note that details of the transistor 500 will be described later.
  • An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order so as to cover the transistor 300.
  • the insulator 320, the insulator 322, the insulator 324, and the insulator 326 for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like is used. That's fine.
  • silicon oxynitride refers to a material having a higher oxygen content than nitrogen as its composition
  • silicon nitride oxide refers to a material having a higher nitrogen content than oxygen as its composition.
  • aluminum oxynitride refers to a material having a higher oxygen content than nitrogen as its composition
  • aluminum nitride oxide refers to a material having a higher nitrogen content than oxygen as its composition.
  • the insulator 322 may have a function as a planarization film that planarizes a step generated by the transistor 300 or the like provided thereunder.
  • the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve planarity.
  • CMP chemical mechanical polishing
  • the insulator 324 is preferably formed using a film having a barrier property such that hydrogen and impurities do not diffuse from the substrate 311 or the transistor 300 into a region where the transistor 500 is provided.
  • a film having a barrier property against hydrogen for example, silicon nitride formed by a CVD method can be used.
  • silicon nitride formed by a CVD method when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the transistor 500, characteristics of the semiconductor element may be deteriorated. Therefore, a film for suppressing hydrogen diffusion is preferably used between the transistor 500 and the transistor 300.
  • the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.
  • the amount of desorption of hydrogen can be analyzed using, for example, a temperature programmed desorption gas analysis method (TDS).
  • TDS temperature programmed desorption gas analysis method
  • the amount of hydrogen desorbed from the insulator 324 is calculated by converting the amount of desorption converted to hydrogen atoms per area of the insulator 324 when the surface temperature of the film is in the range of 50 ° C. to 500 ° C. 10 ⁇ 10 15 atoms / cm 2 or less, preferably 5 ⁇ 10 15 atoms / cm 2 or less.
  • the insulator 326 preferably has a lower dielectric constant than the insulator 324.
  • the dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3.
  • the relative dielectric constant of the insulator 326 is preferably equal to or less than 0.7 times, more preferably equal to or less than 0.6 times that of the insulator 324.
  • the insulator 320, the insulator 322, the insulator 324, and the insulator 326 are embedded with the capacitor 600 or the conductor 328 connected to the transistor 500, the conductor 330, and the like.
  • the conductor 328 and the conductor 330 function as plugs or wirings.
  • a conductor having a function as a plug or a wiring may be given the same reference numeral by collecting a plurality of structures.
  • the wiring and the plug connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
  • a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is used as a single layer or a stacked layer. be able to. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Or it is preferable to form with low resistance conductive materials, such as aluminum and copper. Wiring resistance can be lowered by using a low-resistance conductive material.
  • a wiring layer may be provided over the insulator 326 and the conductor 330.
  • an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked.
  • a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354.
  • the conductor 356 functions as a plug connected to the transistor 300 or a wiring. Note that the conductor 356 can be provided using a material similar to that of the conductor 328 and the conductor 330.
  • the insulator 350 is preferably an insulator having a barrier property against hydrogen, similarly to the insulator 324.
  • the conductor 356 preferably includes a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 350 having a barrier property against hydrogen.
  • tantalum nitride may be used as the conductor having a barrier property against hydrogen. Further, by stacking tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 300 can be suppressed while maintaining conductivity as a wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.
  • a wiring layer may be provided over the insulator 354 and the conductor 356.
  • an insulator 360, an insulator 362, and an insulator 364 are sequentially stacked.
  • a conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364.
  • the conductor 366 functions as a plug or a wiring. Note that the conductor 366 can be provided using a material similar to that of the conductor 328 and the conductor 330.
  • an insulator having a barrier property against hydrogen is preferably used as the insulator 360.
  • the conductor 366 preferably includes a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen.
  • a wiring layer may be provided over the insulator 364 and the conductor 366.
  • an insulator 370, an insulator 372, and an insulator 374 are sequentially stacked.
  • a conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374.
  • the conductor 376 functions as a plug or a wiring. Note that the conductor 376 can be provided using a material similar to that of the conductor 328 and the conductor 330.
  • the insulator 370 is preferably an insulator having a barrier property against hydrogen, similarly to the insulator 324.
  • the conductor 376 preferably includes a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 370 having a barrier property against hydrogen.
  • a wiring layer may be provided over the insulator 374 and the conductor 376.
  • an insulator 380, an insulator 382, and an insulator 384 are stacked in this order.
  • a conductor 386 is formed over the insulator 380, the insulator 382, and the insulator 384.
  • the conductor 386 has a function as a plug or a wiring. Note that the conductor 386 can be provided using a material similar to that of the conductor 328 and the conductor 330.
  • an insulator having a barrier property against hydrogen is preferably used as the insulator 380.
  • the conductor 386 preferably includes a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 380 having a barrier property against hydrogen.
  • the semiconductor device has been described above, the semiconductor device according to this embodiment It is not limited to this.
  • the number of wiring layers similar to the wiring layer including the conductor 356 may be three or less, or the number of wiring layers similar to the wiring layer including the conductor 356 may be five or more.
  • an insulator 510, an insulator 512, an insulator 514, and an insulator 516 are sequentially stacked.
  • Any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 is preferably formed using a substance having a barrier property against oxygen or hydrogen.
  • a film having a barrier property so that hydrogen and impurities do not diffuse from a region where the substrate 311 or the transistor 300 is provided to a region where the transistor 500 is provided for example.
  • a material similar to that of the insulator 324 can be used.
  • silicon nitride formed by a CVD method can be used as an example of a film having a barrier property against hydrogen.
  • silicon nitride formed by a CVD method when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the transistor 500, characteristics of the semiconductor element may be deteriorated. Therefore, a film for suppressing hydrogen diffusion is preferably used between the transistor 500 and the transistor 300.
  • the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.
  • a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used for the insulator 510 and the insulator 514.
  • aluminum oxide has a high blocking effect that prevents the film from permeating both oxygen and impurities such as hydrogen and moisture, which cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide included in the transistor 500 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 500.
  • the insulator 512 and the insulator 516 can be formed using the same material as the insulator 320.
  • a material having a relatively low dielectric constant to these insulators, parasitic capacitance generated between wirings can be reduced.
  • a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 512 and the insulator 516.
  • a conductor 518 In the insulator 510, the insulator 512, the insulator 514, and the insulator 516, a conductor 518, a conductor included in the transistor 500 (eg, the conductor 503), and the like are embedded. Note that the conductor 518 functions as a plug or a wiring connected to the capacitor 600 or the transistor 300.
  • the conductor 518 can be provided using a material similar to that of the conductor 328 and the conductor 330.
  • the insulator 510 and the conductor 518 in a region in contact with the insulator 514 are preferably conductors having a barrier property against oxygen, hydrogen, and water.
  • the transistor 300 and the transistor 500 can be separated by a layer having a barrier property against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.
  • a transistor 500 is provided above the insulator 516.
  • the transistor 500 is provided over the insulator 512 and the insulator 516 and the conductor 503 which is embedded in the insulator 512 and the insulator 516, and the insulator 516 and the conductor 503.
  • an insulator 544 is provided between the oxide 530a, the oxide 530b, the conductor 542a, the conductor 542b, and the insulator 580.
  • a conductor 560 includes a conductor 560a provided inside the insulator 550 and a conductor provided so as to be embedded inside the conductor 560a. 560b.
  • an insulator 574 is preferably provided over the insulator 580, the conductor 560, and the insulator 550.
  • oxide 530a the oxide 530b, and the oxide 530c may be collectively referred to as an oxide 530.
  • the transistor 500 a structure in which three layers of the oxide 530a, the oxide 530b, and the oxide 530c are stacked in the vicinity of the region where the channel is formed is described; however, the present invention is not limited thereto. It is not a thing. For example, a single layer of the oxide 530b, a two-layer structure of the oxide 530b and the oxide 530a, a two-layer structure of the oxide 530b and the oxide 530c, or a stacked structure of four or more layers may be provided.
  • the conductor 560 is illustrated as a two-layer structure; however, the present invention is not limited to this.
  • the conductor 560 functions as a gate electrode of the transistor, and the conductor 542a and the conductor 542b function as a source electrode or a drain electrode, respectively.
  • the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductors 542a and 542b.
  • the arrangement of the conductor 560, the conductor 542a, and the conductor 542b is selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be disposed in a self-aligned manner between the source electrode and the drain electrode. Therefore, the conductor 560 can be formed without providing a margin for alignment, so that the area occupied by the transistor 500 can be reduced. Thereby, miniaturization and high integration of the semiconductor device can be achieved.
  • the conductor 560 is formed in a self-aligned manner in a region between the conductors 542a and 542b, the conductor 560 does not have a region overlapping with the conductor 542a or the conductor 542b. Accordingly, parasitic capacitance formed between the conductor 560 and the conductors 542a and 542b can be reduced. Thus, the switching speed of the transistor 500 can be improved and high frequency characteristics can be obtained.
  • the conductor 560 may function as a first gate (also referred to as a top gate) electrode.
  • the conductor 503 may function as a second gate (also referred to as a bottom gate) electrode.
  • the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560 without being linked.
  • the threshold voltage of the transistor 500 can be higher than 0 V and the off-state current can be reduced. Therefore, when a negative potential is applied to the conductor 503, the drain current when the potential applied to the conductor 560 is 0 V can be made smaller than when a negative potential is not applied.
  • the conductor 503 is disposed so as to overlap with the oxide 530 and the conductor 560. Accordingly, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected to cover the channel formation region formed in the oxide 530. Can do.
  • a transistor structure in which a channel formation region is electrically surrounded by an electric field of the first gate electrode and the second gate electrode is referred to as a surrounded channel (S-channel) structure.
  • the conductor 503 has the same structure as that of the conductor 518, and a conductor 503a is formed in contact with the inner walls of the openings of the insulator 514 and the insulator 516, and a conductor 503b is further formed inside.
  • the insulator 520, the insulator 522, the insulator 524, and the insulator 550 have a function as a gate insulating film.
  • the insulator 524 in contact with the oxide 530 is preferably an insulator containing more oxygen than oxygen that satisfies the stoichiometric composition. That is, it is preferable that an excess oxygen region be formed in the insulator 524.
  • an insulator containing excess oxygen in contact with the oxide 530 oxygen vacancies in the oxide 530 can be reduced and the reliability of the transistor 500 can be improved.
  • an oxide material from which part of oxygen is released by heating is preferably used as the insulator having an excess oxygen region.
  • the oxide that desorbs oxygen by heating means that the amount of desorbed oxygen in terms of oxygen atom is 1.0 ⁇ 10 18 atoms / cm 3 or more, preferably 1 in TDS (Thermal Desorption Spectroscopy) analysis.
  • the oxide film has a thickness of 0.0 ⁇ 10 19 atoms / cm 3 or more, more preferably 2.0 ⁇ 10 19 atoms / cm 3 or more, or 3.0 ⁇ 10 20 atoms / cm 3 or more.
  • the surface temperature of the film at the time of the TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 400 ° C.
  • the insulator 522 preferably has a function of suppressing diffusion of oxygen (for example, oxygen atoms and oxygen molecules) (the oxygen hardly transmits).
  • the insulator 522 have a function of suppressing diffusion of oxygen and impurities so that oxygen included in the oxide 530 does not diffuse to the insulator 520 side. Further, the conductor 503 can be prevented from reacting with the oxygen included in the insulator 524 and the oxide 530.
  • the insulator 522 includes, for example, aluminum oxide, hafnium oxide, aluminum and an oxide containing hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or An insulator containing a so-called high-k material such as (Ba, Sr) TiO 3 (BST) is preferably used in a single layer or a stacked layer. As transistor miniaturization and higher integration progress, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material for the insulator functioning as a gate insulating film, the gate potential during transistor operation can be reduced while maintaining the physical film thickness.
  • an insulator including one or both of oxides of aluminum and hafnium which is an insulating material having a function of suppressing diffusion of impurities and oxygen (the oxygen hardly transmits) may be used.
  • the insulator containing one or both of aluminum and hafnium aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.
  • the insulator 522 is formed using such a material, the insulator 522 suppresses release of oxygen from the oxide 530 and entry of impurities such as hydrogen from the periphery of the transistor 500 to the oxide 530. Acts as a layer.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators.
  • these insulators may be nitrided. Silicon insulator, silicon oxynitride, or silicon nitride may be stacked over the above insulator.
  • the insulator 520 is preferably thermally stable.
  • silicon oxide and silicon oxynitride are thermally stable.
  • the insulator 520, the insulator 522, and the insulator 524 may have a stacked structure of two or more layers. In that case, it is not limited to the laminated structure which consists of the same material, The laminated structure which consists of a different material may be sufficient.
  • the oxide 530 includes an In-M-Zn oxide (the element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium) It is preferable to use a metal oxide such as one or more selected from hafnium, tantalum, tungsten, or magnesium.
  • the In-M-Zn oxide that can be used as the oxide 530 is preferably a CAAC-OS or a CAC-OS described in Embodiment 4.
  • an In—Ga oxide or an In—Zn oxide may be used as the oxide 530.
  • the metal oxide that functions as a channel formation region in the oxide 530 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. In this manner, off-state current of a transistor can be reduced by using a metal oxide having a large band gap.
  • the oxide 530 includes the oxide 530a below the oxide 530b, diffusion of impurities from the structure formed below the oxide 530a to the oxide 530b can be suppressed. In addition, by including the oxide 530c over the oxide 530b, diffusion of impurities from the structure formed above the oxide 530c to the oxide 530b can be suppressed.
  • the oxide 530 preferably has a stacked structure of oxides having different atomic ratios of metal atoms.
  • the atomic ratio of the element M in the constituent element is larger than the atomic ratio of the element M in the constituent element in the metal oxide used for the oxide 530b. It is preferable.
  • the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b.
  • the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 530a.
  • a metal oxide that can be used for the oxide 530a or the oxide 530b can be used.
  • the energy at the lower end of the conduction band of the oxide 530a and the oxide 530c is higher than the energy at the lower end of the conduction band of the oxide 530b.
  • the electron affinity of the oxide 530a and the oxide 530c is preferably smaller than the electron affinity of the oxide 530b.
  • the energy level at the lower end of the conduction band changes gently.
  • the energy level at the lower end of the conduction band at the junction of the oxide 530a, the oxide 530b, and the oxide 530c is continuously changed or continuously joined.
  • the density of defect states in the mixed layer formed at the interface between the oxide 530a and the oxide 530b and the interface between the oxide 530b and the oxide 530c is preferably lowered.
  • the oxide 530a and the oxide 530b, and the oxide 530b and the oxide 530c have a common element (main component) in addition to oxygen, so that a mixed layer with a low density of defect states is formed.
  • the oxide 530b is an In—Ga—Zn oxide
  • an In—Ga—Zn oxide, a Ga—Zn oxide, a gallium oxide, or the like may be used as the oxide 530a and the oxide 530c.
  • the main path of the carrier is the oxide 530b.
  • the oxide 530a and the oxide 530c have the above structures, the density of defect states at the interface between the oxide 530a and the oxide 530b and the interface between the oxide 530b and the oxide 530c can be reduced. Therefore, the influence on carrier conduction due to interface scattering is reduced, and the transistor 500 can obtain a high on-state current.
  • a conductor 542a and a conductor 542b functioning as a source electrode and a drain electrode are provided over the oxide 530b.
  • the conductor 542a and the conductor 542b aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium It is preferable to use a metal element selected from iridium, strontium, and lanthanum, an alloy containing the above-described metal element, or an alloy combining the above-described metal elements.
  • tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, or the like is used. It is preferable. Also, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel are difficult to oxidize. A conductive material or a material that maintains conductivity even when oxygen is absorbed is preferable.
  • a region 543a and a region 543b are formed as low resistance regions at and near the interface between the oxide 530 and the conductor 542a (conductor 542b). There is. At this time, the region 543a functions as one of a source region and a drain region, and the region 543b functions as the other of the source region and the drain region. In addition, a channel formation region is formed in a region between the region 543a and the region 543b.
  • the oxygen concentration in the region 543a (region 543b) may be reduced in some cases.
  • a metal compound layer including a metal contained in the conductor 542a (conductor 542b) and a component of the oxide 530 may be formed in the region 543a (region 543b). In such a case, the carrier concentration in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low-resistance region.
  • the insulator 544 is provided so as to cover the conductor 542a and the conductor 542b, and suppresses oxidation of the conductor 542a and the conductor 542b. At this time, the insulator 544 may be provided so as to cover a side surface of the oxide 530 and to be in contact with the insulator 524.
  • a metal oxide containing one or more kinds selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like is used. it can.
  • the insulator 544 it is preferable to use aluminum oxide, hafnium oxide, aluminum, an oxide containing hafnium (hafnium aluminate), or the like, which is an insulator containing one or both of aluminum and hafnium. .
  • hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in a heat treatment in a later step.
  • the insulator 544 is not an essential component in the case where the conductor 542a and the conductor 542b do not have a significant decrease in conductivity even when the material has oxidation resistance or absorbs oxygen. What is necessary is just to design suitably according to the transistor characteristic to request
  • the insulator 550 functions as a gate insulating film.
  • the insulator 550 is preferably provided in contact with the inside (upper surface and side surfaces) of the oxide 530c.
  • the insulator 550 is preferably formed using an insulator that contains excess oxygen and from which oxygen is released by heating, like the insulator 524 described above.
  • silicon oxide having excess oxygen silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and voids
  • silicon oxide which has can be used.
  • silicon oxide and silicon oxynitride are preferable because they are stable against heat.
  • An insulator from which oxygen is released by heating is provided as the insulator 550 so as to be in contact with the top surface of the oxide 530c, so that oxygen can be effectively supplied from the insulator 550 to the channel formation region of the oxide 530b through the oxide 530c. Can be supplied.
  • the concentration of impurities such as water or hydrogen in the insulator 550 is preferably reduced.
  • the thickness of the insulator 550 is preferably greater than or equal to 1 nm and less than or equal to 20 nm.
  • a metal oxide may be provided between the insulator 550 and the conductor 560 in order to efficiently supply excess oxygen included in the insulator 550 to the oxide 530.
  • the metal oxide preferably suppresses oxygen diffusion from the insulator 550 to the conductor 560.
  • diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. That is, a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed. Further, oxidation of the conductor 560 due to excess oxygen can be suppressed.
  • a material that can be used for the insulator 544 may be used.
  • the conductor 560 functioning as the first gate electrode is illustrated as a two-layer structure in FIGS. 19A and 19B, but may have a single-layer structure or a stacked structure including three or more layers. .
  • the conductor 560a has a function of suppressing diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitric oxide molecule (N 2 O, NO, NO 2, and the like) and a copper atom. It is preferable to use a material. Alternatively, a conductive material having a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) is preferably used. When the conductor 560a has a function of suppressing the diffusion of oxygen, the conductivity of the conductor 560b can be suppressed from being oxidized by oxygen contained in the insulator 550 and thus reduced. For example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used as the conductive material having a function of suppressing oxygen diffusion.
  • the conductor 560b is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component.
  • the conductor 560b also functions as a wiring, and thus a conductor having high conductivity is preferably used.
  • a conductive material whose main component is tungsten, copper, or aluminum can be used.
  • the conductor 560b may have a stacked structure, for example, a stacked structure of titanium, titanium nitride, and the above conductive material.
  • the insulator 580 is provided over the conductor 542a and the conductor 542b with the insulator 544 provided therebetween.
  • the insulator 580 preferably has an excess oxygen region.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, oxide having voids It is preferable to have silicon or resin.
  • silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • silicon oxide and silicon oxide having holes are preferable because an excess oxygen region can be easily formed in a later step.
  • the insulator 580 preferably has an excess oxygen region. By providing the insulator 580 from which oxygen is released by heating in contact with the oxide 530c, oxygen in the insulator 580 can be efficiently supplied to the oxide 530 through the oxide 530c. Note that the concentration of impurities such as water or hydrogen in the insulator 580 is preferably reduced.
  • the opening of the insulator 580 is formed so as to overlap with a region between the conductor 542a and the conductor 542b.
  • the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductors 542a and 542b.
  • the conductor 560 can have a shape with a high aspect ratio.
  • the conductor 560 since the conductor 560 is provided so as to be embedded in the opening of the insulator 580, the conductor 560 can be formed without collapsing during the process even when the conductor 560 has a high aspect ratio. Can do.
  • the insulator 574 is preferably provided in contact with the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 550.
  • an excess oxygen region can be provided in the insulator 550 and the insulator 580. Accordingly, oxygen can be supplied into the oxide 530 from the excess oxygen region.
  • a metal oxide containing one or more kinds selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like is used as the insulator 574. Can do.
  • aluminum oxide has a high barrier property and can suppress diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by a sputtering method can serve as an oxygen supply source and function as a barrier film for impurities such as hydrogen.
  • an insulator 581 functioning as an interlayer film is preferably provided over the insulator 574.
  • the insulator 581 preferably has reduced concentration of impurities such as water or hydrogen in the film.
  • the conductor 540a and the conductor 540b are disposed in openings formed in the insulator 581, the insulator 574, the insulator 580, and the insulator 544.
  • the conductors 540a and 540b are provided to face each other with the conductor 560 interposed therebetween.
  • the conductor 540a and the conductor 540b have the same structure as a conductor 546 and a conductor 548 described later.
  • An insulator 582 is provided on the insulator 581.
  • the insulator 582 is preferably formed using a substance having a barrier property against oxygen or hydrogen. Therefore, the insulator 582 can be formed using a material similar to that of the insulator 514.
  • the insulator 582 is preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.
  • aluminum oxide has a high blocking effect that prevents the film from permeating both oxygen and impurities such as hydrogen and moisture, which cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide included in the transistor 500 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 500.
  • an insulator 586 is provided on the insulator 582.
  • the insulator 586 can be formed using a material similar to that of the insulator 320.
  • parasitic capacitance generated between wirings can be reduced.
  • a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 586.
  • the insulator 520, the insulator 522, the insulator 524, the insulator 544, the insulator 580, the insulator 574, the insulator 581, the insulator 582, and the insulator 586 include the conductor 546, the conductor 548, and the like. Is embedded.
  • the conductor 546 and the conductor 548 function as a plug or a wiring connected to the capacitor 600, the transistor 500, or the transistor 300.
  • the conductor 546 and the conductor 548 can be provided using a material similar to that of the conductor 328 and the conductor 330.
  • the capacitor 600 includes a conductor 610, a conductor 620, and an insulator 630.
  • the conductor 612 may be provided over the conductor 546 and the conductor 548.
  • the conductor 612 functions as a plug connected to the transistor 500 or a wiring.
  • the conductor 610 functions as an electrode of the capacitor 600. Note that the conductor 612 and the conductor 610 can be formed at the same time.
  • the conductor 612 and the conductor 610 include a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing any of the above elements as a component (Tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film) or the like can be used.
  • indium tin oxide indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide added It is also possible to apply a conductive material such as indium tin oxide.
  • the conductor 612 and the conductor 610 have a single-layer structure; however, the structure is not limited thereto, and a stacked structure of two or more layers may be used.
  • a conductor having a high barrier property and a conductor having a high barrier property may be formed between a conductor having a barrier property and a conductor having a high conductivity.
  • a conductor 620 is provided so as to overlap with the conductor 610 with the insulator 630 interposed therebetween.
  • the conductor 620 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. In the case of forming simultaneously with other structures such as a conductor, Cu (copper), Al (aluminum), or the like, which is a low resistance metal material, may be used.
  • An insulator 650 is provided over the conductor 620 and the insulator 630.
  • the insulator 650 can be provided using a material similar to that of the insulator 320.
  • the insulator 650 may function as a planarization film that covers the concave and convex shapes below the insulator 650.
  • the transistor 500 of the semiconductor device described in this embodiment is not limited to the above structure.
  • structural examples that can be used for the transistor 500 will be described.
  • the transistor described below is a modified example of the transistor described above. Therefore, in the following description, different points are mainly described, and the same points may be omitted.
  • FIG. 20A is a top view of the transistor 500A.
  • FIG. 20B is a cross-sectional view taken along dashed-dotted line L1-L2 in FIG.
  • FIG. 20C is a cross-sectional view illustrating a portion indicated by dashed-dotted line W1-W2 in FIG. Note that in the top view of FIG. 20A, some elements are not illustrated for the sake of clarity.
  • the transistor 500A, the insulator 511 functioning as an interlayer film, the insulator 512, the insulator 514, the insulator 516, the insulator 580, the insulator 574, and the insulator A body 581 is shown.
  • a conductor 540a and a conductor 540b that are electrically connected to the transistor 500A and function as contact plugs, and a conductor 505 that functions as a wiring are illustrated.
  • the transistor 500A includes a conductor 560 (a conductor 560a and a conductor 560b) that functions as a first gate electrode, a conductor 503 (a conductor 503a and a conductor 503b) that functions as a second gate electrode, An insulator 550 functioning as a first gate insulating film, an insulator 520 functioning as a second gate insulating film, an insulator 522, an insulator 524, and an oxide 530 having a region where a channel is formed (oxide) 530a, an oxide 530b, and an oxide 530c), a conductor 542a functioning as one of a source and a drain, a conductor 542b functioning as the other of a source and a drain, and an insulator 544.
  • a conductor 560 a conductor 560a and a conductor 560b
  • An insulator 550 functioning as a first gate insulating film
  • an insulator 520 functioning as a second gate
  • the oxide 530c, the insulator 550, and the conductor 560 are disposed in the opening provided in the insulator 580 with the insulator 544 interposed therebetween.
  • the oxide 530c, the insulator 550, and the conductor 560 are disposed between the conductor 542a and the conductor 542b.
  • the insulator 511 and the insulator 512 function as an interlayer film.
  • An insulator such as TiO 3 (BST) can be used in a single layer or a stacked layer.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators.
  • these insulators may be nitrided. Silicon insulator, silicon oxynitride, or silicon nitride may be stacked over the above insulator.
  • the insulator 511 preferably functions as a barrier film that suppresses impurities such as water or hydrogen from entering the transistor 500A from the substrate side. Therefore, the insulator 511 is preferably formed using an insulating material having a function of suppressing diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, and a copper atom (the impurity is difficult to transmit). Alternatively, it is preferable to use an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules). For example, aluminum oxide, silicon nitride, or the like may be used as the insulator 511. With this structure, impurities such as hydrogen and water can be prevented from diffusing from the substrate side to the transistor 500A side with respect to the insulator 511.
  • the insulator 512 preferably has a lower dielectric constant than the insulator 511.
  • parasitic capacitance generated between the wirings can be reduced.
  • the conductor 505 is formed so as to be embedded in the insulator 512.
  • the height of the upper surface of the conductor 505 and the height of the upper surface of the insulator 512 can be approximately the same.
  • the conductor 505 has a single-layer structure, the present invention is not limited to this.
  • the conductor 505 may have a multilayer film structure including two or more layers.
  • the conductor 505 is preferably formed using a highly conductive material whose main component is tungsten, copper, or aluminum.
  • the conductor 560 may function as a first gate (also referred to as a top gate) electrode.
  • the conductor 503 may function as a second gate (also referred to as a bottom gate) electrode.
  • the threshold voltage of the transistor 500A can be controlled by independently changing the potential applied to the conductor 503 without being linked to the potential applied to the conductor 560.
  • the threshold voltage of the transistor 500A can be higher than 0 V and the off-state current can be reduced. Therefore, when a negative potential is applied to the conductor 503, the drain current when the potential applied to the conductor 560 is 0 V can be made smaller than when a negative potential is not applied.
  • the conductor 560 and the conductor 503 when a potential is applied to the conductor 560 and the conductor 503 by overlapping the conductor 503 and the conductor 560, an electric field generated from the conductor 560 and an electric field generated from the conductor 503 are used. And the channel formation region formed in the oxide 530 can be covered.
  • the channel formation region can be electrically surrounded by the electric field of the conductor 560 functioning as the first gate electrode and the electric field of the conductor 503 functioning as the second gate electrode.
  • a transistor structure that electrically surrounds a channel formation region by an electric field of the first gate electrode and the second gate electrode is referred to as a surrounded channel (S-channel) structure.
  • the insulator 514 and the insulator 516 function as interlayer films similarly to the insulator 511 or the insulator 512.
  • the insulator 514 preferably functions as a barrier film that prevents impurities such as water or hydrogen from entering the transistor 500A from the substrate side. With this structure, diffusion of impurities such as hydrogen and water from the substrate side to the transistor 500A side than the insulator 514 can be suppressed.
  • the insulator 516 preferably has a lower dielectric constant than the insulator 514. By using a material having a low dielectric constant as the interlayer film, parasitic capacitance generated between the wirings can be reduced.
  • the conductor 503 functioning as the second gate, the conductor 503a is formed in contact with the inner walls of the openings of the insulator 514 and the insulator 516, and the conductor 503b is further formed inside.
  • the height of the upper surfaces of the conductors 503a and 503b and the height of the upper surface of the insulator 516 can be approximately the same.
  • the transistor 500A illustrates a structure in which the conductors 503a and 503b are stacked, the present invention is not limited thereto.
  • the conductor 503 may be provided as a single layer or a stacked structure including three or more layers.
  • the conductor 503a is preferably formed using a conductive material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the impurities are difficult to permeate).
  • a conductive material having a function of suppressing diffusion of oxygen for example, at least one of an oxygen atom and an oxygen molecule
  • the oxygen hardly transmits.
  • the function of suppressing diffusion of impurities or oxygen is a function of suppressing diffusion of any one or all of the impurities and oxygen.
  • the conductor 503a since the conductor 503a has a function of suppressing the diffusion of oxygen, it can be suppressed that the conductor 503b is oxidized and the conductivity is lowered.
  • the conductor 503b is preferably formed using a highly conductive material mainly containing tungsten, copper, or aluminum. In that case, the conductor 505 is not necessarily provided. Note that although the conductor 503b is illustrated as a single layer, it may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above conductive material.
  • the insulator 520, the insulator 522, and the insulator 524 function as a second gate insulating film.
  • the insulator 522 preferably has a barrier property.
  • the insulator 522 functions as a layer that suppresses entry of impurities such as hydrogen from the peripheral portion of the transistor 500A to the transistor 500A.
  • FIG. 20 illustrates a three-layer stacked structure as the second gate insulating film
  • a single-layer structure or a stacked structure of two or more layers may be used. In that case, it is not limited to the laminated structure which consists of the same material, The laminated structure which consists of a different material may be sufficient.
  • the oxide 530 having a region functioning as a channel formation region includes an oxide 530a, an oxide 530b over the oxide 530a, and an oxide 530c over the oxide 530b.
  • an oxide 530a below the oxide 530b, diffusion of impurities from the structure formed below the oxide 530a to the oxide 530b can be suppressed.
  • the oxide 530c over the oxide 530b, diffusion of impurities from the structure formed above the oxide 530c to the oxide 530b can be suppressed.
  • the oxide 530 an oxide semiconductor which is a kind of the metal oxide described above can be used.
  • the oxide 530 c is preferably provided in the opening provided in the insulator 580 through the insulator 544. In the case where the insulator 544 has barrier properties, diffusion of impurities from the insulator 580 into the oxide 530 can be suppressed.
  • the conductor 542a functions as one of a source electrode or a drain electrode
  • the conductor 542b functions as the other of the source electrode or the drain electrode.
  • a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing the metal as a main component can be used.
  • a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen and has high oxidation resistance.
  • a laminated structure of two or more layers may be used.
  • a tantalum nitride film and a tungsten film are preferably stacked.
  • a titanium film and an aluminum film may be stacked.
  • a two-layer structure in which an aluminum film is stacked on a tungsten film a two-layer structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked on a titanium film, and a tungsten film
  • a two-layer structure in which copper films are stacked may be used.
  • a titanium film or a titanium nitride film and a three-layer structure in which an aluminum film or a copper film is laminated on the titanium film or the titanium nitride film, and a titanium film or a titanium nitride film is further formed thereon, a molybdenum film or
  • a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.
  • a barrier layer may be provided over the conductor 542a and the conductor 542b.
  • a substance having a barrier property against oxygen or hydrogen is preferably used. With this structure, oxidation of the conductors 542a and 542b can be suppressed when the insulator 544 is formed.
  • a metal oxide for example, a metal oxide can be used.
  • an insulating film having a barrier property against oxygen and hydrogen such as aluminum oxide, hafnium oxide, and gallium oxide, is preferably used.
  • silicon nitride formed by a CVD method may be used.
  • the material selection range of the conductor 542a and the conductor 542b can be widened.
  • the conductor 542a and the conductor 542b can be formed using a material having low conductivity but high conductivity such as tungsten or aluminum.
  • a conductor that can be easily formed or processed can be used.
  • the insulator 550 functions as a first gate insulating film.
  • the insulator 550 is preferably provided in the opening provided in the insulator 580 through the oxide 530c and the insulator 544.
  • the insulator 550 may have a stacked layer structure like the second gate insulating film.
  • the insulator that functions as a gate insulating film has a stacked structure of a high-k material and a thermally stable material, so that the gate potential during transistor operation can be reduced while maintaining the physical film thickness. It becomes.
  • the conductor 560 functioning as the first gate electrode includes a conductor 560a and a conductor 560b over the conductor 560a.
  • the conductor 560a is preferably formed using a conductive material having a function of suppressing diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, and a copper atom, like the conductor 503a.
  • a conductive material having a function of suppressing diffusion of oxygen for example, at least one of oxygen atoms and oxygen molecules is preferably used.
  • the conductor 560a has a function of suppressing the diffusion of oxygen, the material selectivity of the conductor 560b can be improved. That is, by including the conductor 560a, oxidation of the conductor 560b can be suppressed and reduction in conductivity can be prevented.
  • the conductive material having a function of suppressing oxygen diffusion for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used.
  • the conductor 560a an oxide semiconductor that can be used as the oxide 530 can be used. In that case, by forming the conductor 560b by a sputtering method, the electrical resistance value of the conductor 560a can be reduced to obtain a conductor. This can be called an OC (Oxide Conductor) electrode.
  • the conductive material 560b is preferably formed using a conductive material mainly containing tungsten, copper, or aluminum.
  • a conductor having high conductivity is preferably used.
  • a conductive material whose main component is tungsten, copper, or aluminum can be used.
  • the conductor 560b may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above conductive material.
  • An insulator 544 is provided between the insulator 580 and the transistor 500A.
  • an insulating material having a function of suppressing diffusion of impurities such as water or hydrogen and oxygen is preferably used.
  • aluminum oxide or hafnium oxide is preferably used.
  • metal oxide such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.
  • the insulator 544 By including the insulator 544, it is possible to suppress diffusion of impurities such as water and hydrogen contained in the insulator 580 into the oxide 530b through the oxide 530c and the insulator 550. Further, the conductor 560 can be prevented from being oxidized by excess oxygen which the insulator 580 has.
  • the insulator 580, the insulator 574, and the insulator 581 function as an interlayer film.
  • the insulator 574 preferably functions as a barrier insulating film that suppresses entry of impurities such as water or hydrogen into the transistor 500A from the outside.
  • the insulator 580 and the insulator 581 preferably have a lower dielectric constant than the insulator 574.
  • parasitic capacitance generated between the wirings can be reduced.
  • the transistor 500A may be electrically connected to another structure through a plug or a wiring of the insulator 580, the insulator 574, and the conductor 540a and the conductor 540b embedded in the insulator 581. .
  • a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is used as a single layer or a stacked layer.
  • a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity.
  • low resistance conductive materials such as aluminum and copper. Wiring resistance can be lowered by using a low-resistance conductive material.
  • the conductor 540a and the conductor 540b for example, a stacked structure of tantalum nitride, which is a conductor having a barrier property against hydrogen and oxygen, and tungsten having high conductivity can be used. The diffusion of impurities from the outside can be suppressed while maintaining the electrical conductivity as described above.
  • a semiconductor device including a transistor including an oxide semiconductor with high on-state current can be provided.
  • a semiconductor device including a transistor including an oxide semiconductor with low off-state current can be provided.
  • FIG. 21A is a top view of the transistor 500B.
  • FIG. 21B is a cross-sectional view illustrating a portion indicated by dashed-dotted line L1-L2 in FIG.
  • FIG. 21C is a cross-sectional view illustrating a portion indicated by dashed-dotted line W1-W2 in FIG. Note that for simplification of the drawing, some components are not illustrated in the top view in FIG.
  • Transistor 500B is a modification of transistor 500A. Therefore, in order to prevent repeated description, differences from the transistor 500A are mainly described.
  • the transistor 500B includes a region where the conductor 542a (conductor 542b), the oxide 530c, the insulator 550, and the conductor 560 overlap with each other. With such a structure, a transistor with high on-state current can be provided. In addition, a transistor with high controllability can be provided.
  • the conductor 560 functioning as the first gate electrode includes a conductor 560a and a conductor 560b over the conductor 560a.
  • the conductor 560a is preferably formed using a conductive material having a function of suppressing diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, and a copper atom, like the conductor 503a.
  • a conductive material having a function of suppressing diffusion of oxygen for example, at least one of oxygen atoms and oxygen molecules is preferably used.
  • the conductor 560a has a function of suppressing the diffusion of oxygen, the material selectivity of the conductor 560b can be improved. That is, by including the conductor 560a, oxidation of the conductor 560b can be suppressed and reduction in conductivity can be prevented.
  • the insulator 544 is preferably provided so as to cover the top surface and the side surface of the conductor 560, the side surface of the insulator 550, and the side surface of the oxide 530c.
  • the insulator 544 is preferably formed using an insulating material having a function of suppressing diffusion of impurities such as water or hydrogen and oxygen.
  • aluminum oxide or hafnium oxide is preferably used.
  • metal oxide such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.
  • oxidation of the conductor 560 can be suppressed.
  • diffusion of water and impurities such as hydrogen included in the insulator 580 into the transistor 500B can be suppressed.
  • the contact plug of the transistor 500B is different from the configuration of the contact plug of the transistor 500A.
  • an insulator 576a (insulator 576b) having a barrier property is provided between the conductor 546a (conductor 546b) functioning as a contact plug and the insulator 580.
  • oxygen in the insulator 580 can be prevented from reacting with the conductor 546 and the conductor 546 being oxidized.
  • insulator 576a (insulator 576b) having a barrier property
  • the range of selection of materials for conductors used for plugs and wirings can be widened.
  • a low power consumption semiconductor device can be provided by using a metal material having high conductivity while absorbing oxygen for the conductor 546a (conductor 546b).
  • a material having high conductivity while having low oxidation resistance such as tungsten or aluminum can be used.
  • a conductor that can be easily formed or processed can be used.
  • FIG. 22A is a top view of the transistor 500C.
  • 22B is a cross-sectional view illustrating a portion indicated by dashed-dotted line L1-L2 in FIG.
  • FIG. 22C is a cross-sectional view taken along dashed-dotted line W1-W2 in FIG. Note that in the top view of FIG. 22A, some elements are omitted for clarity.
  • the transistor 500C is a modification of the transistor 500A. Therefore, in order to prevent repeated description, differences from the transistor 500A are mainly described.
  • a conductor 547a is disposed between the conductor 542a and the oxide 530b
  • a conductor 547b is disposed between the conductor 542b and the oxide 530b.
  • the conductor 542a extends beyond the top surface of the conductor 547a (conductor 547b) and the side surface on the conductor 560 side, and has a region in contact with the top surface of the oxide 530b.
  • a conductor that can be used for the conductor 542a and the conductor 542b may be used.
  • the conductors 547a and 547b are preferably thicker than the conductors 542a and 542b.
  • the conductor 542a and the conductor 542b can be made closer to the conductor 560 than the transistor 500A.
  • the conductor 560 can overlap the end portion of the conductor 542a and the end portion of the conductor 542b. Accordingly, the substantial channel length of the transistor 500C can be shortened, and the on-current and the frequency characteristics can be improved.
  • the conductor 547a (conductor 547b) is preferably provided so as to overlap with the conductor 542a (conductor 542b).
  • the conductor 547a (conductor 547b) functions as a stopper, and the oxide 530b is over-etched. Can be prevented.
  • the 22 may have a structure in which the insulator 545 is provided in contact with the insulator 544.
  • the insulator 544 preferably functions as a barrier insulating film which suppresses entry of impurities such as water or hydrogen and excess oxygen into the transistor 500C from the insulator 580 side.
  • an insulator that can be used for the insulator 544 can be used.
  • a nitride insulator such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride, or silicon nitride oxide may be used.
  • the conductor 503 may be provided with a single-layer structure.
  • an insulating film to be the insulator 516 is formed over the patterned conductor 503, and the upper portion of the insulating film is removed by a CMP method or the like until the upper surface of the conductor 503 is exposed.
  • the flatness of the upper surface of the conductor 503 is preferably improved.
  • the average surface roughness (Ra) of the upper surface of the conductor 503 may be 1 nm or less, preferably 0.5 nm or less, more preferably 0.3 nm or less. Accordingly, the flatness of the insulating layer formed over the conductor 503 can be improved, and the crystallinity of the oxide 530b and the oxide 530c can be improved.
  • FIG. 23A is a top view of the transistor 500D.
  • FIG. 23B is a cross-sectional view taken along dashed-dotted line L1-L2 in FIG.
  • FIG. 23C is a cross-sectional view taken along dashed-dotted line W1-W2 in FIG. Note that for simplification of the drawing, some components are not illustrated in the top view in FIG.
  • Transistor 500D is a modification of the above transistor. Therefore, in order to prevent the description from being repeated, differences from the above transistor will be mainly described.
  • the transistor 500D illustrated in FIGS. 23A to 23C does not include the conductor 505, and the conductor 503 functioning as a second gate can be used as a wiring. It is functioning.
  • the insulator 550 is provided over the oxide 530c, and the metal oxide 552 is provided over the insulator 550.
  • the conductor 560 is provided over the metal oxide 552 and the insulator 570 is provided over the conductor 560.
  • the insulator 571 is provided over the insulator 570.
  • the metal oxide 552 preferably has a function of suppressing oxygen diffusion.
  • the metal oxide 552 that suppresses diffusion of oxygen between the insulator 550 and the conductor 560 diffusion of oxygen into the conductor 560 is suppressed. That is, a decrease in the amount of oxygen supplied to the oxide 530 can be suppressed. Further, oxidation of the conductor 560 due to oxygen can be suppressed.
  • the metal oxide 552 may function as a part of the first gate.
  • an oxide semiconductor that can be used as the oxide 530 can be used as the metal oxide 552.
  • the conductor 560 by forming the conductor 560 by a sputtering method, the electric resistance value of the metal oxide 552 can be reduced to form a conductive layer. This can be called an OC (Oxide Conductor) electrode.
  • the metal oxide 552 may function as a part of the gate insulating film. Therefore, in the case where silicon oxide, silicon oxynitride, or the like is used for the insulator 550, the metal oxide 552 is preferably a metal oxide that is a high-k material with a high relative dielectric constant. By setting it as the said laminated structure, it can be set as the laminated structure stable with respect to a heat
  • EOT equivalent oxide thickness
  • the metal oxide 552 is illustrated as a single layer; however, a stacked structure including two or more layers may be used.
  • a metal oxide that functions as part of the gate electrode and a metal oxide that functions as part of the gate insulating film may be stacked.
  • the on-state current of the transistor 500D can be improved without weakening the influence of the electric field from the conductor 560.
  • the distance between the conductor 560 and the oxide 530 is maintained by the physical thickness of the insulator 550 and the metal oxide 552, so that the conductor 560 Leakage current with the oxide 530 can be suppressed. Therefore, by providing a stacked structure of the insulator 550 and the metal oxide 552, the physical distance between the conductor 560 and the oxide 530 and the electric field strength applied from the conductor 560 to the oxide 530 can be reduced. It can be easily adjusted as appropriate.
  • an oxide semiconductor that can be used for the oxide 530 can be used as the metal oxide 552 by reducing the resistance.
  • a metal oxide containing one kind or two or more kinds selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used.
  • hafnium oxide aluminum
  • hafnium aluminate oxide containing hafnium
  • hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in a heat treatment in a later step.
  • the metal oxide 552 is not an essential component. What is necessary is just to design suitably according to the transistor characteristic to request
  • an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen may be used.
  • impurities such as water or hydrogen and oxygen
  • aluminum oxide or hafnium oxide is preferably used.
  • impurities such as water or hydrogen from above the insulator 570 can be prevented from entering the oxide 530 through the conductor 560 and the insulator 550.
  • the insulator 571 functions as a hard mask.
  • the side surface of the conductor 560 is substantially vertical.
  • the angle formed between the side surface of the conductor 560 and the substrate surface is 75 ° to 100 °, Preferably, it can be set to 80 degrees or more and 95 degrees or less.
  • the insulator 571 may also function as a barrier layer by using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. In that case, the insulator 570 is not necessarily provided.
  • insulator 571 By using the insulator 571 as a hard mask, a part of the insulator 570, the conductor 560, the metal oxide 552, the insulator 550, and the oxide 530c is selectively removed, so that these side surfaces are substantially matched. In addition, a part of the surface of the oxide 530b can be exposed.
  • the transistor 500D includes a region 531a and a region 531b in part of the exposed surface of the oxide 530b.
  • One of the region 531a and the region 531b functions as a source region, and the other functions as a drain region.
  • the formation of the region 531a and the region 531b is performed by introducing an impurity element such as phosphorus or boron into the exposed oxide 530b surface by using, for example, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or a plasma treatment. This can be achieved.
  • an impurity element such as phosphorus or boron
  • an ion implantation method an ion doping method
  • a plasma immersion ion implantation method or a plasma treatment.
  • the “impurity element” in this embodiment and the like refers to an element other than the main component elements.
  • a metal film is formed after part of the surface of the oxide 530b is exposed, and then heat treatment is performed, whereby an element included in the metal film is diffused into the oxide 530b to form the region 531a and the region 531b.
  • the region 531a and the region 531b may be referred to as “impurity region” or “low resistance region”.
  • the region 531a and the region 531b can be formed in a self-alignment manner. Therefore, the region 531a and / or the region 531b does not overlap with the conductor 560, so that parasitic capacitance can be reduced. Further, no offset region is formed between the channel formation region and the source / drain region (the region 531a or the region 531b). By forming the region 531a and the region 531b in a self-alignment manner, an increase in on-state current, a reduction in threshold voltage, an improvement in operating frequency, and the like can be realized.
  • an offset region may be provided between the channel formation region and the source / drain region in order to further reduce the off-state current.
  • the offset region is a region having a high electrical resistivity and is a region where the impurity element is not introduced.
  • the offset region can be formed by introducing the impurity element described above after the insulator 575 is formed.
  • the insulator 575 functions as a mask similarly to the insulator 571 and the like. Therefore, the impurity element is not introduced into the region overlapping with the insulator 575 of the oxide 530b, and the electrical resistivity of the region can be kept high.
  • the transistor 500D includes the insulator 575 on the side surfaces of the insulator 570, the conductor 560, the metal oxide 552, the insulator 550, and the oxide 530c.
  • the insulator 575 is preferably an insulator having a low relative dielectric constant.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having a hole for the insulator 575 because an excess oxygen region can be easily formed in the insulator 575 in a later step.
  • Silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • the insulator 575 preferably has a function of diffusing oxygen.
  • the transistor 500D includes the insulator 575 and the insulator 544 over the oxide 530.
  • the insulator 544 is preferably formed by a sputtering method. By using a sputtering method, an insulator with few impurities such as water or hydrogen can be formed. For example, aluminum oxide may be used as the insulator 544.
  • an oxide film formed by a sputtering method may extract hydrogen from a deposition target structure. Therefore, the insulator 544 absorbs hydrogen and water from the oxide 530 and the insulator 575, whereby the hydrogen concentration in the oxide 530 and the insulator 575 can be reduced.
  • FIG. 24A is a top view of the transistor 500E.
  • FIG. 24B is a cross-sectional view taken along dashed-dotted line L1-L2 in FIG.
  • FIG. 24C is a cross-sectional view illustrating a portion indicated by dashed-dotted line W1-W2 in FIG. Note that in the top view of FIG. 24A, some elements are omitted for clarity.
  • Transistor 500E is a modification of the above transistor. Therefore, in order to prevent the description from being repeated, differences from the above transistor will be mainly described.
  • a region 531a and a region 531b are provided in part of the exposed surface of the oxide 530b without providing the conductor 542a and the conductor 542b.
  • One of the region 531a and the region 531b functions as a source region, and the other functions as a drain region.
  • an insulator 573 is provided between the oxide 530b and the insulator 544.
  • a region 531a and a region 531b are regions in which the following elements are added to the oxide 530b.
  • the region 531a and the region 531b can be formed by using a dummy gate, for example.
  • a dummy gate may be provided over the oxide 530b, and the dummy gate may be used as a mask, and an element for reducing the resistance of a part of the oxide 530b may be added. That is, the element is added to a region where the oxide 530 does not overlap with the dummy gate, so that the region 531a and the region 531b are formed.
  • an ion implantation method in which an ionized source gas is added by mass separation an ion doping method in which an ionized source gas is added without mass separation, a plasma immersion ion implantation method, or the like Can be used.
  • boron or phosphorus is given as an element for reducing the resistance of part of the oxide 530b.
  • hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, rare gas, or the like may be used.
  • the rare gas include helium, neon, argon, krypton, and xenon. What is necessary is just to measure the density
  • boron and phosphorus can be added to an Si transistor manufacturing line apparatus in which amorphous silicon, low-temperature polysilicon, or the like is contained in a semiconductor layer. Therefore, by using the manufacturing line apparatus, one of oxides 530b can be added. The resistance of the part can be reduced. That is, part of the Si transistor manufacturing line can be used for the manufacturing process of the transistor 500E.
  • an insulating film to be the insulator 573 and an insulating film to be the insulator 544 may be formed over the oxide 530b and the dummy gate.
  • a CMP (Chemical Mechanical Polishing) process is performed on the insulating film to be the insulator 580.
  • a part of the insulating film is removed to expose the dummy gate.
  • part of the insulator 573 in contact with the dummy gate may be removed. Therefore, the insulator 544 and the insulator 573 are exposed on the side surface of the opening provided in the insulator 580, and the region 531a and the region 531b provided in the oxide 530b are exposed on the bottom surface of the opening. Each part is exposed.
  • an oxide film to be the oxide 530c, an insulating film to be the insulator 550, and a conductive film to be the conductor 560 are sequentially formed in the opening, CMP treatment or the like is performed until the insulator 580 is exposed.
  • the transistor illustrated in FIG. 24 can be formed by removing part of the oxide film to be the oxide 530c, the insulating film to be the insulator 550, and the conductive film to be the conductor 560.
  • the insulator 573 and the insulator 544 are not essential components. What is necessary is just to design suitably according to the transistor characteristic to request
  • FIG. 19 illustrates the structural example in which the conductor 560 functioning as a gate is formed inside the opening of the insulator 580.
  • the insulator is disposed above the conductor.
  • the provided structure can also be used. Examples of the structure of such a transistor are shown in FIGS.
  • FIG. 25A is a top view of the transistor
  • FIG. 25B is a perspective view of the transistor.
  • a cross-sectional view taken along line L1-L2 in FIG. 25A is shown in FIG. 26A
  • a cross-sectional view taken along W1-W2 is shown in FIG.
  • the transistors illustrated in FIGS. 25 and 26 each include a conductor BGE that functions as a back gate, an insulator BGI that functions as a gate insulating film, an oxide semiconductor S, and an insulating film that functions as a gate insulating film.
  • the conductor PE has a function as a plug for connecting the conductor WE to the oxide S, the conductor BGE, or the conductor FGE.
  • the oxide semiconductor S includes three layers of oxides S1, S2, and S3 is shown.
  • a metal oxide that can be used for the OS transistor described in any of the above embodiments a CAC-OS (Cloud-Aligned Composite Oxide Semiconductor), and a CAAC-OS (C-axis Aligned Crystal Oxide Semiconductor Semiconductor).
  • CAC represents an example of a function or a structure of a material
  • CAAC represents an example of a crystal structure.
  • the CAC-OS or the CAC-metal oxide has a conductive function in part of the material and an insulating function in part of the material, and the whole material has a function as a semiconductor.
  • the conductive function is a function of flowing electrons (or holes) serving as carriers
  • the insulating function is an electron serving as carriers. It is a function that does not flow.
  • the CAC-OS or the CAC-metal oxide has a conductive region and an insulating region.
  • the conductive region has the above-described conductive function
  • the insulating region has the above-described insulating function.
  • the conductive region and the insulating region may be separated at the nanoparticle level.
  • the conductive region and the insulating region may be unevenly distributed in the material, respectively.
  • the conductive region may be observed with the periphery blurred and connected in a cloud shape.
  • the conductive region and the insulating region are dispersed in the material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm, respectively. There is.
  • CAC-OS or CAC-metal oxide is composed of components having different band gaps.
  • CAC-OS or CAC-metal oxide includes a component having a wide gap caused by an insulating region and a component having a narrow gap caused by a conductive region.
  • the carrier when the carrier flows, the carrier mainly flows in the component having the narrow gap.
  • the component having a narrow gap acts in a complementary manner to the component having a wide gap, and the carrier flows through the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the CAC-OS or the CAC-metal oxide is used for a channel formation region of a transistor, high current driving force, that is, high on-state current and high field-effect mobility can be obtained in the on-state of the transistor.
  • CAC-OS or CAC-metal oxide can also be called a matrix composite (metal matrix composite) or a metal matrix composite (metal matrix composite).
  • An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor.
  • a non-single-crystal oxide semiconductor for example, a CAAC-OS, a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline line semiconductor), a pseudo-amorphous oxide semiconductor (a-like OS), and Examples include amorphous oxide semiconductors.
  • the CAAC-OS has a c-axis orientation and a crystal structure in which a plurality of nanocrystals are connected in the ab plane direction and has a strain.
  • the strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned in a region where a plurality of nanocrystals are connected.
  • Nanocrystals are based on hexagons, but are not limited to regular hexagons and may be non-regular hexagons.
  • a lattice arrangement such as a pentagon and a heptagon in terms of distortion.
  • a clear crystal grain boundary also referred to as a grain boundary
  • the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal elements. This is probably because of this.
  • the CAAC-OS is a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer including elements M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers) are stacked.
  • In layer a layer containing indium and oxygen
  • M, Zn elements M, zinc, and oxygen
  • indium and the element M can be replaced with each other, and when the element M in the (M, Zn) layer is replaced with indium, it can also be expressed as an (In, M, Zn) layer. Further, when indium in the In layer is replaced with the element M, it can also be expressed as an (In, M) layer.
  • CAAC-OS is an oxide semiconductor with high crystallinity.
  • CAAC-OS cannot confirm a clear crystal grain boundary, it can be said that a decrease in electron mobility due to the crystal grain boundary hardly occurs.
  • the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of the oxide semiconductor including a CAAC-OS are stable. Therefore, an oxide semiconductor including a CAAC-OS is resistant to heat and has high reliability.
  • the CAAC-OS is stable even at a high temperature (so-called thermal budget) in the manufacturing process. Therefore, when a CAAC-OS is used for the OS transistor, the degree of freedom in the manufacturing process can be increased.
  • Nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm).
  • the nc-OS has no regularity in crystal orientation between different nanocrystals. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.
  • the a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor.
  • the a-like OS has a void or a low density region. That is, the a-like OS has lower crystallinity than the nc-OS and the CAAC-OS.
  • Oxide semiconductors have various structures and have different characteristics.
  • the oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.
  • the oxide semiconductor for a transistor, a transistor with high field-effect mobility can be realized. In addition, a highly reliable transistor can be realized.
  • an oxide semiconductor with low carrier concentration is preferably used.
  • the impurity concentration in the oxide semiconductor film may be decreased and the defect state density may be decreased.
  • a low impurity concentration and a low density of defect states are referred to as high purity intrinsic or substantially high purity intrinsic.
  • an oxide semiconductor is less than the carrier concentration of 8 ⁇ 10 11 cm -3, preferably less than 1 ⁇ 10 11 cm -3, more preferably less than 1 ⁇ 10 10 cm- 3, 1 ⁇ 10 -9 cm -3 or more.
  • a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low defect level density and thus may have a low trap level density.
  • the charge trapped in the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap state density may have unstable electrical characteristics.
  • Impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon, and the like.
  • the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon in the vicinity of the interface with the oxide semiconductor are 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less.
  • the oxide semiconductor contains an alkali metal or an alkaline earth metal
  • a defect level may be formed and carriers may be generated. Therefore, a transistor including an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to be normally on. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor.
  • the concentration of an alkali metal or an alkaline earth metal in an oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less.
  • the nitrogen in the oxide semiconductor is preferably reduced as much as possible.
  • the nitrogen concentration in the oxide semiconductor is less than 5 ⁇ 10 19 atoms / cm 3 in SIMS, preferably 5 ⁇ 10 18. atoms / cm 3 or less, more preferably 1 ⁇ 10 18 atoms / cm 3 or less, and even more preferably 5 ⁇ 10 17 atoms / cm 3 or less.
  • the oxide semiconductor reacts with oxygen bonded to a metal atom to become water, so that an oxygen vacancy may be formed in some cases.
  • an oxygen vacancy may be formed in some cases.
  • electrons serving as carriers may be generated.
  • a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor including an oxide semiconductor containing hydrogen is likely to be normally on. For this reason, it is preferable that hydrogen in the oxide semiconductor be reduced as much as possible.
  • the hydrogen concentration obtained by SIMS is less than 1 ⁇ 10 20 atoms / cm 3 , preferably less than 1 ⁇ 10 19 atoms / cm 3 , more preferably 5 ⁇ 10 18 atoms / cm 3. Less than 3 , more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • Stable electrical characteristics can be provided by using an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor.
  • FIG. 27A illustrates a laptop personal computer which is a kind of information terminal device, which includes a housing 5401, a display portion 5402, a keyboard 5403, a pointing device 5404, and the like.
  • FIG. 27B illustrates a smart watch which is a kind of wearable terminal, which includes a housing 5901, a display portion 5902, operation buttons 5903, operation elements 5904, a band 5905, and the like.
  • a display device to which a function as a position input device is added may be used for the display portion 5902.
  • the function as a position input device can be added by providing a touch panel on the display device.
  • the function as a position input device can be added by providing a photoelectric conversion element called a photosensor in a pixel portion of a display device.
  • the operation button 5903 can be provided with any one of a power switch for starting a smart watch, a button for operating a smart watch application, a volume adjustment button, a switch for turning on or off the display portion 5902, and the like.
  • the number of operation buttons 5903 is two, but the number of operation buttons included in the smart watch is not limited thereto.
  • the operation element 5904 functions as a crown for adjusting the time of the smart watch. Further, the operation element 5904 may be used as an input interface for operating the smartwatch application in addition to the time adjustment. Note that the smart watch illustrated in FIG. 27B includes the operation element 5904; however, the present invention is not limited to this and may have a structure without the operation element 5904.
  • a video camera illustrated in FIG. 27C includes a first housing 5801, a second housing 5802, a display portion 5803, operation keys 5804, a lens 5805, a connection portion 5806, and the like.
  • the operation key 5804 and the lens 5805 are provided in the first housing 5801
  • the display portion 5803 is provided in the second housing 5802.
  • the first housing 5801 and the second housing 5802 are connected by a connection portion 5806, and the angle between the first housing 5801 and the second housing 5802 can be changed by the connection portion 5806. is there.
  • the video on the display portion 5803 may be switched in accordance with the angle between the first housing 5801 and the second housing 5802 in the connection portion 5806.
  • FIG. 27D illustrates a cellular phone having an information terminal function, which includes a housing 5501, a display portion 5502, a microphone 5503, a speaker 5504, and operation buttons 5505.
  • a display device to which a function as a position input device is added may be used for the display portion 5502.
  • the function as a position input device can be added by providing a touch panel on the display device.
  • the function as a position input device can be added by providing a photoelectric conversion element called a photosensor in a pixel portion of a display device.
  • the operation button 5505 can be provided with any one of a power switch for starting a mobile phone, a button for operating a mobile phone application, a volume adjustment button, a switch for turning on or off the display portion 5502, and the like.
  • the number of operation buttons 5505 is two, but the number of operation buttons included in the mobile phone is not limited to this.
  • the cellular phone illustrated in FIG. 27D may have a structure including a flashlight or a light-emitting device for illumination.
  • FIG. 27E illustrates a game machine body 7520 and a controller 7522 as stationary game machines.
  • a controller 7522 can be connected to the game machine body 7520 wirelessly or by wire.
  • the controller 7522 can include a display unit for displaying a game image, a touch panel or stick serving as an input interface other than buttons, a rotary knob, a slide knob, and the like.
  • the controller 7522 is not limited to the shape illustrated in FIG. 27E, and the shape of the controller 7522 may be variously changed depending on the game genre.
  • a controller having a shape imitating a gun with a trigger as a button can be used.
  • a controller shaped like a musical instrument or music device can be used.
  • the stationary game machine may be configured to use a game player's gesture and / or voice instead of using a controller, instead of including a camera, a depth sensor, a microphone, and the like.
  • a portable game machine shown in FIG. 27F includes a housing 5201, a display portion 5202, a button 5203, and the like. Note that the portable game machine illustrated in FIG. 27F is an example, and the arrangement, shape, and number of display portions and buttons of the portable game machine to which the semiconductor device of one embodiment of the present invention is applied are illustrated in FIG. It is not limited to the configuration shown in F). In addition, the shape of the housing of the portable game machine is not limited to the structure illustrated in FIG.
  • a stationary game machine a portable game machine, and the like are given as examples of game machines.
  • the semiconductor device of one embodiment of the present invention can be applied to an arcade game machine other than the above. can do.
  • a television device illustrated in FIG. 27G includes a housing 9000, a display portion 9001, a speaker 9003, operation keys 9005 (including a power switch and an operation switch), a connection terminal 9006, and the like.
  • the television device can incorporate a display portion 9001 having a large screen, for example, 50 inches or more, or 100 inches or more.
  • the semiconductor device of one embodiment of the present invention can be applied to the vicinity of a driver's seat of an automobile that is a moving body.
  • FIG. 27 (H) is a view showing the periphery of the windshield in the interior of an automobile.
  • FIG. 27H illustrates a display panel 5704 attached to a pillar in addition to the display panel 5701, the display panel 5702, and the display panel 5703 attached to the dashboard.
  • Display panels 5701 to 5703 can provide various information by displaying navigation information, speedometers and tachometers, travel distances, fuel gauges, gear states, air conditioner settings, and the like.
  • the display items, layout, and the like displayed on the display panel can be changed as appropriate according to the user's preference, and the design can be improved.
  • the display panels 5701 to 5703 can also be used as lighting devices.
  • the display panel 5704 can complement the view (dead angle) obstructed by the pillar by projecting an image from the imaging means provided on the vehicle body. That is, by displaying an image from the imaging means provided outside the automobile, the blind spot can be compensated and safety can be improved. Also, by displaying a video that complements the invisible part, it is possible to confirm the safety more naturally and without a sense of incongruity.
  • the display panel 5704 can also be used as a lighting device.
  • FIG. 28A illustrates an example of a digital signage (digital signage) that can be attached to a wall.
  • FIG. 28A shows a state where the electronic signboard 6200 is attached to the wall 6201.
  • FIG. 28B illustrates a tablet information terminal having a structure that can be folded.
  • An information terminal illustrated in FIG. 28B includes a housing 5321a, a housing 5321b, a display portion 5322, and operation buttons 5323.
  • the display portion 5322 has a flexible base material, and a structure that can be folded by the base material can be realized.
  • the housing 5321a and the housing 5321b are coupled by a hinge portion 5321c, and the hinge portion 5321c can be folded in half.
  • the display portion 5322 is provided in the housing 5321a, the housing 5321b, and the hinge portion 5321c.
  • the electronic devices illustrated in FIGS. 27A to 27C, 28E, and 28A and 28B may have a microphone and a speaker. With this configuration, for example, a voice input function can be added to the electronic device described above.
  • the electronic devices shown in FIGS. 27A, 27B, 27D, 28A, and 28B may have a camera.
  • the electronic devices shown in FIGS. 27A to 27F, FIGS. 28A and 28B are provided with sensors (force, displacement, position, speed, acceleration) inside the housing. Measure angular velocity, number of revolutions, distance, light, liquid, magnetism, temperature, chemical, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, smell or infrared It may be configured to have a function).
  • sensors force, displacement, position, speed, acceleration
  • a detection device having a sensor that detects a tilt, such as a gyroscope or an acceleration sensor, so that the orientation of the mobile phone (which direction the mobile phone is relative to the vertical direction)
  • the screen display of the display portion 5502 can be automatically switched according to the orientation of the mobile phone.
  • the electronic devices shown in FIGS. 27A to 27F, FIGS. 28A and 28B are devices that acquire biological information such as fingerprints, veins, irises, or voiceprints.
  • an electronic device having a biometric authentication function can be realized.
  • a flexible substrate may be used as the display portion of the electronic device shown in FIGS. 27A to 27E and FIG.
  • the display portion may have a structure in which a transistor, a capacitor element, a display element, and the like are provided over a flexible base material.
  • a material having a property of transmitting visible light is used as an example.
  • PET Polyethylene terephthalate resin
  • PEN polyethylene naphthalate resin
  • PES polyethersulfone resin
  • acrylic resin acrylic resin
  • polyimide resin polymethyl methacrylate resin
  • polycarbonate resin polyamide resin
  • polycycloolefin resin Polystyrene resin, polyamideimide resin, polypropylene resin, polyester resin, polyvinyl halide resin, aramid resin, epoxy resin, and the like can be used. These materials may be mixed or laminated.
  • FIG. 29 shows a block diagram of a circuit 150 configured by a circuit simulator.
  • the circuit 150 includes a neural network circuit ANN, a digital controller DCTR, a digital / analog conversion circuit DACx, a digital / analog conversion circuit DACw, and an XOR (exclusive OR) circuit LC.
  • the neural network circuit ANN is the arithmetic circuit 100 described in the first embodiment.
  • the memory cell array MCA has five rows, three columns of memory cells AM that hold the first data, three columns of memory cells AM that hold the first reference data, Memory cells AM holding 2 reference data are arranged in 3 columns.
  • the digital controller DCTR has a storage device for holding a plurality of parameters for input to the neural network circuit ANN.
  • the plurality of parameters are first data W [3: 0], second data X [3: 0], teacher data T, and the like.
  • the digital controller DCTR inputs the first data W [3: 0] (weight coefficient), which is a digital value, to the digital / analog conversion circuit DACw, converts the first data W [3: 0] into an analog value,
  • First data of values is input to the neural network circuit ANN. This operation corresponds to the operation of storing the first data, the first reference data, and the second reference data in the memory cell AM of the memory cell array MCA from the time T01 to the time T04 described in the operation example of the first embodiment. .
  • the digital controller DCTR inputs the second data X [3: 0], which is a digital value, to the digital-analog conversion circuit DACx, converts the second data X [3: 0] into an analog value, and converts the analog value
  • the first data is input to the neural network circuit ANN. This operation corresponds to the operation of applying a potential corresponding to the second data to the wiring VL [1] and the wiring VL [2] from the time T05 to the time T07 described in the operation example of Embodiment 1.
  • the digital controller DCTR inputs the teacher data T to the neural network circuit ANN.
  • This operation corresponds to the operation in which teacher data is input to the terminal gi3 of the learning circuit LEC from time T07 to time T08 described in the operation example of the first embodiment.
  • the digital controller DCTR has a function of inputting teacher data to the first input terminal of the XOR circuit LC.
  • the digital controller DCTR has a function of transmitting a command signal SIG to the neural network circuit ANN.
  • the neural network circuit ANN Upon receiving the instruction signal SIG, the neural network circuit ANN performs operations such as a product-sum operation of the first data and the second data, calculation of an activation function value, and updating of the first data using the teacher data. . Further, the neural network circuit ANN receives the command signal and transmits the result of the operation to the digital controller DCTR. In particular, the neural network circuit ANN transmits the calculation result data Y (corresponding to the calculation result data described in the first embodiment) as the calculated activation function value to the second input terminal of the XOR circuit LC.
  • the XOR circuit LC has a function of taking an exclusive OR of the teacher data T input to the first input terminal and the operation result data Y input to the second input terminal.
  • the XOR circuit LC transmits “0” to the digital controller when the teacher data and the operation result data match, and when the teacher data and the operation result data do not match, the XOR circuit LC outputs “0” as an error signal to the digital controller. 1 "is transmitted.
  • test data was classified in the circuit configuration shown in FIG.
  • an Iris data set (Fisher, RA (1936) The use of multiple measurements in taxomics. Anals of Eugenics, 7, Part II, 179-188.) was used.
  • the Iris data set includes data on the length and width of the sepals and petals of three types of iris flowers, Setosa, Versiccolor, and Virginia.
  • FIG. 30 is a distribution diagram in which Setosa and Versiccolor pieces (Petal Length) are plotted on the ordinate, and petals (Sepal Length) are plotted on the abscissa.
  • the plotted data is 50 each in Setosa and Versiccolor.
  • the first data W held in the memory cell AM of the neural network circuit ANN were inputted as the same value.
  • the first data W may be an arbitrary value or may be a random value.
  • the neural network circuit ANN is assumed to update the first data W one or more times during learning.
  • the two feature quantities of the sepal length and the petal length were converted into 8-bit binary numbers (digital values).
  • the feature value converted into the digital value was converted into an analog value by the digital-analog conversion circuit DACx, and the feature value converted into the analog value was input to the neural network circuit ANN as the second data X.
  • the feature amount is randomly selected from a total of 100 test data (50 each for Setosa and Versicoror).
  • the teacher data of the feature amount (second data X) is also input to the neural network circuit ANN.
  • the teacher data T input to the neural network circuit ANN is set to 0 for Setosa and 1 for Versiccolor.
  • Update of the first data W by learning is performed once every 4 ⁇ s.
  • the feature quantity and the teacher data T are randomly selected from the remaining test data and input to the neural network circuit ANN.
  • FIG. 31 the result of classification of Setosa and Versiccolor by the circuit 150 is shown in FIG.
  • the vertical axis indicates the potential output from the output terminal of the XOR circuit, and the horizontal axis indicates time.
  • the XOR circuit of the circuit 150 outputs a high level potential to the output terminal when the data input to the first input terminal and the second input terminal are different. That is, in FIG. 31, it can be seen that there are many inconsistencies between the calculation result data and the teacher data in the range from approximately 0 s to 500 ⁇ s. In addition, in the range from about 500 ⁇ s to 2.0 ms, there is a lot of coincidence between the calculation result data and the teacher data.
  • FIGS. 32A and 32B are graphs showing changes in the internal voltages of the circuit 150 when the first data (weighting factor) is updated 50 times.
  • FIG. 32A shows the potential output from the output terminal of the XOR circuit
  • FIG. 32B shows the wirings of the first and second rows for transmitting the update amount (of the arithmetic circuit 100 shown in FIG. 1).
  • the potentials of the wirings corresponding to HW [1] and HW [2] for transmitting the second reference data are shown.
  • the first data (weighting coefficient) is updated at the time when the high-level potential is output from the output terminal of the XOR circuit.
  • the first data can be updated by the arithmetic circuit 100 and learning is optimally performed.
  • MCA memory cell array
  • IS current supply circuit
  • WDD circuit
  • WLD circuit
  • VLD circuit
  • ACTV activation function circuit
  • LEC learning circuit
  • CS bias circuit
  • CM current mirror circuit
  • CS1 circuit
  • CS2 Circuit
  • CS3 Circuit
  • CS4 Circuit
  • CMx Circuit
  • CMw Circuit
  • CSx Circuit
  • CSxw Circuit
  • CSxw Circuit
  • CSxw Circuit
  • CSxw Circuit
  • BL Wiring, BLxr: Wiring, BLwr: Wiring, WD: Wiring, WDxr: Wiring WDwr: wiring

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2021229373A1 (https=) * 2020-05-15 2021-11-18
WO2023242666A1 (ja) * 2022-06-17 2023-12-21 株式会社半導体エネルギー研究所 半導体装置、及び電子機器
JP2024502785A (ja) * 2020-12-26 2024-01-23 インターナショナル・ビジネス・マシーンズ・コーポレーション 隠れ行列訓練ｄｎｎのフィルタリング
WO2025181636A1 (ja) * 2024-03-01 2025-09-04 株式会社半導体エネルギー研究所 半導体装置、演算装置及び電子機器

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11515873B2 (en) * 2018-06-29 2022-11-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic device
TWI846810B (zh) * 2019-02-15 2024-07-01 日商半導體能源研究所股份有限公司 半導體裝置及電子裝置
US12099543B2 (en) 2019-04-26 2024-09-24 Semiconductor Energy Laboratory Co., Ltd. Document search system and document search method
US11888446B2 (en) 2019-05-08 2024-01-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP7123860B2 (ja) * 2019-06-17 2022-08-23 株式会社東芝 演算装置
WO2020254914A1 (ja) 2019-06-21 2020-12-24 株式会社半導体エネルギー研究所 酸化物半導体を用いる記憶回路
EP3839833A1 (en) * 2019-12-16 2021-06-23 ams International AG Neural amplifier, neural network and sensor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016219011A (ja) * 2015-05-21 2016-12-22 株式会社半導体エネルギー研究所 電子装置
JP2017194963A (ja) * 2016-04-14 2017-10-26 株式会社半導体エネルギー研究所 半導体装置

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3533074B2 (ja) 1997-10-20 2004-05-31 日本電気株式会社 Ｖｒａｍ機能内蔵のｌｅｄパネル
JP5078246B2 (ja) 2005-09-29 2012-11-21 株式会社半導体エネルギー研究所 半導体装置、及び半導体装置の作製方法
JP5064747B2 (ja) 2005-09-29 2012-10-31 株式会社半導体エネルギー研究所 半導体装置、電気泳動表示装置、表示モジュール、電子機器、及び半導体装置の作製方法
EP3614442A3 (en) 2005-09-29 2020-03-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having oxide semiconductor layer and manufactoring method thereof
KR101371604B1 (ko) 2007-11-26 2014-03-06 삼성디스플레이 주식회사 액정 표시 장치
JP5491833B2 (ja) 2008-12-05 2014-05-14 株式会社半導体エネルギー研究所 半導体装置
EP2494597A4 (en) 2009-10-30 2015-03-18 Semiconductor Energy Lab SEMICONDUCTOR COMPONENT
JP2012058335A (ja) 2010-09-06 2012-03-22 Seiko Epson Corp 電気光学装置および電子機器
KR20120110387A (ko) 2011-03-29 2012-10-10 삼성전자주식회사 화소 회로 및 화소 회로의 구동 방법
CN106462020B (zh) 2014-04-25 2019-08-23 夏普株式会社 液晶显示装置
JP2017027012A (ja) 2015-07-24 2017-02-02 株式会社ジャパンディスプレイ 表示装置
US10140940B2 (en) 2015-07-24 2018-11-27 Japan Display Inc. Display device
KR102472837B1 (ko) 2017-08-11 2022-11-30 가부시키가이샤 한도오따이 에네루기 켄큐쇼 표시 장치 및 전자 기기
KR20250022260A (ko) 2017-08-31 2025-02-14 가부시키가이샤 한도오따이 에네루기 켄큐쇼 표시 장치 및 전자 기기
JP2019045614A (ja) 2017-08-31 2019-03-22 株式会社半導体エネルギー研究所 表示装置および電子機器
JP2019045613A (ja) 2017-08-31 2019-03-22 株式会社半導体エネルギー研究所 表示装置および電子機器
WO2019053549A1 (en) 2017-09-15 2019-03-21 Semiconductor Energy Laboratory Co., Ltd. DISPLAY DEVICE AND ELECTRONIC DEVICE

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016219011A (ja) * 2015-05-21 2016-12-22 株式会社半導体エネルギー研究所 電子装置
JP2017194963A (ja) * 2016-04-14 2017-10-26 株式会社半導体エネルギー研究所 半導体装置

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2021229373A1 (https=) * 2020-05-15 2021-11-18
WO2021229373A1 (ja) * 2020-05-15 2021-11-18 株式会社半導体エネルギー研究所 半導体装置、及び電子機器
US12136465B2 (en) 2020-05-15 2024-11-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic device
JP7578683B2 (ja) 2020-05-15 2024-11-06 株式会社半導体エネルギー研究所 半導体装置、及び電子機器
JP2024502785A (ja) * 2020-12-26 2024-01-23 インターナショナル・ビジネス・マシーンズ・コーポレーション 隠れ行列訓練ｄｎｎのフィルタリング
JP7649616B2 (ja) 2020-12-26 2025-03-21 インターナショナル・ビジネス・マシーンズ・コーポレーション 隠れ行列訓練ｄｎｎのフィルタリング
US12321852B2 (en) 2020-12-26 2025-06-03 International Business Machines Corporation Filtering hidden matrix training DNN
WO2023242666A1 (ja) * 2022-06-17 2023-12-21 株式会社半導体エネルギー研究所 半導体装置、及び電子機器
WO2025181636A1 (ja) * 2024-03-01 2025-09-04 株式会社半導体エネルギー研究所 半導体装置、演算装置及び電子機器

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