WO2019192243A1 - 一种半导体器件 - Google Patents

一种半导体器件 Download PDF

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Publication number
WO2019192243A1
WO2019192243A1 PCT/CN2019/071724 CN2019071724W WO2019192243A1 WO 2019192243 A1 WO2019192243 A1 WO 2019192243A1 CN 2019071724 W CN2019071724 W CN 2019071724W WO 2019192243 A1 WO2019192243 A1 WO 2019192243A1
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region
oxide layer
field oxide
semiconductor device
gate
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French (fr)
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汪广羊
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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Priority to US16/772,031 priority Critical patent/US11264468B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H10D30/655—Lateral DMOS [LDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/112—Field plates comprising multiple field plate segments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs

Definitions

  • the present application relates to the field of semiconductor technology, and in particular to a semiconductor device.
  • LDMOS metal oxide semiconductor field effect transistor
  • the depletion of the drift region is mainly increased by the field plate structure, and the withstand voltage is improved on the basis that the on-resistance is substantially unchanged.
  • the thickness of the field oxide layer or shallow trench isolation (STI) determines how fast the depletion is. The smaller the thickness of the field oxide layer, the more the field plate structure enhances the depletion of the drift region, and the breakdown voltage can be increased on the basis that the on-resistance is substantially constant.
  • the thickness of the field oxide layer cannot be reduced indefinitely, and the depletion of the drift region cannot be infinitely enhanced, and there is a limit to the improvement of the breakdown voltage.
  • the electric field strength between the drain and the gate also limits the increase in breakdown voltage, resulting in breakdown of the field oxide layer between the drain and the gate.
  • a semiconductor device is provided in accordance with various embodiments of the present application.
  • a semiconductor device comprising:
  • a semiconductor substrate in which a body region and a drift region are formed, an active region is formed in the body region, and a drain region is formed in the drift region;
  • the field oxide layer is located on the drift region and the drift region surrounds at least a portion of the field oxide layer;
  • gate-field plate monolithic structure a gate-field plate monolithic structure, the gate and field plate monolith structure being spanned over the semiconductor substrate and the field oxide layer and extending onto the body region;
  • a plurality of contact holes deep into the field oxide layer wherein a contact hole adjacent to the source region penetrates deeper into the field oxide layer than a contact hole near the drain region penetrates the field oxide layer The depth in the middle.
  • Figure 1 shows a schematic cross-sectional view of a conventional LDMOS device.
  • FIG. 2A is a schematic cross-sectional view of an LDMOS device in accordance with an exemplary embodiment of the present application.
  • FIG. 2B is a partial schematic view of a top view of an LDMOS device in accordance with an exemplary embodiment of the present application.
  • Spatial relationship terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc. This description may be used to describe the relationship of one element or feature shown in the figures to the other elements or features. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned “on” or “below” or “below” or “under” the element or feature is to be “on” the other element or feature. Thus, the exemplary terms “below” and “include” can include both the above and the The device may be otherwise oriented (rotated 90 degrees or other orientation) and the spatial descriptors used herein interpreted accordingly.
  • composition and/or “comprising”, when used in the specification, is used to determine the presence of the features, integers, steps, operations, components and/or components, but does not exclude one or more The presence or addition of features, integers, steps, operations, components, components, and/or groups.
  • the term “and/or” includes any and all combinations of the associated listed items.
  • FIG. 1 shows a schematic cross-sectional view of a conventional LDMOS device including: a P-type substrate 101, and a P-type body region 102 and an N-type drift region 103 in the P-type substrate 101; and a P-type body region 102.
  • a body lead-out region 106 and a source region 104 are formed therein, and a drain region 105 is formed in the N-type drift region 103; a field oxide layer 107 is formed on the drift region 103, and a gate electrode is disposed across the field oxide layer 107 and the semiconductor substrate 101.
  • Field plate integrated structure 108 In the LDMOS device, the depletion of the drain drift region is increased by forming a gate-field plate integrated structure.
  • the thickness of the field oxide layer or shallow trench isolation (STI) determines how fast the depletion is.
  • the thickness of the field oxide layer cannot be reduced indefinitely, and the depletion of the drift region cannot be infinitely enhanced, and there is a limit to the improvement of the breakdown voltage.
  • the electric field strength between the drain and the gate also limits the increase in breakdown voltage, resulting in breakdown of the field oxide layer between the drain and the gate.
  • the semiconductor substrate 201 has a body region 202 and a drift region 203 formed therein, an active region 204 formed in the body region 202, and a drain region 205 formed in the drift region 203; the field oxide layer 207 is located on the drift region 203 and drifts The region 203 surrounds at least a portion of the field oxide layer 207; the gate and field plate monolith 208 is disposed across the semiconductor substrate 201 and the field oxide layer 207 and extends onto the body region 202; the plurality of contact holes 209 penetrate the field oxide layer In 207, the depth of the contact hole 209 near the source region 204 deep into the field oxide layer 207 is greater than the depth of the contact hole 209 near the drain region 205 deep into the field oxide layer 207.
  • the semiconductor device of the present application includes a laterally double-diffused metal oxide semiconductor (LDMOS) device.
  • LDMOS laterally double-diffused metal oxide semiconductor
  • the present application provides a reduced surface field (RESURF) type LDMOS device. .
  • RESURF reduced surface field
  • the semiconductor device of the present application includes a first conductivity type and a second conductivity type.
  • the first conductivity type is P-type and the second conductivity type is N-type, wherein the P-type dopant ions include, but are not limited to, boron ions, and the N-type dopant ions include, but are not limited to, phosphorus ions or arsenic ions.
  • the LDMOS device of the present application includes a semiconductor substrate 201.
  • the semiconductor substrate 201 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), and insulator Silicon (SiGeOI) and germanium on insulator (GeOI).
  • the semiconductor substrate 201 is a silicon substrate having a first conductivity type or a second conductivity type.
  • a P well is formed in the semiconductor substrate 201 as a body 202.
  • a P-well is formed in a semiconductor substrate using a standard well implantation process, a P-well can be formed by a high-energy implantation process, or a P-well can be formed by a low-energy implantation with a high-temperature thermal annealing process.
  • a drift region 203 is also formed in the semiconductor substrate 201.
  • the drift region 203 is located within the semiconductor substrate 201, typically a lightly doped region, and for the N-channel LDMOS, the drift region is N-type doped.
  • the drift region 203 and the P well are formed in a similar manner, either by a high energy implantation process or by a low energy implantation, combined with a high temperature thermal annealing process.
  • the semiconductor substrate 201 has a first conductivity type or a second conductivity type
  • the body region 202 has a first conductivity type
  • the drift region 203 has a second conductivity type to form an NLDMOS device.
  • the semiconductor substrate 201 has a first conductivity type or a second conductivity type
  • the body region 202 has a second conductivity type
  • the drift region 203 has a first conductivity type to form a PLDMOS device.
  • a source 204 and a body lead-out region 206 are formed in the body region 202, and a drain 205 is formed in the drift region 203.
  • the source region and the drain region 205 respectively lead to a source and a drain.
  • the N-type impurity is formed in the body region 202 to form the source region 204
  • the N-type impurity is implanted in the drift region 203 to form the drain region 205.
  • the doping concentration of the source region 204 and the drain region 205 may be the same. Synchronous doping is formed.
  • a P-type impurity forming body lead-out region 206 is implanted in the body region 202.
  • the LDMOS device of the present application also includes a field oxide layer 207.
  • the field oxide layer 207 is located on the drift region 203 and the drift region 203 surrounds at least a portion of the field oxide layer 207.
  • the upper surface of the field oxide layer 207 is flush with the upper surface of the drift region 203 or the upper surface of the field oxide layer 207 is higher.
  • the material of the field oxide layer 207 is silicon oxide, and the field oxide layer 207 can be formed by any method known to those skilled in the art. Specifically, a silicon dioxide layer is grown on the surface of the semiconductor substrate, a silicon dioxide layer is patterned by a photolithography process, and the remaining silicon dioxide layer is thermally oxidized to form a field oxide layer 207.
  • the drift region 203 surrounds the entire field oxide layer 207, that is, the field oxide layer 207 and the semiconductor substrate 201 are completely separated by the drift region 203.
  • the LDMOS device of the present application also includes a gate and field plate monolith 208.
  • a gate and field plate monolith 208 is disposed across the semiconductor substrate 201 and the field oxide layer 207 and extends onto the body region 202 as shown in FIG. 2A.
  • the side of the grid-to-field plate monolith 208 adjacent the body region 202 extends onto the body region 202, the gate and field plate unitary structure 208 at least partially overlapping the body region 202, the grid and field plate integral structure 208
  • the material is polysilicon.
  • the LDMOS device of the present application further includes a dielectric layer overlying the semiconductor substrate 201, the field oxide layer 207, and the gate and field plate monolith 208.
  • the portion stacked on the field oxide layer 207 is a field plate structure, and the remaining portion is a gate region.
  • Contact holes penetrating through the dielectric layer are formed in the source region 204, the drain region 205, the gate region in the gate and field plate integrated structure 208, and the dielectric layer above the body lead-out region 206, respectively, to extract the source and the drain.
  • the gate, the contact hole 209 in the field oxide layer 207 is connected to the gate, wherein the contact hole of the source is in contact with the surface of the source region 204 and the body lead-out region 206, and the contact hole and drain region 205 of the drain are taken out.
  • the surfaces of the contacts contact the gate and the surface of the gate region in the field plate monolith 208.
  • a plurality of contact holes 209 are formed, and the plurality of contact holes 209 penetrate into the field oxide layer 207, wherein the contact hole 209 near the source region 204 penetrates deeper into the field oxide layer 207 than the near leak.
  • the contact hole 209 of the region 205 penetrates deep into the field oxide layer 207.
  • the plurality of contact holes 209 have different depths deep into the field oxide layer 207, facilitating the adjustment of different effective thicknesses of the field oxide layer 207, and the structure is flexible and easy to control. Compared with the device not using the LDMOS device structure of the present application, the present application can effectively increase the breakdown voltage and optimize the on-resistance without reducing the overall thickness of the field oxide layer.
  • the size of the opening of the contact hole 209 near the source region 204 is larger than the size of the opening of the contact hole 209 near the drain region 205.
  • the rate of etching the field oxide layer 207 can be controlled, thereby realizing the formation of contact holes 209 of different depths to deplete the drift region 203, and to better form the field oxide layer effectively.
  • the step thickness makes the depletion more optimized.
  • the plurality of contact holes 209 extend through the gate and field plate unitary structure 208.
  • the partial contact hole 209 penetrates the gate and the field plate unitary structure 208 to facilitate the depletion of the drift region below the gate and field plate unit structure 208.
  • the contact hole 209 is directly etched from above the gate and field plate unit structure 208 to form a contact hole 209. The dielectric layer etching makes it easier to control the etching rate, which is more advantageous for forming contact holes 209 of different depths.
  • the formation of the above-described LDMOS device does not require an increase in new process steps as compared with the conventional technology, and thus does not cause an increase in production cost.
  • the plurality of contact holes 209 can be divided into several groups, and the contact holes 209 in each group have the same opening size, and the depth into the field oxide layer 207 is also the same, and the adjacent two groups are close to the source.
  • the size of the opening of the contact hole 209 in the pole group is larger than the size of the opening of the contact hole 209 in the group near the drain, and the depth of the contact hole 209 in the group near the source is deeper into the field oxide layer 207 than to be near the drain.
  • the contact holes 209 in the grouping pass deep into the depth in the field oxide layer 207. As an example, as shown in FIGS.
  • the contact hole 209 is divided into four groups, wherein from the first group near the source to the fourth group near the drain, the opening of the contact hole 209 gradually decreases, going deep into the field. The depth of the oxide layer 207 also gradually decreases.
  • the first to third grouping contact holes 209 extend through the gate and field plate unitary structure 208.
  • the LDMOS device provided by the present application forms a contact hole deep into the field oxide layer, and controls the contact hole close to the source region to penetrate into the field oxide layer to a depth greater than the depth of the contact hole near the drain region into the field oxide layer, so that the proximity leak
  • the effective thickness of the field oxide layer is greater than the effective thickness of the field oxide layer away from the drain, which enhances the drift region depletion and maximizes the breakdown voltage and on-resistance of the LDMOS device. Since there is no limit that the thickness of the field oxide layer cannot be reduced indefinitely, the depletion of the drift region is further enhanced, the breakdown voltage can be increased to a greater extent, and the field oxide layer between the drain and the gate is less prone to breakdown. . Furthermore, forming the LDMOS device of the present application does not increase production costs.

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Abstract

本申请提供一种半导体器件，包括半导体衬底(201)、场氧化层(207)、栅与场板一体结构(208)和多个接触孔(209)，其中，半导体衬底(201)中形成有体区(202)和漂移区(203)，体区(202)内形成有源区(204)，漂移区(203)内形成有漏区(205)；场氧化层(207)位于漂移区(203)上且漂移区(203)包围至少部分场氧化层(207)；栅与场板一体结构(208)跨设在半导体衬底(201)和场氧化层(207)上，并延伸到体区(202)上；接触孔(209)深入场氧化层(207)中，其中靠近源区(204)的接触孔(209)深入场氧化层(207)中的深度大于靠近漏区(205)的接触孔(209)深入场氧化层(207)中的深度。

Description

一种半导体器件 技术领域
本申请涉及半导体技术领域，具体而言涉及一种半导体器件。
背景技术
随着半导体技术的不断发展，横向双扩散金属氧化物半导体场效应晶体管(Lateral Double Diffused MOSFET，LDMOS)器件具有良好的短沟道特性。LDMOS器件在漏极有一个轻掺杂注入区，被称为漂移区。漂移区掺杂浓度越低则耗尽越多，击穿电压(BV)越高，导通电阻(Rdson)越大，器件耐压能力虽然提高了，但导通电阻变大会降低器件的驱动能力；漂移区掺杂浓度越高则耗尽越少，击穿电压越低，导通电阻越小，导通电阻变小虽然提高了器件的驱动能力，但器件的耐压能力却降低了。
针对LDMOS器件中的击穿电压与导通电阻的设计矛盾，传统技术中主要通过场板结构增加漂移区的耗尽，在导通电阻基本不变的基础上提高耐压。场氧化层或者浅沟槽隔离(STI)的厚度决定了耗尽的快慢。场氧化层的厚度越小，场板结构会增强漂移区的耗尽，在导通电阻基本不变的基础上，可以提高击穿电压。但场氧化层的厚度不可能无限减小，漂移区的耗尽也就不可能无限增强，击穿电压的提高存在限制。此外，漏极与栅极之间的电场强度也会限制击穿电压的提升，导致漏极和栅极之间的场氧化层变薄后容易发生击穿。
因此，有必要提出一种新的LDMOS器件，以解决上述技术问题。
发明内容
根据本申请的各种实施例提供一种半导体器件。
一种半导体器件，包括：
半导体衬底，所述半导体衬底中形成有体区和漂移区，所述体区内形成有源区，所述漂移区内形成有漏区；
场氧化层，所述场氧化层位于所述漂移区上且所述漂移区包围至少部分所述场氧化层；
栅与场板一体结构，所述栅与场板一体结构跨设在所述半导体衬底和所述场氧化层上，并延伸到所述体区上；及
多个接触孔，所述接触孔深入所述场氧化层中，其中靠近所述源区的接触孔深入所述场氧化层中的深度大于靠近所述漏区的接触孔深入所述场氧化层中的深度。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一副或多副附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1示出了传统技术的LDMOS器件的剖面示意图。
图2A是根据本申请示例性实施例的LDMOS器件的剖面示意图。
图2B是根据本申请示例性实施例的LDMOS器件的俯视图的局部示意图。
具体实施方式
在下文的描述中，给出了大量具体的细节以便提供对本申请更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本申请可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本申请发生混淆，对于本领域公知的一些技术特征未进行描述。
应当理解的是，本申请能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本申请的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本申请教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本申请的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的 存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本申请，将在下列的描述中提出详细的步骤以及详细的结构，以便阐释本申请提出的技术方案。本申请的较佳实施例详细描述如下，然而除了这些详细描述外，本申请还可以具有其他实施方式。
图1示出了一种传统的LDMOS器件的剖面示意图，其包括：P型衬底101，以及位于P型衬底101中的P型体区102以及N型漂移区103；P型体区102内形成有体引出区106和源区104，N型漂移区103内形成有漏区105；漂移区103上形成有场氧化层107以及跨设在场氧化层107和半导体衬底101上的栅与场板一体结构108。在该LDMOS器件中，通过形成栅与场板一体结构来实现增加漏极漂移区的耗尽。场氧化层或者浅沟槽隔离(STI)的厚度决定了耗尽的快慢。场氧化层的厚度越小，栅与场板一体结构会增强漂移区的耗尽，在导通电阻基本不变的基础上，可以提高击穿电压。但场氧化层的厚度不可能无限减小，漂移区的耗尽也就不可能无限增强，击穿电压的提高存在限制。此外，漏极与栅极之间的电场强度也会限制击穿电压的提升，导致漏极和栅极之间的场氧化层变薄后容易发生击穿。
下面，参考图2A对本申请示例性实施例的半导体器件做详细描述。
半导体衬底201，半导体衬底201中形成有体区202和漂移区203，体区202内形成有源区204，漂移区203内形成漏区205；场氧化层207位于漂移区203上且漂移区203包围至少部分场氧化层207；栅与场板一体结构208跨设在半导体衬底201和场氧化层207上，并延伸到所述体区202上；多个接触孔209深入场氧化层207中，其中靠近源区204的接触孔209深入场氧化层207中的深度大于靠近漏区205的接触孔209深入场氧化层207中的深度。
示例性地，本申请的半导体器件包括横向双扩散金属氧化物半导体(Laterally Diffused Metal Oxide Semiconductor，LDMOS)器件，具体地，本申请提供了一种表面降场(Reduced Surface Field，RESURF)型LDMOS器件。
示例性地，本申请的半导体器件中包括第一导电类型和第二导电类型。示例性地，第一导电类型为P型，第二导电类型为N型，其中，P型掺杂离子包括但不限于硼离子，N型掺杂离子包括但不限于磷离子或砷离子。
本申请的LDMOS器件包括半导体衬底201。半导体衬底201可以是以下所提到的材料中的至少一种：硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。在本实施例中，半导体衬底201为硅衬底，具有第一导电类型或者第二导电类型。
示例性地，在半导体衬底201中形成P阱作为体区(Body)202。作为一个实例，采用标准的阱注入工艺在半导体衬底中形成P阱，可以通过高能量注入工艺形成P阱，也可以通过低能量注入，搭配高温热退火过程形成P阱。
示例性地，还在半导体衬底201中形成漂移区(Drift)203，漂移区203位于半导体衬底201内，一般为轻掺杂区，对于N沟槽LDMOS，漂移区为N型掺杂。作为一个实例，漂移区203和P阱形成方式相似，可以通过高能量注入工艺形成，也可以通过低能量注入，搭配高温热退火过程形成。
在上述实施例中，半导体衬底201具有第一导电类型或第二导电类型，体区202具有第一导电类型，漂移区203具有第二导电类型，以形成NLDMOS器件。在另一个实施例中，半导体衬底201具有第一导电类型或第二导电类型，体区202具有第二导电类型，漂移区203具有第一导电类型，以形成PLDMOS器件。
进一步，在体区202内形成源区(source)204和体引出区206，在漂移区203内形成漏区(drain)205，源区204、漏区205上可以分别引出源极、漏极。作为一个实例，在体区202注入N型杂质形成源区204，在漂移区203内注入N型杂质形成漏区205，源区204和漏区205的掺杂浓度可以相同，因此，二者可以同步地掺杂形成。作为一个实例，在体区202注入P型杂质 形成体引出区206。
本申请的LDMOS器件还包括场氧化层207。场氧化层207位于漂移区203上且漂移区203包围至少部分场氧化层207，具体地，场氧化层207的上表面与漂移区203的上表面平齐或者场氧化层207的上表面高于漂移区203的上表面。示例性地，场氧化层207的材料为氧化硅，可以采用本领域技术人员熟知的任何方法形成场氧化层207。具体地，在半导体衬底表面生长二氧化硅层，采用光刻工艺图案化二氧化硅层，热氧化剩余的二氧化硅层以形成场氧化层207。
进一步，当漂移区203的导电类型与半导体衬底201的导电类型不同时，漂移区203包围全部场氧化层207，即场氧化层207与半导体衬底201之间完全被漂移区203隔开。
本申请的LDMOS器件还包括栅与场板一体结构208。栅与场板一体结构208跨设在半导体衬底201和场氧化层207上，并延伸到所述体区202上，如图2A所示。示例性地，栅与场板一体结构208靠近体区202的一侧延伸到所述体区202上，栅与场板一体结构208与体区202至少有部分重叠，栅与场板一体结构208的材料为多晶硅。
本申请的LDMOS器件还包括介电层，介电层覆盖半导体衬底201、场氧化层207和栅与场板一体结构208。在该栅与场板一体结构208中，叠设于场氧化层207上的部分为场板结构，其余部分为栅区。在源区204、漏区205、栅与场板一体结构208中的栅区和体引出区206上方的介电层中分别形成有贯穿介电层的接触孔，以引出源极、漏极和栅极，深入场氧化层207中的接触孔209连接于该栅极，其中，引出源极的接触孔与源区204和体引出区206的表面接触，引出漏极的接触孔与漏区205的表面相接触，引出栅极的接触孔与栅与场板一体结构208中的栅区的表面相接触。
在本申请提供的LDMOS器件中，还形成有多个接触孔209，多个接触 孔209深入场氧化层207中，其中靠近源区204的接触孔209深入场氧化层207中的深度大于靠近漏区205的接触孔209深入场氧化层207中的深度。通过控制接触孔209深入场氧化层207的深度不同，使得靠近漏极的场氧化层207的有效厚度适当变厚，远离漏极的场氧化层207的有效厚度适当变薄，既最大限度地增强了漂移区203耗尽，又解决了场氧化层207限制击穿电压(BV)的问题。此外，多个接触孔209深入场氧化层207中的深度不同，便于场氧化层207的不同有效厚度的调整，结构灵活，易于控制。与未采用本申请的LDMOS器件结构的器件相比，本申请无需减小场氧化层整体厚度，即可有效提高击穿电压并优化导通电阻。
进一步，靠近源区204的接触孔209的开孔尺寸大于靠近漏区205的接触孔209的开孔尺寸。通过改变接触孔209的开孔尺寸，可以控制刻蚀场氧化层207的速率，从而实现形成不同深度的接触孔209来对漂移区203进行耗尽，并且能够更好地形成场氧化层的有效阶梯厚度，使耗尽更加优化。
进一步，至少多个接触孔209中的一部分贯穿栅与场板一体结构208。部分接触孔209贯穿栅与场板一体结构208更有利于增强栅与场板一体结构208下方漂移区的耗尽，此外，从栅与场板一体结构208上方直接刻蚀形成接触孔209比通过介质层刻蚀更容易控制刻蚀速率，则更有利于形成不同深度的接触孔209。
此外，形成上述LDMOS器件与传统技术相比无需增加新的工艺步骤，因此不会导致生产成本的增加。
示例性地，多个接触孔209可以分为若干分组，每个分组中的接触孔209的开孔尺寸相同，深入场氧化层207中的深度也相同，相邻的两个分组中，靠近源极的分组中的接触孔209的开孔尺寸大于靠近漏极的分组中的接触孔209的开孔尺寸，靠近源极的分组中的接触孔209深入场氧化层207中的深度大于靠近漏极的分组中的接触孔209深入场氧化层207中的深度。作为一个实例，如图2A和2B所示，接触孔209分为四个分组，其中从靠近源极的第一分组到靠近漏极的第四分组，接触孔209的开口逐渐减小，深入场氧化 层207的深度也逐渐减小。其中，第一分组至第三分组接触孔209贯穿栅与场板一体结构208。
本申请提供的LDMOS器件，通过形成深入场氧化层的接触孔，并控制靠近源区的接触孔深入场氧化层中的深度大于靠近漏区的接触孔深入场氧化层中的深度，使得靠近漏极的场氧化层的有效厚度大于远离漏极的场氧化层的有效厚度，既增强了漂移区耗尽，又最大限度优化了LDMOS器件的击穿电压和导通电阻。由于不存在场氧化层厚度无法无限减小的限制，漂移区的耗尽进一步增强，击穿电压可以得到更大限度的提高，且漏极和栅极之间的场氧化层不容易发生击穿。此外，形成本申请的LDMOS器件不会增加生产成本。
本申请已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本申请限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本申请并不局限于上述实施例，根据本申请的教导还可以做出更多种的变型和修改，这些变型和修改均落在本申请所要求保护的范围以内。本申请的保护范围由附属的权利要求书及其等效范围所界定。

Claims (20)

  1. 一种半导体器件，包括：
    半导体衬底，所述半导体衬底中形成体区和漂移区，所述体区内形成源区，所述漂移区内形成漏区；
    场氧化层，所述场氧化层位于所述漂移区上且所述漂移区包围至少部分所述场氧化层；
    栅与场板一体结构，所述栅与场板一体结构跨设在所述半导体衬底和所述场氧化层上，并延伸到所述体区上；及
    多个接触孔，所述接触孔深入所述场氧化层中，其中，靠近所述源区的接触孔深入所述场氧化层中的深度大于靠近所述漏区的接触孔深入所述场氧化层中的深度。
  2. 如权利要求1所述的半导体器件，其中，靠近所述源区的接触孔的开孔尺寸大于靠近所述漏区的接触孔的开孔尺寸。
  3. 如权利要求1所述的半导体器件，其中，所述多个接触孔中的部分接触孔先贯穿所述栅与场板一体结构后再深入所述场氧化层中。
  4. 如权利要求1所述的半导体器件，其中，所述多个接触孔分为若干分组，同一个分组中的接触孔的开孔尺寸相同且深入所述场氧化层中的深度也相同。
  5. 如权利要求4所述的半导体器件，其中，相邻的两个分组中，靠近所述源区的分组中的接触孔的开孔尺寸大于靠近所述漏区的分组中的接触孔的开孔尺寸，靠近所述源区的分组中的接触孔深入所述场氧化层中的深度大于靠近所述漏区的分组中的接触孔深入所述场氧化层中的深度。
  6. 如权利要求5所述的半导体器件，其中，所述接触孔分为四个分组。
  7. 如权利要求6所述的半导体器件，其中，从靠近所述源区到靠近所述漏区依次为第一分组至第四分组，其中，所述第一分组至所述第三分组的接触孔贯穿所述栅与场板一体结构。
  8. 如权利要求1所述的半导体器件，还包括：
    体引出区，所述体引出区形成于所述体区内，并与所述源区相邻接。
  9. 如权利要求1所述的半导体器件，其中，所述场氧化层的上表面高于所述漂移区的上表面。
  10. 如权利要求1所述的半导体器件，其中，所述场氧化层的上表面与所述漂移区的上表面齐平。
  11. 如权利要求1所述的半导体器件，其中，当所述漂移区的导电类型与所述半导体衬底的导电类型不同时，所述漂移区包围全部所述场氧化层。
  12. 如权利要求1所述的半导体器件，其中，所述半导体器件包括LDMOS器件。
  13. 如权利要求12所述的半导体器件，其中，所述体区为P型掺杂且所述漂移区为N型掺杂以形成NLDMOS器件。
  14. 如权利要求12所述的半导体器件，其中，所述体区为N型掺杂且所述漂移区为P型掺杂以形成PLDMOS器件。
  15. 如权利要求1所述的半导体器件，其中，所述栅与场板一体结构的材料为多晶硅。
  16. 如权利要求1所述的半导体器件，其中，所述场氧化层的材料为氧化硅。
  17. 如权利要求1所述的半导体器件，其中，所述源区和所述漏区的掺杂浓度相同。
  18. 如权利要求8所述的半导体器件，还包括：
    介电层，所述介电层覆盖所述半导体衬底、所述场氧化层和所述栅与场板一体结构，在所述栅与场板一体结构中，叠设于所述场氧化层上的部分为场板结构，未叠设于所述场氧化层上的部分为栅区，在所述源区、漏区、栅区和体引出区上方的介电层中分别形成有贯穿所述介电层的接触孔，以引出源极、漏极和栅极。
  19. 如权利要求1所述的半导体器件，其中，所述漂移区为轻掺杂区。
  20. 如权利要求1所述的半导体器件，其中，所述半导体衬底为硅衬底。
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