WO2019119264A1 - 低压差线性稳压电路 - Google Patents

低压差线性稳压电路 Download PDF

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Publication number
WO2019119264A1
WO2019119264A1 PCT/CN2017/117136 CN2017117136W WO2019119264A1 WO 2019119264 A1 WO2019119264 A1 WO 2019119264A1 CN 2017117136 W CN2017117136 W CN 2017117136W WO 2019119264 A1 WO2019119264 A1 WO 2019119264A1
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Prior art keywords
field effect
effect transistor
source
circuit
voltage
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English (en)
French (fr)
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李亮
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Shenzhen Goodix Technology Co Ltd
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Shenzhen Goodix Technology Co Ltd
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Priority to PCT/CN2017/117136 priority Critical patent/WO2019119264A1/zh
Priority to CN201780002309.6A priority patent/CN108235744B/zh
Publication of WO2019119264A1 publication Critical patent/WO2019119264A1/zh
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
    • G05F1/56—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices

Definitions

  • Embodiments of the present invention relate to circuit technologies, and in particular, to a low dropout linear regulator circuit.
  • LDO Low Dropout Regulator
  • FET field effect transistor
  • the LDO circuit is mainly composed of the following three modules: an output voltage detection circuit composed of a first feedback resistor R F1 and a second feedback resistor R F2 , which generates a corresponding feedback voltage, and a feedback voltage VF and a reference voltage VREF The comparison is made, and the error amplifier EA of the corresponding error voltage VEA is generated, and the power tube M P is adjusted according to the error voltage VEA.
  • AVDD and AVSS are the power supply and the common ground, respectively, and I L is the load current.
  • A is the gain of the error amplifier
  • g mp is the transconductance of the power transistor M P
  • r out is the equivalent impedance of the LDO output point.
  • the above LDO circuit has at least two poles: a pole ⁇ p1 corresponding to the output point of the error amplifier and a pole ⁇ p2 corresponding to the output point of the LDO, which can be expressed as equations (1) and (2), respectively:
  • r EA is the equivalent output impedance of the error amplifier
  • C EA is the equivalent capacitance of the error amplifier output point
  • C OUT is the equivalent capacitance of the LDO output point.
  • a uF-level load capacitor is usually added to the output of the LDO, making C OUT large.
  • ⁇ P2 is very low.
  • ⁇ P1 is low. This can cause the negative feedback loop to be unstable.
  • the prior art has made many improvements to the LDO circuit, including Miller compensation technology, indirect compensation technology and pole splitting, which improve the loop stability of the LDO under a wide range of current loads.
  • the current output capability cannot be effectively improved. This causes the existing LDO circuit to increase the current output capability while increasing the size of the power transistor M P , the size of the compensation circuit, and the static power consumption. In some cases, this is an unacceptable overhead. .
  • the embodiment of the invention provides a low-dropout linear voltage regulator circuit to solve the problem that the current LDO circuit has excessive current capacity overhead.
  • a low dropout linear regulator circuit comprises: an output voltage detecting circuit for detecting an output voltage of the low-dropout linear voltage stabilizing circuit and generating a corresponding feedback voltage; an error amplifying circuit for comparing the feedback voltage and the reference voltage, and generating corresponding The error voltage; the power tube, the output current of the power tube is adjusted according to the error voltage; and the substrate voltage adjustment circuit is connected to the power tube and configured to adjust the substrate voltage of the power tube according to the output current of the power tube, so that the substrate The voltage decreases with increasing output current within a predetermined fluctuation range.
  • the substrate voltage adjusting circuit comprises: a current detecting unit for detecting an output current of the power tube; and a voltage adjusting unit connected to the output of the current detecting unit and configured to be based on the output current of the power tube to the substrate voltage Feedback control is performed such that the substrate voltage decreases as the output current increases.
  • the current detecting unit includes: a first FET, forming a first current mirror with the power tube, and the first current mirror is configured to output the first mirror current of the output current according to the first current mirror ratio; the second field effect Both the tube and the third field effect transistor operate in the weak inversion region, and are used to approximate the drain voltage of the first field effect transistor and the power tube to improve the mirroring accuracy of the first current mirror, and the first mirror current passes through Two FET outputs; a bias current source that provides a bias current for the third FET. And a fourth FET, forming a second current mirror with the fifth FET, wherein the fourth FET receives the first mirror current as a mirror source of the second current mirror.
  • the first FET, the second FET, and the third FET are respectively P-channel MOSFETs
  • the fourth FET is an N-channel MOSFET.
  • the gate, the source and the substrate of the first FET are respectively connected to the gate, the source and the substrate of the power tube; the gate of the second FET and the gate of the third FET Connected, the source of the second FET is connected to the drain of the first FET; the source of the third FET is connected to the drain of the power transistor, the drain of the third FET and the gate of the third field effect
  • the poles and the bias current sources are all connected; the source of the fourth field effect transistor is grounded, and the gate and the drain of the fourth field effect transistor are connected to the drain of the second field effect transistor.
  • the voltage adjustment unit includes: a fifth FET, forming a second current mirror with the fourth FET, and the second current mirror is configured to reduce the first mirror current to the second mirror current according to the second current mirror ratio And a resistive component respectively connected to the fifth FET and the substrate of the power transistor to generate a corresponding substrate voltage according to the second mirror current.
  • the fifth FET is an N-channel MOSFET, the gate of the fifth FET is connected to the gate of the fourth FET, and the source of the fifth FET is grounded;
  • the resistance component includes a first resistor and a second resistor connected in series, wherein the first resistor is connected to the source of the power tube, the second resistor is connected to the drain of the fifth field effect transistor, and the connection point of the first resistor and the second resistor is connected to the power tube
  • the substrate is connected to provide a substrate voltage.
  • the low-dropout linear regulator circuit further includes: a substrate leakage protection unit connected in parallel across the resistance component.
  • the substrate leakage protection unit comprises: a sixth field effect transistor, the sixth field effect transistor is a P-channel metal oxide semiconductor field effect transistor, and the gate and the drain of the sixth field effect transistor are respectively connected to the first The drain of the fifth field effect transistor, the source of the sixth field effect transistor is connected to the source of the power tube.
  • the output voltage detecting circuit includes a first feedback resistor and a second feedback resistor connected in series, the first feedback resistor is connected to the output end of the power tube, the second feedback resistor is grounded, and the first feedback resistor and the second feedback resistor are connected.
  • the voltage is used as the feedback voltage.
  • the low dropout linear regulator circuit further includes a Miller compensation circuit
  • the Miller compensation circuit includes: a Miller compensation capacitor and a Miller compensation resistor connected in series, a Miller compensation capacitor is connected to an output terminal of the error amplifier, and a Miller compensation resistor is connected to the drain of the power tube. pole.
  • the low-dropout linear regulator circuit further comprises an indirect compensation circuit, wherein the indirect compensation circuit comprises: an indirect compensation capacitor and a cascode tube of the error amplifier, the indirect compensation capacitor is connected to the output end of the error amplifier at one end, and the common source is connected to the other end. The source of the common gate.
  • the indirect compensation circuit comprises: an indirect compensation capacitor and a cascode tube of the error amplifier, the indirect compensation capacitor is connected to the output end of the error amplifier at one end, and the common source is connected to the other end. The source of the common gate.
  • the error amplifier comprises a seventh field effect transistor, an eighth field effect transistor, a ninth field effect transistor, a tenth field effect transistor, an eleventh field effect transistor, a twelfth field effect transistor, and a thirteenth field effect.
  • Tube, fourteenth field effect transistor, fifteenth field effect transistor, twelfth field effect transistor, thirteenth field effect transistor, fourteenth field effect transistor, fifteenth field effect transistor are respectively N channel field effect transistors
  • the seventh field effect transistor, the eighth field effect transistor, the ninth field effect transistor, the tenth field effect transistor, and the eleventh effect transistor are respectively P-channel field effect transistors; the twelfth field effect transistor and the fifteenth field
  • the effect tube is used as a cascode tube; one end of the indirect compensation capacitor is connected to the source of the fifteenth field effect transistor, and the other end is connected to the output end of the power tube; the source of the seventh field effect transistor and the tenth field effect transistor The source and the source of the eleventh effect transistor are respectively connected to the power source; the source of
  • the low dropout linear regulator circuit further includes: a pole splitting circuit, the pole splitting circuit comprising: a buffer stage having a low input capacitance and a low output resistance, the buffer stage being connected between the error amplifier and the power tube.
  • a pole splitting circuit comprising: a buffer stage having a low input capacitance and a low output resistance, the buffer stage being connected between the error amplifier and the power tube.
  • the buffer stage comprises: a buffer level tube, which is a P-channel metal oxide semiconductor field effect transistor, a gate of the buffer level tube is connected to an output end of the error amplifier, and a source of the buffer level tube is connected to a gate of the power tube, The drain of the buffer level tube is grounded; the buffer current source is connected to the first end of the buffer current source, and the second end of the buffer current source is connected to the gate of the power tube and the source of the buffer stage.
  • a buffer level tube which is a P-channel metal oxide semiconductor field effect transistor, a gate of the buffer level tube is connected to an output end of the error amplifier, and a source of the buffer level tube is connected to a gate of the power tube, The drain of the buffer level tube is grounded; the buffer current source is connected to the first end of the buffer current source, and the second end of the buffer current source is connected to the gate of the power tube and the source of the buffer stage.
  • the substrate voltage of the power tube is adaptively adjusted by detecting the output current of the power tube, thereby appropriately reducing the threshold voltage of the power tube and greatly increasing the low-voltage difference.
  • the maximum output current of the linear regulator circuit is provided by the embodiment of the invention.
  • the current detecting unit detects the current of the LDO power tube in real time; and then the substrate voltage adjusting unit adjusts the substrate voltage of the power tube according to the output of the current detecting circuit.
  • the larger the power tube current the lower the substrate voltage and the stronger the current capability of the power tube.
  • the substrate leakage protection unit is used to avoid leakage caused by the power tube substrate voltage being too low.
  • the substrate voltage adaptive adjustment circuit and the main feedback loop of the LDO circuit are independent of each other. Therefore, the solution does not affect the stability of the LDO circuit, and can be widely applied to most existing LDO circuits.
  • FIG. 2 is a schematic block diagram of a low dropout linear regulator circuit in accordance with one embodiment of the present invention
  • FIG. 3 is a schematic diagram of a low dropout linear regulator circuit in accordance with one embodiment of the present invention.
  • FIG. 4 is a circuit diagram of a low dropout linear regulator circuit in accordance with one embodiment of the present invention.
  • FIG. 5 is a circuit diagram of an LDO applied to a Miller compensation structure of a low dropout linear regulator circuit in accordance with one embodiment of the present invention
  • FIG. 6 is a circuit diagram of an LDO applied to an indirect compensation structure of a low dropout linear regulator circuit according to an embodiment of the present invention
  • FIG. 7 is a circuit diagram of an LDO applied to a pole splitting technique of a low dropout linear regulator circuit in accordance with one embodiment of the present invention.
  • FIG. 2 is a schematic block diagram of a low dropout linear regulator circuit according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a low dropout linear regulator circuit according to an embodiment of the present invention, which is generally
  • the output voltage detecting circuit 110, the error amplifying circuit 120, the power transistor M P , and the substrate voltage adjusting circuit 130 may be included.
  • the output voltage detecting circuit 110, the error amplifying circuit 120, and the power tube M P together constitute a main feedback control circuit of the low-dropout linear voltage stabilizing circuit, wherein the output voltage detecting circuit 110 is configured to detect the output voltage of the low-dropout linear voltage stabilizing circuit, and generate The corresponding feedback voltage.
  • the error amplifying circuit 120 is configured to compare the feedback voltage and the reference voltage of the low-dropout linear voltage stabilizing circuit, and generate a corresponding error voltage, and the output current of the power tube M P is adjusted according to the error voltage, that is, the power tube M P It adjusts its own output current according to the error voltage.
  • the output voltage detection circuit 110 includes a first feedback resistor and a second feedback resistor R F1 R F2, first and second feedback resistors R F1
  • the two feedback resistors R F2 are connected in series, wherein the first feedback resistor R F1 is connected to the output end of the power tube M P , the second feedback resistor R F2 is grounded, and the voltage of the first feedback resistor R F1 and the second feedback resistor R F2 is connected
  • the feedback voltage that is, the output voltage is divided by the first feedback resistor R F1 and the second feedback resistor R F2 , so that the output voltage value of the low-dropout linear regulator circuit is in accordance with the first feedback resistor R F1 and the second feedback resistor
  • the resistance ratio of R F2 is reduced to the feedback voltage VF.
  • the error amplifying circuit 120 mainly includes an error amplifier EA that compares the feedback voltage VF with a reference voltage VREF and generates a corresponding error voltage VEA.
  • EA error amplifier
  • VEA error voltage
  • the substrate voltage adjusting circuit 130 is connected to the power transistor M P and configured to adjust the substrate voltage V B of the power transistor M P according to the output current of the power transistor M P such that the substrate voltage V B follows the output current within a predetermined fluctuation range. Increase and decrease.
  • the substrate voltage adjustment circuit 130 may include a current detection unit 131, a voltage adjustment unit 132, and may further include a substrate leakage protection unit 133 in some embodiments.
  • the current detecting unit 131 is configured to detect an output current of the power tube.
  • the voltage adjustment unit 132 is connected to the output of the current detecting unit 131 and is configured to feedback control the substrate voltage V B according to the output current of the power transistor M P such that the substrate voltage V B decreases as the output current increases.
  • the substrate leakage protection unit 133 is for avoiding leakage generated by diode conduction between the power source PT source and the substrate.
  • FIG. 4 is a circuit diagram of a low dropout linear regulator circuit in accordance with one embodiment of the present invention.
  • the current detecting unit 131 includes a first field effect transistor M PC , a second field effect transistor M 1 , a third field effect transistor M 2 , a bias current source I B , and a fourth field effect transistor M 3 .
  • the first field effect transistor M PC and the power tube M P form a first current mirror, and the first current mirror can output a first mirror current of the output current according to a first current mirror ratio (expressed as X:1).
  • the second field effect transistor M 1 and the third field effect transistor M 2 both operate in the weak inversion region for approximately equalizing the drain voltage of the first field effect transistor M PC and the power tube to improve the first current mirror the accuracy of the mirror, and the first current mirror output through the second field effect transistor M 1, a bias current source I B M 2 is a third FET bias current.
  • the fourth field effect transistor M 3 is coupled to the second field effect transistor M 1 for receiving the first mirror current.
  • the X:1 ratio of the first current mirror ratio is generally taken to be a larger value, so that the currents on the M 1 tube and the M 3 tube are smaller.
  • the voltage adjusting unit 132 includes a fifth field effect transistor M 4 and a resistance component, and the fifth field effect transistor M 4 is connected to the fourth field effect transistor M 3 to form a second current mirror.
  • the second current mirror is configured to reduce the first mirror current to a second mirror current according to a second current mirror ratio (denoted as Y:1).
  • the substrate leakage protection unit 133 is connected in parallel across the resistance member.
  • the first field effect transistor M PC , the second field effect transistor M 1 , and the third field effect transistor M 2 are respectively P-channel metal oxide semiconductor field effect transistors
  • the four field effect transistor M 3 is an N-channel metal oxide semiconductor field effect transistor
  • the fifth field effect transistor M 4 is an N-channel metal oxide semiconductor field effect transistor as a sixth field effect transistor of the substrate leakage protection unit 133.
  • M D is a P-channel metal oxide semiconductor field effect transistor.
  • the gate, the source and the substrate of the first field effect transistor M PC are respectively connected to the gate, the source and the substrate of the power transistor M P in one-to-one correspondence; the gate and the third field of the second field effect transistor M 1
  • the gate of the effect transistor M 2 is connected, the source of the second field effect transistor M 1 is connected to the drain of the first field effect transistor M PC ;
  • the source of the third field effect transistor M 2 is connected to the drain of the power transistor M P , drain of the third FET M M gate of the third FET and the bias current source I B 2 2 are connected;
  • source of the fourth field-effect transistor M 3 is connected to ground AVSS, fourth FET M 3 a gate and a drain are connected to the drain of the second FET M 1.
  • the gate of the fifth field effect transistor M 4 is connected to the gate of the fourth field effect transistor M 3 , the source of the fifth field effect transistor M 4 is grounded to AVSS;
  • the resistance component includes the first resistor R 1 and the second resistor connected in series R 2, wherein a first resistor R 1 connected to the power source of the pipe M P electrode (connected to a power supply AVDD), the drain tube 2 M 4 is connected to a second resistor fifth field R, a first resistor R1 and second resistor R2
  • the connection point is connected to the substrate of the power transistor M P to provide a substrate voltage V B .
  • the gate and the drain of the sixth field effect transistor M D are respectively connected to the drain of the fifth field effect transistor M 4 , and the source of the sixth field effect transistor M D is connected to the source of the power transistor M P .
  • the output voltage detecting circuit 110 includes a first feedback resistor RF1 and a second feedback resistor RF2 connected in series, wherein the first feedback resistor RF1 is connected to the output end of the power tube M P1 , the second feedback resistor RF2 is grounded, and the first feedback resistor RF1 is The voltage of the second feedback resistor RF2 connection point is used as a feedback voltage.
  • the power tube M P and the M PC tube constitute a first current mirror, and the first current mirror ratio is X:1, and X generally takes a larger value, so that the current on the M 1 tube and the M 3 tube is smaller, and the M 1 tube Configured to a large aspect ratio (W/L), the M 1 tube can be operated in a weak inversion zone.
  • the bias current I B takes a small value to reduce the static power consumption of the LDO.
  • the M 2 tube is also configured to have a larger W/L, which allows the M 2 tube to operate in the weak inversion region, and the M PC tube can be obtained.
  • the drain voltage V1 is expressed as equation (4):
  • V2 is the gate voltage of the M 1 tube and the M 2 tube
  • V TH, 1 is the threshold voltage of the M1 tube
  • V TH, 2 is the threshold voltage of the M 2 tube
  • VOUT is the output of the low voltage difference linear regulator circuit Voltage (feedback voltage). Since the gate voltages of the power transistors M P and M PC tubes are the same, the source voltages are the same, and the substrate voltages are the same. And the drain voltages of the power transistors M P and M PC tubes are approximately equal. Therefore, the current in the M PC tube can accurately mirror the current of the power tube M P , which can be expressed as equation (5):
  • I M3 is the current on the M 3 tube and I MP is the output current of the power tube M P .
  • the M 3 tube and the M 4 tube form a second current mirror, the second current mirror ratio is Y:1, and the M 3 tube and the M 4 tube are respectively configured as smaller W/L, all working in the saturation region to obtain more accurate The mirror ratio.
  • the current in the M 4 tube flows through the resistor R 1 to generate the substrate control voltage V B , thereby obtaining the equation (6):
  • V SB, MP is the source lining voltage of the power tube. It can be known from equation (6) that the larger the current I MP on the power tube M P , the larger the source lining voltage V SB, MP , and the appropriate values of X, Y and R 1 can be selected within the load current range. A reasonable range of source lining voltages V SB, MP is obtained . Further, the threshold voltage and saturation current of the power transistor M P can be obtained:
  • V TH0 is the threshold voltage when there is no shimming effect, and is a negative value for PMOS
  • ⁇ is the body effect coefficient
  • Is a potential associated with the substrate doping concentration and temperature
  • ⁇ n is the electron mobility
  • C OX is the gate oxide capacitance per unit area
  • W / L is the width to length ratio of the power transistor M P .
  • the substrate voltage adaptive adjustment circuit and the LDO main loop are independent of each other, so that the stability of the LDO is not significantly affected, and thus can be widely applied to existing large-scale In some LDO circuit structures, the current capability of these LDOs can be greatly improved, and according to experimental simulation results, for example, about 20 times can be improved. And the overhead is only negligible static power and area.
  • Miller compensation structures LDO M P between the power tube and the additional Miller error amplifier circuit compensating circuit
  • indirect compensation structures LDO M P in the power transistor
  • An example of adding an indirect compensation circuit to the error amplifying circuit and an LDO of a pole splitting technique (adding a pole splitting circuit between the power transistor M P and the error amplifying circuit).
  • FIG. 5 is a circuit diagram of an LDO applied to a Miller compensation structure according to an embodiment of the present invention
  • C c is a Miller compensation capacitor
  • R c is a Miller compensation resistor
  • R c is connected in series with C c
  • the output of the error amplifier EA is connected to the drain of the power transistor M P (ie, the output terminal VOUT of the low dropout linear regulator circuit), wherein R c is connected to the output of the error amplifier, and C c is connected to the drain of the power transistor.
  • M P the output terminal VOUT of the low dropout linear regulator circuit
  • the indirect compensation circuit 160 includes: an indirect compensation capacitor C C and a cascode tube of the error amplifier EA (including the twelfth field effect transistor M 12 and the fifteenth field effect transistor M C ), and the indirect compensation capacitor Cc is connected at one end. To the source of the fifteenth effect transistor M C , the other end is connected to the drain of the power transistor M P (ie, the output terminal VOUT of the low dropout linear regulator circuit).
  • the error amplifier EA includes: a seventh field effect transistor M 7 , an eighth field effect transistor M 8 , a ninth field effect transistor M 9 , a tenth field effect transistor M 10 , an eleventh effect transistor M 11 , and a tenth Two field effect transistors M 12 , a thirteenth field effect transistor M 13 , a fourteenth field effect transistor M 14 , and a fifteenth field effect transistor M C .
  • the twelfth field effect transistor M 12 , the thirteenth field effect transistor M 13 , the fourteenth field effect transistor M 14 , and the fifteenth field effect transistor M C are respectively N-channel field effect transistors, and the seventh field effect transistor M 7 , the eighth field effect transistor M 8 , the ninth field effect transistor M 9 , the tenth field effect transistor M 10 , and the eleventh field effect transistor M 11 are respectively P channel field effect transistors.
  • the source of the seventh field effect transistor M 7 , the source of the tenth field effect transistor M 10 , and the source of the eleventh field effect transistor M 11 are respectively connected to the power source; the source of the eighth field effect transistor M 8 and the first The source of the nine field effect transistors M 9 is respectively connected to the drain of the seventh field effect transistor M 7 ; the gate of the eighth field effect transistor M 8 is connected to the feedback voltage VF; the drain of the eighth field effect transistor M 8 is connected to the tenth The source of the second field effect transistor M 12 ; the gate of the ninth field effect transistor M 9 is connected to the reference voltage VREF; the drain of the ninth field effect transistor M 9 is connected to the source of the fifteenth field effect transistor M C ; M eleventh FET gate field effect transistor M 10 is connected to the gate 11; a gate of the tenth field effect transistor and the drain of the tenth field effect transistor M 10 M 10 is connected to the twelfth connection The drain of the FET M 12; the drain of the eleventh effect transistor M 11 outputs
  • the substrate voltage adjusting circuit 130 In the case where the substrate voltage adjusting circuit 130 is not added, increasing the maximum output current of the LDO of the indirect compensation structure requires an increase in the size of the power transistor M P and the area of the compensation capacitor C C , which also leads to a larger static Power consumption.
  • the substrate voltage adjusting circuit 130 is applied to the LDO of the indirect compensation structure, that is, when the circuit shown in FIG. 6 is utilized, the overhead of boosting the current capability is only negligible static power consumption and area. Thereby, the characteristics of the indirect compensation structure are retained, and the current capability is also improved with minimal overhead.
  • FIG. 7 is a circuit diagram of an LDO applied to a pole splitting technique of a low dropout linear regulator circuit according to an embodiment of the present invention.
  • the circuit is at the output of the error amplifier and the power transistor M.
  • a pole split circuit is added between the gates of P , and the pole split circuit includes a buffer stage 140 having a low input capacitance and a low output resistance (as shown by the dotted line in the dotted line in FIG. 7), that is, the input of the buffer stage 140.
  • the capacitance (capacitance at the point of connection to the error amplifier) is lower than the gate capacitance of the power tube, and the output resistance of the buffer stage (the equivalent resistance at the point where the power tube gate is connected) is lower than the output resistance of the error amplifier.
  • the input capacitance of the buffer stage is two orders of magnitude (100 times) lower than the gate capacitance of the power tube, and the output resistance of the buffer stage is two orders of magnitude (100 times) lower than the output resistance of the error amplifier.
  • the buffer stage 140 includes: a buffer level tube M buf , which is a P-channel metal oxide semiconductor field effect transistor, a gate of M buf is connected to an output terminal of the error amplifier, a source of M buf is connected to a gate of the power tube, and M buf The drain is grounded; the first end of the buffer current source I buf , I buf is connected to the power source, and the second end of the I buf is connected to the gate of the power tube and the source of the M buf .
  • a buffer level tube M buf which is a P-channel metal oxide semiconductor field effect transistor, a gate of M buf is connected to an output terminal of the error amplifier, a source of M buf is connected to a gate of the power tube, and M buf The drain is grounded; the first end of the buffer current source I buf , I buf is connected to the power source, and the second end of the I buf is connected to the gate of the power tube and the source of the M buf .
  • the substrate voltage adjusting circuit 130 When the substrate voltage adjusting circuit 130 is applied to the LDO of the pole splitting technique, that is, when the circuit shown in FIG. 7 is used, the overhead of boosting the current capability is only negligible static power consumption and area. Thereby, the characteristics of the pole splitting structure are preserved, and the current capability is also improved with a small overhead.
  • the low-dropout linear voltage regulator circuit of the present embodiment can be widely applied to most existing LDO structures, and while maintaining the original LDO characteristics, the LDO is greatly improved with negligible overhead. Current capability.

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Abstract

一种低压差线性稳压电路。该低压差线性稳压电路包括：输出电压检测电路（110），用于检测所述低压差线性稳压电路的输出电压，并产生对应的反馈电压（VF）；误差放大电路（120），用于比较反馈电压（VF）和参考电压（VREF），并产生相应的误差电压（VEA）；功率管（Mp），所述功率管（Mp）的输出电流根据所述误差电压（VEA）进行调整；以及衬底电压（V B）调整电路（130），连接至所述功率管（Mp），并配置成根据所述功率管（Mp）的输出电流调整所述功率管（Mp）的衬底电压（V B），使得所述衬底电压（V B）在预定波动范围内随所述输出电流增大而降低，以此来适当降低功率管（Mp）的阈值电压，大幅增加低压差线性稳压电路的最大输出电流。

Description

低压差线性稳压电路 技术领域
本发明实施例涉及电路技术，尤其涉及一种低压差线性稳压电路。
背景技术
LDO(Low Dropout Regulator，低压差线性稳压器)使用在其线性区域内运行的晶体管或场效应管(FET)，从输入电压中减去超额的电压，产生经过调节的输出电压。因其成本低，噪音低，静态电流小的特点，广泛应用于电源电路中。
图1是现有技术中一种LDO电路的基本电路结构图。LDO电路主要由以下三个模块构成：第一反馈电阻R F1和第二反馈电阻R F2组成的检测输出电压VOUT，并产生相应的反馈电压的输出电压检测电路、将反馈电压VF与参考电压VREF进行比较，并产生相应的误差电压VEA的误差放大器EA、根据误差电压VEA对输出电流进行调整的功率管M P。AVDD和AVSS分别为电源以及公共地，I L为负载电流。上述电路共同构成了负反馈网络，使得理想状态下输出电压VOUT与参考电压VREF成线性关系，以此抵消因输入电压、环境温度、负载电流等变化的影响，得到一个稳定的输出电压VOUT。输出电压的表达式如式(1)所示：
Figure PCTCN2017117136-appb-000001
其中A为误差放大器的增益，g mp为功率管M P的跨导，r out为LDO输出点的等效阻抗。
上述LDO电路至少存在两个极点：误差放大器输出点对应的极点ω p1以及LDO输出点对应的极点ω p2，其中分别可以表达为式(1)和式(2)：
Figure PCTCN2017117136-appb-000002
Figure PCTCN2017117136-appb-000003
其中，r EA为误差放大器的等效输出阻抗，C EA为误差放大器输出点的等效电容，C OUT为LDO输出点的等效电容。
为了获得良好的瞬态响应特性，通常会在LDO的输出加入uF级别的负载电容，使得C OUT很大。根据式(3)可知：ω P2很低。为了能够提供大的负 载电流范围，需要将功率管M P的尺寸做的很大，这会使得C EA较大，根据式(3)可知：ω P1较低。这会导致负反馈环路不稳定。
为了保证环路稳定，现有技术对LDO电路已经进行了许多改进，包括Miller补偿技术、间接补偿技术和极点分裂等技术，这些技术虽然提高了LDO在大范围电流负载下的环路稳定性，但是无法有效提升电流输出能力，这导致现有的LDO电路在提升电流输出能力的同时需要增加功率管M P的尺寸、补偿电路的尺寸以及静态功耗，有的情况下这是无法接受的开销。
发明内容
本发明实施例提供一种低压差线性稳压电路，以解决现有LDO电路提升电流能力开销过大的问题。
根据本发明实施例的第一方面，提供了一种低压差线性稳压电路。该低压差线性稳压电路包括：输出电压检测电路，用于检测低压差线性稳压电路的输出电压，并产生相应的反馈电压；误差放大电路，用于比较反馈电压和参考电压，并产生相应的误差电压；功率管，功率管的输出电流根据误差电压进行调整；以及衬底电压调整电路，连接至功率管，并配置成根据功率管的输出电流调整功率管的衬底电压，使得衬底电压在预定波动范围内随输出电流增大而降低。
可选地，衬底电压调整电路包括：电流检测单元，用于检测功率管的输出电流；以及电压调整单元，与电流检测单元的输出相连，并配置成根据功率管的输出电流对衬底电压进行反馈控制，以使得衬底电压随输出电流增大而降低。
可选地，电流检测单元包括：第一场效应管，与功率管形成第一电流镜，第一电流镜用于按照第一电流镜像比例输出上述输出电流的第一镜像电流；第二场效应管和第三场效应管均工作在弱反型区，用于使第一场效应管与功率管的漏级电压近似相等，以提高第一电流镜的镜像精度，并且第一镜像电流通过第二场效应管输出；偏置电流源，为第三场效应管提供偏置电流。以及第四场效应管，与第五场效应管形成第二电流镜，其中第四场效应管接收第一镜像电流作为第二电流镜的镜像源。
可选地，第一场效应管、第二场效应管、第三场效应管分别为P沟道金属氧化物半导体场效应晶体管，第四场效应管为N沟道金属氧化物半导体场效应晶体管，并且第一场效应管的栅极、源极、衬底分别与功率管的栅极、源极、衬底一一连接；第二场效应管的栅极与第三场效应管的栅极连接，第二场效应管的源极连接第一场效应管的漏极；第三场效应管的源极连接功率管的漏极，第三场效应管的漏极与第三场效应的栅极以及偏置电流源均相连；第四场效应管的源极接地，第四场效应管的栅极以及漏极均与第二场效应管的漏极相连。
可选地，电压调整单元包括：第五场效应管，与第四场效应管形成第二电流镜，第二电流镜用于将第一镜像电流按照第二电流镜像比例缩小为第二镜像电流；电阻部件，与第五场效应管以及功率管的衬底分别连接，以根据第二镜像电流产生相应的衬底电压。
可选地，第五场效应管为N沟道金属氧化物半导体场效应晶体管，第五场效应管的栅极与第四场效应管的栅极连接，第五场效应管的源极接地；电阻部件包括串联的第一电阻和第二电阻，其中第一电阻连接功率管的源极，第二电阻连接第五场效应管的漏极，第一电阻和第二电阻的连接点与功率管的衬底连接，从而提供衬底电压。
可选地，上述低压差线性稳压电路还包括：衬底漏电保护单元，并联于电阻部件两端。
可选地，衬底漏电保护单元包括：第六场效应管，第六场效应管为P沟道金属氧化物半导体场效应晶体管，并且第六场效应管的栅极以及漏极分别连接至第五场效应管的漏极，第六场效应管的源极连接至功率管的源极。
可选地，输出电压检测电路包括串联连接的第一反馈电阻和第二反馈电阻，第一反馈电阻连接功率管的输出端，第二反馈电阻接地，第一反馈电阻和第二反馈电阻连接点的电压作为反馈电压。
可选地，低压差线性稳压电路还包括Miller补偿电路，Miller补偿电路包括：串联连接的Miller补偿电容和Miller补偿电阻，Miller补偿电容连接误差放大器的输出端，Miller补偿电阻连接功率管的漏极。
可选地，低压差线性稳压电路还包括间接补偿电路，间接补偿电路包括：间接补偿电容和误差放大器的共源共栅管，间接补偿电容一端连接误差放大器的输出端，另一端连接共源共栅管的源极。
可选地，误差放大器包括第七场效应管、第八场效应管、第九场效应管、第十场效应管、第十一场效应管、第十二场效应管、第十三场效应管、第十四场效应管、第十五场效应管，第十二场效应管、第十三场效应管、第十四场效应管、第十五场效应管分别为N沟道场效应晶体管；第七场效应管、第八场效应管、第九场效应管、第十场效应管、第十一场效应管分别为P沟道场效应晶体管；第十二场效应管以及第十五场效应管作为共源共栅管；间接补偿电容一端连接至第十五场效应管的源极，另一端连接至功率管的输出端；第七场效应管的源极、第十场效应管的源极、第十一场效应管的源极分别连接电源；第八场效应管的源极以及第九场效应管的源极分别连接第七场效应管的漏极；第八场效应管的栅极连接反馈电压；第八场效应管的漏极连接第十二场效应管的源极；第九场效应管的栅极连接参考电压；第九场效应管的漏极连接第十五场效应管的源极；第十场效应管的栅极与第十一场效应管的栅极连接；第十场效应管的漏极与第十场效应管的栅极连接后连接至第十二场效应管的漏级；第十一场效应管的漏极输出误差电压，并与功率管的栅极以及第十五场效应管的漏极连接；第十二场效应管的源极还与第十三场效应管的漏极连接；第十五场效应管的源极与第十四场效应管的漏极连接；第十三场效应管的源极以及第十四场效应管的源极分别接地。
可选地，低压差线性稳压电路还包括：极点分裂电路，该极点分裂电路包括：具有低输入电容和低输出电阻的缓冲级，缓冲级连接在误差放大器与功率管之间。
可选地，缓冲级包括：缓冲级管，为P沟道金属氧化物半导体场效应晶体管，缓冲级管的栅极连接误差放大器的输出端，缓冲级管的源极连接功率管的栅极，缓冲级管的漏极接地；缓冲电流源，缓冲电流源的第一端连接电源，缓冲电流源的第二端连接功率管的栅极和缓冲级管的源极。
根据本发明实施例提供的低压差线性稳压电路，通过检测功率管的输出电流的大小，自适应地调整功率管的衬底电压，以此来适当降低功率管的阈值电压，大幅增加低压差线性稳压电路的最大输出电流。
进一步地，本发明实施例提供的低压差线性稳压电路中，电流检测单元实时检测LDO功率管的电流大小；然后衬底电压调整单元根据电流检测电路的输出来调整功率管的衬底电压，功率管电流越大，衬底电压越低，功率管的电流能力就越强。
另外，衬底漏电保护单元用于避免功率管衬底电压过低导致的漏电。衬底电压自适应调整电路与LDO电路的主反馈环路是相互独立的，因此采用本方案不会对LDO电路的稳定性造成影响，可以被广泛应用于绝大多数现有结构的LDO电路。
根据下文结合附图对本发明具体实施例的详细描述，本领域技术人员将会更加明了本发明的上述以及其他目的、优点和特征。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术中一种LDO电路的基本电路结构图；
图2为根据本发明一个实施例的低压差线性稳压电路的示意框图；
图3为根据本发明一个实施例的低压差线性稳压电路的原理图；
图4为根据本发明一个实施例的低压差线性稳压电路的电路图；
图5为根据本发明一个实施例的低压差线性稳压电路应用于Miller补偿结构的LDO的电路示意图；
图6为根据本发明一个实施例的低压差线性稳压电路应用于间接补偿结构的LDO的电路示意图；以及
图7为根据本发明一个实施例的低压差线性稳压电路应用于极点分裂技术的LDO的电路示意图。
具体实施方式
为使得本发明实施例的发明目的、特征、优点能够更加的明显和易懂，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、 完整地描述，显然，所描述的实施例仅仅是本发明实施例一部分实施例，而非全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明实施例保护的范围。
图2为根据本发明一个实施例的低压差线性稳压电路的示意框图，图3为根据本发明一个实施例的低压差线性稳压电路的原理图，该低压差线性稳压电路一般性地可以包括：输出电压检测电路110、误差放大电路120、功率管M P、以及衬底电压调整电路130。
输出电压检测电路110、误差放大电路120、功率管M P共同构成低压差线性稳压电路的主反馈控制电路，其中输出电压检测电路110用于检测低压差线性稳压电路的输出电压，并产生相应的反馈电压。误差放大电路120用于比较低压差线性稳压电路的反馈电压和参考电压，并产生相应的误差电压，功率管M P的输出电流根据所述误差电压进行调整，也即，功率管M P用于根据误差电压对自身的输出电流进行调整。图3中示出的功率管M P使用P沟道金属氧化物半导体场效应晶体管，输出电压检测电路110包括第一反馈电阻R F1和第二反馈电阻R F2，第一反馈电阻R F1和第二反馈电阻R F2串联连接，其中第一反馈电阻R F1连接功率管M P的输出端，第二反馈电阻R F2接地，第一反馈电阻R F1和第二反馈电阻R F2连接点的电压作为反馈电压，也即利用第一反馈电阻R F1和第二反馈电阻R F2对输出电压进行分压，从而使得低压差线性稳压电路的输出电压值按照第一反馈电阻R F1和第二反馈电阻R F2的阻值比例减小为反馈电压VF。该反馈电压VF直接反馈至误差放大器EA。误差放大电路120主要包括误差放大器EA，误差放大器EA将反馈电压VF与参考电压VREF进行比较，并产生相应的误差电压VEA。在另一些实施例中，本领域技术人员可以采用其他替代器件实现上述电路的功能。
衬底电压调整电路130连接至功率管M P，并配置成根据功率管M P的输出电流调整功率管M P的衬底电压V B，使得衬底电压V B在预定波动范围内随输出电流增大而降低。一种实施例中，功率管M P的漏极作为稳压电路的输出电压VOUT的输出端。
衬底电压调整电路130可以包括电流检测单元131、电压调整单元132、另外在一些实施例中还可以进一步包括衬底漏电保护单元133。
电流检测单元131用于检测功率管的输出电流。电压调整单元132与电流检测单元131的输出相连，并配置成根据功率管M P的输出电流对衬底电压V B进行反馈控制，以使得衬底电压V B随输出电流增大而降低。衬底漏电保护单元133用于避免功率管M P源极和衬底之间的二极管导通所产生的漏电。
以下结合一个实施例的电路图对上述衬底电压调整电路130进行介绍。图4为根据本发明一个实施例的低压差线性稳压电路的电路图。
电流检测单元131包括：第一场效应管M PC、第二场效应管M 1、第三场效应管M 2、偏置电流源I B、第四场效应管M 3。第一场效应管M PC与功率管M P形成第一电流镜，该第一电流镜可以按照第一电流镜像比例(表示为X:1)输出上述输出电流的第一镜像电流。第二场效应管M 1和第三场效应管M 2，均工作在弱反型区，用于使第一场效应管M PC与功率管的漏级电压近似相等，以提高第一电流镜的镜像精度，并且第一镜像电流通过第二场效应管M 1输出，偏置电流源I B为第三场效应管M 2提供偏置电流。第四场效应管M 3与第二场效应管M 1连接，用于接收第一镜像电流。其中，第一电流镜像比例的X:1通常取较大的值，这样M 1管和M 3管上的电流较小。
电压调整单元132包括：第五场效应管M 4以及电阻部件，第五场效应管M 4与第四场效应管M 3连接，形成第二电流镜。第二电流镜用于将第一镜像电流按照第二电流镜像比例(表示为Y:1)缩小为第二镜像电流。
电阻部件与第五场效应管M 4以及功率管M P的衬底分别连接，以根据第二镜像电流产生相应的衬底电压V B。衬底漏电保护单元133并联于电阻部件两端。
在本实施例一种可选的电路结构中，第一场效应管M PC、第二场效应管M 1、第三场效应管M 2分别为P沟道金属氧化物半导体场效应晶体管，第四场效应管M 3为N沟道金属氧化物半导体场效应晶体管，第五场效应管M 4为N沟道金属氧化物半导体场效应晶体管，作为衬底漏电保护单元133的第六场效应管M D为P沟道金属氧化物半导体场效应晶体管。
第一场效应管M PC的栅极、源极、衬底分别与功率管M P的栅极、源极、衬底一一对应连接；第二场效应管M 1的栅极与第三场效应管M 2的栅极连接，第二场效应管M 1的源极连接第一场效应管M PC的漏极；第三场 效应管M 2的源极连接功率管M P的漏极，第三场效应管M 2的漏极与第三场效应管M 2的栅极以及偏置电流源I B均相连；第四场效应管M 3的源极接地AVSS，第四场效应管M 3的栅极以及漏极均与第二场效应管M 1的漏极相连。
第五场效应管M 4的栅极与第四场效应管M 3的栅极连接，第五场效应管M 4的源极接地AVSS；电阻部件包括串联的第一电阻R 1和第二电阻R 2，其中第一电阻R 1连接功率管M P的源极(连接至电源AVDD)，第二电阻R 2连接第五场效应管M 4的漏极，第一电阻R1和第二电阻R2的连接点与功率管M P的衬底连接，从而提供衬底电压V B。第六场效应管M D的栅极以及漏极分别连接至第五场效应管M 4的漏极，第六场效应管M D的源极连接至功率管M P的源极。
输出电压检测电路110包括串联连接的第一反馈电阻RF1和第二反馈电阻RF2，其中，第一反馈电阻RF1连接功率管M P的输出端，第二反馈电阻RF2接地，第一反馈电阻RF1和第二反馈电阻RF2连接点的电压作为反馈电压。
上述电路的工作原理为：
功率管M P和M PC管组成第一电流镜，其第一电流镜像比例为X:1，X通常取较大的值，这样M 1管和M 3管上的电流较小，M 1管配置为一个较大的宽长比(W/L)，可以使得M 1管工作在弱反型区。偏置电流I B取一个很小的值，以减少LDO的静态功耗，M 2管也配置为较大的W/L，可以使得M 2管工作于弱反型区，可以得到M PC管的漏极电压V1表达为式(4)：
V1≈V2+|V TH,1|≈VOUT-|V TH,2|+|V TH,1|≈VOUT     式(4)
在式中，V2为M 1管和M 2管的栅极电压，V TH,1为M1管的阈值电压，V TH,2为M2管的阈值电压，VOUT是低压差线性稳压电路的输出电压(反馈电压)。由于功率管M P和M PC管的栅极电压相同，源极电压相同，衬底电压相同。并且功率管M P和M PC管的漏极电压近似相等。因此，M PC管中的电流可以较为准确地镜像功率管M P的电流，从而可以表达为式(5)：
Figure PCTCN2017117136-appb-000004
其中，I M3是M 3管上的电流，I MP是功率管M P的输出电流。
M 3管和M 4管组成第二电流镜，第二电流镜像比例为Y:1，M 3管和M 4管分别配置为较小的W/L，均工作在饱和区，以获得更准确的镜像比例。M 4管中的电流流过电阻R 1产生衬底控制电压V B，从而得到式(6)：
Figure PCTCN2017117136-appb-000005
V SB,MP为功率管的源衬电压。由式(6)式可知：功率管M P上的电流I MP越大，源衬电压V SB,MP就越大，并且选择合适的X、Y和R 1的值，可以在负载电流范围内得到一个范围合理的源衬电压V SB,MP。进一步可以得到功率管M P的阈值电压和饱和电流：
Figure PCTCN2017117136-appb-000006
Figure PCTCN2017117136-appb-000007
其中V TH0是不存在衬偏效应时的阈值电压，对于PMOS为一负值；Υ是体效应系数；
Figure PCTCN2017117136-appb-000008
是与衬底掺杂浓度和温度相关的一个电势；μ n是电子迁移率；C OX是单位面积的栅氧化电容；W/L是功率管M P的宽长比。由式(7)和式(8)可知：源衬电压V SB,MP越大，功率管M P饱和时能够提供越大的电流，并且电流成指数增长。
当功率管M P上的电流I MP增加到一定程度时，电阻R 1和R 2上产生的压降将会使得M D管导通，此后继续增加功率管上的电流，功率管的衬底电压V B几乎不再下降。而R 1和R 2的分压作用使得M D管栅源电压差始终大于功率管的源衬电压V SB,MP。因此，功率管M P的源衬电压V SB,MP一定会小于M D管的阈值电压，这可以避免功率管M P源极和衬底之间的二极管导通所产生的漏电。
本实施例的低压差线性稳压电路，衬底电压自适应调整电路与LDO的主环路是相互独立的，从而不会对LDO的稳定性造成明显影响，因此可以广泛应用于现有的大部分LDO电路结构中，可以使得这些LDO的电流能力大幅提高，根据实验仿真结果，可以提高例如20倍左右。并且开销仅有可以忽略不计的静态功耗和面积。以下是将本实施例的低压差线性稳压电路分别应用于Miller补偿结构的LDO(在功率管M P与误差放大电路之间增设Miller补偿电路)、间接补偿结构的LDO(在功率管M P与误差放大电路之间增设间接补偿电路)、极点分裂技术的LDO(在功率管M P与误差放大电路之间增设极点分裂电路)的实例。
图5为根据本发明一个实施例的低压差线性稳压电路应用于Miller补偿结构的LDO的电路示意图，C c是Miller补偿电容，R c是Miller补偿电阻，R c与C c串联后连接于误差放大器EA的输出端与功率管M P的漏极(即低压差线性稳压电路的输出端VOUT)之间，其中，R c连接误差放大器的输出端，C c连接功率管的漏极，其他元件的连接关系可参看图4及对应描述，此处不再赘述。在不增加衬底电压调整电路130的情况下，增加Miller补偿结构的LDO的最大输出电流，需要等比增加功率管M P的尺寸。而在衬底电压调整电路130应用于Miller补偿结构时，也即利用图5所示的电路时，通过检测M P输出电流的大小，自适应地调整功率管M P的衬底电压V B，提升电流能力的开销仅有可以忽略不计的静态功耗和面积。从而既保留了Miller补偿结构的特点，又以极小的开销提高了电流能力。
图6为根据本发明一个实施例的低压差线性稳压电路应用于间接补偿结构的LDO的电路示意图，与图4所示实施例相比较，图6所示实施例的电路增加了间接补偿电路160，间接补偿电路160包括：间接补偿电容C C和误差放大器EA的共源共栅管(包括第十二场效应管M 12和第十五场效应管M C)，间接补偿电容Cc一端连接至第十五场效应管M C的源极，另一端连接至功率管M P的漏极(即低压差线性稳压电路的输出端VOUT)。
其中，误差放大器EA包括：第七场效应管M 7、第八场效应管M 8、第九场效应管M 9、第十场效应管M 10、第十一场效应管M 11、第十二场效应管M 12、第十三场效应管M 13、第十四场效应管M 14、第十五场效应管M C。其中，第十二场效应管M 12、第十三场效应管M 13、第十四场效应管M 14、第十五场效应管M C分别为N沟道场效应晶体管，第七场效应管M 7、第八场效应管M 8、第九场效应管M 9、第十场效应管M 10、第十一场效应管M 11分别为P沟道场效应晶体管。
其中第七场效应管M 7的源极、第十场效应管M 10的源极、第十一场效应管M 11的源极分别连接电源；第八场效应管M 8的源极以及第九场效应管M 9的源极分别连接第七场效应管M 7的漏极；第八场效应管M 8的栅极连接反馈电压VF；第八场效应管M 8的漏极连接第十二场效应管M 12的源极；第九场效应管M 9的栅极连接参考电压VREF；第九场效应管M 9的漏极连接第十五场效应管M C的源极；第十场效应管M 10的栅极与第十一场效应 管M 11的栅极连接；第十场效应管M 10的漏极与第十场效应管M 10的栅极连接后连接至第十二场效应管M 12的漏级；第十一场效应管M 11的漏极输出误差电压VEA，并与功率管M P的栅极以及第十五场效应管M C的漏极连接；第十二场效应管M 12的源极还与第十三场效应管M 13的漏极连接；第十五场效应管M C的源极与第十四场效应管M 14的漏极连接；第十三场效应管M 13的源极以及第十四场效应管M 14的源极分别接地。
在不增加衬底电压调整电路130的情况下，增加间接补偿结构的LDO的最大输出电流，需要等比增加功率管M P的尺寸和补偿电容C C的面积，这还会导致更大的静态功耗。而在衬底电压调整电路130应用于间接补偿结构的LDO时，也即利用图6所示的电路时，提升电流能力的开销也仅有可以忽略不计的静态功耗和面积。从而既保留了间接补偿结构的特点，也以极小的开销提高了电流能力。
图7为根据本发明一个实施例的低压差线性稳压电路应用于极点分裂技术的LDO的电路示意图，与图4的电路相比较，图7中该电路在误差放大器的输出端与功率管M P的栅极之间增加了极点分裂电路，极点分裂电路包括具有低输入电容和低输出电阻的缓冲级140(如图7中点线虚线框中所示)，也即，缓冲级140的输入电容(与误差放大器相连点的电容)比功率管的栅极电容低，缓冲级的输出电阻(与功率管栅极相连点的等效电阻)比误差放大器的输出电阻低。比如，缓冲级的输入电容比功率管的栅极电容低两个数量级(100倍)以上，缓冲级的输出电阻比误差放大器的输出电阻低两个数量级(100倍)以上。
缓冲级140包括：缓冲级管M buf，为P沟道金属氧化物半导体场效应晶体管，M buf的栅极连接误差放大器的输出端，M buf的源极连接功率管的栅极，M buf的漏极接地；缓冲电流源I buf，I buf的第一端连接电源，I buf的第二端连接功率管的栅极和M buf的源极。在不增加衬底电压调整电路130的情况下，增加极点分裂技术的LDO的最大输出电流，需要等比增加功率管M P的尺寸，还需要大幅增加缓冲级跨导，这会大幅增加静态功耗。而在衬底电压调整电路130应用于极点分裂技术的LDO时，也即利用图7所示的电路时，提升电流能力的开销也仅有可以忽略不计的静态功耗和面积。从而既保留了极点分裂结构的特点，也以极小的开销提高了电流能力。
通过上述分析，可以看出本实施例的低压差线性稳压电路可以广泛应用于绝大多数现有的LDO结构，在保留原有LDO特点的同时，以可以忽略不计的开销，大幅提高LDO的电流能力。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述电路结构亦可以采用其他相同逻辑的器件实现。最后应说明的是：以上实施例仅用以说明本发明实施例的技术方案，而非对其限制；尽管参照前述实施例对本发明实施例进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims (14)

  1. 一种低压差线性稳压电路，包括：
    输出电压检测电路，用于检测所述低压差线性稳压电路的输出电压，并产生对应的反馈电压；
    误差放大电路，用于比较所述反馈电压和参考电压，并产生相应的误差电压；
    功率管，所述功率管的输出电流根据所述误差电压进行调整；以及
    衬底电压调整电路，连接至所述功率管，并配置成根据所述功率管的输出电流调整所述功率管的衬底电压，使得所述衬底电压在预定波动范围内随所述输出电流增大而降低。
  2. 根据权利要求1所述的电路，其中，所述衬底电压调整电路包括：
    电流检测单元，用于检测所述功率管的输出电流；以及
    电压调整单元，与所述电流检测单元的输出相连，并配置成根据所述功率管的输出电流对衬底电压进行反馈控制，以使得所述衬底电压随所述输出电流增大而降低。
  3. 根据权利要求2所述的电路，其中，所述电流检测单元包括：
    第一场效应管，与所述功率管形成第一电流镜，所述第一电流镜用于按照第一电流镜像比例输出所述输出电流的第一镜像电流；
    第二场效应管，以及第三场效应管，均工作在弱反型区，用于使所述第一场效应管与所述功率管的漏级电压近似相等，并且使所述第一镜像电流通过第二场效应管输出；
    偏置电流源，为所述第三场效应管提供偏置电流；以及
    第四场效应管，与所述第二场效应管连接。
  4. 根据权利要求3所述的电路，其中，
    所述第一场效应管、所述第二场效应管、所述第三场效应管分别为P沟道金属氧化物半导体场效应晶体管，所述第四场效应管为N沟道金属氧化物半导体场效应晶体管，并且
    所述第一场效应管的栅极、源极、衬底分别与所述功率管的栅极、源极、衬底一一对应连接；
    所述第二场效应管的栅极与所述第三场效应管的栅极连接，所述第二场效应管的源极连接所述第一场效应管的漏极；
    所述第三场效应管的源极连接所述功率管的漏极，所述第三场效应管的漏极与所述第三场效应管的栅极以及所述偏置电流源均相连；
    所述第四场效应管的源极接地，所述第四场效应管的栅极以及漏极均与所述第二场效应管的漏极相连。
  5. 根据权利要求3或4所述的电路，其中，所述电压调整单元包括：
    第五场效应管，与所述第四场效应管形成第二电流镜，所述第二电流镜用于将所述第一镜像电流按照第二电流镜像比例缩小为第二镜像电流；
    电阻部件，与所述第五场效应管以及所述功率管的衬底分别连接，以根据所述第二镜像电流产生相应的所述衬底电压。
  6. 根据权利要求5所述的电路，其中，
    第五场效应管为N沟道金属氧化物半导体场效应晶体管，所述第五场效应管的栅极与所述第四场效应管的栅极连接，所述第五场效应管的源极接地；
    所述电阻部件包括串联的第一电阻和第二电阻，其中所述第一电阻连接所述功率管的源极，所述第二电阻连接所述第五场效应管的漏极，所述第一电阻和所述第二电阻的连接点与所述功率管的衬底连接，从而提供所述衬底电压。
  7. 根据权利要求6所述的电路，其中，所述电路还包括：
    衬底漏电保护单元，并联于所述电阻部件两端。
  8. 根据权利要求7所述的电路，其中，所述衬底漏电保护单元包括：
    第六场效应管，所述第六场效应管为P沟道金属氧化物半导体场效应晶体管，并且所述第六场效应管的栅极以及漏极分别连接至所述第五场效 应管的漏极，所述第六场效应管的源极连接至所述功率管的源极。
  9. 根据权利要求4所述的电路，其中，
    所述输出电压检测电路包括串联连接的第一反馈电阻和第二反馈电阻，所述第一反馈电阻连接所述功率管的输出端，所述第二反馈电阻接地，所述第一反馈电阻和所述第二反馈电阻连接点的电压作为反馈电压。
  10. 根据权利要求4所述的电路，其中，所述电路还包括Miller补偿电路，所述Miller补偿电路包括：
    串联连接的Miller补偿电容和Miller补偿电阻，所述Miller补偿电阻连接所述误差放大器的输出端，所述Miller补偿电容连接所述功率管的漏极。
  11. 根据权利要求4所述的电路，其中，所述电路还包括间接补偿电路，所述间接补偿电路包括：间接补偿电容和误差放大器的共源共栅管，间接补偿电容一端连接所述功率管的漏极，另一端连接所述误差放大器的共源共栅管的源极。
  12. 根据权利要求11所述的电路，其中，
    所述误差放大器包括第七场效应管、第八场效应管、第九场效应管、第十场效应管、第十一场效应管、第十二场效应管、第十三场效应管、第十四场效应管、第十五场效应管，
    所述第十二场效应管、所述第十三场效应管、所述第十四场效应管、所述第十五场效应管分别为N沟道场效应晶体管；
    所述第七场效应管、第八场效应管、第九场效应管、第十场效应管、第十一场效应管分别为P沟道场效应晶体管；
    所述第十二场效应管以及所述第十五场效应管作为所述共源共栅管；
    所述间接补偿电容一端连接至所述第十五场效应管的源极，另一端连接至所述功率管的输出端；
    所述第七场效应管的源极、所述第十场效应管的源极、所述第十一场效应管的源极分别连接电源；所述第八场效应管的源极以及所述第九场效 应管的源极分别连接所述第七场效应管的漏极；所述第八场效应管的栅极连接所述反馈电压；
    所述第八场效应管的漏极连接第十二场效应管的源极；所述第九场效应管的栅极连接所述参考电压；所述第九场效应管的漏极连接所述第十五场效应管的源极；所述第十场效应管的栅极与所述第十一场效应管的栅极连接；所述第十场效应管的漏极与所述第十场效应管的栅极连接后连接至所述第十二场效应管的漏级；所述第十一场效应管的漏极输出所述误差电压，并与所述功率管的栅极以及所述第十五场效应管的漏极连接；所述第十二场效应管的源极还与所述第十三场效应管的漏极连接；所述第十五场效应管的源极与所述第十四场效应管的漏极连接；所述第十三场效应管的源极以及所述第十四场效应管的源极分别接地。
  13. 根据权利要求4所述的电路，其中，所述电路还包括极点分裂电路，所述极点分裂电路包括：具有低输入电容和低输出电阻的缓冲级，所述缓冲级连接在所述误差放大器与所述功率管之间。
  14. 根据权利要求13所述的电路，其中，所述缓冲级包括：
    缓冲级管，为P沟道金属氧化物半导体场效应晶体管，所述缓冲级管的栅极连接所述误差放大器的输出端，所述缓冲级管的源极连接所述功率管的栅极，所述缓冲级管的漏极接地；
    缓冲电流源，所述缓冲电流源的第一端连接电源，所述缓冲电流源的第二端连接所述功率管的栅极和所述缓冲级管的源极。
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