WO2019114079A1 - Tft阵列基板全接触式测试线路 - Google Patents

Tft阵列基板全接触式测试线路 Download PDF

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Publication number
WO2019114079A1
WO2019114079A1 PCT/CN2018/072300 CN2018072300W WO2019114079A1 WO 2019114079 A1 WO2019114079 A1 WO 2019114079A1 CN 2018072300 W CN2018072300 W CN 2018072300W WO 2019114079 A1 WO2019114079 A1 WO 2019114079A1
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test
array substrate
tft array
driving
terminal
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PCT/CN2018/072300
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English (en)
French (fr)
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陈彩琴
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武汉华星光电半导体显示技术有限公司
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Publication of WO2019114079A1 publication Critical patent/WO2019114079A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

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  • the present invention relates to the field of display panel detection technologies, and in particular, to a TFT array substrate full contact test circuit.
  • OLED Organic Light Emitting Display
  • OLED has no self-illumination, no backlight, high contrast, thin thickness, wide viewing angle, fast response, flexible panel, wide temperature range, and construction. And the excellent features such as simple process, is considered to be an emerging application technology for next-generation flat panel displays.
  • OLED display panels can be divided into Passive Matrix (PM) OLED and Active Matrix (AM) OLED, namely direct addressing and Thin Film Transistor (TFT).
  • PM Passive Matrix
  • AM Active Matrix
  • TFT Thin Film Transistor
  • the AMOLED display panel includes a TFT array substrate on which pixels (Pixel) arranged in an array are provided.
  • a Full Contact Test (so-called full-contact test is performed for each pixel) is performed, and the TFT array substrate is input through the test device.
  • a series of driving signals such as a pixel driving signal and a GOA driving signal to output a display area scanning signal (Gate) and a lighting signal (EM).
  • a conventional TFT array substrate full-contact test circuit includes a plurality of data lines 100, a test chip 300 disposed outside a fan-out area 101 of the plurality of data lines 100, and a test chip 300 disposed on The test chip 300 is away from the driving chip (COF) 500 on the side of the fan-out area 101, and the test chip 300 and the driving chip 500 are both located within the cutting boundary line 700 of the AMOLED display panel; the test chip 300 includes A plurality of test terminals 301, one test terminal 301 is electrically connected to a data line 100; the drive chip 500 includes a plurality of drive terminals 501, and a drive terminal 501 is electrically connected to a corresponding test terminal 301 through a metal trace 350.
  • the test terminal 301, the driving terminal 501, and the metal trace 350 are all made of metal M in the same layer as the source/drain of the TFT in the TFT array substrate.
  • the number of the data lines 100 increases, and the number of test terminals 301 in the test chip 300 increases accordingly, which may cause some design and process risks, such as:
  • the number of test terminals 301 in the test chip 300 is large, the arrangement is dense, and the success rate of the test equipment contacting the test terminal 301 is reduced;
  • the test chip 300 is located between the driving chip 500 and the fan-out area 101 of the data line 100. After the full-contact test of the TFT array substrate is completed, the OLED process is subsequently performed, and the boundary of the package will not reach the area. The test terminal 301 in the test chip 300 is exposed, which increases the risk of short circuit between the test terminals 301 due to the falling of the particulate particles on the test terminals 301 and the entry of the water and oxygen into the test terminal 301 or the metal. The risk of corrosion caused by the trace 350;
  • the test terminal 301 in the test chip 300 is covered by the insulating organic layer 900 to prevent the impurity particles from falling or the water oxygen from entering, so the existing TFT array
  • the substrate full-contact test line can only be tested after the source/drain of the TFT in the TFT array substrate is fabricated in the case shown in FIG. 2, and the TFT array substrate cannot be completely fabricated in the case shown in FIG. Then test again.
  • the object of the present invention is to provide a TFT array substrate full-contact test circuit, which can improve the success rate of the test equipment contacting the test terminal, prevent the risk of line corrosion and electrostatic discharge after the panel is cut, and allow the TFT array substrate to be fabricated.
  • the test can be performed after the source/drain of the TFT and when the TFT array substrate is completely fabricated.
  • the present invention provides a TFT array substrate full-contact test circuit, including a plurality of data lines, a driving chip disposed outside the fan-out area of the plurality of data lines, and a driving chip disposed away from the driving chip.
  • a test chip on one side of the fan-out area, and the drive chip is located within a panel cutting boundary, and the test chip is located outside the panel cutting boundary;
  • the driving chip includes a plurality of driving terminals, and a driving terminal is electrically connected to a data line.
  • the test chip includes a plurality of test terminals, and a test terminal is electrically connected to a driving terminal through at least one trace.
  • the driving terminal and the test terminal are both made of a semiconductor in the same layer as the active layer of the TFT in the TFT array substrate and a metal in the same layer as the source/drain of the TFT in the TFT array substrate, and the trace is formed by the TFT.
  • the active layer of the TFT in the array substrate is made of a semiconductor of the same layer.
  • the semiconductor in the same layer as the active layer of the TFT in the TFT array substrate is polysilicon doped with phosphorus ions or boron ions.
  • the metal in the same layer as the source/drain of the TFT in the TFT array substrate is a laminated combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the test chip is cut off when the panel is cut.
  • the number of the test terminals is equal to the number of the driving terminals, and a test terminal is electrically connected to a driving terminal through a trace.
  • the number of the driving terminals is m times the number of the test terminals, m is a positive integer greater than 1, and a test terminal is electrically connected to the multiplexer through adjacent m traces. Adjacent m drive terminals.
  • the number of the driving terminals is twice the number of the test terminals, and one test terminal is electrically connected to the adjacent two driving terminals corresponding to the multiplexer through two adjacent wires;
  • the multiplexer includes a first switching thin film transistor and a second switching thin film transistor disposed at intervals; a gate of the first switching thin film transistor is connected to a first control signal, and a gate of the second switching thin film transistor Accessing the second control signal; setting n to a positive integer, the nth test terminal and the 2n-1th test trace are respectively connected to the source and the drain of the nth first switching thin film transistor, the second n-1
  • the test trace is electrically connected to the 2n-1th driving terminal; the nth test terminal and the 2nth test trace are respectively connected to the source and the drain of the nth second switching thin film transistor, and the 2nth test trace Electrically connect the 2nth drive terminal.
  • the present invention also provides a TFT array substrate full-contact test circuit, comprising a plurality of data lines, a driving chip disposed outside the fan-out area of the plurality of data lines, and the driving chip disposed away from the fan-out a test chip on one side of the zone, and the drive chip is located within the panel cutting boundary, and the test chip is located outside the panel cutting boundary;
  • the driving chip includes a plurality of driving terminals, and a driving terminal is electrically connected to a data line;
  • the test chip includes a plurality of test terminals, and a test terminal is electrically connected to a driving terminal through at least one trace;
  • the driving terminal and the test terminal are both made of a semiconductor in the same layer as the active layer of the TFT in the TFT array substrate and a metal in the same layer as the source/drain of the TFT in the TFT array substrate, wherein the routing is made of Fabricated in the same layer as the active layer of the TFT in the TFT array substrate;
  • the semiconductor in the same layer as the active layer of the TFT in the TFT array substrate is polysilicon doped with phosphorus ions or boron ions;
  • the metal in the same layer as the source/drain of the TFT in the TFT array substrate is a laminated combination of one or more of molybdenum, titanium, aluminum, and copper;
  • the test chip is cut off when the panel is cut.
  • the invention has the beneficial effects that the TFT array substrate full-contact test circuit provided by the invention has the test chip disposed outside the panel cutting boundary, and the available space outside the panel cutting boundary is large, allowing the test chip to be used.
  • the size of each test terminal and the distance between adjacent test terminals are increased, so that the success rate of the test device contacting the test terminal can be improved; the test chip is cut off when the panel is cut, and does not remain in the TFT array.
  • the wiring on the substrate and connecting the test terminal and the driving terminal on the driving chip is made of a semiconductor in the same layer as the active layer of the TFT in the TFT array substrate, and the semiconductor chemical characteristics are less active, and the water and oxygen resistance is stronger.
  • test can be performed after the source/drain of the TFT in the TFT array substrate is fabricated and when the TFT array substrate is completely fabricated.
  • FIG. 1 is a schematic structural view of a conventional TFT array substrate full-contact test line
  • FIG. 2 is a schematic cross-sectional view showing a structure of a film layer corresponding to A-A in FIG. 1 after fabricating a source/drain of a TFT in a TFT array substrate;
  • FIG. 3 is a schematic cross-sectional view showing a structure of a film layer corresponding to A-A in FIG. 1 after the TFT array substrate is completely fabricated;
  • FIG. 4 is a schematic structural view of a first embodiment of a TFT array substrate full-contact test line according to the present invention.
  • FIG. 5 is a schematic cross-sectional view showing a structure of a film layer corresponding to B-B in FIG. 4 after the TFT array substrate is completely fabricated;
  • FIG. 6 is a schematic structural view of a second embodiment of a TFT array substrate full-contact test line of the present invention.
  • the invention provides a TFT array substrate full contact test circuit.
  • the TFT array substrate full-contact test line of the present invention includes a plurality of data lines 1, and a driving chip disposed outside the fan-out area 11 of the plurality of data lines 1. 3 and a test chip 5 disposed on a side of the driving chip 3 away from the fan-out area 11.
  • the test chip and the driving chip are both disposed within the panel cutting boundary.
  • the TFT array substrate full-contact test circuit of the present invention sets the driving chip 3 within the panel cutting boundary 7, and the The test chip 5 is disposed outside the panel cutting boundary 7 (the panel is not limited to the AMOLED display panel, the liquid crystal display panel, etc.; in order to achieve the specific size and shape requirements of the panel, the panel is cut along the panel cutting boundary 7) After the TFT array substrate is fully contact tested, the test chip 5 is cut off when the panel is cut.
  • the driving chip 3 includes a plurality of driving terminals 31, and a driving terminal 31 is electrically connected to a data line 1.
  • the test chip 5 includes a plurality of test terminals 51.
  • the number of the test terminals 51 is equal to the number of the driving terminals 31, the test terminals 51 and the driving terminals 31 are in a one-to-one relationship, and a test terminal 51 passes through a trace 35.
  • a driving terminal 31 is electrically connected.
  • the driving terminal 31 and the test terminal 51 are both semiconductors in the same layer as the active layer of the TFT in the TFT array substrate.
  • the active layer of the inner TFT is formed in the same layer as the semiconductor S.
  • the two ends of the trace 35 respectively correspond to the region of the semiconductor S corresponding to the driving terminal 31 and the semiconductor S corresponds to the test terminal 51.
  • the semiconductor S in the same layer as the active layer of the TFT in the TFT array substrate is polysilicon (P-Si) doped with phosphorus (P) ions or boron (B) ions; and the TFT array substrate
  • the metal M of the source/drain of the TFT is a laminated combination of one or more of molybdenum (Mo), titanium (Ti), aluminum (Al), and copper (Cu).
  • n be a positive integer. After the test device contacts all the test terminals 51 successfully, the nth test terminal 51 performs a loop current test on the pixels on the nth data line 1 via the corresponding nth drive terminal 31.
  • test chip 5 Since the test chip 5 is cut off when the panel is cut, it does not remain on the TFT array substrate, and the trace 35 connecting the test terminal 51 and the drive terminal 31 on the drive chip 3 is connected to the TFT in the TFT array substrate.
  • the active layer is made of the same layer of semiconductor S. The chemical properties of the semiconductor S are less active and the water-insulating ability is stronger, so that the risk of line corrosion and electrostatic discharge after the panel is cut can be prevented.
  • test terminal 51 Since the test chip 5 is cut off when the panel is cut, the test terminal 51 does not have to cover the insulating organic layer 9 thereon in order to prevent the falling of the impurity particles or the entry of water oxygen as in the prior art, thereby allowing the fabrication of the organic layer 9
  • the test can be performed after the source/drain of the TFT in the TFT array substrate and after the TFT array substrate is completely fabricated.
  • test terminal 51 is the number of the drive terminals 31. Two times, the test terminal 51 and the driving terminal 31 are in a one-to-two relationship, and one test terminal 51 is electrically connected to the adjacent two driving terminals via the adjacent two wires 35 and the multiplexer 6 31.
  • the multiplexer 6 includes a first switching thin film transistor T1 and a second switching thin film transistor T2 disposed at intervals; a gate of the first switching thin film transistor T1 is connected to a first control signal MS1, The gate of the second switching thin film transistor T2 is connected to the second control signal MS2; n is a positive integer, and the nth test terminal 51 and the 2n-1 test trace 35 are respectively connected to the nth first switching thin film transistor.
  • the source and the drain of the T1, the 2n-1 test traces 35 are electrically connected to the 2n-1th drive terminal 31; the nth test terminal 51 and the 2nth test trace 35 are respectively connected to the nth The source and the drain of the second switching thin film transistor T2, and the 2nth test trace 35 are electrically connected to the 2nth driving terminal 31.
  • the test device contacts all the test terminals 51 successfully, if the first control signal MS1 controls the first switch thin film transistor T1 to be turned on, the nth test terminal 51 passes through the nth first switch thin film transistor T1 and the 2n-1th.
  • the test trace 35 is connected to the 2n-1th drive terminal 31 to perform a loop current test on the pixels on the 2n-1th data line 1; if the second control signal MS2 controls the second switch thin film transistor T2 to be turned on,
  • the nth test terminal 51 communicates with the 2nth drive terminal 31 through the nth second switching thin film transistor T2 and the 2nth test trace 35, thereby performing loop current test on the pixels on the 2nth data line 1.
  • the second embodiment is only an example in which the number of the driving terminals 31 is twice the number of the test terminals 51, and the relationship between the test terminals 51 and the driving terminals 31 is one-to-two.
  • the number of the drive terminals 31 is three times, four times, and the like of the number of the test terminals 51, and it is only necessary to adaptively adjust the number of the switching thin film transistors and the control signals in the multiplexer 6.
  • the TFT array substrate full-contact test circuit of the present invention has the test chip disposed outside the panel cutting boundary, and the available space outside the panel cutting boundary is large, allowing each test terminal on the test chip.
  • the size and the distance between adjacent test terminals are increased, so that the success rate of the test device contacting the test terminal can be improved; the test chip is cut off when the panel is cut, and does not remain on the TFT array substrate, and
  • the wiring connecting the test terminal and the driving terminal on the driving chip is made of a semiconductor in the same layer as the active layer of the TFT in the TFT array substrate, and the semiconductor has relatively inactive chemical characteristics and is highly resistant to water and oxygen, thereby preventing The risk of line corrosion and electrostatic discharge occurs after panel cutting; since the test chip is cut off when the panel is cut, the test terminal does not need to be covered with an insulating organic layer as in the prior art, thereby allowing the TFT array to be fabricated.
  • the test can be performed after the source/drain of the TFT in the substrate and when the T

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Abstract

一种TFT阵列基板全接触式测试线路，将测试芯片(5)设于面板切割界线(7)之外，允许测试芯片(5)上的各测试端子(51)的尺寸以及相邻测试端子(51)之间的距离加大，能够提高测试设备接触测试端子(51)的成功率；测试芯片(5)在面板切割时被切割掉，且连接测试端子(51)与驱动芯片(3)上驱动端子(31)的走线(35)由与TFT阵列基板内TFT的有源层同层的半导体(S)制作而成，能够防止面板切割后发生线路腐蚀与静电放电的风险；由于测试芯片(5)在面板切割时被切割掉，测试端子(51)上无需覆盖绝缘的有机层，从而允许在制作出TFT阵列基板内TFT的源/漏极后及在TFT阵列基板全部制作完成的情况下都可以进行测试。

Description

TFT阵列基板全接触式测试线路 技术领域
本发明涉及显示面板检测技术领域，尤其涉及一种TFT阵列基板全接触式测试线路。
背景技术
有机发光二极管显示面板(Organic Light Emitting Display，OLED)由于同时具备自发光，不需背光源、对比度高、厚度薄、视角广、反应速度快、可用于挠曲性面板、使用温度范围广、构造及制程较简单等优异特性，被认为是下一代平面显示器的新兴应用技术。
OLED显示面板按照驱动类型可分为无源矩阵型(Passive Matrix，PM)OLED和有源矩阵型(Active Matrix，AM)OLED两大类，即直接寻址和薄膜晶体管(Thin Film Transistor，TFT)矩阵寻址两类。AMOLED显示面板包括TFT阵列基板，在所述TFT阵列基板上设有呈阵列式排布的像素(Pixel)。
在AMOLED显示面板的TFT阵列基板的制作过程中，会对其进行全接触式测试(Full Contact Test)(所谓全接触式测试即对每个像素都进行测试)，通过测试设备向TFT阵列基板输入像素驱动信号、GOA驱动信号等一系列的驱动信号，以输出显示区扫描信号(Gate)和发光信号(EM)。
由于进行全接触式测试时会对每个像素进行回路电流测试，故而TFT阵列基板内的每条数据线(Data Line)都需要信号给入。请参阅图1，现有的TFT阵列基板全接触式测试线路包括多条数据线100、设于所述多条数据线100的扇出区(Fan out)101之外的测试芯片300及设于所述测试芯片300远离所述扇出区101一侧的驱动芯片(COF)500，并且所述测试芯片300与驱动芯片500均位于AMOLED显示面板的切割界线700之内；所述测试芯片300包括多个测试端子301，一测试端子301对应电性连接一数据线100；所述驱动芯片500包括多个驱动端子501，一驱动端子501通过一金属走线350电性连接一对应的测试端子301。结合图1与图3，所述测试端子301、驱动端子501及金属走线350均采用与TFT阵列基板内TFT的源/漏极同层的金属M制作。随着AMOLED显示面板解析度的增加，所述数据线100的数量增多，所述测试芯片300内测试端子301的数量相应增多，这样会引发一些设计和工艺方面的风险，例如：
A、所述测试芯片300内测试端子301的数量众多，排布较密集，测试设备接触所述测试端子301的成功率降低；
B、所述测试芯片300位于所述驱动芯片500到数据线100的扇出区101之间，TFT阵列基板全接触式测试完成后，后续会进行OLED制程，封装的边界将不会到达此区域，造成所述测试芯片300内的测试端子301裸露，加大了由于杂质颗粒(Particle)掉落在各测试端子301上造成测试端子301之间短路的风险以及由于水氧进入测试端子301或金属走线350造成腐蚀的风险；
C、随着所述测试芯片300内测试端子301的数量增多，全部测试端子301所占的金属面积较大，金属的导电性良好，有静电放电(Electro-StaticDischarge，ESD)的风险。
此外，如图3所示，TFT阵列基板制作完成后，所述测试芯片300内的测试端子301被绝缘的有机层900覆盖以防止杂质颗粒掉落或水氧进入，故而该现有的TFT阵列基板全接触式测试线路只允许在图2所示的情况下即制作出TFT阵列基板内TFT的源/漏极后进行测试，而不能在图3所示的情况下即TFT阵列基板全部制作完成后再进行测试。
发明内容
本发明的目的在于提供一种TFT阵列基板全接触式测试线路，能够提高测试设备接触测试端子的成功率，防止面板切割后发生线路腐蚀与静电放电的风险，并允许在制作出TFT阵列基板内TFT的源/漏极后及在TFT阵列基板全部制作完成的情况下都可以进行测试。
为实现上述目的，本发明提供一种TFT阵列基板全接触式测试线路，包括多条数据线、设于所述多条数据线的扇出区之外的驱动芯片及设于所述驱动芯片远离所述扇出区一侧的测试芯片，并且所述驱动芯片位于面板切割界线之内，而所述测试芯片位于面板切割界线之外；
所述驱动芯片包括多个驱动端子，一驱动端子对应电性连接一数据线；所述测试芯片包括多个测试端子，一测试端子至少通过一走线电性连接一驱动端子。
所述驱动端子与测试端子均由与TFT阵列基板内TFT的有源层同层的半导体及与TFT阵列基板内TFT的源/漏极同层的金属制作而成，所述走线由与TFT阵列基板内TFT的有源层同层的半导体制作而成。
所述与TFT阵列基板内TFT的有源层同层的半导体为掺杂了磷离子或硼离子的多晶硅。
所述与TFT阵列基板内TFT的源/漏极同层的金属为钼、钛、铝、铜中的一种或几种的层叠组合。
完成TFT阵列基板全接触式测试后，所述测试芯片在面板切割时被切割掉。
可选的，所述测试端子的数量与所述驱动端子的数量相等，一测试端子通过一走线对应电性连接一驱动端子。
可选的，所述驱动端子的数量是所述测试端子的数量的m倍，m为大于1的正整数，一测试端子通过相邻的m条走线与多路复用器对应电性连接相邻的m个驱动端子。
优选的，所述驱动端子的数量是所述测试端子的数量的两倍，一测试端子通过相邻的两条走线与多路复用器对应电性连接相邻的两个驱动端子；
所述多路复用器包括间隔设置的第一开关薄膜晶体管与第二开关薄膜晶体管；所述第一开关薄膜晶体管的栅极接入第一控制信号，所述第二开关薄膜晶体管的栅极接入第二控制信号；设n为正整数，第n个测试端子与第2n-1条测试走线分别电线连接第n个第一开关薄膜晶体管的源极与漏极，第2n-1条测试走线电性连接第2n-1个驱动端子；第n个测试端子与第2n条测试走线分别电线连接第n个第二开关薄膜晶体管的源极与漏极，第2n条测试走线电性连接第2n个驱动端子。
本发明还提供一种TFT阵列基板全接触式测试线路，包括多条数据线、设于所述多条数据线的扇出区之外的驱动芯片及设于所述驱动芯片远离所述扇出区一侧的测试芯片，并且所述驱动芯片位于面板切割界线之内，而所述测试芯片位于面板切割界线之外；
所述驱动芯片包括多个驱动端子，一驱动端子对应电性连接一数据线；所述测试芯片包括多个测试端子，一测试端子至少通过一走线电性连接一驱动端子；
其中，所述驱动端子与测试端子均由与TFT阵列基板内TFT的有源层同层的半导体及与TFT阵列基板内TFT的源/漏极同层的金属制作而成，所述走线由与TFT阵列基板内TFT的有源层同层的半导体制作而成；
其中，所述与TFT阵列基板内TFT的有源层同层的半导体为掺杂了磷离子或硼离子的多晶硅；
其中，所述与TFT阵列基板内TFT的源/漏极同层的金属为钼、钛、铝、铜中的一种或几种的层叠组合；
其中，完成TFT阵列基板全接触式测试后，所述测试芯片在面板切割时被切割掉。
本发明的有益效果：本发明提供的一种TFT阵列基板全接触式测试线路，将测试芯片设于面板切割界线之外，面板切割界线之外的可利用空间较大，允许所述测试芯片上的各测试端子的尺寸以及相邻测试端子之间的距离加大，从而能够提高测试设备接触所述测试端子的成功率；所述测试芯片在面板切割时被切割掉，不会残留在TFT阵列基板上，且连接所述测试端子与驱动芯片上驱动端子的走线由与TFT阵列基板内TFT的有源层同层的半导体制作而成，半导体化学特性较不活泼，隔水氧能力较强，从而能够防止面板切割后发生线路腐蚀与静电放电的风险；由于测试芯片在面板切割时被切割掉，所述测试端子不必像现有技术那样需要在其上覆盖绝缘的有机层，从而允许在制作出TFT阵列基板内TFT的源/漏极后及在TFT阵列基板全部制作完成的情况下都可以进行测试。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的TFT阵列基板全接触式测试线路的结构示意图；
图2为在制作出TFT阵列基板内TFT的源/漏极后对应于图1中A-A处的膜层结构剖面示意图；
图3为TFT阵列基板全部制作完成后对应于图1中A-A处的膜层结构剖面示意图；
图4为本发明的TFT阵列基板全接触式测试线路的第一实施例的结构示意图；
图5为TFT阵列基板全部制作完成后对应于图4中B-B处的膜层结构剖面示意图；
图6为本发明的TFT阵列基板全接触式测试线路的第二实施例的结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
本发明提供一种TFT阵列基板全接触式测试线路。请同时参阅图4与图5，本发明的TFT阵列基板全接触式测试线路包括多条数据线1、设于所 述多条数据线1的扇出区(Fan out)11之外的驱动芯片3及设于所述驱动芯片3远离所述扇出区11一侧的测试芯片5。与现有技术将测试芯片与驱动芯片均设在面板切割界线之内不同，本发明的TFT阵列基板全接触式测试线路将所述驱动芯片3设于面板切割界线7之内，而将所述测试芯片5设于面板切割界线7之外(面板不限于AMOLED显示面板、液晶显示面板等；为使面板达到特定的尺寸及形状要求，会沿所述面板切割界线7对面板进行切割)，完成TFT阵列基板全接触式测试后，所述测试芯片5在面板切割时便被切割掉。
所述驱动芯片3包括多个驱动端子31，一驱动端子31对应电性连接一数据线1。所述测试芯片5包括多个测试端子51。在该第一实施例中，所述测试端子51的数量与所述驱动端子31的数量相等，所述测试端子51与驱动端子31是一对一的关系，一测试端子51通过一走线35对应电性连接一驱动端子31。
值得注意的是，如图5所示，在本发明的TFT阵列基板全接触式测试线路中，所述驱动端子31与测试端子51均由与TFT阵列基板内TFT的有源层同层的半导体S及与TFT阵列基板内TFT的源/漏极同层的金属M制作而成，所述金属M设于所述半导体S上与所述半导体S接触；所述走线35由与TFT阵列基板内TFT的有源层同层的半导体S制作而成，该走线35的两端分别与所述半导体S对应于所述驱动端子31的区域及所述半导体S对应于所述测试端子51的区域连贯。
具体地，所述与TFT阵列基板内TFT的有源层同层的半导体S为掺杂了磷(P)离子或硼(B)离子的多晶硅(P-Si)；所述与TFT阵列基板内TFT的源/漏极同层的金属M为钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)中的一种或几种的层叠组合。
由于将所述测试芯片5设于面板切割界线7之外，面板切割界线7之外的可利用空间较大，允许所述测试芯片5上的各测试端子51的尺寸以及相邻测试端子51之间的距离加大，从而能够提高测试设备接触所述测试端子51的成功率。设n为正整数，测试设备接触全部测试端子51成功后，第n个测试端子51经由对应的第n个驱动端子31对第n条数据线1上的像素进行回路电流测试。
由于所述测试芯片5在面板切割时被切割掉，不会残留在TFT阵列基板上，且连接所述测试端子51与驱动芯片3上驱动端子31的走线35由与TFT阵列基板内TFT的有源层同层的半导体S制作而成，半导体S的化学特性较不活泼，隔水氧能力较强，从而能够防止面板切割后发生线路腐蚀 与静电放电的风险。
由于所述测试芯片5在面板切割时被切割掉，所述测试端子51不必像现有技术那样为了防止杂质颗粒掉落或水氧进入而在其上覆盖绝缘的有机层9，从而允许在制作出TFT阵列基板内TFT的源/漏极后及在TFT阵列基板全部制作完成的情况下都可以进行测试。
图6所示为本发明的TFT阵列基板全接触式测试线路的第二实施例，其与第一实施例的不同之处在于：所述测试端子51的数量是所述驱动端子31的数量的两倍，所述测试端子51与驱动端子31是一对二的关系，一测试端子51通过相邻的两条走线35与多路复用器6对应电性连接相邻的两个驱动端子31。
具体地，所述多路复用器6包括间隔设置的第一开关薄膜晶体管T1与第二开关薄膜晶体管T2；所述第一开关薄膜晶体管T1的栅极接入第一控制信号MS1，所述第二开关薄膜晶体管T2的栅极接入第二控制信号MS2；设n为正整数，第n个测试端子51与第2n-1条测试走线35分别电线连接第n个第一开关薄膜晶体管T1的源极与漏极，第2n-1条测试走线35电性连接第2n-1个驱动端子31；第n个测试端子51与第2n条测试走线35分别电线连接第n个第二开关薄膜晶体管T2的源极与漏极，第2n条测试走线35电性连接第2n个驱动端子31。
测试设备接触全部测试端子51成功后，若所述第一控制信号MS1控制第一开关薄膜晶体管T1打开，则第n个测试端子51通过第n个第一开关薄膜晶体管T1及第2n-1条测试走线35连通第2n-1个驱动端子31，从而对第2n-1条数据线1上的像素进行回路电流测试；若所述第二控制信号MS2控制第二开关薄膜晶体管T2打开，则第n个测试端子51通过第n个第二开关薄膜晶体管T2及第2n条测试走线35连通第2n个驱动端子31，从而对第2n条数据线1上的像素进行回路电流测试。
该第二实施例仅是以所述驱动端子31的数量是所述测试端子51的数量的两倍、所述测试端子51与驱动端子31是一对二的关系为例，也可以设置所述驱动端子31的数量是所述测试端子51的数量的三倍、四倍等，只需适应性的调整所述多路复用器6中开关薄膜晶体管及控制信号的数量即可。
除上述不同之处外，其余均与第一实施例相同，此处不再进行重复性描述。
综上所述，本发明的TFT阵列基板全接触式测试线路，将测试芯片设于面板切割界线之外，面板切割界线之外的可利用空间较大，允许所述测 试芯片上的各测试端子的尺寸以及相邻测试端子之间的距离加大，从而能够提高测试设备接触所述测试端子的成功率；所述测试芯片在面板切割时被切割掉，不会残留在TFT阵列基板上，且连接所述测试端子与驱动芯片上驱动端子的走线由与TFT阵列基板内TFT的有源层同层的半导体制作而成，半导体化学特性较不活泼，隔水氧能力较强，从而能够防止面板切割后发生线路腐蚀与静电放电的风险；由于测试芯片在面板切割时被切割掉，所述测试端子不必像现有技术那样需要在其上覆盖绝缘的有机层，从而允许在制作出TFT阵列基板内TFT的源/漏极后及在TFT阵列基板全部制作完成的情况下都可以进行测试。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明的权利要求的保护范围。

Claims (12)

  1. 一种TFT阵列基板全接触式测试线路，包括多条数据线、设于所述多条数据线的扇出区之外的驱动芯片及设于所述驱动芯片远离所述扇出区一侧的测试芯片，并且所述驱动芯片位于面板切割界线之内，而所述测试芯片位于面板切割界线之外；
    所述驱动芯片包括多个驱动端子，一驱动端子对应电性连接一数据线；所述测试芯片包括多个测试端子，一测试端子至少通过一走线电性连接一驱动端子。
  2. 如权利要求1所述的TFT阵列基板全接触式测试线路，其中，所述驱动端子与测试端子均由与TFT阵列基板内TFT的有源层同层的半导体及与TFT阵列基板内TFT的源/漏极同层的金属制作而成，所述走线由与TFT阵列基板内TFT的有源层同层的半导体制作而成。
  3. 如权利要求2所述的TFT阵列基板全接触式测试线路，其中，所述与TFT阵列基板内TFT的有源层同层的半导体为掺杂了磷离子或硼离子的多晶硅。
  4. 如权利要求2所述的TFT阵列基板全接触式测试线路，其中，所述与TFT阵列基板内TFT的源/漏极同层的金属为钼、钛、铝、铜中的一种或几种的层叠组合。
  5. 如权利要求1所述的TFT阵列基板全接触式测试线路，其中，完成TFT阵列基板全接触式测试后，所述测试芯片在面板切割时被切割掉。
  6. 如权利要求1所述的TFT阵列基板全接触式测试线路，其中，所述测试端子的数量与所述驱动端子的数量相等，一测试端子通过一走线对应电性连接一驱动端子。
  7. 如权利要求1所述的TFT阵列基板全接触式测试线路，其中，所述驱动端子的数量是所述测试端子的数量的m倍，m为大于1的正整数，一测试端子通过相邻的m条走线与多路复用器对应电性连接相邻的m个驱动端子。
  8. 如权利要求7所述的TFT阵列基板全接触式测试线路，其中，所述驱动端子的数量是所述测试端子的数量的两倍，一测试端子通过相邻的两条走线与多路复用器对应电性连接相邻的两个驱动端子；
    所述多路复用器包括间隔设置的第一开关薄膜晶体管与第二开关薄膜晶体管；所述第一开关薄膜晶体管的栅极接入第一控制信号，所述第二开 关薄膜晶体管的栅极接入第二控制信号；设n为正整数，第n个测试端子与第2n-1条测试走线分别电线连接第n个第一开关薄膜晶体管的源极与漏极，第2n-1条测试走线电性连接第2n-1个驱动端子；第n个测试端子与第2n条测试走线分别电线连接第n个第二开关薄膜晶体管的源极与漏极，第2n条测试走线电性连接第2n个驱动端子。
  9. 一种TFT阵列基板全接触式测试线路，包括多条数据线、设于所述多条数据线的扇出区之外的驱动芯片及设于所述驱动芯片远离所述扇出区一侧的测试芯片，并且所述驱动芯片位于面板切割界线之内，而所述测试芯片位于面板切割界线之外；
    所述驱动芯片包括多个驱动端子，一驱动端子对应电性连接一数据线；所述测试芯片包括多个测试端子，一测试端子至少通过一走线电性连接一驱动端子；
    其中，所述驱动端子与测试端子均由与TFT阵列基板内TFT的有源层同层的半导体及与TFT阵列基板内TFT的源/漏极同层的金属制作而成，所述走线由与TFT阵列基板内TFT的有源层同层的半导体制作而成；
    其中，所述与TFT阵列基板内TFT的有源层同层的半导体为掺杂了磷离子或硼离子的多晶硅；
    其中，所述与TFT阵列基板内TFT的源/漏极同层的金属为钼、钛、铝、铜中的一种或几种的层叠组合；
    其中，完成TFT阵列基板全接触式测试后，所述测试芯片在面板切割时被切割掉。
  10. 如权利要求9所述的TFT阵列基板全接触式测试线路，其中，所述测试端子的数量与所述驱动端子的数量相等，一测试端子通过一走线对应电性连接一驱动端子。
  11. 如权利要求9所述的TFT阵列基板全接触式测试线路，其中，所述驱动端子的数量是所述测试端子的数量的m倍，m为大于1的正整数，一测试端子通过相邻的m条走线与多路复用器对应电性连接相邻的m个驱动端子。
  12. 如权利要求11所述的TFT阵列基板全接触式测试线路，其中，所述驱动端子的数量是所述测试端子的数量的两倍，一测试端子通过相邻的两条走线与多路复用器对应电性连接相邻的两个驱动端子；
    所述多路复用器包括间隔设置的第一开关薄膜晶体管与第二开关薄膜晶体管；所述第一开关薄膜晶体管的栅极接入第一控制信号，所述第二开关薄膜晶体管的栅极接入第二控制信号；设n为正整数，第n个测试端子 与第2n-1条测试走线分别电线连接第n个第一开关薄膜晶体管的源极与漏极，第2n-1条测试走线电性连接第2n-1个驱动端子；第n个测试端子与第2n条测试走线分别电线连接第n个第二开关薄膜晶体管的源极与漏极，第2n条测试走线电性连接第2n个驱动端子。
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CN109782503B (zh) * 2019-03-14 2021-11-30 京东方科技集团股份有限公司 一种显示模组及终端
CN110047412A (zh) * 2019-04-30 2019-07-23 厦门天马微电子有限公司 显示面板及其制备方向、显示面板母板及其测试方法
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CN110910804B (zh) * 2019-12-26 2022-08-12 厦门天马微电子有限公司 一种显示面板及显示装置
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