WO2019085715A1 - 阵列基板及其制造方法、显示面板 - Google Patents

阵列基板及其制造方法、显示面板 Download PDF

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Publication number
WO2019085715A1
WO2019085715A1 PCT/CN2018/109620 CN2018109620W WO2019085715A1 WO 2019085715 A1 WO2019085715 A1 WO 2019085715A1 CN 2018109620 W CN2018109620 W CN 2018109620W WO 2019085715 A1 WO2019085715 A1 WO 2019085715A1
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WIPO (PCT)
Prior art keywords
electrode
common electrode
shield
pixel
line
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PCT/CN2018/109620
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English (en)
French (fr)
Inventor
龙春平
乔勇
吴新银
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/476,191 priority Critical patent/US11204531B2/en
Priority to EP18874663.0A priority patent/EP3709078B1/en
Publication of WO2019085715A1 publication Critical patent/WO2019085715A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136218—Shield electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a method of manufacturing the same, and a display panel.
  • the present disclosure provides an array substrate comprising: a plurality of pixel structures, the pixel structure comprising: at least one pixel region, one side of the pixel region is provided with a signal trace;
  • the shield electrode when the signal trace is the common electrode line, the shield electrode includes: a first shield sub-electrode, and the first shield sub-electrode is connected to the common electrode line through a via.
  • the shield electrode when the signal trace is the gate line, includes: a second shield sub-electrode, the second shield sub-electrode is located in the pixel region;
  • the second shield sub-electrode is electrically connected to the common electrode.
  • the shield electrode when the signal trace is the gate line, includes: a third shield sub-electrode, the orthographic projection of the third shield sub-electrode at a plane where the gate line is located Falling into the area where the grid line is located;
  • the third shield sub-electrode is electrically connected to the common electrode.
  • the shield electrode when the signal trace includes the common electrode line and the gate line, the shield electrode includes a first shield sub-electrode and a second shield sub-electrode, and the first shield sub-electrode passes a via is connected to the common electrode line, and the second shield sub-electrode is located in the pixel area;
  • the shield electrode when the signal trace includes the common electrode line and the gate line, the shield electrode includes a first shield sub-electrode and a third shield sub-electrode, and the first shield sub-electrode passes a via is connected to the common electrode line, and an orthographic projection of the third shield sub-electrode at a plane where the gate line is located falls into a region where the gate line is located;
  • a common electrode is further disposed in the pixel region, and the common electrode is electrically connected to the common electrode line;
  • the third shield sub-electrode is electrically connected to the common electrode.
  • the common electrode is disposed in the same layer as the pixel electrode, and the shield electrode is directly connected to the common electrode.
  • the common electrode is a comb electrode, and the common electrode includes: a plurality of first comb teeth, a shape and an arrangement direction of the shield electrode and a shape and arrangement of the first comb portion The same direction.
  • the pixel structure includes: two of the pixel regions, between which two gate lines are disposed, and the two pixel regions share one of the gate lines.
  • the pixel structure includes: two of the pixel regions, and the two pixel regions are disposed along a first direction;
  • a side of the pixel area parallel to the first direction is provided with a data line, and the two of the pixel areas share one of the data lines.
  • the pixel electrode is a comb electrode.
  • the method further includes: a thin film transistor disposed in one-to-one correspondence with the pixel region.
  • the present disclosure also provides a display panel comprising: the array substrate as described above.
  • the present disclosure further provides a method for fabricating the above array substrate, wherein the array substrate comprises: a plurality of pixel structures, the pixel structure comprising: at least one pixel region, wherein a pixel electrode is disposed in the pixel region, One side of the pixel area is provided with a signal trace, as shown in FIG. 7, the manufacturing method includes the steps of:
  • a shield electrode disposed in the same layer as the pixel electrode is disposed on a side of the pixel electrode adjacent to the signal trace, and the shield electrode is electrically connected to the common electrode line.
  • the signal trace is the gate line
  • the shield electrode includes a second shield sub-electrode
  • the second shield sub-electrode is located in the pixel region
  • the pixel region is further disposed a common electrode
  • the manufacturing method further comprising the steps of:
  • the second shield sub-electrode is electrically connected to the common electrode.
  • the signal trace is the gate line
  • the shield electrode includes a third shield sub-electrode
  • the third shield sub-electrode is located outside the pixel region
  • the third shield sub-electrode is located at An orthographic projection of a plane in which the gate line is located is completed in a region where the gate line is located, and a common electrode is further disposed in the pixel region
  • the manufacturing method further includes the steps of:
  • the third shield sub-electrode is electrically connected to the common electrode.
  • FIG. 1 is a top plan view of a pixel structure in an array substrate in the prior art
  • FIG. 2 is a top plan view of a pixel structure in an array substrate according to an embodiment of the present disclosure
  • FIG. 3 is a top plan view of a pixel structure in an array substrate according to an embodiment of the present disclosure
  • FIG. 4 is a top plan view of a pixel structure in an array substrate according to an embodiment of the present disclosure
  • FIG. 5 is a top view of a pixel structure in an array substrate according to an embodiment of the present disclosure
  • FIG. 6 is a top plan view of a pixel structure in an array substrate according to an embodiment of the present disclosure.
  • FIG. 7 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present disclosure.
  • the array substrate generally includes a plurality of pixel structures, and each pixel structure includes a pixel region 1, wherein the pixel region 1 is set by a relative a common electrode line 5 and a gate line 6 and an area surrounded by two adjacent parallel data lines 4, the pixel area 2 is provided with a pixel electrode 2, and the pixel electrode 2 is disposed on the array substrate or the pair of boxes An electric field is formed between the common electrodes on the substrate to control the rotation of the liquid crystal molecules, thereby controlling the light transmittance.
  • the pixel electrode 2 forms a fringe electric field between the common electrode line 5 (which is disposed in the same layer as the gate line 6 and disposed separately from the pixel electrode 2), and the edge electric field causes the corresponding pixel electrode 2 in the pixel region 1
  • the electric field of the area A between the common electrode line 5 is confusing, and light leakage is likely to occur.
  • a black matrix is often placed in a region between the pixel electrode and the common electrode to block light to avoid light leakage.
  • the setting of the black matrix causes the aperture ratio of the pixel region to decrease.
  • the array substrate includes: a plurality of pixel structures, each pixel structure includes: at least one pixel region 1, one side of the pixel region 1 is provided with a signal trace, and the pixel region 1 is provided with a pixel electrode 2, A side of the pixel electrode 2 adjacent to the signal trace is provided with a shield electrode disposed in the same layer as the pixel electrode, and the shield electrode is electrically connected to the common electrode line.
  • a shield electrode disposed in the same layer as the pixel electrode 2 is disposed on a side of the pixel electrode 2 adjacent to the signal trace, and the shield electrode is connected to the common electrode line, so that the shield electrode can be connected to the pixel electrode 2
  • the plane electric field can effectively shield the fringe electric field formed between the pixel electrode 2 and the signal trace 5 located outside the pixel region 1 to prevent the fringe electric field from affecting the liquid crystal molecules, thereby improving the corresponding pixel in the pixel region 1.
  • the chaotic electric field at the edge portion of the region between the electrode 2 and the signal trace is advantageous for reducing light leakage and increasing the aperture ratio.
  • the shield electrode of the pixel electrode 2 near the side of the common electrode line 5 is the first shield sub-electrode 7 , first The shield sub-electrode 7 is disposed in the same layer as the pixel electrode 2 and is connected to the common electrode line 5 through the via hole 8.
  • the first shield sub-electrode 7 is disposed in the same layer as the pixel electrode 2 and connected to the common electrode line 5 through the via hole.
  • FIG. 3 is a top plan view of a pixel structure in an array substrate according to an embodiment of the present disclosure.
  • the signal trace in the embodiment is the gate line 6
  • the shield electrode on the side of the pixel electrode 2 adjacent to the gate line 6 is the second shield sub-electrode 9 , and the second shield sub-electrode 9 and the pixel electrode 2 .
  • the same layer is disposed and electrically connected to the common electrode line 5, and the second shield sub-electrode 9 is located in the pixel region.
  • the second shield sub-electrode 9 is disposed in the same layer as the pixel electrode 2 and electrically connected to the common electrode line 5, the second The shielding sub-electrode 9 can form a planar electric field (parallel to the plane in which the pixel electrode 2 is located) with the pixel electrode 2, and the planar electric field can effectively shield the influence of the fringe electric field formed between the pixel electrode 2 and the gate line 6 on the liquid crystal molecules.
  • the chaotic electric field of the edge portion of the region between the pixel electrode 2 and the gate line 6 in the pixel region 1 is improved, which is advantageous for reducing light leakage and increasing the aperture ratio.
  • a common electrode is further disposed in the pixel region 1, and the common electrode 3 is electrically connected to the common electrode line 5 through the via hole, and the second shield sub-electrode 9 is connected to the common electrode 3. More specifically, when the common electrode 3 is disposed in the same layer as the pixel electrode 2, the second shield sub-electrode 9 is directly connected to the common electrode 3; when the common electrode 3 and the pixel electrode 2 are disposed in different layers, the second shield sub-electrode 9 is The common electrode 3 is connected by a via.
  • the foregoing second shield sub-electrode 9 is connected to the common electrode to realize electrical connection with the common electrode line 5, which is a specific embodiment in the embodiment, and does not limit the technical solution of the present disclosure. .
  • not only the second shield sub-electrode 9 but also the first shield sub-electrode 7 in the embodiment described above with reference to FIG. 2 may be disposed in the pixel region 1.
  • the signal traces in this embodiment include the gate line 6 and the common electrode line 5, and the chaotic electric field of the edge portion of the region between the pixel electrode 2 and the gate line 6 in the pixel region 1 can be effectively improved.
  • the chaotic electric field of the edge portion of the region between the pixel electrode 2 and the common electrode line 5 in the pixel region 1 is improved.
  • the common electrode 3 and the pixel electrode 2 are comb electrodes, and the common electrode 3 includes: a plurality of first comb teeth portions 301 and a first connecting portion 302 connecting the first comb tooth portions 301; 2 includes a plurality of second comb-shaped portions 201 and a second connecting portion 202 connecting the second comb-tooth portions 201, and the first comb-tooth portion 301 and the second comb-tooth portion 201 are alternately disposed.
  • the shape of the first shield sub-electrode 7 is the same as the shape of the first comb-tooth portion 301
  • the shape of the second shield sub-electrode 9 is the same as the shape of the first comb-tooth portion 301.
  • a planar electric field formed between the first shield sub-electrode 7 and the pixel electrode 2 and a planar electric field formed between the second shield sub-electrode 9 and the pixel electrode 2 both of which may be combined with the first comb-tooth portion 301 and
  • the electric fields between the second comb-tooth portions 201 are approximately the same or the same, thereby improving the uniformity of the light transmittance at each position in the pixel region 1.
  • the first shield sub-electrode 7 is taken as an example.
  • the array substrate is an array substrate in an In-Plane Switching (IPS) display panel
  • the common electrode 3 and the pixel electrode 2 are disposed in the same layer.
  • the shape and arrangement direction of the first shield sub-electrode 7 is designed to be the same as the shape and arrangement direction of the first comb-tooth portion 301, and between the first shield sub-electrode 7 and the closest second comb-tooth portion 201
  • the distance is equal to the distance between the adjacent first comb tooth portion 301 and the second comb tooth portion 201, so that the planar electric field between the first shield sub-electrode 7 and the pixel electrode 2 can be made, and the first comb-tooth portion 301 and The plane electric field between the second comb-tooth portions 201 is completely the same, and the uniformity of the light transmittance at each position in the pixel region 1 is optimal.
  • the principle that the shape of the second shield sub-electrode 9 is the same as that of the first comb-tooth portion 301 in the present embodiment to improve the uniformity of the light transmittance at each position in the pixel region 1 is the same as described above. I won't go into details here.
  • the common electrode 3 may be disposed in the same layer as the pixel electrode 2 or in a different layer from the pixel electrode 2, which are all within the protection scope of the present disclosure.
  • the first shield sub-electrode 7 and the common electrode 3 may be connected to the common electrode line 5 through the same via 8 or the first shield sub-electrode 7 may be directly connected to the common electrode 3, the second shield sub-electrode 9 is directly connected to the common electrode 3;
  • the first shield sub-electrode 7 and the common electrode 3 pass through two different vias and the common electrode line respectively
  • the 5 connection or first shield sub-electrode 7 is connected to the common electrode 3 through the via hole
  • the second shield sub-electrode 9 is connected to the common electrode 3 through the via hole (the corresponding drawing is not given in this case).
  • the area covered by the planar electric field formed between the third shield sub-electrode 11 and the pixel electrode 2 in this embodiment is larger, and the pair of pixels The effect of improving the chaotic electric field between the electrode 2 and the gate line 6 is better.
  • the third shield sub-electrode 11 is in a region covered by the gate line 6 (outside the pixel region 1), even if a fringe electric field is generated between the third shield sub-electrode 11 and the gate line 6, the fringe electric field is located in the pixel region 1 In addition, it does not affect the display effect of the pixel area 1.
  • the pixel structure in this embodiment includes two thin film transistors 10, and the thin film transistors 10 are in one-to-one correspondence with the pixel regions 1, and the gates of the two thin film transistors 10 are connected to the same gate line 6.
  • the embodiment of the present disclosure provides an array substrate, the array substrate includes a plurality of pixel structures, and at least one of the first shielding sub-electrode, the second shielding sub-electrode, and the third shielding sub-electrode is disposed in the pixel structure. Effectively improving light leakage at the edge of the pixel region in the pixel structure, and increasing the pixel aperture ratio.
  • a sixth embodiment of the present disclosure provides a display panel, which includes an array substrate, and the array substrate adopts the array substrate in the above embodiments. For detailed description of the array substrate, details are not described herein again.
  • the present disclosure also provides a method for fabricating an array substrate in the above embodiment, wherein the array substrate includes: a plurality of pixel structures, the pixel structure including: at least one pixel region, and pixels are disposed in the pixel region An electrode, one side of the pixel area is provided with a signal trace, as shown in FIG. 7, the manufacturing method includes the step 701:
  • a shield electrode disposed in the same layer as the pixel electrode is disposed on a side of the pixel electrode adjacent to the signal trace, and the shield electrode is electrically connected to the common electrode line.
  • the signal trace is the common electrode line
  • the shield electrode includes a first shield sub-electrode
  • the manufacturing method further includes the step of: the first shield sub-electrode and the common through the via The electrode wires are connected.
  • the signal trace is the gate line
  • the shield electrode includes a second shield sub-electrode
  • the second shield sub-electrode is located in the pixel region
  • the pixel region is further disposed.
  • the manufacturing method further includes the steps of:
  • the second shield sub-electrode is electrically connected to the common electrode.
  • the signal trace is the gate line
  • the shield electrode includes a third shield sub-electrode
  • the third shield sub-electrode is located outside the pixel region
  • the third shield sub-electrode is An orthographic projection of a plane in which the gate line is located is completed in a region where the gate line is located, and a common electrode is further disposed in the pixel region
  • the manufacturing method further includes the steps of:
  • the third shield sub-electrode is electrically connected to the common electrode.
  • the present disclosure provides an array substrate and a display panel, wherein the array substrate includes: a plurality of pixel structures, each pixel structure includes: at least one pixel region, one side of the pixel region is provided with a signal trace, and the pixel region is set There is a pixel electrode, and a side of the pixel electrode close to the signal trace is provided with a shield electrode disposed in the same layer as the pixel electrode, and the shield electrode is electrically connected to the common electrode line.
  • the technical solution of the present disclosure provides a shielding electrode disposed between the pixel electrode and the signal trace, the shielding electrode being disposed in the same layer as the pixel electrode and electrically connected to the common electrode line, which can form a planar electric field with the pixel electrode, the planar electric field
  • the edge electric field formed between the pixel electrode and the signal trace can be effectively shielded to avoid the influence of the fringe electric field on the liquid crystal molecules, thereby improving the chaotic electric field of the edge portion of the region between the corresponding pixel electrode and the signal trace in the pixel region. It is beneficial to reduce light leakage and increase the aperture ratio.

Abstract

一种阵列基板、显示面板以及制造方法，阵列基板包括：若干个像素结构，每个像素结构包括：至少一个像素区域，像素区域的一侧设置有信号走线，像素区域内设置有像素电极，像素电极靠近信号走线的一侧设置有与像素电极同层设置的屏蔽电极，屏蔽电极与公共电极线电连接。能够改善像素区域中对应像素电极与信号走线之间区域的边缘部分的混乱电场，有利于降低漏光和提高开口率。

Description

阵列基板及其制造方法、显示面板
相关公开的交叉引用
本公开要求于2017年11月6日提交的中国专利公开No.201721462164.1的优先权，所公开的内容以引用的方式合并于此。
技术领域
本公开涉及显示技术领域，特别涉及阵列基板及其制造方法、显示面板。
背景技术
显示装置已被大量地用作于手机、笔记本电脑、个人电脑及个人数字助理等消费电子产品的显示屏幕。显示装置一般包括有源矩阵阵列基板，其中各个有源元件调节光束强度以显示出影像。阵列基板包括多条栅线、多条数据线以及电性连接至对应的栅线及数据线的多个像素结构；每个像素结构由薄膜晶体管单独控制光透过率。
发明内容
本公开提供了一种阵列基板，包括：若干个像素结构，所述像素结构包括：至少一个像素区域，所述像素区域的一侧设置有信号走线；
所述像素区域内设置有像素电极，所述像素电极靠近所述信号走线的一侧设置有与所述像素电极同层设置的屏蔽电极，所述屏蔽电极与公共电极线电连接。
在一些实施方式中，所述信号走线包括：栅线和/或公共电极线。
在一些实施方式中，当所述信号走线为所述公共电极线时，所述屏蔽电极包括：第一屏蔽子电极，所述第一屏蔽子电极通过 过孔与所述公共电极线连接。
在一些实施方式中，当所述信号走线为所述栅线时，所述屏蔽电极包括：第二屏蔽子电极，所述第二屏蔽子电极位于所述像素区域内；
所述像素区域内还设置有公共电极，所述公共电极与所述公共电极线电连接；
所述第二屏蔽子电极与所述公共电极电连接。
在一些实施方式中，当所述信号走线为所述栅线时，所述屏蔽电极包括：第三屏蔽子电极，所述第三屏蔽子电极在所述栅线所处平面的正投影完成落入所述栅线所处区域；
所述像素区域内还设置有公共电极，所述公共电极与所述公共电极线电连接；
所述第三屏蔽子电极与所述公共电极电连接。
在一些实施方式中，当所述信号走线包括所述公共电极线和所述栅线时，所述屏蔽电极包括第一屏蔽子电极和第二屏蔽子电极，所述第一屏蔽子电极通过过孔与所述公共电极线连接，所述第二屏蔽子电极位于所述像素区域内；
所述像素区域内还设置有公共电极，所述公共电极与所述公共电极线电连接；
所述第二屏蔽子电极与所述公共电极电连接。
在一些实施方式中，当所述信号走线包括所述公共电极线和所述栅线时，所述屏蔽电极包括第一屏蔽子电极和第三屏蔽子电极，所述第一屏蔽子电极通过过孔与所述公共电极线连接，所述第三屏蔽子电极在所述栅线所处平面的正投影完成落入所述栅线所处区域；
所述像素区域内还设置有公共电极，所述公共电极与所述公共电极线电连接；
所述第三屏蔽子电极与所述公共电极电连接。
在一些实施方式中，所述公共电极与所述像素电极同层设置，所述屏蔽电极与所述公共电极直接连接。
在一些实施方式中，所述公共电极为梳状电极，所述公共电极包括：若干个第一梳齿部，所述屏蔽电极的形状和布置方向与所述第一梳齿部的形状和布置方向相同。
在一些实施方式中，所述像素结构包括：两个所述像素区域，两个所述像素区域之间设置有栅线，两个所述像素区域共用一条所述栅线。
在一些实施方式中，所述像素结构包括：两个所述像素区域，两个所述像素区域沿第一方向设置；
所述像素区域的与所述第一方向平行的一侧设置有数据线，两个所述像素区域共用一条所述数据线。
在一些实施方式中，所述像素电极为梳状电极。
在一些实施方式中，还包括：与所述像素区域一一对应设置的薄膜晶体管。
本公开还提供了一种显示面板，包括：如上述的阵列基板。
本公开还提供了一种上述阵列基板的制造方法，其中所述阵列基板包括：若干个像素结构，所述像素结构包括：至少一个像素区域，在所述像素区域内设置有像素电极，所述像素区域的一侧设置有信号走线，如图7所示，该制造方法包括步骤：
在所述像素电极靠近所述信号走线的一侧设置与所述像素电极同层设置的屏蔽电极，所述屏蔽电极与公共电极线电连接。
在一些实施方式中，所述信号走线为所述公共电极线，所述屏蔽电极包括第一屏蔽子电极，该制造方法还包括步骤：通过过孔将第一屏蔽子电极与所述公共电极线连接。
在一些实施方式中，所述信号走线为所述栅线，所述屏蔽电极包括第二屏蔽子电极，所述第二屏蔽子电极位于所述像素区域内，所述像素区域内还设置有公共电极，该制造方法还包括步骤：
将所述公共电极与所述公共电极线电连接；以及
将所述第二屏蔽子电极与所述公共电极电连接。
在一些实施方式中，所述信号走线为所述栅线，所述屏蔽电极包括第三屏蔽子电极，所述第三屏蔽子电极位于所述像素区域 外，且第三屏蔽子电极在所述栅线所处平面的正投影完成落入所述栅线所处区域，所述像素区域内还设置有公共电极，该制造方法还包括步骤：
将所述公共电极与所述公共电极线电连接；以及
将所述第三屏蔽子电极与所述公共电极电连接。
附图说明
图1为现有技术中阵列基板内一个像素结构的俯视图；
图2为本公开的一个实施例提供的一种阵列基板内的一个像素结构的俯视图；
图3为本公开一个实施例提供的一种阵列基板内的一个像素结构的俯视图；
图4为本公开一个实施例提供的一种阵列基板内的一个像素结构的俯视图；
图5为本公开一个实施例提供的一种阵列基板内对一个像素结构的俯视图；
图6为本公开的一个实施例提供的一种阵列基板内的一个像素结构的俯视图。
图7为本公开的一个实施例提供的一种阵列基板的制造方法的流程图。
具体实施方式
为使本领域的技术人员更好地理解本公开的技术方案，下面结合附图对本公开提供的一种阵列基板和显示面板进行详细描述。
图1为相关技术中的阵列基板内的一个像素结构的俯视图，如图1所示，阵列基板一般包括若干个像素结构，每个像素结构包括一个像素区域1，其中像素区域1是由相对设置的一条公共电极线5和一条栅线6与相邻的两条平行设置的数据线4所围成的区域，像素区域1内设置有像素电极2，像素电极2与设置于 阵列基板或对盒基板上公共电极之间形成电场，以控制液晶分子进行转动，从而控制光透过率。
在实际应用中，像素电极2会与公共电极线5(与栅线6同层设置，与像素电极2异层设置)之间形成边缘电场，该边缘电场会使得像素区域1中对应像素电极2与公共电极线5之间的区域A的电场混乱，容易造成漏光。
为此，相关技术中往往在像素电极与公共电极之间的区域中设置黑矩阵进行遮挡，以避免出现漏光。然而，黑矩阵的设置，会导致该像素区域的开口率下降。
图2为本公开的一个实施例提供的一种阵列基板内的一个像素结构的俯视图。如图2所示，该阵列基板包括：若干个像素结构，每个像素结构包括：至少一个像素区域1，像素区域1的一侧设置有信号走线，像素区域1内设置有像素电极2，像素电极2靠近信号走线的一侧设置有与像素电极同层设置的屏蔽电极，屏蔽电极与公共电极线电连接。
需要说明的是，图2中仅示例性画出了一个像素结构包括一个像素区域1的情况，其不会对本公开的技术方案产生限制。
本实施例中，通过在像素电极2靠近信号走线的一侧设置与像素电极2同层设置的屏蔽电极，该屏蔽电极与公共电极线连接，从而该屏蔽电极可与像素电极2之间可形成平面电场，该平面电场可有效屏蔽像素电极2与位于像素区域1外的信号走线5之间形成的边缘电场，以避免该边缘电场对液晶分子造成影响，从而改善像素区域1中对应像素电极2与该信号走线之间区域的边缘部分的混乱电场，有利于降低漏光和提高开口率。
继续参见图2所示，作为一种具体方案，以该信号走线为公共电极线5为例，像素电极2靠近公共电极线5的一侧的屏蔽电极为第一屏蔽子电极7，第一屏蔽子电极7与像素电极2同层设置且通过过孔8与公共电极线5连接。
在本公开中，通过在像素电极2与公共电极线5之间设置与第一屏蔽子电极7，该第一屏蔽子电极7与像素电极2同层设置 且通过过孔与公共电极线5连接，其可与像素电极2之间形成平面电场(与像素电极2所处平面平行)，该平面电场可有效屏蔽像素电极2与公共电极线5之间形成的边缘电场对液晶分子的影响，从而改善像素区域1中对应像素电极2与公共电极线5之间区域的边缘部分的混乱电场，有利于降低漏光和提高开口率。
需要说明的是，由于第一屏蔽子电极7上的电压与公共电极线5上的电压相同，因此第一屏蔽子电极7与公共电极线5之间不会产生边缘电场。
图3为本公开一个实施例提供的一种阵列基板内的一个像素结构的俯视图。如图3所示，本实施例中的信号走线为栅线6，像素电极2靠近栅线6的一侧的屏蔽电极为第二屏蔽子电极9，第二屏蔽子电极9与像素电极2同层设置且与公共电极线5电连接，第二屏蔽子电极9位于像素区域内。
在本公开中，通过在像素电极2与栅线6之间设置第二屏蔽子电极9，该第二屏蔽子电极9与像素电极2同层设置且与公共电极线5电连接，该第二屏蔽子电极9可与像素电极2之间形成平面电场(与像素电极2所处平面平行)，该平面电场可有效屏蔽像素电极2与栅线6之间形成的边缘电场对液晶分子的影响，从而改善像素区域1中对应像素电极2与栅线6之间区域的边缘部分的混乱电场，有利于降低漏光和提高开口率。
作为一种具体实施方案，像素区域1内还设置有公共电极，公共电极3通过过孔与公共电极线5电连接，第二屏蔽子电极9与公共电极3连接。更具体地，当公共电极3与像素电极2同层设置时，第二屏蔽子电极9与公共电极3直接连接；当公共电极3与像素电极2异层设置时，第二屏蔽子电极9与公共电极3通过过孔连接。
需要说明的是，上述第二屏蔽子电极9与公共电极连接以实现与公共电极线5电连接的情况，为本实施例中的一种具体实施方式，其不会对本公开的技术方案产生限制。在本公开中，还可使得第二屏蔽子电极通过过孔与公共电极线5连接(此种情况未 给出相应附图)。
继续参见图3所示，在本实施例中，该像素区域1内不仅可设置第二屏蔽子电极9，还可以设置上述参照图2所描述的实施例中的第一屏蔽子电极7，即，本实施例中的信号走线包括栅线6和公共电极线5，此时既可有效改善像素区域1中对应像素电极2与栅线6之间区域的边缘部分的混乱电场，同时也能改善像素区域1中对应像素电极2与公共电极线5之间区域的边缘部分的混乱电场。
在一些具体实施方式中，公共电极3和像素电极2均为梳状电极，公共电极3包括：若干个第一梳齿部301和连接第一梳齿部301的第一连接部302；像素电极2包括：若干个第二梳齿部201和连接第二梳齿部201的第二连接部202，第一梳齿部301和第二梳齿部201交替设置。
在一些具体实施方式中，第一屏蔽子电极7的形状与第一梳齿部301的形状相同，第二屏蔽子电极9的形状与第一梳齿部301的形状相同。此时可使得第一屏蔽子电极7与像素电极2之间形成的平面电场，以及第二屏蔽子电极9与像素电极2之间形成的平面电场，两者均与第一梳齿部301和第二梳齿部201之间的电场近似或相同，从而提升像素区域1内各位置光透过率的均一性。
具体地，以第一屏蔽子电极7为例，当该阵列基板为平面转换型(In-Plane Switching，简称IPS)显示面板中的阵列基板时，此时公共电极3与像素电极2同层设置。通过将第一屏蔽子电极7的形状和布置方向设计为与第一梳齿部301的形状和布置方向相同，并使得第一屏蔽子电极7与最接近的第二梳齿部201之间的距离等于相邻的第一梳齿部301与第二梳齿部201之间的距离，从而可使得第一屏蔽子电极7和像素电极2之间的平面电场，与第一梳齿部301和第二梳齿部201之间的平面电场完全相同，此时像素区域1内各位置光透过率的均一性最佳。
当公共电极3与像素电极2异层设置时，例如高级超维场转 换型(Advanced-Super Dimension Switching，简称ADS)、边缘场开关技术型(Fringe Filed Switching，简称FFS)等，通过将第一屏蔽子电极7的形状设计为与第一梳齿部301的形状相同，可在一定程度上使得第一屏蔽子电极7和像素电极2之间的平面电场，与第一梳齿部301和第二梳齿部201之间的电场近似，此时也能在一定程度上改善像素区域1内各位置光透过率的均一性。
对于本实施例中将第二屏蔽子电极9的形状设计的与第一梳齿部301的形状相同，以提升像素区域1内各位置光透过率的均一性的原理，与上述相同，此处不再赘述。
需要说明的是，在本实施例中，公共电极3既可以与像素电极2同层设置，也可与像素电极2异层设置，其均属于本公开的保护范围。
进一步地，当公共电极3与像素电极2同层设置时，第一屏蔽子电极7和公共电极3可通过同一过孔8与公共电极线5连接或者第一屏蔽子电极7直接连接至公共电极3上，第二屏蔽子电极9与公共电极3直接连接；当公共电极3与像素电极2异层设置时，第一屏蔽子电极7和公共电极3通过两个不同过孔分别与公共电极线5连接或第一屏蔽子电极7通过过孔与公共电极3连接，第二屏蔽子电极9通过过孔与公共电极3连接(此种情况未给出相应附图)。
在一些实施方式中，该像素结构中还包括：薄膜晶体管10，薄膜晶体管10的源极与栅线6连接，源极与对应的数据线4连接，漏极与对应的像素电极2连接。
图4为本公开的一个实施例提供的一种阵列基板内的一个像素结构的俯视图。如图4所示，本实施例中的信号走线为栅线6，像素电极2靠近栅线6的一侧的屏蔽电极为第三屏蔽子电极11，第三屏蔽子电极11与像素电极2同层设置，第三屏蔽子电极11在栅线6所处平面上的正投影完成落入栅线6所处区域，第三屏蔽子电极11与公共电极3电连接。
相较于上述参照图3描述的实施例中的第二屏蔽子电极9，本实施例中的第三屏蔽子电极11与像素电极2之间形成的平面电场覆盖的区域更大，其对像素电极2与栅线6之间混乱电场的改善效果更佳。
此外，由于第三屏蔽子电极11处于栅线6所覆盖的区域(像素区域1外)，因此即便第三屏蔽子电极11与栅线6之间产生边缘电场，该边缘电场也位于像素区域1外，其不会对像素区域1的显示效果造成影响。
在一些具体实施方式中，第三屏蔽子电极11的形状与第一梳齿部301的形状和布置方向相同。此时可使得第三屏蔽子电极11和像素电极2之间形成的平面电场，与第一梳齿部301和第二梳齿部201之间的电场近似或相同，从而提升像素区域1内各位置光透过率的均一性，具体原理可参见前述相应内容，此处不再赘述。
继续参见图4所示，在本实施例中，该像素区域1内不仅可设置第三屏蔽子电极11，还可以设置上述实施例一中的第一屏蔽子电极7，即，本实施例中的信号走线包括栅线6和公共电极线5，此时既可有效改善像素区域1中对应像素电极2与栅线6之间区域的边缘部分的混乱电场，同时也能改善像素区域1中对应像素电极2与公共电极线5之间区域的边缘部分的混乱电场。
对于本实施例中第三屏蔽子电极11与公共电极线5实现电连接的具体方式，可参见前述参照图3描述的实施例中的第二屏蔽子电极9与公共电极线5实现电连接的方式，此处不再赘述。对于本实施例中第一屏蔽子电极7与公共电极线5实现电连接的具体方式，可参见上述实施例的相应内容，此处不再赘述。
需要说明的是，上述各实施例中所示的像素电极2、公共电极3为梳状的情况，仅起到示例性作用，其不会对本公开的技术方案产生限制。本公开中的公共电极3和像素电极2还可以为其他形状，例如；条形、线形、螺旋形等，此处不再一一举例。
图5为本公开的一个实施例提供的一种阵列基板内的一个 像素结构的俯视图。如图5所示，与上述参照图3描述的实施例不同的是，本实施例提供的像素结构包括两个像素区域1，栅线6位于两个像素区域1之间，两个像素区域1共用一条栅线6，两个像素区域1与栅线6相对的一侧设置有对应的公共电极线5。
两个像素区域1沿第一方向设置，像素区域1的与第一方向平行的一侧设置有数据线4，两个像素区域1共用一条数据线4。
本实施例中的两个像素区域1均采用上述参照图3描述的实施例中的像素区域1，即每个像素区域1内均设置有一个第一屏蔽子电极7和一个第二屏蔽子电极9。对于本实施例中像素区域1的描述可参见上述参照图2描述实施例中的相应内容此处不再赘述。
需要说明的是，在本实施例中的像素结构包括两个薄膜晶体管10，薄膜晶体管10与像素区域1一一对应，这两个薄膜晶体管10的栅极连接同一栅线6。
图6为本公开的一个实施例提供的阵列基板内的一个像素结构的俯视图。如图6所示，与上述参照图5描述的实施例中的像素结构包括第二屏蔽子电极9不同的是，本实施例中的像素结构包括第三屏蔽子电极11，第三屏蔽子电极11像素电极2同层设置，第三屏蔽子电极11电极在栅线6所处平面上的正投影完成落入栅线6所处区域，第三屏蔽子电极11与公共电极线电连接。
对于该第三屏蔽子电极11的具体描述，可参见上述参照图3描述的实施例中的相应内容，此处不再赘述。
需要说明的是，在本实施例中为实现第三屏蔽子电极11能够与公共电极3连接，可使得两个像素区域1内的公共电极3(第二连接部302)在栅线6所处区域直接连接，第三屏蔽子电极11与公共电极3在栅线6所处区域的部分直接连接。换言之，在本实施例中，两个像素区域共用第三屏蔽子电极11。
此外，上述实施例中仅示例性的给出了一个像素结构包括1 个像素区域或2个像素区域的情况，推而广之，本公开中的像素结构还可包括多个像素区域，其也应属于本公开的保护范围，对于一个像素结构包括多个像素区域的情况，此处不再详细描述。
本公开实施例提供了一种阵列基板，该阵列基板包括若干个像素结构，通过在像素结构中设置第一屏蔽子电极、第二屏蔽子电极、第三屏蔽子电极中的至少一者，可有效改善像素结构中像素区域的边缘处漏光，提高像素开口率。
本公开实施例六提供了一种显示面板，该显示面板包括阵列基板，该阵列基板采用上述各实施例中的阵列基板，对于该阵列基板的具体描述，此处不再赘述。
本公开还提供了一种上述实施例中的阵列基板的制造方法，其中所述阵列基板包括：若干个像素结构，所述像素结构包括：至少一个像素区域，在所述像素区域内设置有像素电极，所述像素区域的一侧设置有信号走线，如图7所示，该制造方法包括步骤701：
在所述像素电极靠近所述信号走线的一侧设置与所述像素电极同层设置的屏蔽电极，所述屏蔽电极与公共电极线电连接。
在一些具体实施方式中，所述信号走线为所述公共电极线，所述屏蔽电极包括第一屏蔽子电极，该制造方法还包括步骤：通过过孔将第一屏蔽子电极与所述公共电极线连接。
在一些具体实施方式中，所述信号走线为所述栅线，所述屏蔽电极包括第二屏蔽子电极，所述第二屏蔽子电极位于所述像素区域内，所述像素区域内还设置有公共电极，该制造方法还包括步骤：
将所述公共电极与所述公共电极线电连接；以及
将所述第二屏蔽子电极与所述公共电极电连接。
在一些具体实施方式中，所述信号走线为所述栅线，所述屏蔽电极包括第三屏蔽子电极，所述第三屏蔽子电极位于所述像素区域外，且第三屏蔽子电极在所述栅线所处平面的正投影完成落入所述栅线所处区域，所述像素区域内还设置有公共电极，该制 造方法还包括步骤：
将所述公共电极与所述公共电极线电连接；以及
将所述第三屏蔽子电极与所述公共电极电连接。
本公开具有以下有益效果：
本公开提供了一种阵列基板和显示面板，其中，该阵列基板包括：若干个像素结构，每个像素结构包括：至少一个像素区域，像素区域的一侧设置有信号走线，像素区域内设置有像素电极，像素电极靠近信号走线的一侧设置有与像素电极同层设置的屏蔽电极，屏蔽电极与公共电极线电连接。本公开的技术方案通过在像素电极与信号走线之间设置屏蔽电极，该屏蔽电极与像素电极同层设置且与公共电极线电连接，其可与像素电极之间形成平面电场，该平面电场可有效屏蔽像素电极与信号走线之间形成的边缘电场，以避免该边缘电场对液晶分子造成影响，从而改善像素区域中对应像素电极与该信号走线之间区域的边缘部分的混乱电场，有利于降低漏光和提高开口率。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (20)

  1. 一种阵列基板，其特征在于，包括：若干个像素结构，所述像素结构包括：至少一个像素区域，所述像素区域的一侧设置有信号走线；
    所述像素区域内设置有像素电极，所述像素电极靠近所述信号走线的一侧设置有与所述像素电极同层设置的屏蔽电极，所述屏蔽电极与公共电极线电连接。
  2. 根据权利要求1所述的阵列基板，其特征在于，所述信号走线包括：栅线和/或公共电极线。
  3. 根据权利要求2所述的阵列基板，其特征在于，当所述信号走线为所述公共电极线时，所述屏蔽电极包括：第一屏蔽子电极，所述第一屏蔽子电极通过过孔与所述公共电极线连接。
  4. 根据权利要求2所述的阵列基板，其特征在于，当所述信号走线为所述栅线时，所述屏蔽电极包括：第二屏蔽子电极，所述第二屏蔽子电极位于所述像素区域内；
    所述像素区域内还设置有公共电极，所述公共电极与所述公共电极线电连接；
    所述第二屏蔽子电极与所述公共电极电连接。
  5. 根据权利要求2所述的阵列基板，其特征在于，当所述信号走线为所述栅线时，所述屏蔽电极包括：第三屏蔽子电极，所述第三屏蔽子电极在所述栅线所处平面的正投影完成落入所述栅线所处区域；
    所述像素区域内还设置有公共电极，所述公共电极与所述公共电极线电连接；
    所述第三屏蔽子电极与所述公共电极电连接。
  6. 根据权利要求2所述的阵列基板，其特征在于，当所述信号走线包括所述公共电极线和所述栅线时，所述屏蔽电极包括第一屏蔽子电极和第二屏蔽子电极，所述第一屏蔽子电极通过过孔与所述公共电极线连接，所述第二屏蔽子电极位于所述像素区域内；
    所述像素区域内还设置有公共电极，所述公共电极与所述公共电极线电连接；
    所述第二屏蔽子电极与所述公共电极电连接。
  7. 根据权利要求2所述的阵列基板，其特征在于，当所述信号走线包括所述公共电极线和所述栅线时，所述屏蔽电极包括第一屏蔽子电极和第三屏蔽子电极，所述第一屏蔽子电极通过过孔与所述公共电极线连接，所述第三屏蔽子电极在所述栅线所处平面的正投影完成落入所述栅线所处区域；
    所述像素区域内还设置有公共电极，所述公共电极与所述公共电极线电连接；
    所述第三屏蔽子电极与所述公共电极电连接。
  8. 根据权利要求4至7中任一项所述的阵列基板，其特征在于，所述公共电极与所述像素电极同层设置，所述屏蔽电极与所述公共电极直接连接。
  9. 根据权利要求4至7中任一项所述的阵列基板，其特征在于，
    所述公共电极为梳状电极，所述公共电极包括：若干个第一梳齿部，所述屏蔽电极的形状和布置方向与所述第一梳齿部的形状和布置方向相同。
  10. 根据权利要求1所述的阵列基板，其特征在于，所述像素结构包括：两个所述像素区域，两个所述像素区域之间设置有 栅线，两个所述像素区域共用一条所述栅线。
  11. 根据权利要求1所述的阵列基板，其特征在于，所述像素结构包括：两个所述像素区域，两个所述像素区域沿第一方向设置；
    所述像素区域的与所述第一方向平行的一侧设置有数据线，两个所述像素区域共用一条所述数据线。
  12. 根据权利要求1所述的阵列基板，其特征在于，所述像素电极为梳状电极。
  13. 根据权利要求1所述的阵列基板，其特征在于，还包括：与所述像素区域一一对应设置的薄膜晶体管。
  14. 一种显示面板，其特征在于，包括：如上述权利要求1-13中任一所述的显示面板。
  15. 一种权利要求1所述的阵列基板的制造方法，其特征在于，包括：
    在所述像素电极靠近所述信号走线的一侧设置与所述像素电极同层设置的屏蔽电极，所述屏蔽电极与公共电极线电连接。
  16. 根据权利要求15所述的制造方法，其特征在于，所述信号走线为所述公共电极线，所述屏蔽电极包括第一屏蔽子电极，该制造方法还包括步骤：
    通过过孔将第一屏蔽子电极与所述公共电极线连接。
  17. 根据权利要求15所述的制造方法，其特征在于，所述信号走线为所述栅线，所述屏蔽电极包括第二屏蔽子电极，所述第二屏蔽子电极位于所述像素区域内，所述像素区域内还设置有 公共电极，该制造方法还包括步骤：
    将所述公共电极与所述公共电极线电连接；以及
    将所述第二屏蔽子电极与所述公共电极电连接。
  18. 根据权利要求15所述的制造方法，其特征在于，所述信号走线为所述栅线，所述屏蔽电极包括第三屏蔽子电极，所述第三屏蔽子电极位于所述像素区域外，且第三屏蔽子电极在所述栅线所处平面的正投影完成落入所述栅线所处区域，所述像素区域内还设置有公共电极，该制造方法还包括步骤：
    将所述公共电极与所述公共电极线电连接；以及
    将所述第三屏蔽子电极与所述公共电极电连接。
  19. 根据权利要求15所述的制造方法，其特征在于，所述信号走线包括所述公共电极线和所述栅线，所述屏蔽电极包括第一屏蔽子电极和第二屏蔽子电极，所述第二屏蔽子电极位于所述像素区域内，所述像素区域内还设置有公共电极，所述制造方法进一步包括步骤：
    通过过孔将所述第一屏蔽子电极与所述公共电极线连接；
    将所述公共电极与所述公共电极线电连接；以及
    将所述第二屏蔽子电极与所述公共电极电连接。
  20. 根据权利要求15所述的制造方法，其特征在于，所述信号走线包括所述公共电极线和所述栅线，所述屏蔽电极包括第一屏蔽子电极和第三屏蔽子电极，所述第三屏蔽子电极在所述栅线所处平面的正投影完成落入所述栅线所处区域，所述像素区域内还设置有公共电极，所述制造方法进一步包括步骤：
    通过过孔将所述第一屏蔽子电极与所述公共电极线连接；
    将所述公共电极与所述公共电极线电连接；以及
    将所述第三屏蔽子电极与所述公共电极电连接。
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US11204531B2 (en) 2021-12-21
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