WO2019056833A1 - 移位寄存器单元及其驱动方法、扫描驱动电路、阵列基板和显示装置 - Google Patents

移位寄存器单元及其驱动方法、扫描驱动电路、阵列基板和显示装置 Download PDF

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Publication number
WO2019056833A1
WO2019056833A1 PCT/CN2018/095121 CN2018095121W WO2019056833A1 WO 2019056833 A1 WO2019056833 A1 WO 2019056833A1 CN 2018095121 W CN2018095121 W CN 2018095121W WO 2019056833 A1 WO2019056833 A1 WO 2019056833A1
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WIPO (PCT)
Prior art keywords
node
reset
transistor
level
shift register
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PCT/CN2018/095121
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English (en)
French (fr)
Inventor
郭宏涛
柴国卫
唐福
许邦荣
Original Assignee
京东方科技集团股份有限公司
合肥京东方显示技术有限公司
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Priority to US16/335,408 priority Critical patent/US11361702B2/en
Publication of WO2019056833A1 publication Critical patent/WO2019056833A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • Embodiments of the present disclosure relate to a shift register unit and a driving method thereof, a scan driving circuit, an array substrate, and a display device.
  • the Gate Driver On Array (GOA) technology can not only save the circuit board carrying the gate driver, but also realize the symmetrical design on both sides of the display panel, and can also save the edge of the display panel.
  • the chip bonding area and the wiring area such as the fan-out area facilitate the implementation of the narrow bezel design.
  • GOA technology can eliminate the chip bonding process in the row direction, it will also greatly help the overall productivity and yield improvement.
  • At least one embodiment of the present disclosure provides a shift register unit including an input terminal, an output terminal, and a reset terminal, and further comprising: input circuits respectively connecting the input terminal and the first node, at the input terminal Disposing the first node as an active level when the active level is active; respectively connecting the output terminal and the output circuit of the first node for using the first clock signal when the first node is active
  • the output is disposed as an active level; a reset circuit respectively connecting the first node and the second node, configured to dispose the first node as an invalid level when the second node is at an active level;
  • a first reset control circuit respectively connected to the second node, the input end, and the reset end, configured to dispose the second node as an active level when the reset end is at an active level, and
  • the input is disposed as an inactive level; and a second reset control circuit is coupled to the second node and the input, respectively, for disposing the second node when the input is at an active level Inactive level.
  • the first reset control circuit includes: a first conductive sub-circuit connecting the reset terminal and the third node, respectively, for the reset end Turning the reset terminal to the third node when the active level is at an active level; respectively connecting the third node, the reset terminal, and the second conductive sub-circuit of the second node, The reset terminal is turned on to the second node when the third node is the active level at the reset end; and the reset sub-circuits respectively connecting the reset terminal and the input terminal are used for The input terminal is disposed as an inactive level when the reset terminal is at an active level; accordingly, the second reset control circuit is further connected to the third node, and the second reset control circuit is further configured to The third node is disposed as an inactive level when the input is at an active level.
  • the first conductive sub-circuit includes a first transistor
  • the second conductive sub-circuit includes a second transistor
  • the reset sub-circuit includes a third a transistor
  • a gate of the first transistor is connected to the reset terminal, one of a source and a drain is connected to the reset terminal, and the other is connected to the third node
  • a gate of the second transistor is connected to the a third node, one of a source and a drain is connected to the reset terminal, and the other is connected to the second node
  • a gate of the third transistor is connected to the reset terminal, and one of a source and a drain is connected
  • the input terminal is connected to the inactive level voltage line.
  • the first reset control circuit further includes a first capacitor, and the first end of the first capacitor is connected to the second node, the first capacitor The second end is connected to the third node.
  • the third node is connected to the second node.
  • the second reset control circuit includes a fourth transistor and a fifth transistor; a gate of the fourth transistor is connected to the input terminal, the source and the drain One of the poles is connected to the second node, the other is connected to the inactive level voltage line; the gate of the fifth transistor is connected to the input terminal, and one of the source and the drain is connected to the third node, and One is connected to an invalid level voltage line.
  • the reset circuit includes a sixth transistor, a gate of the sixth transistor is connected to the second node, and one of a source and a drain is connected.
  • the first node is described, and the other is connected to the inactive level voltage line.
  • the reset circuit further includes a seventh transistor, a gate of the seventh transistor is connected to the second node, and one of a source and a drain is connected. The output is connected to an inactive level voltage line.
  • the reset circuit further includes an eighth transistor, a gate of the eighth transistor is connected to the reset terminal, and one of a source and a drain is connected.
  • the first node is connected, and the other is connected to the first clock signal or the inactive level voltage line.
  • the reset circuit further includes a ninth transistor, and a gate of the ninth transistor is connected to the reset terminal or a second clock signal, a source and a drain.
  • One of the connections is connected to the output, and the other is connected to an inactive level voltage line; the phases of the first clock signal and the second clock signal are opposite to each other.
  • the input circuit includes a tenth transistor, a gate of the tenth transistor is connected to the input end, and one of a source and a drain is connected to the At the input end, the other is connected to the first node.
  • the output circuit includes an eleventh transistor and a second capacitor; a gate of the eleventh transistor is connected to the first node, a source and a drain One of the poles is connected to the first clock signal, and the other is connected to the output terminal; the first end of the second capacitor is connected to the first node, and the second end of the second capacitor is connected to the output end .
  • At least one embodiment of the present disclosure also provides a scan driving circuit comprising the shift register unit of any of the above embodiments.
  • At least one embodiment of the present disclosure further provides an array substrate comprising the shift register unit of any of the above embodiments or the scan driving circuit of any of the above embodiments.
  • At least one embodiment of the present disclosure further provides a display device, comprising the shift register unit according to any one of the above embodiments, the scan driving circuit according to any one of the above embodiments, or any of the above embodiments.
  • a display device comprising the shift register unit according to any one of the above embodiments, the scan driving circuit according to any one of the above embodiments, or any of the above embodiments.
  • Array substrate comprising the shift register unit according to any one of the above embodiments, the scan driving circuit according to any one of the above embodiments, or any of the above embodiments.
  • At least one embodiment of the present disclosure also provides a driving method of a shift register unit having an input terminal, a reset terminal, and an output terminal, the driving method including: when the input terminal is at an active level Handling the first node to an active level, disposing the second node to an inactive level; and when the first node is at an active level, disposing the output terminal to an active level using the first clock signal; When the reset end is at an active level, the second node is disposed as an active level, and the input is disposed as an inactive level; the first node is when the second node is an active level Disposition is an invalid level.
  • FIG. 1 is a structural block diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 2 is a partial circuit structural diagram of a shift register unit according to still another embodiment of the present disclosure.
  • FIG. 3 is a circuit structural diagram of a shift register unit according to still another embodiment of the present disclosure.
  • FIG. 4 is a circuit timing diagram of the shift register unit shown in FIG. 3;
  • Figure 5 is a partial circuit configuration diagram of a shift register unit
  • FIG. 6 is a schematic block diagram of a scan driving circuit according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic block diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic block diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic flow chart of a driving method of a shift register unit according to an embodiment of the present disclosure.
  • the shift register unit can output a gate driving signal by a combination of a signal connected to the input terminal and a signal connected to the reset terminal.
  • the signal connected to the input terminal may interfere with the operation triggered by the signal connected to the reset terminal, and may even affect the normal operation of the shift register unit when the transistor has zero voltage conduction.
  • At least one embodiment of the present disclosure provides a shift register unit and a driving method thereof, a scan driving circuit, an array substrate, and a display device, which can suppress interference caused by a signal connected to an input end of the shift register unit to a signal connected to the reset terminal.
  • the shift register unit based on the setting of the reset circuit, the first reset control circuit, and the second reset control circuit, the shift register unit can be an active level period at the reset end based on the implementation of the reset control The signal at the input end is prevented from affecting the second node, so that the interference caused by the signal connected to the input terminal to the signal connected to the reset terminal can be suppressed, which helps to reduce the output noise of the shift register unit and improve the reliability of the product.
  • FIG. 1 is a structural block diagram of a shift register unit according to an embodiment of the present disclosure.
  • the shift register unit includes an input terminal IN, a reset terminal RES, and an output terminal OUT, and further includes:
  • a reset circuit 13 connecting the first node PU and the second node PD, respectively, for disposing the first node PU to an inactive level when the second node PD is at an active level;
  • a first reset control circuit 14 respectively connected to the second node PD, the input terminal IN and the reset terminal RES for disposing the second node PD to an active level when the reset terminal RES is at an active level, and disposing the input terminal IN Invalid level;
  • a second reset control circuit 15 is coupled to the second node PD and the input terminal IN, respectively, for disposing the second node PD to an inactive level when the input terminal IN is at an active level.
  • the effective level and the inactive level herein refer to two different pre-configured voltage ranges (both based on the common terminal voltage) for a specific circuit node, respectively.
  • the active levels of all circuit nodes are high in the digital circuit in which they are located.
  • the active levels of all circuit nodes are low in the digital circuitry in which they are located.
  • the active level at the input terminal IN and the reset terminal RES is a low level in the digital circuit
  • the effective level at the output terminal OUT, the first node PU, and the second node PD is the number High level in the circuit.
  • the setting of the effective level and the inactive level may not be limited to the above example.
  • the process of setting the active level at the second node PD may be completed when the first reset control circuit 14 is at the active level at the reset terminal RES, while the first reset control circuit 14 also inputs the input at the same time.
  • the IN is handled as an inactive level, ie the noise voltage at the input IN can be released to the circuit node providing the inactive level. Therefore, the noise voltage at the input terminal IN will not affect the level at the second node PD, so that the first node PU can be smoothly set to an inactive level, and the output terminal OUT can be prevented from returning to the invalid power.
  • Flat abnormal situation may be completed when the first reset control circuit 14 is at the active level at the reset terminal RES, while the first reset control circuit 14 also inputs the input at the same time.
  • the IN is handled as an inactive level, ie the noise voltage at the input IN can be released to the circuit node providing the inactive level. Therefore, the noise voltage at the input terminal IN will not affect the level at the second node PD, so that the first no
  • the shift register unit provided by the embodiment of the present disclosure can be implemented at the reset terminal RES on the basis of implementing the reset control.
  • the signal at the input terminal IN is prevented from affecting the second node PD, so that the interference caused by the signal connected to the input terminal IN to the signal connected to the reset terminal RES can be suppressed, which helps to reduce the shift register unit.
  • the output noise increases the reliability of the product.
  • the first reset control circuit 14 in this embodiment includes a first conduction sub-circuit 14a, a second conduction sub-circuit 14b, and a reset sub-circuit 14c.
  • the first conduction sub-circuit 14a is connected to the reset terminal RES and the third node PC, respectively, for turning on the reset terminal RES to the third node PC when the reset terminal RES is at an active level.
  • the first conduction sub-circuit 14a is exemplified by a structure including a first transistor M1 whose gate is connected to the reset terminal RES, one of the source and the drain is connected to the reset terminal RES, and the other One is connected to the third node PC so that the source-drain current can be used to form a conduction relationship between the reset terminal RES and the third node PC when the reset terminal RES is at a high level as an active level.
  • connection relationship between the source and the drain may be respectively set to match the direction of the current flowing through the transistor; and the transistor has a structure in which the source and the drain are symmetric.
  • the source and drain can be considered as two electrodes that are not particularly distinguished.
  • the second conductive sub-circuit 14b is connected to the third node PC, the reset terminal RES and the second node PD, respectively, for turning on the reset terminal RES to the second node when the third node PC is at the active level at the reset terminal RES PD.
  • the second conductive sub-circuit 14b is exemplified by a structure including a second transistor M2 whose gate is connected to the third node PC, and one of the source and the drain is connected to the reset terminal RES, The other is connected to the second node PD so that the source-drain current can be used to form a conduction relationship between the reset terminal RES and the second node PD when the third node PC is at a high level as an active level.
  • the reset sub-circuit 14c is connected to the reset terminal RES and the input terminal IN, respectively, for handling the input terminal IN to an inactive level when the reset terminal RES is at an active level.
  • the reset sub-circuit 14c is exemplified by a structure including a third transistor M3 whose gate is connected to the reset terminal RES, one of the source and the drain is connected to the input terminal IN, and the other connection is invalid.
  • Level voltage line VGL low level voltage line
  • the second reset control circuit 15 includes a first portion 15a and a second portion 15b, and is further connected to the third node PC on the basis of respectively connecting the second node PD and the input terminal IN.
  • the second reset control circuit 15 is used not only to dispose the second node PD to an inactive level when the input terminal IN is at an active level, but also to use the third node when the input terminal IN is at an active level.
  • the PC is handled as an inactive level at the reset terminal RES.
  • the first portion 15a of the second reset control circuit 15 is exemplified by a structure including a fourth transistor M4 whose gate is connected to the input terminal IN, and one of the source and the drain is connected to the second.
  • the node PD the other connected to the inactive level voltage line VGL, is capable of utilizing the source leakage current flowing from the second node PD to the inactive level voltage line VGL at the high level as the active level at the input terminal IN.
  • the node PD is pulled down to a low level as an inactive level.
  • the second portion 15b of the second reset control circuit 15 is exemplified by a structure including a fifth transistor M5 whose gate is connected to the input terminal IN, and one of the source and the drain is connected.
  • the three-node PC is capable of utilizing the source-leakage current flowing from the third node PC to the inactive level voltage line VGL when the input terminal IN is at a high level as an active level
  • the three-node PC pulls down to a low level that is an inactive level.
  • the second node PD is connected to the third node PC, that is, the level of the second node PD and the level of the third node PC are always consistent. Based on this, the second node PD and the third node PC are subjected to the first portion 15a and the second portion of the second reset control circuit 15 during the period in which the input terminal IN is the active level and the reset terminal RES is in the inactive level. 15b is set to an inactive level, and the diode-connected first transistor M1 of FIG. 2 causes the noise voltage at the reset terminal RES to be released to an inactive level by the source-drain currents of the first transistor M1 and the fifth transistor M5. Voltage line VGL.
  • the second node PD and the first conduction sub-circuit 14a and the second conduction sub-circuit 14b are under the action of the first conduction sub-circuit 14a and the second conduction sub-circuit 14b.
  • the third node PC can be set to an active level while the reset sub-circuit 14c can release the noise voltage at the output terminal IN onto the inactive level voltage line VGL.
  • the second node PD is disconnected from the third node PC, that is, the level of the second node PD and the level of the third node PC remain independent of each other. Based on this, in the period in which the input terminal IN is the active level and the reset terminal RES is in the inactive level, the second node PD is set to the inactive level by the first portion 15a of the second reset control circuit 15, the third node The PC is set to the inactive level by the second portion 15b of the second reset control circuit 15, and the first transistor M1 having the diode connection mode in FIG. 2 causes the noise voltage at the reset terminal RES and the noise voltage at the third node PC.
  • the source and drain currents of the first transistor M1 and the fifth transistor M5 can be discharged to the inactive level voltage line VGL.
  • the third node PC is set to the active level under the action of the first conduction sub-circuit 14a, in the second
  • the second node PD is set to an active level by the conduction sub-circuit 14b, and the reset sub-circuit 14c is capable of releasing the noise voltage at the output terminal IN to the inactive level voltage line VGL.
  • the process of being set to the inactive level at the second node PD may be completed when the second reset control circuit 15 is at the active level at the input terminal IN, and the second reset control circuit 15 will also be the third time in the same time.
  • the node PC is disposed at an inactive level, i.e., the noise voltage at the third node PC can be released to the circuit node providing the inactive level.
  • the noise voltage at the reset terminal RES will not affect the level at the third node PC and at the second node PD, so that the reset circuit 13 can temporarily stop disposing of the first node PU during the operating time of the input circuit 11. It is an inactive level to avoid an abnormal situation in which the active level is not normally output at the output terminal OUT when the first node PU is set to an inactive level.
  • the shift register unit of the present embodiment can implement reset control based on the settings of the first conductive sub-circuit 14a, the second conductive sub-circuit 14b, the reset sub-circuit 14c, and the second reset control circuit 15 described above.
  • the signal at the reset terminal RES is prevented from affecting the second node PD, so that the interference caused by the signal connected to the reset terminal RES on the signal connected to the input terminal IN can be suppressed.
  • FIG. 3 is a circuit structural diagram of a shift register unit according to still another embodiment of the present disclosure.
  • the shift register unit of the present embodiment adds a first capacitor C1 to the first reset control circuit 14 as compared with the structure shown in FIG. 2, and also shows the input circuit 11 and the output circuit.
  • the input circuit 11 includes a tenth transistor M10 having a gate connected to the input terminal IN, one of the source and the drain connected to the input terminal IN, and the other connected to the first node PU, thereby being able to
  • the first node PU is pulled up to a high level as an active level by using a source leakage current flowing from the input terminal IN to the first node PU, and the above-mentioned input is realized.
  • the output circuit 12 includes an eleventh transistor M11 and a second capacitor C2.
  • the gate of the eleventh transistor M11 is connected to the first node PU, and one of the source and the drain is connected to the first clock signal line (or One clock signal terminal CK1 and the other terminal are connected to the output terminal OUT; the first terminal of the second capacitor C2 is connected to the first node PU, and the second terminal of the second capacitor C2 is connected to the output terminal OUT.
  • a positive phase clock signal and an inverted clock signal may be respectively loaded on the first clock signal line CK1 and the second clock signal line (or the second clock signal terminal) CK2 described hereinafter.
  • One of the signals ie, the signals on the first clock signal line CK1 and the second clock signal line CK2 are opposite to each other.
  • the eleventh transistor M11 is turned on under the high level of the gate, so that the output terminal OUT can be pulled up by using the high level on the first clock signal line CK1.
  • the above-described function of disposing the output terminal OUT to the active level by the first clock signal when the first node PU is at the active level is realized.
  • the circuit configuration of the output unit 12 may not be limited to the above form.
  • the reset circuit 13 includes a sixth transistor M6 whose gate is connected to the second node PD, one of the source and the drain is connected to the first node PU, and the other is connected to the inactive level voltage line VGL. , thereby being able to pull down the first node PU to a low level as an inactive level with a source leakage current flowing from the first node PU to the inactive level voltage line VGL when the second node PD is at a high level as an active level Level, a function of disposing the first node PU to an inactive level when the second node PD is at an active level.
  • the reset circuit 13 further includes a seventh transistor M7 whose gate is connected to the second node PD, one of the source and the drain is connected to the output terminal OUT, and the other is connected to the inactive level voltage line VGL. Therefore, when the second node PD is at a high level as an active level, the source-drain current flowing from the output terminal OUT to the low-level reactive level voltage line VGL can be pulled down to the output terminal OUT as an invalid power. A flat low level helps to reset the output OUT.
  • the reset circuit 13 further includes an eighth transistor M8 whose gate is connected to the reset terminal RES, one of the source and the drain is connected to the first node PU, and the other is connected to the first clock signal line CK1. Therefore, when the reset terminal RES is at the high level as the active level, the source and drain currents flowing from the first node PU to the first clock signal line CK1 that is at the low level are pulled down to the first node PU as invalid. The low level of the level helps complete the reset at the first node PU.
  • the reset circuit 13 further includes a ninth transistor M9 having a gate connected to the second clock signal line CK2, one of the source and the drain connected to the output terminal OUT, and the other connected to the inactive level voltage line. VGL, so that the source-drain current flowing from the output terminal OUT to the inactive level voltage line VGL can be pulled down to the output terminal OUT as an inactive level when the high level is the active level at the second clock signal line CK2.
  • Low level helps to complete the reset at the output terminal OUT, and periodically releases the noise voltage at the output terminal OUT with the clock signal of the second clock signal line CK2, maintaining the stability of the signal at the output terminal OUT.
  • FIG. 4 is a circuit timing diagram of the shift register unit shown in FIG.
  • the working phase of the above shift register unit mainly includes an input phase I, an output phase II, and a reset phase III.
  • FIG. 4 and the following description CK1, CK2, IN, OUT, RES, etc. are used to indicate the corresponding signal terminals, and are also used to indicate corresponding signals. The following embodiments are the same. No longer.
  • the input terminal IN is turned to a high level
  • the fourth transistor M4, the fifth transistor M5, and the tenth transistor M10 are turned on, and the first node PU is pulled up to a high level, so that the eleventh transistor M11 is turned on.
  • the first clock signal CK1 is at a low level
  • the second clock signal CK2 is at a high level
  • the output terminal OUT is kept at a low level under the pull-down of the ninth transistor M9 in an on state.
  • the first end of the second capacitor C2 is at a high level at the first node PU, and at the second end is at a low level at the output terminal OUT.
  • the first end of the first capacitor C1 is at a low level at the second node PD, and at the second end is at a low level at the third node PC.
  • the input terminal IN is turned to a low level, and the first clock signal CK1 is turned to a high level.
  • the first node PU will jump to a higher level at a higher potential as the first clock signal CK1 changes from a low level to a high level. This causes the eleventh transistor M11 to be fully turned on, and the potential pull-up at the output terminal OUT is quickly completed, that is, the output of the gate drive signal is started at the output terminal OUT.
  • the reset terminal RES is turned to a high level
  • the first clock signal CK1 is turned to a low level
  • the second clock signal CK2 is turned to a high level
  • the first transistor M1, the third transistor M3, and the seventh transistor are turned M7, the eighth transistor M8, and the ninth transistor M9 are turned on.
  • the potential at the third node PC gradually rises as the source-drain current of the first transistor M1 is injected, and before the potential at the third node PC rises until the second transistor M2 is turned on, the second transistor M2 is not yet turned on, and thus the second
  • the potential at the node PD rises as the potential of the third node PC rises under the charge holding of the first capacitor C1.
  • the potential at the second node PD is rapidly raised to a high level by the combination of the rise of the first capacitor C1 and the source and drain current of the second transistor M2, thereby causing the sixth transistor M6 and the Seven transistors M7 are turned on.
  • the third transistor M3 will keep the input terminal IN low, avoiding the noise at the input terminal IN from affecting the above process.
  • the first node PU is pulled down to a low level; under the joint action of the seventh transistor M7 and the ninth transistor M9, the output terminal OUT is pulled down to a low level Level, complete reset of the shift register unit.
  • FIG. 5 is a partial circuit configuration diagram of a shift register unit.
  • the shift register unit sets the second reset control circuit 15 to include only the circuit structure of the fourth transistor M4 described above, and sets the first reset control circuit 14 to include only the circuit shown in FIG.
  • the gate and the drain are connected to the reset terminal RES, and the source is connected to the first transistor M1 of the second node PD.
  • the noise voltage at the reset terminal RES may have a pull-up effect on the potential at the second node PD through the first transistor M1, and it is easy to accidentally turn on the sixth transistor M6 to make the first node
  • the PU cannot be pulled high to cause a high level at the output terminal OUT in the output phase II, resulting in an output abnormality.
  • the noise voltage at the input terminal IN may have a pull-down effect on the potential at the second node PD through the fourth transistor M4, so that the second node PD cannot easily reach a high level, resulting in the first
  • the node PU pull-down is incomplete and causes a false output at the output after reset phase III.
  • the bit register unit can reduce the mutual interference between the input terminal IN and the reset terminal RES on the basis of implementing the reset control, thereby helping to further reduce the output noise of the shift register unit and improving the reliability of the product.
  • the first node PU, the second node PD, and the third node PC do not represent actual components, but represent convergence points of related electrical connections in the circuit diagram.
  • the transistors used in the embodiments of the present disclosure may each be a thin film transistor, a field effect transistor, or other switching device having the same characteristics.
  • a thin film transistor is taken as an example for description.
  • the source and drain of the transistor used here may be structurally symmetrical, so that the source and the drain may be structurally indistinguishable.
  • the embodiment of the present disclosure in order to distinguish the two poles of the transistor except the gate, one of the first poles and the other pole are directly described.
  • the transistors shown in FIG. 3 are all N-type transistors, that is, they can be formed by the same fabrication process to reduce the manufacturing cost.
  • Indium Gallium Zinc Oxide (IGZO) can be used as an active layer of a thin film transistor, compared to low temperature polysilicon (LTPS) or amorphous silicon (for example, hydrogenation non-hydrogenation).
  • LTPS low temperature polysilicon
  • amorphous silicon for example, hydrogenation non-hydrogenation
  • crystalline silicon can effectively reduce the size of the transistor and prevent leakage current.
  • all the transistors are N-type transistors, and the high level is taken as the active level and the low level is taken as the inactive level.
  • the first of the transistors The pole is the drain and the second pole is the source.
  • embodiments of the present disclosure include, but are not limited to, such.
  • the first pole of the transistor is The source and the second pole are drains, and each pole of the selected type of transistor is simply connected with reference to each pole of the corresponding transistor in the embodiment of the present disclosure, and the corresponding voltage terminal is provided with a corresponding high voltage or low.
  • the voltage is OK.
  • all the transistors in FIG. 3 are set as P-type transistors, and the high level and the low level of the related signals are exchanged with each other, for example, the inactive level voltage is made.
  • Line VGL is changed from output low level to output high level. It is easy to understand that such a change will cause the high level of the circuit to change to a low level, the low level to a high level, the potential pull-up to a potential pull-down, and the potential pull-down to a potential pull-up.
  • the essence of the circuit's working principle remains unchanged. Therefore, the changed circuit structure, circuit timing, and circuit operation principle can be understood in comparison with the above embodiments, and details are not described herein again.
  • pulse-up means charging one node or one electrode of a transistor such that the level of the node or the electrode is absolute. The value is increased to achieve the operation of the corresponding transistor (eg, conduction); “pull-down” means discharging one electrode of one node or one transistor, so that the absolute value of the level of the node or the electrode is lowered, thereby achieving corresponding Operation of the transistor (eg cut-off).
  • pulse-up means discharging one electrode of one node or one transistor, so that the absolute value of the level of the node or the electrode is lowered, thereby implementing the corresponding transistor.
  • Operation eg, conduction
  • pulse-down means charging one node or one electrode of a transistor to increase the absolute value of the level of the node or the electrode to achieve operation of the corresponding transistor (eg, cutoff) .
  • the embodiments shown in FIG. 3 and FIG. 4 are merely exemplary, and may be modified as needed in a specific application scenario without departing from the technical idea of the embodiments of the present disclosure.
  • the source of the eighth transistor M8 described above may be changed to the inactive level voltage line VGL such that the function and function of the eighth transistor M8 are unchanged.
  • the source of the ninth transistor M9 can be changed to the reset terminal RES such that the ninth transistor M9 does not introduce noise on the second clock signal CK2 to the output terminal OUT.
  • the first end of the first capacitor C1 is connected to the second node PD, and the second end of the first capacitor C1 is connected to the third node PC.
  • the potential at the third node PC gradually rises with the injection of the source and drain current of the first transistor M1 at the time when the reset terminal RES changes from the low level to the high level.
  • the second transistor M2 is not yet turned on, and thus the potential at the second node PD will follow the potential of the third node PC under the charge holding of the first capacitor C1.
  • the potential at the second node PD is raised when the second transistor M2 is turned on, so that the second node PD can reach the high level faster, and then the sixth transistor M6 and the seventh transistor M7 are turned on faster, speeding up the reset speed of the first node PU and the output terminal OUT at the beginning of the reset phase III.
  • Still another embodiment of the present disclosure provides a scan driving circuit including a plurality of stages of shift register units of any of the above.
  • the scan drive circuit can achieve the same or corresponding beneficial effects based on the beneficial effects that the shift register unit can achieve.
  • FIG. 6 is a schematic block diagram of a scan driving circuit according to an embodiment of the present disclosure.
  • the input terminal IN of any stage shift register unit is shifted from the upper stage except the first stage shift register unit.
  • the output terminal OUT of the register unit is connected; except for the first stage shift register unit, the output terminal OUT of any one of the shift register units is connected to the reset terminal RES of the shift register unit of the previous stage.
  • the input terminal IN of the first stage shift register unit is connected to the trigger signal STV, and the reset terminal RES of the last stage shift register unit is connected to a reset line provided separately.
  • the first clock signal terminal CK1 of the odd-numbered shift register unit and the second clock signal terminal CK2 of the even-numbered shift register unit are connected to the same first system clock line CK_1, odd-numbered
  • the second clock signal terminal CK2 of the shift register unit is connected to the same second system clock line CK_2 of the even-numbered shift register unit. That is to say, except for the first stage, the clock signal of the shift register unit of any stage is connected in the opposite manner to the connection mode of the shift register unit of the previous stage.
  • the working principle of the scan driving circuit is similar to that of the shift register unit in the above embodiment, and details are not described herein again.
  • Still another embodiment of the present disclosure provides an array substrate including the shift register unit of any one of the above or at least one of the scan drive circuits of any of the above.
  • the array substrate can also achieve the same or corresponding beneficial effects based on the beneficial effects that can be achieved by the shift register unit or the scan drive circuit.
  • FIG. 7 is a schematic block diagram of an array substrate provided by an embodiment of the present disclosure.
  • the array substrate includes a shift register unit according to any one of the embodiments of the present disclosure or a scan driving circuit according to any one of the embodiments of the present disclosure.
  • the scan driving circuit may be disposed on a side of the array substrate outside the display area.
  • the array substrate includes a plurality of rows of gate lines, and the output terminals OUT of the stages of the shift register units in the scan driving circuit may be configured to be sequentially connected to the plurality of rows of gate lines for outputting the scan driving signals.
  • the array substrate is provided with a plurality of (for example, two) scan driving circuits of any one of the above, and two scan driving circuits are respectively disposed on both sides of the array substrate to realize bilateral drive.
  • one scan driving circuit may be disposed on one side of the array substrate for driving odd-numbered gate lines
  • another scan driving circuit may be disposed on the other side of the array substrate for driving even-numbered gate lines.
  • still another embodiment of the present disclosure provides a display device including the shift register unit of any of the above, the scan drive circuit of any of the above, or the array substrate of any of the above.
  • the display device can achieve the same or corresponding beneficial effects based on the beneficial effects that can be achieved by the shift register unit, the scan drive circuit or the array substrate.
  • FIG. 8 is a schematic block diagram of a display device according to an embodiment of the present disclosure.
  • the display device 20 includes a display panel 2000, a gate driver 2010, a timing controller 2020, and a data driver 2030.
  • the display panel 2000 includes a plurality of pixel units P defined according to a plurality of scan lines GL and a plurality of data lines DL; a gate driver 2010 for driving a plurality of scan lines GL; and a data driver 2030 for driving a plurality of data lines DL;
  • the timing controller 2020 is for processing the image data RGB input from the outside of the display device 20, supplying the processed image data RGB to the data driver 2030, and outputting the scan control signal GCS and the data control signal DCS to the gate driver 2010 and the data driver 2030 to The gate driver 2010 and the data driver 2030 are controlled.
  • the gate driver 2010 includes the shift register unit or scan drive circuit provided in any of the above embodiments.
  • the display panel 2000 includes the array substrate provided in any of the above embodiments.
  • the output terminal OUT of the plurality of shift register units in the scan driving circuit is correspondingly connected to the plurality of scanning lines GL.
  • the plurality of scanning lines GL are connected to the pixel units P arranged in a plurality of rows.
  • the output terminals OUT of the shift register units in the scan driving circuit sequentially output signals to the plurality of scan lines GL to enable the plurality of rows of pixel units P in the display panel 2000 to perform progressive scan.
  • the gate driver 2010 may be implemented as a semiconductor chip or may be integrated in the display panel 2000 to constitute a GOA circuit.
  • the data driver 2030 converts the digital image data RGB input from the timing controller 2020 into a data signal according to a plurality of data control signals DCS derived from the timing controller 2020 using the reference gamma voltage.
  • the data driver 2030 supplies the converted data signals to the plurality of data lines DL.
  • the data driver 2030 can be implemented as a semiconductor chip.
  • the timing controller 2020 processes the externally input image data RGB to match the size and resolution of the display panel 2000, and then supplies the processed image data to the data driver 2030.
  • the timing controller 2020 generates a plurality of scan control signals GCS and a plurality of data control signals DCS using synchronization signals (for example, a dot clock DCLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync) input from the outside of the display device 20. .
  • the timing controller 2020 supplies the generated scan control signal GCS and data control signal DCS to the gate driver 2010 and the data driver 2030, respectively, for control of the gate driver 2010 and the data driver 2030.
  • the display device 20 may also include other components, such as signal decoding circuits, voltage conversion circuits, etc., which may be, for example, conventional conventional components, and will not be described in detail herein.
  • the display device 20 can be a liquid crystal display (LCD) panel, an LCD TV, a display, an Organic Light-Emitting Diode (OLED) panel, an OLED TV, an electronic paper display device, a mobile phone, a tablet computer, Any of the products or components having a display function, such as a notebook computer, a digital photo frame, a navigator, and the like, are not limited in the embodiments of the present disclosure.
  • LCD liquid crystal display
  • OLED Organic Light-Emitting Diode
  • OLED Organic Light-Emitting Diode
  • another embodiment of the present disclosure provides a driving method of a shift register unit having an input terminal, a reset terminal, and an output terminal.
  • the driving method includes:
  • Step 101 When the input terminal is at an active level, the first node is disposed as an active level and the second node is disposed as an inactive level.
  • Step 102 When the first node is at an active level, the output is processed to an active level by using the first clock signal.
  • Step 103 When the active terminal is at an active level, the second node is disposed as an active level and the input is disposed as an inactive level.
  • Step 104 Dispose of the first node to an inactive level when the second node is at an active level.
  • the driving method of the shift register unit of the present disclosure can prevent the signal at the input end from affecting the second node during the period of the active level at the reset end on the basis of implementing the reset control, thereby being able to suppress
  • the interference caused by the signal connected to the input terminal to the signal connected to the reset terminal helps to reduce the output noise of the shift register unit and improve the reliability of the product.

Abstract

一种移位寄存器单元、扫描驱动电路、阵列基板和显示装置，该移位寄存器单元包括：输入电路(11)，用于在输入端(IN)处为有效电平时将第一节点(PU)处置为有效电平；第一复位控制电路(14)，用于在复位端(RES)处为有效电平时将第二节点(PD)处置为有效电平，并将输入端(IN)处置为无效电平；输出电路(12)，用于在第一节点(PU)处为有效电平时利用时钟信号将输出端(OUT)处置为有效电平；复位电路(13)，用于在第二节点(PD)处为有效电平时将第一节点(PD)处和输出端(OUT)处置为无效电平。该移位寄存器单元可以解决GOA单元中下拉节点的电平转换容易对上拉节点的电平转换造成不良影响的问题。

Description

移位寄存器单元及其驱动方法、扫描驱动电路、阵列基板和显示装置
本申请要求于2017年9月25日递交的中国专利申请第201710877090.6号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种移位寄存器单元及其驱动方法、扫描驱动电路、阵列基板和显示装置。
背景技术
阵列基板行驱动(Gate driver On Array，GOA)技术相较于传统工艺而言，不仅能省去承载栅极驱动器的电路板、能实现显示面板两边对称的设计，还能省去显示面板边缘上芯片绑定区域和例如扇出区的布线区域，有利于窄边框设计的实现。同时，由于GOA技术可以省去行方向上的芯片绑定工艺，对整体的产能、良率提升也有很大的帮助。
发明内容
本公开至少一个实施例提供一种移位寄存器单元，包括输入端、输出端和复位端，以及还包括：分别连接所述输入端和第一节点的输入电路，用于在所述输入端处为有效电平时将所述第一节点处置为有效电平；分别连接所述输出端和所述第一节点的输出电路，用于在所述第一节点为有效电平时利用第一时钟信号将所述输出端处置为有效电平；分别连接所述第一节点和第二节点的复位电路，用于在所述第二节点处为有效电平时将所述第一节点处置为无效电平；分别连接所述第二节点、所述输入端和所述复位端的第一复位控制电路，用于在所述复位端处为有效电平时将所述第二节点处置为有效电平，并将所述输入端处置为无效电平；以及，分别连接所述第二节点和所述输入端的第二复位控制电路，用于在所述输入端处为有效电平时将所述第二节点处置为无效电平。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一复位控制电路包括：分别连接所述复位端和第三节点的第一导通子电路，用于在所述复位端处为有效电平时将所述复位端导通至所述第三节点；分别连接所述第三节点、所述复位端和所述第二节点的第二导通子电路，用于在所述第三节点处为所述复位端处的有效电平时将所述复位端导通至所述第二节点；以及，分别连接所述复位端和所述输入端的复位子电路，用于在所述复位端处为有效电平时将所述输入端处置为无效电平；相应地，所述第二复位控制电路还与所述第三节点相连，所述第二复位控制电路还用于在所述输入端处为有效电平时将所述第三节点处置为无效电平。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一导通子电路包括第一晶体管，所述第二导通子电路包括第二晶体管，所述复位子电路包括第三晶体管；所述第一晶体管的栅极连接所述复位端，源极和漏极中的一个连接所述复位端，另一个连接所述第三节点；所述第二晶体管的栅极连接所述第三节点，源极和漏极中的一个连接所述复位端，另一个连接所述第二节点；所述第三晶体管的栅极连接所述复位端，源极和漏极中的一个连接所述输入端，另一个连接无效电平电压线。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一复位控制电路还包括第一电容，所述第一电容的第一端连接所述第二节点，所述第一电容的第二端连接所述第三节点。
例如，在本公开一实施例提供的移位寄存器单元中，所述第三节点与所述第二节点相连。
例如，在本公开一实施例提供的移位寄存器单元中，所述第二复位控制电路包括第四晶体管和第五晶体管；所述第四晶体管的栅极连接所述输入端，源极和漏极中的一个连接所述第二节点，另一个连接无效电平电压线；所述第五晶体管的栅极连接所述输入端，源极和漏极中的一个连接所述第三节点，另一个连接无效电平电压线。
例如，在本公开一实施例提供的移位寄存器单元中，所述复位电路包括第六晶体管，所述第六晶体管的栅极连接所述第二节点，源极和漏极中的一个连接所述第一节点，另一个连接无效电平电压线。
例如，在本公开一实施例提供的移位寄存器单元中，所述复位电路还包 括第七晶体管，所述第七晶体管的栅极连接所述第二节点，源极和漏极中的一个连接所述输出端，另一个连接无效电平电压线。
例如，在本公开一实施例提供的移位寄存器单元中，所述复位电路还包括第八晶体管，所述第八晶体管的栅极连接所述复位端，源极和漏极中的一个连接所述第一节点，另一个连接所述第一时钟信号或者无效电平电压线。
例如，在本公开一实施例提供的移位寄存器单元中，所述复位电路还包括第九晶体管，所述第九晶体管的栅极连接所述复位端或者第二时钟信号，源极和漏极中的一个连接所述输出端，另一个连接无效电平电压线；所述第一时钟信号与所述第二时钟信号的相位彼此相反。
例如，在本公开一实施例提供的移位寄存器单元中，所述输入电路包括第十晶体管，所述第十晶体管的栅极连接所述输入端，源极和漏极中的一个连接所述输入端，另一个连接所述第一节点。
例如，在本公开一实施例提供的移位寄存器单元中，所述输出电路包括第十一晶体管和第二电容；所述第十一晶体管的栅极连接所述第一节点，源极和漏极中的一个连接所述第一时钟信号，另一个连接所述输出端；所述第二电容的第一端连接所述第一节点，所述第二电容的第二端连接所述输出端。
本公开至少一个实施例还提供一种扫描驱动电路，包括上述任一实施例所述的移位寄存器单元。
本公开至少一个实施例还提供一种阵列基板，所述阵列基板包括上述任一实施例所述的移位寄存器单元或者上述任一实施例所述的扫描驱动电路。
本公开至少一个实施例还提供一种显示装置，所述显示装置包括上述任一实施例所述的移位寄存器单元、上述任一实施例所述的扫描驱动电路或上述任一实施例所述的阵列基板。
本公开至少一个实施例还提供一种移位寄存器单元的驱动方法，所述移位寄存器单元具有输入端、复位端和输出端，所述驱动方法包括：在所述输入端处为有效电平时，将第一节点处置为有效电平，将第二节点处置为无效电平；在所述第一节点为有效电平时，利用第一时钟信号将所述输出端处置为有效电平；在所述复位端处为有效电平时，将所述第二节点处置为有效电平，并将所述输入端处置为无效电平；在所述第二节点处为有效电平时将所述第一节点处置为无效电平。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1是本公开一个实施例提供的移位寄存器单元的结构框图；
图2是本公开又一实施例提供的移位寄存器单元的局部电路结构图；
图3是本公开又一实施例提供的移位寄存器单元的电路结构图；
图4是图3所示的移位寄存器单元的电路时序图；
图5是一种移位寄存器单元的局部电路结构图；
图6是本公开一个实施例提供的扫描驱动电路的示意框图；
图7是本公开一个实施例提供的阵列基板的示意框图；
图8是本公开一个实施例提供的显示装置的示意框图；以及
图9是本公开一个实施例提供的移位寄存器单元的驱动方法的流程示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
作为采用GOA技术的栅极驱动器的基本电路单元，移位寄存器单元可以在输入端所接信号和复位端所接信号的共同作用下输出栅极驱动信号。然而在移位寄存器单元中，输入端所接信号可能会对由复位端所接信号触发的操作造成干扰，在晶体管存在零电压导通的情况时甚至会影响移位寄存器单元的正常工作。
本公开至少一实施例提供一种移位寄存器单元及其驱动方法、扫描驱动电路、阵列基板和显示装置，可以抑制移位寄存器单元的输入端所接信号对复位端所接信号造成的干扰。在该移位寄存器单元中，基于复位电路、第一复位控制电路和第二复位控制电路的设置，该移位寄存器单元能够在实现复位控制的基础上，在复位端处为有效电平的时段内避免输入端处的信号对第二节点造成影响，因而能够抑制输入端所接信号对复位端所接信号造成的干扰，有助于降低移位寄存器单元的输出噪声，提升产品的可靠性。
图1是本公开一个实施例提供的移位寄存器单元的结构框图。参见图1，该移位寄存器单元包括输入端IN、复位端RES和输出端OUT，以及还包括：
分别连接输入端IN和第一节点PU的输入电路11，用于在输入端IN处为有效电平时将第一节点PU处置为有效电平；
分别连接输出端OUT和第一节点PU的输出电路12，用于在第一节点PU为有效电平时利用第一时钟信号将输出端OUT处置为有效电平；
分别连接第一节点PU和第二节点PD的复位电路13，用于在第二节点PD处为有效电平时将第一节点PU处置为无效电平；
分别连接第二节点PD、输入端IN和复位端RES的第一复位控制电路14，用于在复位端RES处为有效电平时将第二节点PD处置为有效电平，并将输入端IN处置为无效电平；以及，
分别连接第二节点PD和输入端IN的第二复位控制电路15，用于在输入端IN处为有效电平时将第二节点PD处置为无效电平。
需要说明的是，本文中的有效电平与无效电平分别指的是针对特定电路节点而言的两个不同的预先配置的电压范围(均以公共端电压为基准)。在一个示例中，所有电路节点的有效电平均为所在数字电路中的高电平。在又一示例中，所有电路节点的有效电平均为所在数字电路中的低电平。在又一示例中，输入端IN和复位端RES处的有效电平是所在数字电路中的低电平， 而输出端OUT、第一节点PU和第二节点PD处的有效电平是所在数字电路中的高电平。当然，有效电平和无效电平的设置方式可以不仅限于以上示例。
例如，第二节点PD处被置为有效电平的过程可以是由第一复位控制电路14在复位端RES处为有效电平时完成的，而同一时间内第一复位控制电路14还将输入端IN处置为无效电平，即可以将输入端IN处的噪声电压向提供无效电平的电路节点处释放。由此，输入端IN处的噪声电压将不会影响第二节点PD处的电平，使得第一节点PU处能顺利地被置为无效电平，避免输出端OUT处出现无法回到无效电平的异常情况。
可以看出，基于复位电路13、第一复位控制电路14和第二复位控制电路15的设置，本公开的实施例提供的移位寄存器单元能够在实现复位控制的基础上，在复位端RES处为有效电平的时段内避免输入端IN处的信号对第二节点PD造成影响，因而能够抑制输入端IN所接信号对复位端RES所接信号造成的干扰，有助于降低移位寄存器单元的输出噪声，提升产品的可靠性。
图2是本公开又一实施例提供的移位寄存器单元的局部电路结构图，示出了移位寄存器单元中第一复位控制电路和第二复位控制电路的一种示例性的电路结构。参见图2，本实施例中的第一复位控制电路14包括第一导通子电路14a、第二导通子电路14b和复位子电路14c。
例如，第一导通子电路14a分别连接复位端RES和第三节点PC，用于在复位端RES处为有效电平时将复位端RES导通至第三节点PC。在图2中，第一导通子电路14a以包括第一晶体管M1的结构作为示例，该第一晶体管M1的栅极连接复位端RES，源极和漏极中的一个连接复位端RES，另一个连接第三节点PC，从而能够在复位端RES处为作为有效电平的高电平时利用源漏电流形成复位端RES与第三节点PC之间的导通关系。需要说明的是，根据晶体管具体类型的不同，可以设置其源极和漏极分别所具有的连接关系，以与流过晶体管的电流的方向相匹配；在晶体管具有源极与漏极对称的结构时，源极和漏极可以视为不作特别区分的两个电极。
第二导通子电路14b分别连接第三节点PC、复位端RES和第二节点PD，用于在第三节点PC处为复位端RES处的有效电平时将复位端RES导通至第二节点PD。在图2中，第二导通子电路14b以包括第二晶体管M2的结构作 为示例，该第二晶体管M2的栅极连接第三节点PC，源极和漏极中的一个连接复位端RES，另一个连接第二节点PD，从而能够在第三节点PC处为作为有效电平的高电平时利用源漏电流形成复位端RES与第二节点PD之间的导通关系。
复位子电路14c分别连接复位端RES和输入端IN，用于在复位端RES处为有效电平时将输入端IN处置为无效电平。在图2中，复位子电路14c以包括第三晶体管M3的结构作为示例，该第三晶体管M3的栅极连接复位端RES，源极和漏极中的一个连接输入端IN，另一个连接无效电平电压线VGL(低电平电压线)，从而能够在复位端RES处为作为有效电平的高电平时利用从输入端IN处流向无效电平电压线VGL的源漏电流将输入端IN处下拉至作为无效电平的低电平。
此外，如图2所示，第二复位控制电路15包括第一部分15a和第二部分15b，并在分别连接第二节点PD和输入端IN的基础上还与第三节点PC相连。本实施例中，第二复位控制电路15不仅用于在输入端IN处为有效电平时将第二节点PD处置为无效电平，还用于在输入端IN处为有效电平时将第三节点PC处置为复位端RES处的无效电平。在图2中，第二复位控制电路15的第一部分15a以包括第四晶体管M4的结构作为示例，该第四晶体管M4的栅极连接输入端IN，源极和漏极中的一个连接第二节点PD，另一个连接无效电平电压线VGL，从而能够在输入端IN处为作为有效电平的高电平时利用从第二节点PD处流向无效电平电压线VGL的源漏电流将第二节点PD下拉至作为无效电平的低电平。在图2中，第二复位控制电路15的第二部分15b以包括第五晶体管M5的结构作为示例，该第五晶体管M5的栅极连接输入端IN，源极和漏极中的一个连接第三节点PC，另一个连接无效电平电压线VGL，从而能够在输入端IN处为作为有效电平的高电平时利用从第三节点PC处流向无效电平电压线VGL的源漏电流将第三节点PC下拉至作为无效电平的低电平。
本实施例中，第二节点PD与第三节点PC相连，即第二节点PD的电平与第三节点PC的电平始终保持一致。基于此，在输入端IN处为有效电平而复位端RES处为无效电平的时段内，第二节点PD和第三节点PC会被第二复位控制电路15的第一部分15a和第二部分15b置为无效电平，而图2中具 有二极管连接方式的第一晶体管M1会使得复位端RES处的噪声电压能够藉由第一晶体管M1和第五晶体管M5的源漏电流释放到无效电平电压线VGL上。而在此后的输入端IN处为无效电平而复位端RES处为有效电平的时段内，在第一导通子电路14a和第二导通子电路14b的作用下，第二节点PD和第三节点PC能够被置为有效电平，同时复位子电路14c能够将输出端IN处的噪声电压释放到无效电平电压线VGL上。由此，能避免输入端IN与复位端RES之间的相互干扰。
在另一个示例中，第二节点PD与第三节点PC之间断开，即第二节点PD的电平与第三节点PC的电平保持彼此独立。基于此，在输入端IN处为有效电平而复位端RES处为无效电平的时段内，第二节点PD会被第二复位控制电路15的第一部分15a置为无效电平，第三节点PC会被第二复位控制电路15的第二部分15b置为无效电平，图2中具有二极管连接方式的第一晶体管M1会使得复位端RES处的噪声电压和第三节点PC处的噪声电压能够藉由第一晶体管M1和第五晶体管M5的源漏电流释放到无效电平电压线VGL上。在此后的输入端IN处为无效电平而复位端RES处为有效电平的时段内，在第一导通子电路14a的作用下第三节点PC处被置为有效电平，在第二导通子电路14b的作用下第二节点PD处被置为有效电平，同时复位子电路14c能够将输出端IN处的噪声电压释放到无效电平电压线VGL上。由此，能够避免输入端IN与复位端RES之间的相互干扰。
可以看出，无论第二节点PD与第三节点PC之间是否相连，均能够避免输入端IN与复位端RES之间的相互干扰。而第二节点PD不与第三节点PC相连时，第二节点PD上的高电平电压不会通过具有二极管连接方式的第二晶体管M2释放到复位端RES处，能使得复位电路13的工作时间更长，更有利于维持第一节点PU处的电平的稳定性。
例如，第二节点PD处被置为无效电平的过程可以是由第二复位控制电路15在输入端IN处为有效电平时完成的，而同一时间内第二复位控制电路15还将第三节点PC处置为无效电平，即可以将第三节点PC处的噪声电压向提供无效电平的电路节点处释放。由此，复位端RES处的噪声电压将不会影响第三节点PC处和第二节点PD处的电平，使得复位电路13能在输入电路11的工作时间内暂时停止将第一节点PU处置为无效电平，以避免第一节 点PU处被置为无效电平而使得输出端OUT处无法正常输出有效电平的异常情况。
可以看出，基于上述第一导通子电路14a、第二导通子电路14b、复位子电路14c和第二复位控制电路15的设置，本实施例的移位寄存器单元能够在实现复位控制的基础上，在输入端IN为有效电平的时段内避免复位端RES处的信号对第二节点PD造成影响，因而能够抑制复位端RES所接信号对输入端IN所接信号造成的干扰，有助于进一步降低移位寄存器单元的输出噪声，提升产品的可靠性。
图3是本公开又一实施例提供的移位寄存器单元的电路结构图。参见图3，本实施例的移位寄存器单元相比于图2所示的结构而言，在第一复位控制电路14中增加了第一电容C1，并且还示出了输入电路11、输出电路12和复位电路13的示例性的电路结构。
参见图3，输入电路11包括第十晶体管M10，该第十晶体管M10的栅极连接输入端IN，源极和漏极中的一个连接输入端IN，另一个连接第一节点PU，从而能够在输入端IN处为作为有效电平的高电平时利用从输入端IN处流向第一节点PU的源漏电流将第一节点PU处上拉至作为有效电平的高电平，实现上述在输入端IN处为有效电平时将第一节点PU处置为有效电平的功能。
参见图3，输出电路12包括第十一晶体管M11和第二电容C2，第十一晶体管M11的栅极连接第一节点PU，源极和漏极中的一个连接第一时钟信号线(或第一时钟信号端)CK1，另一个连接输出端OUT；第二电容C2的第一端连接第一节点PU，第二电容C2的第二端连接输出端OUT。例如，作为本实施例的一种示例，第一时钟信号线CK1上和下文中描述的第二时钟信号线(或第二时钟信号端)CK2上可以分别加载正相时钟信号和反相时钟信号中的一个(即第一时钟信号线CK1和第二时钟信号线CK2上的信号相位彼此相反)。如此，当第一节点PU处为高电平时，第十一晶体管M11在栅极的高电平作用下开启，从而能够利用第一时钟信号线CK1上的高电平将输出端OUT处上拉至高电平，实现上述在第一节点PU为有效电平时利用第一时钟信号将输出端OUT处置为有效电平的功能。当然，输出单元12的电路结构可以不仅限于以上形式。
参见图3，复位电路13包括第六晶体管M6，该第六晶体管M6的栅极连接第二节点PD，源极和漏极中的一个连接第一节点PU，另一个连接无效电平电压线VGL，从而能够在第二节点PD处为作为有效电平的高电平时利用从第一节点PU处流向无效电平电压线VGL的源漏电流将第一节点PU处下拉至作为无效电平的低电平，实现上述第二节点PD处为有效电平时将第一节点PU处置为无效电平的功能。
参见图3，复位电路13还包括第七晶体管M7，该第七晶体管M7的栅极连接第二节点PD，源极和漏极中的一个连接输出端OUT，另一个连接无效电平电压线VGL，从而能够在第二节点PD处为作为有效电平的高电平时利用从输出端OUT处流向为低电平的无效电平电压线VGL的源漏电流将输出端OUT处下拉至作为无效电平的低电平，帮助进行输出端OUT处的复位。
参见图3，复位电路13还包括第八晶体管M8，该第八晶体管M8的栅极连接复位端RES，源极和漏极中的一个连接第一节点PU，另一个连接第一时钟信号线CK1，从而能够在复位端RES处为作为有效电平的高电平时利用从第一节点PU处流向为低电平的第一时钟信号线CK1的源漏电流将第一节点PU处下拉至作为无效电平的低电平，帮助完成第一节点PU处的复位。
参见图3，复位电路13还包括第九晶体管M9，该第九晶体管M9栅极连接第二时钟信号线CK2，源极和漏极中的一个连接输出端OUT，另一个连接无效电平电压线VGL，从而能够在第二时钟信号线CK2处为作为有效电平的高电平时利用从输出端OUT处流向无效电平电压线VGL的源漏电流将输出端OUT处下拉至作为无效电平的低电平，帮助完成输出端OUT处的复位，并随第二时钟信号线CK2的时钟信号周期性释放输出端OUT处的噪声电压，维持输出端OUT处的信号的稳定性。
图4是图3所示的移位寄存器单元的电路时序图。参见图4，上述移位寄存器单元的工作阶段主要包括输入阶段I、输出阶段II和复位阶段III。参见图3和图4，上述移位寄存器单元的工作原理简述如下。需要说明的是，在图4中以及下面的描述中，CK1、CK2、IN、OUT、RES等既用于表示相应的信号端，也用于表示相应的信号，以下各实施例与此相同，不再赘述。
输入阶段I中，输入端IN处转为高电平，第四晶体管M4、第五晶体管M5和第十晶体管M10开启，将第一节点PU处上拉至高电平，使得第十一 晶体管M11开启，并将第二节点PD和第三节点PC处下拉为低电平。此时，第一时钟信号CK1为低电平，第二时钟信号CK2为高电平，输出端OUT处在处于开启状态的第九晶体管M9的下拉作用下保持为低电平。由此，第二电容C2的第一端处为第一节点PU处的高电平，第二端处为输出端OUT处的低电平。而且，第一电容C1的第一端处为第二节点PD处的低电平，第二端处为第三节点PC处的低电平。
输出阶段II中，输入端IN处转为低电平，第一时钟信号CK1转为高电平。在第二电容C2的电荷保持作用下，第一节点PU处会随着第一时钟信号CK1由低电平转为高电平的变化跳变至一电位更高的高电平上。这使得第十一晶体管M11完全开启，快速完成输出端OUT处的电位上拉，即输出端OUT处开始进行栅极驱动信号的输出。
复位阶段III中，复位端RES处转为高电平，第一时钟信号CK1转为低电平，第二时钟信号CK2转为高电平，第一晶体管M1、第三晶体管M3、第七晶体管M7、第八晶体管M8和第九晶体管M9开启。第三节点PC处的电位随着第一晶体管M1的源漏电流的注入而逐渐上升，在第三节点PC处的电位上升到第二晶体管M2开启之前，第二晶体管M2尚未开启，因而第二节点PD处的电位会在第一电容C1的电荷保持作用下随着第三节点PC的电位上升而上升。在第二晶体管M2开启之后，第二节点PD处的电位会在第一电容C1的抬升和第二晶体管M2的源漏电流的共同作用下快速上升至高电平，继而使得第六晶体管M6和第七晶体管M7开启。在此过程中，第三晶体管M3会将输入端IN处保持为低电平，避免输入端IN处的噪声对上述过程造成影响。在第六晶体管M6和第八晶体管M8的共同作用下，第一节点PU被下拉至低电平；在第七晶体管M7和第九晶体管M9的共同作用下，输出端OUT处被下拉至低电平，完成移位寄存器单元的复位。
为了更清楚地体现本公开的实施例的有益效果，图5是一种移位寄存器单元的局部电路结构图。参见图5，该移位寄存器单元在图3所示电路的基础上将第二复位控制电路15设置为仅包含上述第四晶体管M4的电路结构，而将第一复位控制电路14设置为仅包含栅极和漏极连接复位端RES、源极连接第二节点PD的第一晶体管M1。基于此，在上述输入阶段I中，复位端RES处的噪声电压可能通过第一晶体管M1对第二节点PD处的电位有上拉 作用，容易意外地使第六晶体管M6开启而使得第一节点PU无法被上拉至高电平，导致输出阶段II中输出端OUT处不能输出高电平，产生输出异常。而且，在上述复位阶段III中，输入端IN处的噪声电压可能通过第四晶体管M4而对第二节点PD处的电位有下拉作用，容易使得第二节点PD无法达到至高电平，导致第一节点PU下拉不完全，而在复位阶段III之后造成输出端处的误输出。
而将图3和图4所示的实现方式与图5所示的移位寄存器单元相比较后可以看出，本公开的实施例中输入端IN和复位端RES处的噪声电压能够得到抑制，从而使得上述异常状况的出现概率大大减小。也即，基于上述包括第一导通子电路14a、第二导通子电路14b及复位子电路14c的第一复位控制电路14和第二复位控制电路15的设置，本公开的实施例的移位寄存器单元能够在实现复位控制的基础上，减小输入端IN与复位端RES之间的相互干扰，因而有助于进一步降低移位寄存器单元的输出噪声，提升产品的可靠性。
需要注意的是，在本公开的各个实施例的说明中，第一节点PU、第二节点PD和第三节点PC并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管、场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
需要说明的是，图3中示出的晶体管均为N型晶体管，即可以通过相同制作工艺形成以降低制造成本。当采用N型晶体管时，可以采用氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)作为薄膜晶体管的有源层，相对于采用低温多晶硅(Low Temperature Poly Silicon，LTPS)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层，可以有效减小晶体管的尺寸以及防止漏电流。为了便于理解，本公开的实施例中均是以全部晶体管均为N型晶体管，并且高电平作为有效电平、低电平作为无效电平为例进行说明的，此时，晶 体管的第一极是漏极，第二极是源极。当然，本公开的实施例包括但不限于此。例如，实施时也可以采用低电平作为有效电平、高电平作为无效电平，和/或将部分或全部的N型晶体管变更为P型晶体管的设置，此时，晶体管第一极是源极，第二极是漏极，只需将选定类型的晶体管的各极参照本公开的实施例中的相应晶体管的各极相应连接，并且使相应的电压端提供对应的高电压或低电压即可。例如，可以在本公开的实施例的基础上进行如下变更：将图3中的晶体管全部设置为P型晶体管，并将相关信号的高电平与低电平相互交换，例如使无效电平电压线VGL由输出低电平变更为输出高电平。容易理解的是，这样的变更会使得电路工作原理中的高电平变为低电平、低电平变为高电平，电位上拉变为电位下拉、电位下拉变为电位上拉，而电路工作原理的实质则保持不变。因此，变更后的电路结构、电路时序和电路工作原理可以比照上述实施例进行理解，在此不再赘述。
在本公开的实施例中，例如，当各个电路实现为N型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如截止)。又例如，当各个电路实现为P型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如截止)。
需要说明的是，图3和图4所示的实施方式仅是示例性的，在具体应用场景中可以根据需要进行变形，而不脱离本公开的实施例的技术构思。例如，在一种示例中，上述第八晶体管M8的源极可以改接无效电平电压线VGL，而使得第八晶体管M8的功能和作用不变。再如，在另一种示例中，第九晶体管M9的源极可以改接复位端RES，使得第九晶体管M9不会将第二时钟信号CK2上的噪声引入到输出端OUT处。
此外，关于第一电容C1的设置：如图3所示，第一电容C1的第一端连接第二节点PD，第一电容C1的第二端连接第三节点PC。基于第一电容C1 的设置，在复位端RES处从低电平转为高电平的时刻开始，第三节点PC处的电位随着第一晶体管M1的源漏电流的注入而逐渐上升，在第三节点PC处的电位上升到第二晶体管M2开启之前，第二晶体管M2尚未开启，因而第二节点PD处的电位会在第一电容C1的电荷保持作用下随着第三节点PC的电位上升而上升。相比于未设置第一电容C1的情形，在第二晶体管M2恰好开启时第二节点PD处的电位得以抬升，使得第二节点PD处能更快地达到高电平，继而使第六晶体管M6和第七晶体管M7更快地开启，加快第一节点PU和输出端OUT处在复位阶段III开始时的复位速度。
基于同样的构思，本公开的又一实施例提供了一种扫描驱动电路，该扫描驱动电路包括若干级的上述任意一种的移位寄存器单元。基于移位寄存器单元所能取得的有益效果，该扫描驱动电路也能取得相同或相应的有益效果。
图6是本公开一个实施例提供的扫描驱动电路的示意框图。例如，如图6所示，在该扫描驱动电路(栅极驱动电路)中：除第一级移位寄存器单元之外，任一级移位寄存器单元的输入端IN均与上一级移位寄存器单元的输出端OUT相连；除第一级移位寄存器单元之外，任一级移位寄存器单元的输出端OUT均与上一级移位寄存器单元的复位端RES相连。例如，第一级移位寄存器单元的输入端IN与触发信号STV连接，最后一级移位寄存器单元的复位端RES与另行提供的复位线连接。而且为了实现正确的信号时序，奇数级的移位寄存器单元的第一时钟信号端CK1与偶数级的移位寄存器单元的第二时钟信号端CK2连接到相同的第一系统时钟线CK_1，奇数级的移位寄存器单元的第二时钟信号端CK2与偶数级移位寄存器单元的第一时钟信号端CK1连接到相同的第二系统时钟线CK_2。即除第一级之外，任一级移位寄存器单元的时钟信号的连接方式与上一级移位寄存器单元的连接方式相反。该扫描驱动电路的工作原理与上述实施例中的移位寄存器单元的工作原理类似，此处不再赘述。
基于同样的构思，本公开的又一实施例提供了一种阵列基板，该阵列基板包括上述任意一种的移位寄存器单元或至少一个上述任意一种的扫描驱动电路。基于移位寄存器单元或扫描驱动电路所能取得的有益效果，该阵列基板也能取得相同或相应的有益效果。
图7是本公开一个实施例提供的阵列基板的示意框图。如图7所示，该 阵列基板包括本公开任一实施例所述的移位寄存器单元或本公开任一实施例所述的扫描驱动电路。例如，当采用扫描驱动电路驱动该阵列基板时，可以将扫描驱动电路设置于阵列基板在显示区域之外的一侧。例如，该阵列基板包括多行栅线，扫描驱动电路中的各级移位寄存器单元的输出端OUT可以配置为依序和多行栅线连接，以用于输出扫描驱动信号。例如，在一个示例中，该阵列基板在显示区域之外设置有若干个(例如2个)上述任意一种的扫描驱动电路，2个扫描驱动电路分别设置在阵列基板的两侧，以实现双边驱动。例如，可以在阵列基板的一侧设置一个扫描驱动电路以用于驱动奇数行栅线，而在阵列基板的另一侧设置另一个扫描驱动电路以用于驱动偶数行栅线。
基于同样的构思，本公开的又一实施例提供了一种显示装置，该显示装置包括上述任意一种的移位寄存器单元、上述任意一种的扫描驱动电路或上述任意一种的阵列基板。基于移位寄存器单元、扫描驱动电路或阵列基板所能取得的有益效果能，该显示装置也能取得相同或相应的有益效果。
图8是本公开一个实施例提供的显示装置的示意框图。如图8所示，显示装置20包括显示面板2000、栅极驱动器2010、定时控制器2020和数据驱动器2030。显示面板2000包括根据多条扫描线GL和多条数据线DL交叉限定的多个像素单元P；栅极驱动器2010用于驱动多条扫描线GL；数据驱动器2030用于驱动多条数据线DL；定时控制器2020用于处理从显示装置20外部输入的图像数据RGB，向数据驱动器2030提供处理的图像数据RGB以及向栅极驱动器2010和数据驱动器2030输出扫描控制信号GCS和数据控制信号DCS，以对栅极驱动器2010和数据驱动器2030进行控制。
例如，栅极驱动器2010包括上述任一实施例中提供的移位寄存器单元或扫描驱动电路。又例如，显示面板2000包括上述任一实施例中提供的阵列基板。扫描驱动电路中的多个移位寄存器单元的输出端OUT与多条扫描线GL对应连接。多条扫描线GL与排列为多行的像素单元P对应连接。扫描驱动电路中的各级移位寄存器单元的输出端OUT依序输出信号到多条扫描线GL，以使显示面板2000中的多行像素单元P实现逐行扫描。例如，栅极驱动器2010可以实现为半导体芯片，也可以集成在显示面板2000中以构成GOA电路。
例如，数据驱动器2030使用参考伽玛电压根据源自定时控制器2020的多个数据控制信号DCS将从定时控制器2020输入的数字图像数据RGB转换成数据信号。数据驱动器2030向多条数据线DL提供转换的数据信号。例如，数据驱动器2030可以实现为半导体芯片。
例如，定时控制器2020对外部输入的图像数据RGB进行处理以匹配显示面板2000的大小和分辨率，然后向数据驱动器2030提供处理后的图像数据。定时控制器2020使用从显示装置20外部输入的同步信号(例如点时钟DCLK、数据使能信号DE、水平同步信号Hsync以及垂直同步信号Vsync)产生多条扫描控制信号GCS和多条数据控制信号DCS。定时控制器2020分别向栅极驱动器2010和数据驱动器2030提供产生的扫描控制信号GCS和数据控制信号DCS，以用于栅极驱动器2010和数据驱动器2030的控制。
该显示装置20还可以包括其他部件，例如信号解码电路、电压转换电路等，这些部件例如可以采用已有的常规部件，这里不再详述。
例如，显示装置20可以为液晶显示(Liquid Crystal Display,LCD)面板、LCD电视、显示器、有机发光二极管(Organic Light-Emitting Diode,OLED)面板、OLED电视、电子纸显示装置、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开的实施例对此不作限制。显示装置20的技术效果可以参考上述实施例中关于移位寄存器单元的相应描述，这里不再赘述。
基于同样的构思，本公开的又一实施例提供了一种移位寄存器单元的驱动方法，所述移位寄存器单元具有输入端、复位端和输出端，参见图9，所述驱动方法包括：
步骤101：在输入端处为有效电平时，将第一节点处置为有效电平，将第二节点处置为无效电平。
步骤102：在第一节点为有效电平时，利用第一时钟信号将输出端处置为有效电平。
步骤103：在复位端处为有效电平时，将第二节点处置为有效电平，并将输入端处置为无效电平。
步骤104：在第二节点处为有效电平时将第一节点处置为无效电平。
需要说明的是，上述任意一种移位寄存器单元的工作过程均可以视作上 述驱动方法的一种实现方式的示例，因此上述各步骤的具体过程示例可以参见上文，在此不再赘述。
可以看出，本公开的移位寄存器单元的驱动方法能够在实现复位控制的基础上，在复位端处为有效电平的时段内避免输入端处的信号对第二节点造成影响，因而能够抑制输入端所接信号对复位端所接信号造成的干扰，有助于降低移位寄存器单元的输出噪声，提升产品的可靠性。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (16)

  1. 一种移位寄存器单元，包括输入端、输出端和复位端，以及还包括：
    分别连接所述输入端和第一节点的输入电路，用于在所述输入端处为有效电平时将所述第一节点处置为有效电平；
    分别连接所述输出端和所述第一节点的输出电路，用于在所述第一节点为有效电平时利用第一时钟信号将所述输出端处置为有效电平；
    分别连接所述第一节点和第二节点的复位电路，用于在所述第二节点处为有效电平时将所述第一节点处置为无效电平；
    分别连接所述第二节点、所述输入端和所述复位端的第一复位控制电路，用于在所述复位端处为有效电平时将所述第二节点处置为有效电平，并将所述输入端处置为无效电平；以及，
    分别连接所述第二节点和所述输入端的第二复位控制电路，用于在所述输入端处为有效电平时将所述第二节点处置为无效电平。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述第一复位控制电路包括：
    分别连接所述复位端和第三节点的第一导通子电路，用于在所述复位端处为有效电平时将所述复位端导通至所述第三节点；
    分别连接所述第三节点、所述复位端和所述第二节点的第二导通子电路，用于在所述第三节点处为所述复位端处的有效电平时将所述复位端导通至所述第二节点；以及，
    分别连接所述复位端和所述输入端的复位子电路，用于在所述复位端处为有效电平时将所述输入端处置为无效电平；
    相应地，所述第二复位控制电路还与所述第三节点相连，所述第二复位控制电路还用于在所述输入端处为有效电平时将所述第三节点处置为无效电平。
  3. 根据权利要求2所述的移位寄存器单元，其中，所述第一导通子电路包括第一晶体管，所述第二导通子电路包括第二晶体管，所述复位子电路包括第三晶体管；
    所述第一晶体管的栅极连接所述复位端，源极和漏极中的一个连接所述 复位端，另一个连接所述第三节点；
    所述第二晶体管的栅极连接所述第三节点，源极和漏极中的一个连接所述复位端，另一个连接所述第二节点；
    所述第三晶体管的栅极连接所述复位端，源极和漏极中的一个连接所述输入端，另一个连接无效电平电压线。
  4. 根据权利要求2或3所述的移位寄存器单元，其中，所述第一复位控制电路还包括第一电容，
    所述第一电容的第一端连接所述第二节点，所述第一电容的第二端连接所述第三节点。
  5. 根据权利要求2或3所述的移位寄存器单元，其中，所述第三节点与所述第二节点相连。
  6. 根据权利要求2至5中任一项所述的移位寄存器单元，其中，所述第二复位控制电路包括第四晶体管和第五晶体管；
    所述第四晶体管的栅极连接所述输入端，源极和漏极中的一个连接所述第二节点，另一个连接无效电平电压线；
    所述第五晶体管的栅极连接所述输入端，源极和漏极中的一个连接所述第三节点，另一个连接无效电平电压线。
  7. 根据权利要求1至6中任一项所述的移位寄存器单元，其中，所述复位电路包括第六晶体管，
    所述第六晶体管的栅极连接所述第二节点，源极和漏极中的一个连接所述第一节点，另一个连接无效电平电压线。
  8. 根据权利要求1至7中任一项所述的移位寄存器单元，其中，所述复位电路还包括第七晶体管，
    所述第七晶体管的栅极连接所述第二节点，源极和漏极中的一个连接所述输出端，另一个连接无效电平电压线。
  9. 根据权利要求1至8中任一项所述的移位寄存器单元，其中，所述复位电路还包括第八晶体管，
    所述第八晶体管的栅极连接所述复位端，源极和漏极中的一个连接所述第一节点，另一个连接所述第一时钟信号或者无效电平电压线。
  10. 根据权利要求1至9中任一项所述的移位寄存器单元，其中，所述 复位电路还包括第九晶体管，
    所述第九晶体管的栅极连接所述复位端或者第二时钟信号，源极和漏极中的一个连接所述输出端，另一个连接无效电平电压线；
    所述第一时钟信号与所述第二时钟信号的相位彼此相反。
  11. 根据权利要求1至10中任一项所述的移位寄存器单元，其中，所述输入电路包括第十晶体管，
    所述第十晶体管的栅极连接所述输入端，源极和漏极中的一个连接所述输入端，另一个连接所述第一节点。
  12. 根据权利要求1至11中任一项所述的移位寄存器单元，其中，所述输出电路包括第十一晶体管和第二电容；
    所述第十一晶体管的栅极连接所述第一节点，源极和漏极中的一个连接所述第一时钟信号，另一个连接所述输出端；
    所述第二电容的第一端连接所述第一节点，所述第二电容的第二端连接所述输出端。
  13. 一种扫描驱动电路，包括如权利要求1至12中任一项所述的移位寄存器单元。
  14. 一种阵列基板，包括如权利要求1至12中任一项所述的移位寄存器单元或者如权利要求13所述的扫描驱动电路。
  15. 一种显示装置，包括如权利要求1至12中任一项所述的移位寄存器单元、如权利要求13所述的扫描驱动电路或如权利要求14所述的阵列基板。
  16. 一种移位寄存器单元的驱动方法，其中，所述移位寄存器单元具有输入端、复位端和输出端，所述驱动方法包括：
    在所述输入端处为有效电平时，将第一节点处置为有效电平，将第二节点处置为无效电平；
    在所述第一节点为有效电平时，利用第一时钟信号将所述输出端处置为有效电平；
    在所述复位端处为有效电平时，将所述第二节点处置为有效电平，并将所述输入端处置为无效电平；
    在所述第二节点处为有效电平时将所述第一节点处置为无效电平。
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