WO2019052265A1 - 薄膜晶体管、其制造方法及电子装置 - Google Patents

薄膜晶体管、其制造方法及电子装置 Download PDF

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Publication number
WO2019052265A1
WO2019052265A1 PCT/CN2018/094117 CN2018094117W WO2019052265A1 WO 2019052265 A1 WO2019052265 A1 WO 2019052265A1 CN 2018094117 W CN2018094117 W CN 2018094117W WO 2019052265 A1 WO2019052265 A1 WO 2019052265A1
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Prior art keywords
gate
thin film
film transistor
work function
auxiliary layer
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PCT/CN2018/094117
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English (en)
French (fr)
Inventor
王骏
黄中浩
赵永亮
林承武
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京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Priority to EP18849422.3A priority Critical patent/EP3683846A4/en
Priority to US16/330,255 priority patent/US11387371B2/en
Publication of WO2019052265A1 publication Critical patent/WO2019052265A1/zh
Priority to US17/806,578 priority patent/US11837665B2/en

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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • Embodiments of the present disclosure relate to a thin film transistor, a method of fabricating the same, and an electronic device.
  • Thin-film transistors are important components of some electronic devices.
  • thin film transistors are switching elements of pixel circuits in active display devices.
  • the performance of thin film transistors is an important factor affecting the performance of electronic devices.
  • Embodiments of the present disclosure provide a thin film transistor including a gate, a gate insulating layer, an active layer, and a source and a drain disposed on a substrate, the active layer including the source and the drain a channel region between the poles, the channel region including an edge region along a length direction of the channel and a body region other than the edge region, the thin film transistor further including an auxiliary layer, the auxiliary layer and the channel region The projection of the edge regions on the substrate at least partially overlaps, the auxiliary layer for increasing the turn-on voltage of the edge regions of the channel regions.
  • Embodiments of the present disclosure also provide an electronic device including the above thin film transistor.
  • Embodiments of the present disclosure also provide a method of fabricating a thin film transistor, the method comprising: forming a gate, an auxiliary layer, a gate insulating layer, an active layer, a source and a drain on a substrate; the active layer includes a channel region between the source and the drain, the channel region including an edge region along a length direction of the channel and a body region other than the edge region; the auxiliary layer and the channel region The projection of the edge regions on the substrate at least partially overlaps, the auxiliary layer for increasing the turn-on voltage of the edge regions of the channel regions.
  • FIG. 1A is a schematic structural view of a sub-pixel unit of an array substrate in a liquid crystal display device
  • FIG. 1B is a cross-sectional structural view of the thin film transistor of FIG. 1A along a section line A-A'
  • FIG. 1C is a thin film transistor of FIG. 1A along a section line B-B 'Sectional structure diagram.
  • FIG. 2A is a schematic top plan view of a thin film transistor according to a first embodiment of the present disclosure
  • FIG. 2B is an example of a cross-sectional structure of the thin film transistor of FIG. 2A along a section line C-C'
  • FIG. 2C is a cross-sectional view of the thin film transistor of FIG. Another example of a schematic cross-sectional structure of line C-C'.
  • FIG 3 is a schematic cross-sectional view showing a thin film transistor of a second embodiment of the present disclosure.
  • FIG. 4A is a schematic top plan view of a thin film transistor according to a third embodiment of the present disclosure
  • FIG. 4B is an example of a cross-sectional structure diagram of the thin film transistor of FIG. 4A along a section line DD′
  • FIG. 4C is a cross-sectional view of the thin film transistor of FIG. 4A.
  • FIG. 5 is a schematic cross-sectional view showing a thin film transistor of a fourth embodiment of the present disclosure.
  • FIG. 6A-6D and FIG. 7 are schematic cross-sectional views showing respective steps of a method of fabricating a thin film transistor according to a fifth embodiment of the present disclosure and its modified embodiment.
  • FIGS. 8 to 10 are schematic cross-sectional views showing respective steps of a method of manufacturing a thin film transistor according to a sixth embodiment of the present disclosure and its modified embodiment.
  • FIG. 11 is a schematic diagram of an electronic device according to a seventh embodiment of the present disclosure.
  • Figure 12 is a schematic diagram of a 2T1C pixel circuit of the electronic device in the seventh embodiment.
  • FIG. 1A is a schematic structural view of a sub-pixel unit of an array substrate in a liquid crystal display device.
  • the array substrate is used, for example, in a liquid crystal display device, and generally includes a plurality of gate lines 101 and a plurality of data lines 102, and the gate lines 101 and the data lines 102 cross each other thereby defining a plurality of sub-pixel units arranged in an array (only in FIG. 1A)
  • one sub-pixel unit is illustrated, each of which includes a thin film transistor 110 and a pixel electrode 120 for controlling the arrangement of liquid crystals.
  • the thin film transistor 110 functions as a switching element to control signal transmission between the data line 102 and the pixel electrode 120.
  • FIG. 1B is a cross-sectional structural view of the thin film transistor 110 of FIG. 1A taken along line A-A.
  • the thin film transistor 110 is a bottom gate structure including a gate electrode 111, a gate insulating layer 112, an active layer 113, a source 114, and a drain 115 which are sequentially stacked on a substrate.
  • the active layer 113 has a channel region 116 in a region close to the interface of the active layer 113 and the gate insulating layer 112, and the channel region 116 is located between the source 114 and the drain 115.
  • the thin film transistor 110 when a bias voltage greater than the threshold voltage Vth is applied to the gate electrode 111, an inverse charge having the same concentration as that of the doping concentration in the active layer is formed in the channel region 116.
  • the inversion charge is directed to move under the electric field between the source 114 and the drain 115 to form an on current.
  • the "on voltage" in the present disclosure also refers to a threshold voltage; the direction of the channel region 116 in the direction of the current is the channel length direction, and correspondingly the length in the direction is the channel length L, correspondingly perpendicular to the length direction.
  • the direction is the channel width direction; the "edge region along the channel length direction" in the present disclosure refers to a region where the edge portion of the active layer channel region extending along the channel length direction, for example, an extension of the edge region
  • the direction is parallel to the extending direction of the center line of the channel region in the channel width direction; for example, the extending direction of the edge region is parallel to the direction of the channel length.
  • the width of the edge region may be less than or equal to 1/4 of the width of the channel region, and may be, for example, less than or equal to 1/6 of the width of the channel region.
  • FIG. 1C is a schematic cross-sectional view of the thin film transistor 110 along line BB′ in FIG. 1A. Since the gate voltage is easily collected in the edge region 117 of the channel region 116, the edge region 117 is compared.
  • the body region 118 non-edge of the channel region 116 generates an inversion charge in advance, such that when the gate voltage has not reached the threshold voltage of the thin film transistor 110 and the body region 118 of the channel region 116 has not been turned on, the edge region 117
  • the conduction current is formed in advance, resulting in a hump effect.
  • the hump effect greatly affects the subthreshold characteristics of the thin film transistor 110, resulting in unstable performance of the thin film transistor.
  • Embodiments of the present disclosure provide a thin film transistor, a method of fabricating the same, and an electronic device.
  • the thin film transistor includes a substrate and a gate disposed on the substrate, a gate insulating layer, an active layer, and a source and a drain, the active layer including a channel region between the source and the drain, the channel The region includes an edge region along a length direction of the channel and a body region other than the edge region, and the thin film transistor further includes an auxiliary layer, the projection of the edge region of the auxiliary layer and the channel region at least partially overlapping on the substrate, and the auxiliary layer is used for improving The turn-on voltage of the edge region of the channel region.
  • the thin film transistor according to an embodiment of the present disclosure increases the on-voltage of the edge region of the channel region by providing the auxiliary layer in the edge region of the corresponding channel region, so that the edge region of the channel region of the thin film transistor is almost synchronized with the body region The on current is formed, thereby attenuating or eliminating the hump effect of the thin film transistor.
  • the turn-on voltage of the edge region of the channel region can be increased by adjusting the relationship of the work function between the gate material of the corresponding channel edge region and the active layer material.
  • the work function of a material is the minimum energy required for electrons to escape the surface of the material.
  • the difference in work function between the gate material and the active layer material is ⁇ ms It is an important factor affecting the threshold voltage of the thin film transistor. For example, the larger the difference in work function between the gate material and the active layer material, the larger the threshold voltage of the thin film transistor, without considering the influence of the net charge in the gate insulating layer.
  • the thin film transistor is an enhancement transistor (Vth is greater than 0), and a difference ⁇ ms between work functions of the gate material and the active layer material is positive as an example; however, embodiments of the present disclosure may also A transistor suitable for a depletion transistor (Vth less than 0) and a difference in work function between the gate material and the active layer material ⁇ ms is less than or equal to 0, that is, the present disclosure is not limited to a specific type of transistor.
  • an auxiliary layer may be disposed between the gate and the active layer.
  • the material of the auxiliary layer is a conductive material and is electrically connected to the gate to form a secondary gate.
  • the auxiliary layer may be disposed between the gate and the gate insulating layer, or the auxiliary layer may be disposed in the same layer as the gate.
  • the "same layer setting" as referred to herein means that the auxiliary layer and the gate electrode are formed on the same surface of the same layer structure (such as the gate insulating layer), and may be formed of different materials.
  • the difference between the work function of the auxiliary layer material and the active layer material is greater than the work function between the gate material and the active layer material.
  • the difference is ⁇ ms, thereby increasing the turn-on voltage of the edge region of the channel region.
  • the gate material may be one or any combination of the following metal materials: copper, molybdenum, titanium, tungsten, aluminum, and the auxiliary layer material is one or any combination of the following metal materials: platinum, gold, palladium.
  • the gate material and the auxiliary layer material may be electrically conductive materials whose work function is adjustable, such as conductive silicon or conductive metal oxide.
  • the auxiliary layer may be disposed between the active layer and the gate insulating layer to form a secondary active layer, the material of the auxiliary layer is a semiconductor material, and the work function of the auxiliary layer material is smaller than the work function of the active layer material, then the gate The difference between the work function of the work material of the pole material and the material of the auxiliary layer is greater than the difference ⁇ ms of the work function between the material of the gate material and the material of the active layer, thereby increasing the turn-on voltage of the edge region of the channel region.
  • the material of the active layer may be amorphous silicon, polycrystalline silicon, metal oxide semiconductor, etc.
  • the polycrystalline silicon may be high temperature polycrystalline silicon or low temperature polycrystalline silicon
  • the oxide semiconductor may be, for example, zinc oxide, indium tin oxide (ITO), or indium gallium oxide. Zinc (IGZO) and the like.
  • ITO indium tin oxide
  • IGZO indium gallium oxide
  • ion doping can also be performed as needed.
  • the auxiliary layer may include two auxiliary structures spaced apart, respectively corresponding to the two edge regions of the channel region, the two auxiliary structures being spaced apart by a predetermined distance, the portion of the interval corresponding to the body region of the active layer.
  • the thin film transistor may be a bottom gate type, a top gate type, a top gate bottom gate hybrid type or the like, and the projections of the gate electrode, the auxiliary layer, and the active layer on the substrate at least partially overlap in a direction perpendicular to the substrate.
  • the thickness of the auxiliary layer may be less than one tenth of the thickness of the gate.
  • FIG. 2A is a top plan view of a thin film transistor 200 according to a first embodiment of the present disclosure
  • FIG. 2B shows an example of a cross-sectional view of the thin film transistor 200 of FIG. 2A along a section line C-C'
  • FIG. 2C shows FIG. 2A.
  • the thin film transistor 200 of the bottom gate structure includes a gate electrode 202, an auxiliary layer 203, a gate insulating layer 204, an active layer 205, a source 206, and a gate electrode 201, which are sequentially stacked on the substrate 201.
  • the drain 207, the active layer 205 includes a channel region 208 between the source 206 and the drain 207, the channel region 208 including an edge region 209 along the channel length direction and a body region 210 other than the edge region 209.
  • the projection of the auxiliary layer 203 with the edge region 209 of the channel region 208 on the substrate 201 at least partially overlaps.
  • the auxiliary layer 203 is used to increase the turn-on voltage of the edge region 209 of the channel region 208.
  • an auxiliary layer may be disposed between the gate and the active layer.
  • the auxiliary layer 203 is disposed corresponding to the edge region 209 of the channel region 208, and the projections of the gate 202, the auxiliary layer 203, and the active layer 205 on the substrate 201 at least partially overlap.
  • the auxiliary layer 203 is disposed between the gate electrode 202 and the gate insulating layer 204.
  • the thickness of the auxiliary layer is less than one tenth of the thickness of the gate, such as the thickness of the auxiliary layer being 15-30 nm, so as to prevent the auxiliary layer step in the bottom gate structure from affecting the film formation quality of the active layer.
  • the auxiliary layer 203 is two auxiliary gates spaced apart, and the two auxiliary gates are respectively disposed corresponding to the two edge regions 209 of the channel region 208.
  • the auxiliary layer includes only one secondary gate, corresponding only to one edge region of the channel region.
  • the work function of the material of the gate 202 is smaller than the work function of the material of the auxiliary layer 203.
  • the material of the gate 202 is molybdenum (Mo), and its work function is 4.37 eV; the material of the auxiliary layer 203 is platinum (Pt), and its work function is 5.65 eV, so that the work of the auxiliary layer 203 material
  • Mo molybdenum
  • Pt platinum
  • the work function is 5.65 eV
  • the work function of the other auxiliary layer materials may be selected to be greater than the combination of the work functions of the gate materials such that the difference in work function between the auxiliary layer material and the active layer material is greater than the work function of the gate material and the active layer material.
  • the gate material is one or any combination of the following metal materials: copper (4.65 eV), molybdenum (4.37 eV), titanium (4.33 eV), tungsten (4.55 eV), aluminum (4.28 eV), and the auxiliary layer material is as follows One or any combination of metallic materials: platinum (5.65 eV), gold (5.1 eV), palladium (5.12 eV).
  • the gate material and the auxiliary layer material may also be electrically conductive materials whose work function is adjustable, such as conductive silicon or conductive metal oxide.
  • both the gate material and the auxiliary layer material are polysilicon, and the doping concentration of the polysilicon can be adjusted such that the work function of the auxiliary gate material is greater than the work function of the gate material.
  • both the gate material and the secondary gate material are indium tin oxide ITO, and the work function of the secondary gate material can be made larger than the work function of the gate material by adjusting the composition of the ITO.
  • Fig. 2C shows another example of a cross-sectional view of the thin film transistor 200 of Fig. 2A along section line C-C'.
  • the auxiliary layer 203 is disposed in the same layer as the gate electrode 202, that is, the auxiliary layer 203 and the gate electrode 202 are disposed on the same surface of the substrate 201.
  • the auxiliary layer 203 is disposed corresponding to the edge region 209 of the channel region 208
  • the gate 202 is disposed corresponding to the body region 210 of the channel region 208.
  • the auxiliary layer 203 and the gate electrode 202 may have the same thickness.
  • FIG. 3 is a schematic cross-sectional view showing a thin film transistor 200 according to a second embodiment of the present disclosure.
  • the thin film transistor of the second embodiment of the present disclosure is substantially the same as the thin film transistor of the first embodiment except that the set position and material of the auxiliary layer 203 are different.
  • the auxiliary layer 203 is disposed between the active layer 205 and the gate insulating layer 204.
  • the auxiliary layer 203 is a secondary active layer, and the material thereof is a semiconductor material.
  • the auxiliary layer 203 is two auxiliary active layers spaced apart, and the two auxiliary active layers are respectively disposed corresponding to the two edge regions 209 of the channel region 208.
  • the auxiliary layer includes only one secondary active layer, corresponding only to one edge region of the channel region.
  • the work function of the material of the active layer 205 is greater than the work function of the material of the auxiliary layer 203.
  • both the active layer material and the auxiliary layer material are polysilicon.
  • the work function of the polysilicon material for the auxiliary layer 203 is smaller than that of the polysilicon material for the active layer 205.
  • the work function such that the difference between the work function of the material of the gate 202 and the work function of the material of the auxiliary layer 203 is greater than the difference between the work function of the material of the gate 202 and the work function of the material of the active layer 205, ultimately resulting in the edge region of the channel region 208
  • the turn-on voltage of 209 is greater than the turn-on voltage of its body region 210.
  • the work function of the other active layer materials may be selected to be greater than the work function of the auxiliary layer materials such that the difference in work function between the gate material and the auxiliary layer material is greater than the work function of the gate material and the active layer material. The difference.
  • FIG. 4A is a schematic top plan view of a thin film transistor 200 according to a third embodiment of the present disclosure
  • FIG. 4B is an example of a cross-sectional structure diagram of the thin film transistor 200 of FIG. 4A along a line D-D'
  • FIG. 4C is a thin film transistor of FIG. 4A.
  • the same components are denoted by the same reference numerals and will not be described below.
  • the thin film transistor 200 of the top gate structure includes a source 206 and a drain 207, an active layer 205, a gate insulating layer 204, and an auxiliary layer 203 which are sequentially stacked on the substrate 201.
  • the gate 202, the active layer 205 includes a channel region 208 adjacent to the gate insulating layer 204, the channel region 208 including an edge region 209 along the length of the channel and a body region 210 other than the edge region 209.
  • the projection of the auxiliary layer 203 and the edge region 209 on the substrate 201 at least partially overlaps.
  • the auxiliary layer 203 is used to increase the turn-on voltage of the edge region 209 of the channel region 208.
  • an auxiliary layer may be disposed between the gate and the active layer.
  • the auxiliary layer 203 is disposed corresponding to the edge region 209 of the channel region 208, and the projections of the gate 202, the auxiliary layer 203, and the active layer 205 on the substrate 201 at least partially overlap.
  • the auxiliary layer 203 is disposed between the gate electrode 202 and the gate insulating layer 204.
  • the auxiliary layer 203 is two auxiliary gates spaced apart, and the two auxiliary gates are respectively disposed corresponding to the two edge regions 209 of the channel region 208.
  • the auxiliary layer includes only one secondary gate, corresponding only to one edge region of the channel region.
  • the work function of the gate 202 material is less than the work function of the material of the auxiliary layer 203.
  • the material of the gate 202 is molybdenum (Mo), and its work function is 4.37 eV; the material of the auxiliary layer 203 is platinum (Pt), and its work function is 5.65 eV, so that the work of the auxiliary layer 203 material
  • Mo molybdenum
  • Pt platinum
  • the difference between the function and the work function of the active layer 205 material is greater than the difference between the work function of the material of the gate 202 and the work function of the material of the active layer 205, such that the turn-on voltage of the edge region 209 of the channel region 208 is greater than its body region 210. Turn-on voltage.
  • the work function of the other auxiliary layer materials may be selected to be greater than the combination of the work functions of the gate materials such that the difference between the work function of the auxiliary layer material and the work function of the active layer material is greater than the work function of the gate material and The difference in the work function of the source layer material.
  • the gate material is one or any combination of the following metal materials: copper (4.65 eV), molybdenum (4.37 eV), titanium (4.33 eV), tungsten (4.55 eV), aluminum (4.28 eV), and the auxiliary layer material is as follows One or any combination of metallic materials: platinum (5.65 eV), gold (5.1 eV), palladium (5.12 eV).
  • the gate material and the auxiliary layer material may also be electrically conductive materials whose work function is adjustable, such as conductive silicon or conductive metal oxide.
  • both the gate material and the auxiliary layer material are polysilicon, and the doping concentration of the polysilicon can be adjusted such that the work function of the auxiliary gate material is greater than the work function of the gate material.
  • both the gate material and the secondary gate material are indium tin oxide ITO, and the work function of the secondary gate material can be made larger than the work function of the gate material by adjusting the composition of the ITO.
  • Fig. 4C shows another example of a cross-sectional view of the thin film transistor 200 of Fig. 4A along the section line C-C'.
  • the auxiliary layer 203 is disposed in the same layer as the gate electrode 202, that is, the auxiliary layer 203 and the gate electrode 202 are disposed on the gate insulating layer 204.
  • the auxiliary layer 203 is disposed corresponding to the edge region 209 of the channel region 208
  • the gate 202 is disposed corresponding to the body region 210 of the channel region 208.
  • the auxiliary layer 203 and the gate electrode 202 may have the same thickness.
  • FIG. 5 is a cross-sectional structural view of a thin film transistor 200 according to a fourth embodiment of the present disclosure.
  • the thin film transistor of the fourth embodiment of the present disclosure is substantially the same as the thin film transistor structure of the third embodiment except that the arrangement position and material of the auxiliary layer 203 are different.
  • the auxiliary layer 203 is disposed between the active layer 205 and the gate insulating layer 204.
  • the auxiliary layer 203 is a secondary active layer, and the material thereof is a semiconductor.
  • the auxiliary layer 203 is two auxiliary active layers spaced apart, and two auxiliary active layers are respectively disposed on the two edge regions 209 of the channel region 208.
  • the auxiliary layer includes only one secondary active layer, corresponding only to one edge region of the channel region.
  • the work function of the active layer 205 material is greater than the work function of the auxiliary layer 203 material.
  • both the active layer material and the auxiliary layer material are polysilicon.
  • the work function of the polysilicon material for the auxiliary layer 203 is smaller than that of the polysilicon material for the active layer 205.
  • the work function such that the difference between the work function of the material of the gate 202 and the work function of the material of the auxiliary layer 203 is greater than the difference between the work function of the material of the gate 202 and the work function of the material of the active layer 205, ultimately resulting in the edge region of the channel region 208
  • the turn-on voltage of 209 is greater than the turn-on voltage of its body region 210.
  • the work function of the other active layer materials may be selected to be greater than the work function of the auxiliary layer materials such that the difference in work function between the gate material and the auxiliary layer material is greater than the work function of the gate material and the active layer material. The difference.
  • the on-voltage of the edge region of the channel region is increased by providing the auxiliary layer in the edge region of the corresponding channel region along the channel length direction between the gate electrode and the active layer, so that the thin film transistor is The edge region of the channel region and the body region nearly simultaneously form a conduction current, thereby improving the hump effect of the thin film transistor and improving the performance of the thin film transistor.
  • embodiments of the present disclosure also provide a method of manufacturing a thin film transistor which can be used to prepare a thin film transistor of the embodiment described above.
  • the method at least includes: forming a gate, an auxiliary layer, a gate insulating layer, an active layer, a source and a drain on a substrate; an auxiliary layer is formed between forming a gate and forming an active layer, and the active layer is included a channel region between the source and the drain, the channel region including an edge region along the length of the channel and a body region other than the edge region; the projection of the edge region of the auxiliary layer and the channel region at least partially overlaps on the substrate,
  • the auxiliary layer is used to increase the turn-on voltage of the edge region of the channel region.
  • the gate electrode and the auxiliary layer may each be formed by an exposure process, or may be formed by one exposure by a gray tone mask.
  • the active layer and the auxiliary layer may each be formed by an exposure process, or may be formed by one exposure by a gray tone mask.
  • the auxiliary layer is formed between the gate and the active layer.
  • a method of manufacturing a thin film transistor of a fifth embodiment of the present disclosure and its modified embodiment will be described below with reference to FIGS. 6A to 6C and FIG.
  • step S61 the gate 202 is formed.
  • a first conductive layer is formed on the substrate 201 and the first conductive layer is patterned by a first patterning process to form a gate electrode 202.
  • the substrate 201 is provided, and then the substrate 201 is washed and dried.
  • the substrate 100 may be a flexible flexible substrate, for example, various plastic films such as polyethylene terephthalate (PET), polyether sulfone (PES), polycarbonate (Polycarbonate, PC) or A substrate made of polyimide (PI) and its derivatives.
  • the substrate 100 may be a rigid substrate such as a glass substrate, a stainless steel substrate, or the like.
  • step S62 the auxiliary layer 203 is formed, and the auxiliary gate 203 and the gate electrode 202 are formed to be electrically connected to each other.
  • a second conductive layer is formed on the gate 202 and the second conductive layer is patterned to form the auxiliary layer 203.
  • the auxiliary layer 203 is formed on the edge region of the gate electrode 202 along the channel length direction of the thin film transistor to be formed.
  • the auxiliary layer 203 is formed as two auxiliary gates spaced apart, and the two auxiliary gates respectively correspond to the two edge regions 209 of the channel region 208.
  • the auxiliary layer includes only one secondary gate, corresponding only to one edge region of the channel region.
  • the thickness of the auxiliary layer is less than one tenth of the thickness of the gate electrode, for example, the thickness of the auxiliary layer is 15-30 nm, so as to prevent the auxiliary layer step in the bottom gate structure from affecting the film forming quality of the active layer.
  • the work function of the first conductive layer material is selected to be smaller than the second conductive layer such that the work function of the gate 202 material is less than the work function of the auxiliary layer 203 material.
  • the material of the first conductive layer is molybdenum (Mo), and the work function is 4.37 eV; the material of the second conductive layer is platinum (Pt), and the work function is 5.65 eV, so that the auxiliary layer 203 material
  • the difference in work function from the active layer material is greater than the difference in work function of the gate 202 material and the active layer material.
  • the work function of the other second conductive layer material may also be selected to be greater than the combination of the work functions of the first conductive layer material.
  • the first conductive layer material is one or any combination of the following metal materials: copper (4.65 eV), molybdenum (4.37 eV), titanium (4.33 eV), tungsten (4.55 eV), aluminum (4.28 eV), second conductive
  • the layer material is one or any combination of the following metal materials: platinum (5.65 eV), gold (5.1 eV), palladium (5.12 eV).
  • the first conductive layer material and the second conductive layer material may also be conductive materials whose work function is adjustable, such as conductive silicon or conductive metal oxide.
  • both the first conductive layer material and the second conductive layer material are polysilicon, and the doping concentration of the polysilicon can be adjusted such that the work function of the second conductive layer material is greater than the work function of the first conductive layer material.
  • the first conductive layer material and the second conductive layer material are both indium tin oxide ITO, and the work function of the second conductive layer material can be made larger than the work function of the first conductive layer material by adjusting the composition of the ITO. .
  • the gate 202 and the auxiliary layer 203 may be formed by one exposure, for example, by forming a gate 202 and an auxiliary layer 203 by one exposure with a halftone mask.
  • the photoresist layer 310 is formed on the second conductive layer 302, and the light is used using the halftone mask 320.
  • the resist layer 310 performs an exposure process.
  • the halftone mask 320 includes three regions A, B, and C that are symmetrically distributed with different light transmittances.
  • the area A is a fully transparent area
  • the area B is an opaque area
  • the area C is a partially transparent area.
  • the auxiliary layer 203 and the gate electrode 202 may be formed on the same layer, that is, the auxiliary layer 203 and the gate electrode 202 are formed on the same surface of the substrate 201.
  • the gate 202 and the auxiliary layer 203 can be separately formed by performing deposition and patterning processes of the conductive material twice, and details are not described herein again.
  • the auxiliary layer 203 and the gate 202 have the same thickness.
  • step S63 the gate insulating layer 204 and the active layer 205 are formed.
  • a gate insulating layer 204 is formed on the auxiliary layer 203, then a semiconductor layer is formed on the gate insulating layer 204, and the semiconductor layer is patterned by a third patterning process to form the active layer 205.
  • the active layer 205 includes a channel region 208 adjacent to the gate insulating layer 204, the channel region 208 including opposing two edge regions 209 along the channel length direction and a body region 210 other than the edge regions 209.
  • the two edge regions 209 correspond to the auxiliary layer 203, that is, the two edge regions 209 respectively correspond to two auxiliary gates, and the projections of the two edge regions 209 and the corresponding auxiliary gates on the substrate 201 at least partially overlap.
  • the projections of the gate 202, the auxiliary layer 203, and the active layer 205 on the substrate 201 at least partially overlap.
  • step S64 a source and a drain (not shown) are formed.
  • a third conductive layer is formed on the active layer 205, and the third conductive layer is patterned by a fourth patterning process to form the source 206 and the drain 207.
  • the third conductive layer may be selected from materials such as molybdenum, titanium, aluminum, copper, and alloys thereof.
  • the thin film transistor 200 in the first embodiment of the present disclosure is formed.
  • the step of forming the auxiliary layer 203 occurs after the gate insulating layer 204 is formed before the active layer 205 is formed.
  • the material of the auxiliary layer 203 is a semiconductor material
  • the auxiliary layer 203 is a secondary active layer.
  • the number of secondary active layers is two, and two secondary active layers are respectively disposed corresponding to the two edge regions 209 of the channel region 208.
  • the work function of the material of the auxiliary layer 203 is made smaller than the work function of the material of the active layer 203 to increase the turn-on voltage of the edge region 209 of the channel region.
  • both the active layer material and the auxiliary layer material are polysilicon, and by selecting polysilicon of different doping concentrations, the work function of the polysilicon material for the auxiliary layer is smaller than the work function of the polysilicon material for the active layer, thereby making the gate
  • the difference between the work function of the pole material and the work function of the auxiliary layer material is greater than the difference between the work function of the gate material and the work function of the active layer material, such that the turn-on voltage of the edge region 209 of the channel region 208 is greater than its body region 210. Turn-on voltage.
  • the work function of the other active layer materials may be selected to be greater than the work function of the auxiliary layer materials such that the difference between the work function of the gate material and the work function of the auxiliary layer material is greater than the work function of the gate material and The difference in the work function of the source layer material.
  • an array substrate for use in, for example, a liquid crystal display device, an organic light emitting diode display device, or the like, it is also possible to form a storage capacitor, a pixel electrode, and the like while forming the thin film transistor.
  • a method of manufacturing a thin film transistor of a sixth embodiment of the present disclosure and its modified embodiment will be described below with reference to FIGS. 8 to 9.
  • step S81 the active layer 205 is formed.
  • the substrate 201 is provided, and the substrate 201 is washed and dried.
  • the substrate 100 may be a flexible flexible substrate, for example, various plastic films such as polyethylene terephthalate (PET), polyether sulfone (PES), polycarbonate (Polycarbonate, PC) or A substrate made of polyimide (PI) and its derivatives.
  • the substrate 100 may be a rigid substrate such as a glass substrate, a stainless steel substrate, or the like.
  • a first semiconductor layer is formed on a substrate 201 and a first semiconductor layer is patterned by a first patterning process to form an active layer 205.
  • the active layer 205 includes a channel region 208 remote from the substrate 201, the channel region 208 including opposing two edge regions 209 along the channel length direction and a body region 210 other than the edge regions 209.
  • a buffer layer may also be formed between the substrate 201 and the active layer 205 if necessary.
  • the buffer layer can prevent, for example, impurities in the substrate from diffusing into the active layer to affect the performance of the active layer.
  • step S82 the auxiliary layer 203 is formed.
  • a second semiconductor layer is formed on the active layer 205 and a second semiconductor layer is patterned to form the auxiliary layer 203.
  • the auxiliary layer 203 is formed on the edge region 209 of the active layer 205.
  • the first semiconductor layer is made to have a specific relationship with the work function of the semiconductor layer material to increase the turn-on voltage of the channel region edge region 209.
  • the auxiliary layer 203 is two spaced apart auxiliary active layers disposed on the two edge regions 209 of the active layer 205, respectively.
  • the auxiliary layer includes only one secondary active layer, corresponding only to one edge region of the channel region.
  • the materials of the first semiconductor layer and the second semiconductor layer are both polysilicon, and by selecting polysilicon of different doping concentration, the work function of the polysilicon material of the second semiconductor material is smaller than the work function of the polysilicon material of the first semiconductor material, thereby The work function of the auxiliary layer material is made smaller than the work function of the active layer material.
  • the work function of the other active layer materials may also be selected to be greater than the combination of the work function of the auxiliary layer materials.
  • the active layer 205 and the auxiliary layer 203 may be formed by one exposure, for example, the active layer 205 and the auxiliary layer 203 are formed by one exposure with a halftone mask.
  • the specific method is similar to the step of forming the gate electrode 202 and the auxiliary layer 203 in one exposure in the fifth embodiment, and details are not described herein again.
  • step S83 a gate insulating layer and a gate, a source, and a drain are formed.
  • a gate insulating layer 204 is formed on the auxiliary layer 203, then a conductive layer is formed on the gate insulating layer 204, and the conductive layer is patterned by a third patterning process to form a gate 202 and a source. And drain (not shown).
  • the thin film transistor 200 of the fourth embodiment of the present disclosure is formed.
  • the projections of the gate 202, the auxiliary layer 203, and the active layer 205 on the substrate 201 at least partially overlap.
  • the work function of the first semiconductor material is selected to be larger than the work function of the second semiconductor material such that the work function of the auxiliary layer material is smaller than the work function of the active layer material, thereby making the gate material and the auxiliary layer
  • the difference in work function of the material is greater than the difference in work function of the gate material and the active layer material, ultimately resulting in a turn-on voltage of the edge region 209 of the channel region 208 being greater than the turn-on voltage of the body region 210.
  • the step of forming the auxiliary layer 203 occurs after the gate insulating layer 204 is formed, before the gate 202 is formed, or after the gate 202 is formed.
  • the material of the auxiliary layer 203 is a conductive material
  • the auxiliary layer 203 is a secondary gate.
  • the number of the auxiliary gates is two, and the two auxiliary gates are respectively disposed corresponding to the two edge regions 209 of the channel region 208, and the projections of the two auxiliary gates and the corresponding edge regions 209 on the substrate 201 are at least partially overlapping.
  • the work function of the material of the auxiliary layer 203 is made larger than the work function of the material of the gate 202 to increase the turn-on voltage of the edge region 209 of the channel region.
  • the auxiliary layer 203 is formed between the gate electrode 202 and the gate insulating layer 204, thus forming the thin film transistor 200 shown in FIG. 4B.
  • the auxiliary layer 203 and the gate electrode 202 are formed in the same layer, that is, the auxiliary layer 203 and the gate electrode 202 are formed on the same surface of the gate insulating layer 204.
  • the thin film transistor 200 as shown in Fig. 4C is formed.
  • the gate 202 and the auxiliary layer 203 can be separately formed by performing deposition and patterning processes of the conductive material twice, and details are not described herein again.
  • the auxiliary layer 203 and the gate 202 have the same thickness.
  • the material of the gate is molybdenum (Mo) and its work function is 4.37 eV; the material of the auxiliary layer is platinum (Pt), and its work function is 5.65 eV, so that the work function of the auxiliary layer 203 material and the active layer material The difference in work function is greater than the difference between the work function of the material of the gate 202 and the work function of the active layer material.
  • the work function of the other auxiliary layer materials may also be selected to be greater than the combination of the work functions of the gate materials.
  • the gate material is one or any combination of the following metal materials: copper (4.65 eV), molybdenum (4.37 eV), titanium (4.33 eV), tungsten (4.55 eV), aluminum (4.28 eV), and the auxiliary layer material is as follows One or any combination of metallic materials: platinum (5.65 eV), gold (5.1 eV), palladium (5.12 eV).
  • the gate material and the auxiliary layer material may also be electrically conductive materials whose work function is adjustable, such as conductive silicon or conductive metal oxide.
  • both the gate material and the auxiliary layer material are polysilicon, and the doping concentration of the polysilicon can be adjusted such that the work function of the auxiliary layer material is greater than the work function of the gate material.
  • both the gate material and the auxiliary layer material are indium tin oxide ITO, and the work function of the auxiliary layer material can be made larger than the work function of the gate material by adjusting the composition of the ITO.
  • an array substrate for use in, for example, a liquid crystal display device, an organic light emitting diode display device, or the like, it is also possible to form a storage capacitor, a pixel electrode, and the like while forming the thin film transistor.
  • the manufacturing method of the thin film transistor provided by the embodiment of the present disclosure, by providing an auxiliary layer in the thin film transistor and selecting a work function of the material, the work function of the metal-semiconductor corresponding to the edge region of the active region channel region is made
  • the work function of the metal-semiconductor corresponding to the body region of the channel region is different, thereby increasing the turn-on voltage of the edge region of the channel region, so that the edge region of the channel region of the thin film transistor and the body region are nearly simultaneously synchronized to form an on current , thereby improving the hump effect of the thin film transistor and improving the performance of the thin film transistor.
  • Embodiments of the present disclosure also provide an electronic device including the thin film transistor 200 of any of the embodiments of the present disclosure.
  • the electronic device is a display device, and may be a liquid crystal display device, an organic light emitting diode display device, an electronic paper display device, or the like.
  • the pixel unit of the display device includes the thin film transistor 200.
  • the driving circuit of the display device includes the thin film transistor 200.
  • the display device may include an array substrate, and thin film transistors of the pixel unit or thin film transistors (ie, GOAs) of the driving circuit are formed on the array substrate, and the thin film transistors may employ the thin film transistors of any of the embodiments of the present disclosure.
  • GOAs thin film transistors
  • FIG. 11 is a schematic block diagram of an electronic device 400 according to a seventh embodiment of the present disclosure
  • FIG. 12 is a pixel circuit of the electronic device of FIG.
  • the electronic device 400 is an organic light emitting diode display device.
  • the OLED display device includes a plurality of pixel units 401 arranged in an array, each of the pixel units including at least one organic light emitting diode and a pixel circuit connected to the organic light emitting diode, and the organic light emitting diode emits light under the driving of the pixel circuit.
  • Fig. 12 is a view showing a 2T1C pixel circuit of an organic light emitting diode display device.
  • the pixel circuit includes a switching transistor T1, a driving transistor T2, and a storage capacitor Cs.
  • the gate of the switching transistor T1 is connected to the gate line to receive a scan signal (Scan), for example, the source is connected to the data line to receive the data signal (Vdata), the drain is connected to the gate of the driving transistor T2; the source of the driving transistor T2 Connected to the first power terminal (Vdd, high voltage terminal), the drain is connected to the positive terminal of the OLED; one end of the storage capacitor Cs is connected to the drain of the switching transistor T1 and the gate of the driving transistor T2, and the other end is connected to the driving transistor T2
  • the source and the first power terminal; the cathode of the OLED is connected to the second power terminal (Vss, low voltage terminal), such as ground.
  • the driving mode of the 2T1C pixel circuit is to control the brightness and darkness (grayscale) of the pixel via the two TFTs and the storage capacitor Cs.
  • the scan signal Scan is applied through the gate line to turn on the switching transistor T1
  • the data voltage (Vdata) fed by the data driving circuit through the data line charges the storage capacitor Cs via the switching transistor T1, thereby storing the data voltage in the storage capacitor.
  • the stored data voltage controls the degree of conduction of the driving transistor T2, thereby controlling the magnitude of the current flowing through the driving transistor to drive the OLED to emit light, that is, the current determines the gray scale of the pixel illumination.
  • the switching transistor T1 and the driving transistor T2 can employ the thin film transistor 200 of the embodiment of the present disclosure.
  • the organic light emitting diode display device may further include a data driving circuit 6 and a gate driving circuit 7.
  • the data driving circuit 6 is for providing a data signal;
  • the gate driving circuit 7 is for providing a scanning signal (for example, the signal Vscan), and may further be used for providing various control signals.
  • the data driving circuit 6 is electrically connected to the pixel unit 8 through the data line 61, and the gate driving circuit 7 is electrically connected to the pixel unit 401 through the gate line 71.
  • the data driving circuit 6 and the gate driving circuit 7 each include a thin film transistor, and for example, a thin film transistor can employ the thin film transistor 200 of the embodiment of the present disclosure.
  • the display device is applied to any product or component having a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

Abstract

一种薄膜晶体管，包括基板、设置于所述基板(201)上的栅极(202)、栅极绝缘层(204)、有源层以及源极和漏极，所述有源层包括位于所述源极和所述漏极之间的沟道区(208)，所述沟道区(208)包括沿沟道长度方向的边缘区域(209)以及边缘区域(209)以外的主体区域(210)，所述薄膜晶体管还包括辅助层(203)，所述辅助层(203)与所述沟道区的边缘区域(209)在所述基板(201)上的投影至少部分重叠，所述辅助层(203)用于提高所述沟道区边缘区域(209)的导通电压。该薄膜晶体管设置辅助层(203)来提高沟道区边缘区域(209)的导通电压，从而改善薄膜晶体管的驼峰效应，提高薄膜晶体管的性能。

Description

薄膜晶体管、其制造方法及电子装置 技术领域
本公开的实施例涉及一种薄膜晶体管、其制造方法及电子装置。
背景技术
薄膜晶体管(Thin-film Transistor,TFT)是一些电子装置的重要元件，例如，薄膜晶体管是有源显示装置中像素电路的开关元件。薄膜晶体管的性能是影响电子装置的性能的重要因素。
发明内容
本公开的实施例提供一种薄膜晶体管，包括设置于基板上的栅极、栅极绝缘层、有源层以及源极和漏极，所述有源层包括位于所述源极和所述漏极之间的沟道区，所述沟道区包括沿沟道长度方向的边缘区域以及边缘区域以外的主体区域，所述薄膜晶体管还包括辅助层，所述辅助层与所述沟道区的边缘区域在所述基板上的投影至少部分重叠，所述辅助层用于提高所述沟道区边缘区域的导通电压。
本公开的实施例还提供一种电子装置，包括上述薄膜晶体管。
本公开的实施例还提供一种薄膜晶体管的制造方法，该方法包括：在基板上形成栅极、辅助层、栅极绝缘层、有源层、源极和漏极；所述有源层包括位于所述源极和所述漏极之间的沟道区，所述沟道区包括沿沟道长度方向的边缘区域以及边缘区域以外的主体区域；所述辅助层与所述沟道区的边缘区域在所述基板上的投影至少部分重叠，所述辅助层用于提高所述沟道区边缘区域的导通电压。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为液晶显示装置中阵列基板的子像素单元的结构示意图；图1B为图1A中薄膜晶体管沿剖面线A-A’的剖面结构示意图；图1C为1A中薄 膜晶体管沿剖面线B-B’的剖面结构示意图。
图2A为本公开第一实施例的薄膜晶体管的俯视结构示意图；图2B为图2A中薄膜晶体管沿剖面线C-C’的剖面结构示意图的一个示例；图2C为图2A中薄膜晶体管沿剖面线C-C’的剖面结构示意图的另一个示例。
图3为本公开第二实施例的薄膜晶体管的剖面结构示意图。
图4A为本公开第三实施例的薄膜晶体管的俯视结构示意图，图4B为图4A中薄膜晶体管沿剖面线D-D’的剖面结构示意图的一个示例，图4C为图4A中薄膜晶体管沿剖面线D-D’的剖面结构示意图的另一个示例。
图5为本公开第四实施例的薄膜晶体管的剖面结构示意图。
图6A-6D和图7为本公开第五实施例及其变更实施例的薄膜晶体管的制造方法的各步骤的剖面示意图。
图8-图10为本公开第六实施例及其变更实施例的薄膜晶体管的制造方法的各步骤的剖面示意图。
图11为本公开第七实施例的电子装置的示意图。
图12为第七实施例中电子装置的一种2T1C像素电路的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
薄膜晶体管是电子装置中重要的元件。图1A为液晶显示装置中阵列基板的子像素单元的结构示意图。阵列基板例如用于液晶显示装置，通常包括多条栅线101和多条数据线102，这些栅线101和数据线102彼此交叉由此限定了阵列排布的多个子像素单元(图1A中仅具体示出了一个子像素单元)，每个子像素单元包括薄膜晶体管110和用于控制液晶的排列的像素电极120。薄膜晶体管110作为开关元件，控制着数据线102与像素电极120 之间的信号传输。
图1B为图1A中薄膜晶体管110沿A-A剖面线的剖面结构示意图。请一并参阅图1A和图1B，薄膜晶体管110为底栅结构，包括依次层叠设置在基板上的栅极111、栅极绝缘层112、有源层113、源极114和漏极115。有源层113在靠近有源层113与栅极绝缘层112界面的区域具有一个沟道区116，沟道区116位于源极114和漏极115之间。以薄膜晶体管110为增强型晶体管为例，当栅极111上施加大于阈值电压Vth的偏压时，沟道区116内形成与有源层内掺杂浓度相同浓度的反型电荷。反型电荷在源极114和漏极115之间的电场作用下定向移动形成导通电流。本公开中的“导通电压”亦指阈值电压；沟道区116沿电流方向的方向为沟道长度方向，相应地该方向上的长度为沟道长度L，相应地与该长度方向垂直的方向为沟道宽度方向；本公开中的“沿沟道长度方向的边缘区域”指有源层沟道区沿该沟道长度方向延伸的侧边边缘所在的区域，例如，该边缘区域的延伸方向与该沟道区在沟道宽度方向上的中心线的延伸方向平行；例如，该边缘区域的延伸方向与沟道长度的方向平行。例如，该边缘区域的宽度可以小于等于沟道区域宽度的1/4，又例如可以小于等于沟道区宽度的1/6。
发明人发现，薄膜晶体管的有源层在边缘区域容易聚集电压而造成边缘部位相较于非边缘部位提前导通，产生驼峰效应。请一并参阅图1C，图1C为1A中薄膜晶体管110沿B-B’剖面线的剖面结构示意图，由于栅极电压容易聚集在沟道区116的边缘区域117，这造成边缘区域117相较于沟道区116非边缘的主体区域118提前产生反型电荷，从而在栅极电压还未达到薄膜晶体管110的阈值电压、沟道区116的主体区域118还未导通时，其边缘区域117提前形成了导通电流，产生了驼峰效应。驼峰效应极大地影响薄膜晶体管110的亚阈特性，造成薄膜晶体管性能不稳定。
本公开的实施例提供一种薄膜晶体管、其制造方法及电子装置。所述薄膜晶体管包括基板和设置于基板上的栅极、栅极绝缘层、有源层以及源极和漏极，该有源层包括位于源极和漏极之间的沟道区，沟道区包括沿沟道长度方向的边缘区域以及边缘区域以外的主体区域，所述薄膜晶体管还包括辅助层，辅助层与沟道区的边缘区域在基板上的投影至少部分重叠，辅助层用于提高所述沟道区边缘区域的导通电压。
根据本公开实施例的薄膜晶体管通过在对应沟道区的边缘区域设置辅助层，提高了沟道区的边缘区域的导通电压，使得薄膜晶体管的沟道区的边缘区域和主体区域几近同步形成导通电流，从而减弱或消除了薄膜晶体管的驼峰效应。
例如，可以通过调节对应沟道边缘区域的栅极材料与有源层材料间的功函数的关系来提高沟道区的边缘区域的导通电压。材料的功函数是指电子逸出该材料表面所需的最小能量。在薄膜晶体管的栅极、栅极绝缘层、有源层构成的金属-绝缘层-半导体(MIS,Metal-Insulator-Semiconductor)结构中，栅极材料和有源层材料间的功函数之差φms是影响所述薄膜晶体管的阈值电压的一个重要因素。例如，在不考虑栅极绝缘层中净电荷影响的情况下，栅极材料和有源层材料之间功函数的差异越大，薄膜晶体管的阈值电压越大。以下以所述薄膜晶体管为增强型晶体管(Vth大于0)，所述栅极材料和所述有源层材料间的功函数之差φms为正为例进行说明；但是本公开的实施例也可以适用于耗尽型晶体管(Vth小于0)、以及栅极材料和有源层材料间的功函数之差φms小于或等于0的晶体管，即本公开不限于晶体管的具体类型。
例如，可以将辅助层设置于栅极与有源层之间。
例如，辅助层的材料为导电材料并与栅极电连接，形成辅栅极。
例如，可以将该辅助层设置于栅极与栅极绝缘层之间，或者将辅助层与栅极同层设置。这里提到的“同层设置”是指辅助层与栅极形成在同一层结构(如栅极绝缘层)的同一表面上，并且可以由不同的材料形成。
例如，设置辅助层材料的功函数大于栅极材料的功函数，那么辅助层材料的功函数与有源层材料之间的功函数之差大于栅极材料和有源层材料间的功函数之差φms，从而提高了沟道区边缘区域的导通电压。
例如，栅极材料可以为如下金属材料之一或任意组合：铜、钼、钛、钨、铝，辅助层材料为如下金属材料之一或任意组合：铂、金、钯。
例如，栅极材料和辅助层材料可以为功函数可调节的导电材料，如导电硅或导电金属氧化物。例如，可以将辅助层设置于有源层与栅极绝缘层之间形成辅有源层，辅助层的材料为半导体材料，辅助层材料的功函数小 于有源层层材料的功函数，那么栅极材料的功函数与辅助层材料之间的功函数之差大于栅极材料和有源层材料间的功函数之差φms，从而提高了沟道区边缘区域的导通电压。
例如，有源层的材料可以为非晶硅、多晶硅、金属氧化物半导体等，多晶硅可以为高温多晶硅或低温多晶硅，该氧化物半导体例如可以为氧化锌、氧化铟锡(ITO)、氧化铟镓锌(IGZO)等。对于有源层还可以根据需要进行离子掺杂。
例如，辅助层可以包括间隔设置的两个辅助结构，分别对应沟道区的两个边缘区域设置，两个辅助结构之间间隔开预定距离，该间隔的部分对应于有源层的主体区域。
例如，薄膜晶体管可以为底栅型、顶栅型、顶栅底栅混合型等，在垂直于基板的方向上，栅极、辅助层、有源层三者在基板上的投影至少部分重叠。
例如，对于薄膜晶体管为底栅结构的情形，在辅助层与栅极同层设置的情形下，辅助层的厚度可以小于栅极厚度的十分之一。
下面将结合附图对本公开的一些具体实施例进行说明，以便对本公开更好理解。
第一实施例
图2A为本公开第一实施例的薄膜晶体管200的俯视结构示意图，图2B示出了图2A中薄膜晶体管200沿剖面线C-C’的剖视图的一个示例，图2C示出了图2A中薄膜晶体管200沿剖面线C-C’的剖视图的另一个示例。
请参一并参阅图2A和图2B，底栅结构的薄膜晶体管200包括依次层叠设置于基板201上的栅极202、辅助层203、栅极绝缘层204、有源层205、源极206和漏极207，有源层205包括位于源极206和漏极207之间的沟道区208，沟道区208包括沿沟道长度方向的边缘区域209以及除边缘区域209以外的主体区域210。辅助层203与沟道区208的边缘区域209在基板201上的投影至少部分重叠。辅助层203用于提高沟道区208的边缘区域209的导通电压。
例如，可以将辅助层设置于栅极与有源层之间。
例如，辅助层203对应于沟道区208的边缘区域209设置，栅极202、辅助层203和有源层205三者在基板201上的投影至少部分重叠。
例如，如图2B所示，辅助层203设置于栅极202和栅极绝缘层204之间。
例如，辅助层厚度小于栅极厚度的十分之一，如辅助层厚度为15-30nm，以免底栅结构中辅助层台阶影响有源层的成膜质量。
如图所示，辅助层203为间隔设置的两个辅栅极，两个辅栅极分别对应于沟道区208的两个边缘区域209设置。在另一个示例中，辅助层仅包括一个辅栅极，仅对应于沟道区的一个边缘区域。
这里，栅极202材料的功函数小于辅助层203材料的功函数。在本实施例中，栅极202的材料为钼(Mo)，其功函数为4.37eV；辅助层203的材料为铂(Pt)，其功函数为5.65eV，从而使得辅助层203材料的功函数与有源层205材料的功函数的差异大于栅极202材料的功函数与有源层205材料的功函数的差异，最终使得沟道区208的边缘区域209的导通电压大于其主体区域210的导通电压。
在其它示例中，也可以选择其它辅助层材料的功函数大于栅极材料功函数的组合，使得辅助层材料与有源层材料的功函数的差异大于栅极材料与有源层材料的功函数的差异。例如，栅极材料为如下金属材料之一或任意组合：铜(4.65eV)、钼(4.37eV)、钛(4.33eV)、钨(4.55eV)、铝(4.28eV)，辅助层材料为如下金属材料之一或任意组合：铂(5.65eV)、金(5.1eV)、钯(5.12eV)。
或者，栅极材料和辅助层材料还可以为功函数可调节的导电材料，如导电硅或导电金属氧化物。
例如，栅极材料和辅助层材料均为多晶硅，可以通过调节多晶硅的掺杂浓度，使得辅栅极材料的功函数大于栅极材料的功函数。类似地，例如，栅极材料和辅栅极材料均为铟锡氧化物ITO，可以通过调节ITO的组分使得辅栅极材料的功函数大于栅极材料的功函数。
图2C示出了图2A中薄膜晶体管200沿剖面线C-C’的剖视图的另一个示例。与图2B所示实施例中的薄膜晶体管不同的是，在本实施例中，辅 助层203与栅极202同层设置，也即辅助层203与栅极202设置于基板201的同一表面上。如图所示，辅助层203对应于沟道区208的边缘区域209设置，栅极202对应于沟道区208的主体区域210设置。例如，辅助层203与栅极202可以具有相同的厚度。
第二实施例
图3为本公开第二实施例的薄膜晶体管200的剖面结构示意图。请参阅图3，本公开第二实施例的薄膜晶体管与第一实施例的薄膜晶体管结构基本相同，其区别仅在于辅助层203的设置位置和材料不同。如图所示，辅助层203设置于有源层205和栅极绝缘层204之间。本实施例中，辅助层203为辅有源层，其材料为半导体材料。
如图所示，辅助层203为间隔设置的两个辅有源层，两个辅有源层分别对应于沟道区208的两个边缘区域209设置。在另一个示例中，辅助层仅包括一个辅有源层，仅对应于沟道区的一个边缘区域。
这里，有源层205材料的功函数大于辅助层203材料的功函数。在本实施例中，有源层材料和辅助层材料均为多晶硅，通过选择不同掺杂浓度的多晶硅，使得用于辅助层203的多晶硅材料的功函数小于用于有源层205的多晶硅材料的功函数，从而使得栅极202材料的功函数与辅助层203材料的功函数的差异大于栅极202材料的功函数与有源层205材料的功函数的差异，最终使得沟道区208边缘区域209的导通电压大于其主体区域210的导通电压。
在其它示例中，也可以选择其它有源层材料的功函数大于辅助层材料功函数的组合，使得栅极材料与辅助层材料的功函数的差异大于栅极材料与有源层材料的功函数的差异。
第三实施例
图4A为本公开第三实施例的薄膜晶体管200的俯视结构示意图，图4B为图4A中薄膜晶体管200沿D-D’剖面线的剖面结构示意图的一个示例，图4C为图4A中薄膜晶体管200沿D-D’剖面线的剖面结构示意图的另一个示例。为方便起见，相同的元件采用相同的编号，以下不再赘述。
请参一并参阅图4A和图4B，顶栅结构的薄膜晶体管200包括依次层叠 设置于基板201上的源极206和漏极207、有源层205、栅极绝缘层204、辅助层203及栅极202，有源层205包括靠近栅极绝缘层204的沟道区208，沟道区208包括沿沟道长度方向的边缘区域209以及边缘区域209以外的主体区域210。辅助层203与边缘区域209在基板201上的投影至少部分重叠。辅助层203用于提高沟道区208的边缘区域209的导通电压。
例如，可以将辅助层设置于栅极与有源层之间。
例如，辅助层203对应于沟道区208的边缘区域209设置，栅极202、辅助层203和有源层205三者在基板201上的投影至少部分重叠。
例如，如图4B所示，辅助层203设置于栅极202和栅极绝缘层204之间。
如图所示，辅助层203为间隔设置的两个辅栅极，两个辅栅极分别对应于沟道区208的两个边缘区域209设置。在另一个示例中，辅助层仅包括一个辅栅极，仅对应于沟道区的一个边缘区域。
栅极202材料的功函数小于辅助层203材料的功函数。在本实施例中，栅极202的材料为钼(Mo)，其功函数为4.37eV；辅助层203的材料为铂(Pt)，其功函数为5.65eV，从而使得辅助层203材料的功函数与有源层205材料的功函数的差异大于栅极202材料的功函数与有源层205材料的功函数的差异，最终使得沟道区208边缘区域209的导通电压大于其主体区域210的导通电压。
在其它示例中，也可以选择其它辅助层材料的功函数大于栅极材料功函数的组合，使得辅助层材料的功函数与有源层材料的功函数的差异大于栅极材料的功函数与有源层材料的功函数的差异。例如，栅极材料为如下金属材料之一或任意组合：铜(4.65eV)、钼(4.37eV)、钛(4.33eV)、钨(4.55eV)、铝(4.28eV)，辅助层材料为如下金属材料之一或任意组合：铂(5.65eV)、金(5.1eV)、钯(5.12eV)。
例如，栅极材料和辅助层材料还可以为功函数可调节的导电材料，如导电硅或导电金属氧化物。
例如，栅极材料和辅助层材料均为多晶硅，可以通过调节多晶硅的掺杂浓度，使得辅栅极材料的功函数大于栅极材料的功函数。类似地，例 如，栅极材料和辅栅极材料均为铟锡氧化物ITO，可以通过调节ITO的组分使得辅栅极材料的功函数大于栅极材料的功函数。
图4C示出了图4A中薄膜晶体管200沿剖面线C-C’的剖视图的另一个示例。与图4B所示实施例中的薄膜晶体管不同的是，在本实施例中，辅助层203与栅极202同层设置，也即辅助层203与栅极202设置于栅极绝缘层204的同一表面上。如图所示，辅助层203对应于沟道区208的边缘区域209设置，栅极202对应于沟道区208的主体区域210设置。例如，辅助层203与栅极202可以具有相同的厚度。
第四实施例
图5为本公开第四实施例的薄膜晶体管200的剖面结构示意图。本公开第四实施例的薄膜晶体管与第三实施例的薄膜晶体管结构基本相同，其区别仅在于辅助层203的设置位置和材料不同。请参阅图5，辅助层203设置于有源层205和栅极绝缘层204之间。本实施例中，辅助层203为辅有源层，其材料为半导体。
如图所示，辅助层203为间隔设置的两个辅有源层，两个辅有源层分别设置于沟道区208的两个边缘区域209上。在另一个示例中，辅助层仅包括一个辅有源层，仅对应于沟道区的一个边缘区域。
例如，有源层205材料的功函数大于辅助层203材料的功函数。在本实施例中，有源层材料和辅助层材料均为多晶硅，通过选择不同掺杂浓度的多晶硅，使得用于辅助层203的多晶硅材料的功函数小于用于有源层205的多晶硅材料的功函数，从而使得栅极202材料的功函数与辅助层203材料的功函数的差异大于栅极202材料的功函数与有源层205材料的功函数的差异，最终使得沟道区208边缘区域209的导通电压大于其主体区域210的导通电压。
在其它示例中，也可以选择其它有源层材料的功函数大于辅助层材料功函数的组合，使得栅极材料与辅助层材料的功函数的差异大于栅极材料与有源层材料的功函数的差异。
根据本实施例的薄膜晶体管，通过在栅极与有源层之间对应沟道区沿沟道长度方向的边缘区域设置辅助层来提高沟道区的边缘区域的导通电 压，使得薄膜晶体管的沟道区的边缘区域和主体区域几近同步形成导通电流，从而改善薄膜晶体管的驼峰效应，提高薄膜晶体管的性能。
第五实施例
此外，本公开的实施例还提供了一种薄膜晶体管的制造方法，可以用于制备如上所述实施例的薄膜晶体管。该方法至少包括：在基板上形成栅极、辅助层、栅极绝缘层、有源层、源极和漏极；辅助层形成在形成栅极和形成有源层之间，有源层包括位于源极和漏极之间的沟道区，沟道区包括沿沟道长度方向的边缘区域以及边缘区域以外的主体区域；辅助层与沟道区的边缘区域在基板上的投影至少部分重叠，辅助层用于提高沟道区边缘区域的导通电压。
例如，栅极和辅助层可以各自通过曝光工艺形成，或者可以通过灰色调掩模一次曝光形成。或者，例如，有源层和辅助层可以各自通过曝光工艺形成，或者可以通过灰色调掩模一次曝光形成。
例如，所述辅助层形成在所述栅极与所述有源层之间。
以下结合图6A-图6C以及图7对本公开第五实施例及其变更实施例的薄膜晶体管的制造方法进行描述。
步骤S61，形成栅极202。
如图6A所示，在基板201上形成第一导电层并利用第一构图工艺对第一导电层进行图案化处理形成栅极202。对此，提供基板201，然后对基板201进行清洗和干燥。基板100可以为可弯曲的柔性基板，例如，各种塑料膜，如聚对苯二甲酸乙二醇酯(PET)、聚醚砜(polyether sulfone，PES)、聚碳酸酯(Polycarbonate，PC)或聚酰亚胺(PI)及其衍生物等制成的基板。或者，基板100可以刚性基板，例如玻璃基板、不锈钢基板等。
步骤S62，形成辅助层203，辅助栅极203与栅极202形成为彼此电连接。
请继续参阅图6A，在栅极202上形成第二导电层并对第二导电层进行图案化处理形成辅助层203。辅助层203形成在栅极202沿将形成的薄膜晶体管沟道长度方向的边缘区域上。在本实施例中，辅助层203形成为间隔的两个辅栅极，两个辅栅极分别对应于沟道区208的两个边缘区域209。在另 一个示例中，辅助层仅包括一个辅栅极，仅对应于沟道区的一个边缘区域。辅助层厚度小于栅极厚度的十分之一，如辅助层厚度为15-30nm，以免底栅结构中辅助层台阶影响有源层的成膜质量。
选择第一导电层材料的功函数小于第二导电层，以使得栅极202材料的功函数小于辅助层203材料的功函数。在本实施例中，第一导电层的材料为钼(Mo)，其功函数为4.37eV；第二导电层的材料为铂(Pt)，其功函数为5.65eV，从而使得辅助层203材料与有源层材料的功函数的差异大于栅极202材料与有源层材料的功函数的差异。
在其它示例中，也可以选择其它第二导电层材料的功函数大于第一导电层材料功函数的组合。例如，第一导电层材料为如下金属材料之一或任意组合：铜(4.65eV)、钼(4.37eV)、钛(4.33eV)、钨(4.55eV)、铝(4.28eV)，第二导电层材料为如下金属材料之一或任意组合：铂(5.65eV)、金(5.1eV)、钯(5.12eV)。
例如，第一导电层材料和第二导电层材料还可以为功函数可调节的导电材料，如导电硅或导电金属氧化物。
例如，第一导电层材料和第二导电层材料均为多晶硅，可以通过调节多晶硅的掺杂浓度，使得第二导电层材料的功函数大于第一导电层材料的功函数。类似地，例如，第一导电层材料和第二导电层极材料均为铟锡氧化物ITO，可以通过调节ITO的组分使得第二导电层材料的功函数大于第一导电层材料的功函数。
在一变更实施例中，栅极202和辅助层203可通过一次曝光形成，例如，通过半色调掩膜一次曝光形成栅极202和辅助层203。请一并参阅图6B和6C，依次在基板201上形成第一导电层301和第二导电层302后，在第二导电层302上形成光阻层310，并使用半色调掩膜320对光阻层310进行曝光处理。如图6B所示，半色调掩膜320包括对称分布的透光率不同的三个区域A、B和C。其中，区域A为全透光区，区域B为不透光区，区域C为部分透光区。光阻层310经过曝光显影后，形成如图6B所示的图案，通过第一刻蚀步骤除去第一导电层301和第二导电层302未被光阻层310覆盖的区域(未示出)，然后对光阻层310进行处理形成图6B中虚线所示的图 案，接着通过第二刻蚀步骤形成图6C所示的栅极202和辅助层203。
在另一实施例中，如图6D所示，辅助层203与栅极202可以形成于同一层，也即，辅助层203与栅极202形成于基板201的同一表面上。例如可以通过进行两次导电材料的沉积与构图工艺分别形成该栅极202与辅助层203，这里不再赘述。例如，辅助层203与栅极202的厚度相同。
步骤S63，形成栅绝缘层204以及有源层205。
如图7所示，在辅助层203上形成栅极绝缘层204，接着在栅极绝缘层204上形成半导体层，并利用第三构图工艺对半导体层进行图案化形成有源层205。有源层205包括靠近栅极绝缘层204的沟道区208，沟道区208包括沿沟道长度方向的相对的两个边缘区域209以及边缘区域209以外的主体区域210。两个边缘区域209与辅助层203对应，即两个边缘区域209分别对应两个辅栅极，两个边缘区域209与各自对应的辅栅极在基板201上的投影均至少部分重叠。
这里，栅极202、辅助层203与有源层205三者在基板201上的投影至少部分重叠。
步骤S64，形成源极和漏极(未示出)。
在有源层205上形成第三导电层，并通过第四构图工艺对第三导电层进行图案化形成源极206和漏极207。该第三导电层例如可以选择钼、钛、铝、铜及其合金等材料。
如此，形成了本公开第一实施例中的薄膜晶体管200。
在一个变更实施例中，形成辅助层203的步骤发生于形成栅极绝缘层204之后、形成有源层205之前。在这个实施例中，辅助层203的材料为半导体材料，辅助层203为辅有源层。辅有源层的数目为两个，两个辅有源层分别对应于沟道区208的两个边缘区域209设置。并且使得辅助层203材料的功函数小于有源层203材料的功函数，以提高沟道区边缘区域209的导通电压。如此便形成本公开第二实施例的薄膜晶体管200。
例如，有源层材料和辅助层材料均为多晶硅，通过选择不同掺杂浓度的多晶硅，使得用于辅助层的多晶硅材料的功函数小于用于有源层的多晶硅材料的功函数，从而使得栅极材料的功函数与辅助层材料的功函数的差 异大于栅极材料的功函数与有源层材料的功函数的差异，最终使得沟道区208边缘区域209的导通电压大于其主体区域210的导通电压。
在其它示例中，也可以选择其它有源层材料的功函数大于辅助层材料功函数的组合，使得栅极材料的功函数与辅助层材料的功函数的差异大于栅极材料的功函数与有源层材料的功函数的差异。
例如，在制备用于例如液晶显示装置、有机发光二极管显示装置等的阵列基板的情形，还可以在形成该薄膜晶体管的同时形成存储电容、形成像素电极等部件。
第六实施例
以下结合图8-图9对本公开第六实施例及其变更实施例的薄膜晶体管的制造方法进行描述。
步骤S81，形成有源层205。
提供基板201，对基板201进行清洗和干燥。基板100可以为可弯曲的柔性基板，例如，各种塑料膜，如聚对苯二甲酸乙二醇酯(PET)、聚醚砜(polyether sulfone，PES)、聚碳酸酯(Polycarbonate，PC)或聚酰亚胺(PI)及其衍生物等制成的基板。或者，基板100可以刚性基板，例如，玻璃基板、不锈钢基板等。
如图8所示，在基板201上形成第一半导体层并利用第一构图工艺对第一半导体层进行图案化处理形成有源层205。有源层205包括远离基板201的沟道区208，沟道区208包括沿沟道长度方向的相对的两个边缘区域209以及边缘区域209以外的主体区域210。
如果需要，还可以在基板201和有源层205之间形成缓冲层。该缓冲层可以防止例如基板中的杂质扩散到有源层中从而影响有源层的性能。
步骤S82，形成辅助层203。
如图9所示，在有源层205上形成第二半导体层并对第二半导体层进行图案化处理形成辅助层203。辅助层203形成在有源层205的边缘区域209上。使得第一半导体层与对已半导体层材料的功函数具有特定关系，以提高沟道区边缘区域209的导通电压。
如图所示，辅助层203为两个间隔设置的辅有源层，分别设置于有源层205的两个边缘区域209上。在另一个示例中，辅助层仅包括一个辅有源层，仅对应于沟道区的一个边缘区域。
这里，第一半导体层和第二半导体层的材料均为多晶硅，通过选择不同掺杂浓度的多晶硅，使得第二半导体材料的多晶硅材料的功函数小于第一半导体材料的多晶硅材料的功函数，从而使得辅助层材料的功函数小于有源层材料的功函数。
在其它示例中，也可以选择其它有源层材料的功函数大于辅助层材料功函数的组合。
在一变更实施例中，有源层205和辅助层203可通过一次曝光形成，例如，通过半色调掩膜一次曝光形成有源层205和辅助层203。具体方法类似于第五实施例中一次曝光形成栅极202和辅助层203的步骤，这里不再赘述。
步骤S83，形成栅绝缘层以及栅极、源极和漏极。
如图10所示，在辅助层203上形成栅极绝缘层204，接着在栅极绝缘层204上形成导电层，并利用第三构图工艺对导电层进行图案化形成形成栅极202、源极和漏极(未示出)。如此便形成本公开第四实施例的薄膜晶体管200。
如图所示，栅极202、辅助层203与有源层205三者在基板201上的投影至少部分重叠。
在本实施例中，通过选择选择第一半导体材料的功函数大于第二半导体材料的功函数，以使得辅助层材料的功函数小于有源层材料的功函数，从而使得栅极材料与辅助层材料的功函数的差异大于栅极材料与有源层材料的功函数的差异，最终使得沟道区208边缘区域209的导通电压大于主体区域210的导通电压。
在一个变更实施例中，形成辅助层203的步骤发生于形成栅极绝缘层204之后、形成栅极202之前或者形成栅极202之后。在这个实施例中，辅助层203的材料为导电材料，辅助层203为辅栅极。辅栅极的数目为两个，两个辅栅极分别对应于沟道区208的两个边缘区域209设置，两个辅栅极与 各自对应的边缘区域209在基板201上的投影均至少部分重叠。并且使得辅助层203材料的功函数大于栅极202材料的功函数，以提高沟道区边缘区域209的导通电压。
例如，辅助层203形成于栅极202与栅极绝缘层204之间，如此便形成图4B所示的薄膜晶体管200。
例如，辅助层203与栅极202形成于同一层，也即辅助层203与栅极202形成于栅极绝缘层204的同一表面上。这样就形成了如图4C所示的薄膜晶体管200。例如可以通过进行两次导电材料的沉积与构图工艺分别形成该栅极202与辅助层203，这里不再赘述。例如，辅助层203与栅极202的厚度相同。
例如，栅极的材料为钼(Mo)，其功函数为4.37eV；辅助层的材料为铂(Pt)，其功函数为5.65eV，从而使得辅助层203材料的功函数与有源层材料的功函数的差异大于栅极202材料的功函数与有源层材料的功函数的差异。
在其它示例中，也可以选择其它辅助层材料的功函数大于栅极材料功函数的组合。例如，栅极材料为如下金属材料之一或任意组合：铜(4.65eV)、钼(4.37eV)、钛(4.33eV)、钨(4.55eV)、铝(4.28eV)，辅助层材料为如下金属材料之一或任意组合：铂(5.65eV)、金(5.1eV)、钯(5.12eV)。
例如，栅极材料和辅助层材料还可以为功函数可调节的导电材料，如导电硅或导电金属氧化物。
例如，栅极材料和辅助层材料均为多晶硅，可以通过调节多晶硅的掺杂浓度，使得辅助层材料的功函数大于栅极材料的功函数。类似地，例如，栅极材料和辅助层材料均为铟锡氧化物ITO，可以通过调节ITO的组分使得第辅助层材料的功函数大于栅极材料的功函数。
例如，在制备用于例如液晶显示装置、有机发光二极管显示装置等的阵列基板的情形，还可以在形成该薄膜晶体管的同时形成存储电容、形成像素电极等部件。
根据本公开实施例提供的薄膜晶体管的制造方法，通过在薄膜晶体管 中设置辅助层，并对材料的功函数进行选择，使得有源层沟道区的边缘区域对应的金属-半导体的功函数差大于沟道区的主体区域对应的金属-半导体的功函数差，从而提高沟道区的边缘区域的导通电压，使得薄膜晶体管的沟道区的边缘区域和主体区域几近同步形成导通电流，从而改善薄膜晶体管的驼峰效应，提高薄膜晶体管的性能。
第七实施例
本公开的实施例还提供一种电子装置，该电子装置包括本公开任一实施例的薄膜晶体管200。例如，该电子装置为显示装置，可以为液晶显示装置、有机发光二极管显示装置或电子纸显示装置等。例如，显示装置的像素单元包括薄膜晶体管200。或者，例如，显示装置的驱动电路包括薄膜晶体管200。
该显示装置可以包括阵列基板，上述像素单元的薄膜晶体管或驱动电路的薄膜晶体管(即GOA)形成在阵列基板上，这些薄膜晶体管可以采用本公开任一实施例的薄膜晶体管。
图11为本公开第七实施例提供的电子装置400的示意性框图，图12为图11中电子装置的像素电路。请一并参阅图11和图12，电子装置400为有机发光二极管显示装置。有机发光二极管显示装置包括阵列排布的多个像素单元401，每个像素单元包括至少一个有机发光二极管及与有机发光二极管连接的像素电路，有机发光二极管在像素电路的驱动下发光。
图12示出了有机发光二极管显示装置的一种2T1C像素电路的示意图。像素电路包括开关晶体管T1、驱动晶体管T2以及存储电容Cs。开关晶体管T1的栅极连接栅极线以接收扫描信号(Scan)，例如源极连接到数据线以接收数据信号(Vdata)，漏极连接到驱动晶体管T2的栅极；驱动晶体管T2的源极连接到第一电源端(Vdd，高压端)，漏极连接到OLED的正极端；存储电容Cs的一端连接到开关晶体管T1的漏极以及驱动晶体管T2的栅极，另一端连接到驱动晶体管T2的源极以及第一电源端；OLED的负极连接到第二电源端(Vss，低压端)，例如接地。2T1C像素电路的驱动方式是将像素的明暗(灰阶)经由两个TFT和存储电容Cs来控制。当通过栅极线施加扫描信号Scan以开启开关晶体管T1时，数据驱动电路通过数据线送入 的数据电压(Vdata)将经由开关晶体管T1对存储电容Cs充电，由此将数据电压存储在存储电容Cs中，且此存储的数据电压控制驱动晶体管T2的导通程度，由此控制流过驱动晶体管以驱动OLED发光的电流大小，即此电流决定像素发光的灰阶。在图12所示的2T1C像素电路中，例如开关晶体管T1以及驱动晶体管T2均可以采用本公开实施例的薄膜晶体管200。
如图11所示，有机发光二极管显示装置还可以包括数据驱动电路6和栅极驱动电路7。数据驱动电路6用于提供数据信号；栅极驱动电路7用于提供扫描信号(例如信号Vscan)，还可以进一步用于提供各种控制信号。数据驱动电路6通过数据线61与像素单元8电连接，栅极驱动电路7通过栅线71与像素单元401电连接。数据驱动电路6和栅极驱动电路7均包括薄膜晶体管，例如薄膜晶体管均可以采用本公开实施例的薄膜晶体管200。
例如，该显示装置应用于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2017年9月15日递交的中国专利申请第201710835326.X号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (24)

  1. 一种薄膜晶体管，包括基板、设置于所述基板上的栅极、栅极绝缘层、有源层以及源极和漏极，所述有源层包括位于所述源极和所述漏极之间的沟道区，所述沟道区包括沿沟道长度方向的边缘区域以及边缘区域以外的主体区域，
    其中，所述薄膜晶体管还包括辅助层，所述辅助层与所述沟道区的边缘区域在所述基板上的投影至少部分重叠，所述辅助层用于提高所述沟道区边缘区域的导通电压。
  2. 如权利要求1所述的薄膜晶体管，其中，所述辅助层位于所述栅极与所述有源层之间。
  3. 如权利要求1或2所述的薄膜晶体管，其中，所述辅助层包括间隔设置的两个辅助结构，分别对应所述沟道区沿长度方向相对的两个边缘区域设置。
  4. 如权利要求1或2所述的薄膜晶体管，其中，所述栅极、所述辅助层与所述有源层三者在所述基板上的投影至少部分重叠。
  5. 如权利要求1或2所述的薄膜晶体管，其中，所述辅助层材料为导电材料，且位于所述栅极与所述栅极绝缘层之间，并与所述栅极电连接。
  6. 如权利要求1所述的薄膜晶体管，其中，所述辅助层与所述栅极同层设置，并与所述栅极电连接。
  7. 如权利要求5或6所述的薄膜晶体管，其中，所述辅助层材料的功函数与所述有源层材料的功函数的差异大于所述栅极材料的功函数与所述有源层材料的功函数的差异。
  8. 如权利要求5-7任一所述的薄膜晶体管，其中，所述辅助层材料的功函数大于所述栅极材料的功函数。
  9. 如权利要求1-8任一所述的薄膜晶体管，其中，所述栅极材料为铜、钼、钛、铝、导电硅或导电金属氧化物，所述辅助层材料为铂、金或钯、硅或导电金属氧化物。
  10. 如权利要求5所述的薄膜晶体管，其中，所述薄膜晶体管为底栅结构；所述辅助层的厚度小于所述栅极厚度的十分之一。
  11. 如权利要求1或2所述的薄膜晶体管，其中，所述辅助层材料为 半导体，且位于所述有源层与所述栅极绝缘层之间。
  12. 如权利要求10所述的薄膜晶体管，其中，所述栅极材料的功函数与所述辅助层材料的功函数的差异大于所述栅极材料的功函数与所述有源层材料的功函数的差异。
  13. 如权利要求11所述的薄膜晶体管，其中，所述辅助层材料的功函数小于所述有源层材料的功函数。
  14. 一种电子装置，包括如权利要求1-13任意一项所述的薄膜晶体管。
  15. 如权利要求14所述的电子装置，其中，所述电子装置为液晶显示装置、有机发光二极管显示装置或电子纸显示装置。
  16. 一种薄膜晶体管的制造方法，包括：
    在基板上形成栅极、辅助层、栅极绝缘层、有源层、源极和漏极；
    其中，所述有源层包括位于所述源极和所述漏极之间的沟道区，所述沟道区包括沿沟道长度方向的边缘区域以及边缘区域以外的主体区域；
    所述辅助层与所述沟道区的边缘区域在所述基板上的投影至少部分重叠，所述辅助层用于提高所述沟道区边缘区域的导通电压。
  17. 如权利要求16所述的薄膜晶体管的制造方法，其中，所述辅助层形成在所述栅极与所述有源层之间。
  18. 如权利要求16或17所述的薄膜晶体管的制造方法，其中，所述辅助层形成在所述栅极和所述栅极绝缘层之间，所述辅助层材料为导电材料且与所述栅极形成为彼此电连接。
  19. 如权利要求16所述的薄膜晶体管的制造方法，其中，所述辅助层与所述栅极形成于同一层，所述辅助层材料为导电材料且与所述栅极形成为彼此电连接。
  20. 如权利要求18或19所述的薄膜晶体管的制造方法，其中，所述辅助层材料的功函数与所述有源层材料的功函数的差异大于所述栅极材料的功函数与所述有源层材料的功函数的差异。
  21. 如权利要求18-20任一所述的薄膜晶体管的制造方法，其中，所述辅助层材料的功函数大于所述栅极材料的功函数。
  22. 如权利要求16或17所述的薄膜晶体管的制造方法，其中，所述辅 助层形成在所述有源层和所述栅极绝缘层之间，所述辅助层材料为半导体材料。
  23. 如权利要求22所述的薄膜晶体管的制造方法，其中，所述栅极材料的功函数与所述辅助层材料的功函数的差异大于所述栅极材料的功函数与所述有源层材料的功函数的差异。
  24. 如权利要求22或23所述的薄膜晶体管的制造方法，其中，所述辅助层材料的功函数小于所述有源层材料的功函数。
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