WO2019049448A1 - 表示装置の製造方法及び多面取り基板 - Google Patents

表示装置の製造方法及び多面取り基板 Download PDF

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Publication number
WO2019049448A1
WO2019049448A1 PCT/JP2018/021988 JP2018021988W WO2019049448A1 WO 2019049448 A1 WO2019049448 A1 WO 2019049448A1 JP 2018021988 W JP2018021988 W JP 2018021988W WO 2019049448 A1 WO2019049448 A1 WO 2019049448A1
Authority
WO
WIPO (PCT)
Prior art keywords
product
light emitting
pads
current
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2018/021988
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
哲生 森田
木村　裕之
誠 渋沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Display Inc
Original Assignee
Japan Display Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Display Inc filed Critical Japan Display Inc
Priority to CN201880051690.XA priority Critical patent/CN111033600B/zh
Publication of WO2019049448A1 publication Critical patent/WO2019049448A1/ja
Priority to US16/781,009 priority patent/US11322571B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/70—Testing, e.g. accelerated lifetime tests
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/02—Details
    • H05B33/06—Electrode terminals
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/10—Apparatus or processes specially adapted to the manufacture of electroluminescent light sources
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/12—Light sources with substantially two-dimensional [2D] radiating surfaces
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/273—Interconnections for measuring or testing, e.g. probe pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/851—Division of substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/861—Repairing

Definitions

  • the present invention relates to a method of manufacturing a display device and a multi-faceted substrate.
  • Patent Document 1 It is known to integrally manufacture a plurality of display panels using a multi-chamfered substrate and then cutting out the individual display panels.
  • Patent Document 1 cell inspection is performed before cutting into individual display panels.
  • An inspection pad for cell inspection was arranged in the peripheral area outside the display area for each display panel.
  • the peripheral area tends to be narrowed in order to widen the display area, and there is no space for arranging the inspection pad in the peripheral area. Therefore, in the multi-chamfered substrate, the inspection pads are often arranged outside the product area.
  • the wiring becomes long if the inspection pad for supplying the current is outside the product area.
  • the wire may be thinned at the intersection with the cutting line so that the cutting can be easily performed. Therefore, the voltage drop can not perform accurate inspection, and the heat generation affects the light emitting element.
  • the present invention aims to efficiently arrange the test pad in a confined space.
  • a method of manufacturing a display device includes a plurality of product regions integrally provided with a plurality of product regions respectively provided with light emitting elements driven by current, and a blank region adjacent to each of the plurality of product regions.
  • a step of preparing a chamfered substrate, a step of feeding the current through the cathode pad and the anode pad to inspect the light emitting element, and a plurality of display panels respectively corresponding to the plurality of product regions from the multiple chamfered substrate Cutting out the plurality of first inspection pads disposed in each of the plurality of product areas to inspect the light emitting device; and the plurality of chamfered substrates to inspect the light emitting device.
  • a plurality of second test pads disposed in the margin area, wherein the cathode pad and the anode pad are included in the plurality of first test pads, and the plurality of second tests are included. Characterized in that it not be included in the head.
  • arranging the cathode pad and the anode pad for current flow in the product area enables efficient arrangement of the inspection pad in a restricted space.
  • the multi-chamfered substrate according to the present invention is a light emitting element provided so as to be driven by a current in each of a plurality of product areas to be cut out into a plurality of display panels, and the above-mentioned light emitting element for inspection.
  • the plurality of first test pads may include a cathode pad and an anode pad for passing the current, and the plurality of second test pads may not include a pad for passing the current.
  • arranging the cathode pad and the anode pad for current flow in the product area enables efficient arrangement of the inspection pad in a restricted space.
  • FIG. 1 is a plan view of a multiple substrate according to an embodiment of the present invention.
  • FIG. 2 is an enlarged view of a cross section taken along line II-II of the multi-faceted substrate shown in FIG. It is a figure which shows the circuit of a product area
  • FIG. 1 is a plan view of a multi-faceted substrate according to an embodiment of the present invention.
  • the multi-chamfered substrate 10 has a plurality of product areas P.
  • the product area P is an area to be cut out to the display panel.
  • the display panel is an organic electroluminescence panel, and for example, unit pixels (sub-pixels) of plural colors of red, green and blue are combined to form a full-color pixel (pixel), and a full-color image is displayed in the display area DA. It is supposed to be displayed on.
  • the multi-chamfered substrate 10 has a blank area M adjacent to each of the plurality of product areas P.
  • FIG. 2 is an enlarged view of a cross section taken along line II-II of the substrate 10 shown in FIG.
  • the multi-chamfered substrate 10 has a substrate 12.
  • An undercoat layer 14 serving as a barrier to impurities is formed on the substrate 12, and a semiconductor layer 16 is formed thereon.
  • the source electrode 18 and the drain electrode 20 are electrically connected to the semiconductor layer 16, and the gate insulating film 22 is formed to cover the semiconductor layer 16.
  • a gate electrode 24 is formed on the gate insulating film 22, and an interlayer insulating film 26 is formed to cover the gate electrode 24.
  • the source electrode 18 and the drain electrode 20 penetrate the gate insulating film 22 and the interlayer insulating film 26.
  • the semiconductor layer 16, the source electrode 18, the drain electrode 20 and the gate electrode 24 constitute at least a part of the thin film transistor TFT.
  • a passivation film 28 is provided to cover the thin film transistor TFT.
  • a planarization layer 30 is provided on the passivation film 28.
  • a plurality of pixel electrodes 32 eg, anodes
  • the planarization layer 30 is formed such that at least the surface on which the pixel electrode 32 is provided is flat.
  • the pixel electrode 32 is electrically connected to one of the source electrode 18 and the drain electrode 20 on the semiconductor layer 16 by a contact hole 34 penetrating the planarization layer 30 and the passivation film 28.
  • An insulating layer 36 is formed on the planarization layer 30 and the pixel electrode 32.
  • the insulating layer 36 is formed on the peripheral portion of the pixel electrode 32 so as to open a part (for example, the central portion) of the pixel electrode 32.
  • the insulating layer 36 forms a bank surrounding a part of the pixel electrode 32.
  • the pixel electrode 32 is a part of the light emitting element 38.
  • the light emitting element 38 includes an opposing electrode 40 (for example, a cathode) facing the plurality of pixel electrodes 32 and an organic electroluminescent layer 42.
  • the organic electroluminescent layer 42 includes a light emitting layer EML.
  • the light emitting layer EML is provided separately (separately) for each of the pixel electrodes 32 and is also placed on the insulating layer 36.
  • the light emitting layer EML emits light in blue, red or green corresponding to each pixel.
  • the color corresponding to each pixel is not limited to this, and may be yellow or white, for example.
  • the light emitting layer EML is formed, for example, by vapor deposition.
  • the light emitting layer EML may be formed on the entire surface covering the display area DA shown in FIG. 1 so as to extend over a plurality of pixels. That is, the light emitting layer EML may be formed on the insulating layer 36 so as to be continuous.
  • the light emitting layer EML is formed by application by solvent dispersion.
  • the light emitting layer EML is formed to extend over a plurality of pixels, light emission is performed in white in all sub-pixels, and a desired color wavelength portion is extracted through a color filter (not shown).
  • a hole injecting and transporting layer HITL made of at least one of a hole injecting layer and a hole transporting layer is interposed.
  • the hole injection transport layer HITL may be provided separately for each pixel electrode 32, but in the example of FIG. 2, it is continuous throughout the display area DA (see FIG. 1).
  • the hole injection transport layer HITL is in contact with the pixel electrode 32 and the insulating layer 36.
  • an electron injecting and transporting layer EITL formed of at least one of the electron injecting layer and the electron transporting layer is interposed.
  • the electron injecting and transporting layer EITL may be provided separately for each pixel electrode 32, but in the example of FIG. 2, it is continuous over the entire display area DA.
  • the electron injection transport layer EITL is in contact with the counter electrode 40.
  • the light emitting layer EML is sandwiched between the pixel electrode 32 and the counter electrode 40, and the luminance is controlled by the current flowing between the two to emit light.
  • a light emitting element 38 is provided so as to be driven by current.
  • the counter electrode 40 is made of a metal thin film or the like and has light transparency, and transmits light generated in the light emitting layer EML to display an image.
  • the pixel electrode 32 may be a reflective film that reflects light generated in the light emitting layer EML in the direction of the counter electrode 40, and one of the plurality of layers may be a reflective film.
  • the organic electroluminescent layer 42 is sealed by the sealing film 44 and blocked from moisture.
  • the sealing film 44 may include an inorganic layer made of an inorganic layer material such as silicon nitride, and the pair of inorganic layers may sandwich the organic layer.
  • the opposing substrate 48 is attached to the sealing film 44 via the adhesive layer 46.
  • FIG. 3 is a diagram showing a circuit of the product area P.
  • a plurality of light emitting elements 38 for generating an image are driven for each scanning line 50 by a line sequential scanning method.
  • a plurality of scan lines 50 are drawn from the scan circuit 52.
  • a power supply line 54 (a cathode line and an anode line) for supplying a current is connected to the light emitting element 38.
  • a signal line 56 is connected to the light emitting element 38 in order to input an image signal for controlling a current.
  • a signal line selection circuit 58 for selecting one of the plurality of signal lines 56 is provided, and a cell inspection circuit 60 for inspecting all the light emitting elements 38 at one time is provided.
  • a plurality of product pads 62 are arranged.
  • the product pad 62 is used in the cut out display panel.
  • the plurality of product pads 62 include pads for supplying power to the scanning circuit 52, pads for inputting control signals to the scanning circuit 52, pads for inputting control signals to the signal line selection circuit 58, and the like.
  • the plurality of product pads 62 include power supply pads 64 (product cathode pads and product anode pads) connected to power supply lines 54 for supplying current to the light emitting elements 38.
  • a plurality of first inspection pads 66 are disposed to inspect the light emitting elements 38.
  • the plurality of first test pads 66 include a cathode pad 68 and an anode pad 70 for supplying a current to the light emitting device 38.
  • the cathode pad 68 and the anode pad 70 are connected to the power supply pad 64 (product cathode pad and product anode pad), respectively.
  • the plurality of first test pads 66 are closer to the plurality of light emitting elements 38 than the plurality of product pads 62.
  • a plurality of second inspection pads 72 are arranged corresponding to the respective product areas P in order to inspect the light emitting elements 38.
  • the plurality of second test pads 72 are a pad for supplying power to the scanning circuit 52, a pad for inputting a control signal to the scanning circuit 52, a pad for inputting a control signal to the signal line selection circuit 58, and a cell It includes a pad and the like for inputting a control signal to inspection circuit 60.
  • the plurality of second test pads 72 do not include pads for flowing current for causing the light emitting element 38 to emit light.
  • the inspection pad can be efficiently arranged in the restricted space. become.
  • FIG. 1 A current is supplied through the cathode pad 68 and the anode pad 70 to inspect the light emitting element 38. Then, a plurality of display panels are cut out from the multiple substrate 10 so as to correspond to the plurality of product areas P, respectively.
  • the wires 74 connected to the plurality of second test pads 72 have narrow portions 74 a narrowed on the cutting lines so as to be easily cut (see FIG. 1).
  • FIG. 4 is a diagram showing a circuit of a product area P according to a modification of the embodiment of the present invention.
  • the cathode pad 168 and the anode pad 170 are used not only for testing the light emitting element 138 but also for products. That is, the cathode pad 168 and the anode pad 170 are also used to supply current to the light emitting element 138 in each of the plurality of display panels cut out.
  • a plurality of product pads 162 for use in each of the plurality of display panels cut out for applications other than flowing current to the light emitting element 138 are disposed.
  • the cathode pad 168 and the anode pad 170 have a large area, or the distance between adjacent pads is wide. This makes it easier to apply a test probe to the cathode pad 168 and the anode pad 170.
  • the method for manufacturing a display device according to the present embodiment corresponds to the obvious contents from the above description of the structure and the contents described in the above embodiment.
  • the display device is not limited to the organic electroluminescence display device, and may be a display device provided with a light emitting element such as a quantum dot light emitting element (QLED: Quantum-Dot Light Emitting Diode) in each pixel.
  • a light emitting element such as a quantum dot light emitting element (QLED: Quantum-Dot Light Emitting Diode) in each pixel.
  • QLED Quantum-Dot Light Emitting Diode
  • the present invention is not limited to the above-described embodiment, and various modifications are possible.
  • the configurations described in the embodiments can be replaced with configurations that have substantially the same configuration, configurations having the same effects, or configurations that can achieve the same purpose.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
PCT/JP2018/021988 2017-09-07 2018-06-08 表示装置の製造方法及び多面取り基板 Ceased WO2019049448A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201880051690.XA CN111033600B (zh) 2017-09-07 2018-06-08 显示装置的制造方法及拼版基板
US16/781,009 US11322571B2 (en) 2017-09-07 2020-02-04 Display apparatus including negative electrode pads and positive electrode pads that are included in first inspection pads but not in second inspection pads

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017171933A JP7001398B2 (ja) 2017-09-07 2017-09-07 表示装置の製造方法及び多面取り基板
JP2017-171933 2017-09-07

Related Child Applications (1)

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US16/781,009 Continuation US11322571B2 (en) 2017-09-07 2020-02-04 Display apparatus including negative electrode pads and positive electrode pads that are included in first inspection pads but not in second inspection pads

Publications (1)

Publication Number Publication Date
WO2019049448A1 true WO2019049448A1 (ja) 2019-03-14

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US (1) US11322571B2 (https=)
JP (1) JP7001398B2 (https=)
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WO (1) WO2019049448A1 (https=)

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CN111933066A (zh) * 2020-08-28 2020-11-13 京东方科技集团股份有限公司 Oled显示基板、显示模组、显示面板
JP7684851B2 (ja) * 2021-06-29 2025-05-28 株式会社ジャパンディスプレイ 表示装置
CN115692424B (zh) * 2021-07-30 2025-06-20 北京京东方光电科技有限公司 显示面板以及显示面板母板
CN113809134B (zh) * 2021-08-26 2024-06-28 湖北长江新型显示产业创新中心有限公司 一种显示面板及显示装置
CN114023914A (zh) * 2021-12-07 2022-02-08 南京迪钛飞光电科技有限公司 一种有机发光器件测试装置

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JP2011134489A (ja) * 2009-12-22 2011-07-07 Hitachi High-Technologies Corp 有機ｅｌディスプレイ基板の点灯検査設備及び点灯検査方法、有機ｅｌディスプレイ基板の欠陥検査修正装置及び欠陥検査修正方法並びに有機ｅｌディスプレイ製造システム及び製造方法。
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US11322571B2 (en) 2022-05-03
CN111033600A (zh) 2020-04-17
JP7001398B2 (ja) 2022-01-19
US20200176546A1 (en) 2020-06-04
CN111033600B (zh) 2021-11-30
JP2019045823A (ja) 2019-03-22

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