WO2019041674A1 - 移动终端及其芯片封装结构 - Google Patents

移动终端及其芯片封装结构 Download PDF

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Publication number
WO2019041674A1
WO2019041674A1 PCT/CN2017/117756 CN2017117756W WO2019041674A1 WO 2019041674 A1 WO2019041674 A1 WO 2019041674A1 CN 2017117756 W CN2017117756 W CN 2017117756W WO 2019041674 A1 WO2019041674 A1 WO 2019041674A1
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Prior art keywords
chip
substrate
ball
grid array
ball grid
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PCT/CN2017/117756
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English (en)
French (fr)
Inventor
吴方
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深圳市江波龙电子有限公司
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Publication of WO2019041674A1 publication Critical patent/WO2019041674A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present application belongs to the field of chip packaging technologies, and in particular, to a mobile terminal and a chip package structure thereof.
  • the purpose of the present application is to provide a chip package structure, which aims to solve the technical problem that the prior art chip for a special ball position needs to redesign a suitable printed circuit board, which cannot quickly adapt to market demands and affect chip performance.
  • a chip package structure including a substrate, a chip, and an encapsulant, wherein the substrate includes upper and lower surfaces disposed opposite to each other, and a lower surface of the substrate is provided with a ball a gate array, the chip is disposed on an upper surface of the substrate and electrically connected to the ball grid array through the substrate, the encapsulant is coated on the chip and the chip package is fixed on the chip The upper surface of the substrate.
  • the chip is a DRAM chip.
  • the DRAM chip is a 366 ball LPDDR4 chip
  • the ball grid array is a 200 ball ball grid array.
  • the DRAM chip is a 426 ball LPDDR3 chip
  • the ball grid array is a 168 ball ball grid array.
  • the DRAM chip is a 426 ball LPDDR3 chip
  • the ball grid array is a 178 ball ball grid array.
  • the DRAM chip is a 456 ball LPDDR3 chip
  • the ball grid array is a 168 ball ball grid array.
  • the ball grid array comprises a plurality of spheres, each of which is soldered to a lower surface of the substrate.
  • the side end surface of the encapsulant is flush with the side end surface of the substrate.
  • the encapsulant is an epoxy resin.
  • the chip package structure of the present application electrically connects the chip packaged on the upper surface of the substrate and the ball grid array disposed on the lower surface of the substrate through the arrangement of the substrate, and the ball grid array thus disposed can realize the pair
  • the conversion of the chip does not require redesigning the original printed circuit board, reducing the design time cost, quickly adapting to the market demand, and eliminating the need to redesign the circuit traces, thereby not affecting the signal transmission, thereby ensuring stable product performance. reliable.
  • Another technical solution adopted by the present application is: a mobile terminal including the above chip package structure.
  • the mobile terminal of the present application since the above-mentioned chip package structure is used, the mobile terminal does not need to redesign a new printed circuit board to match the installation of different chips, thereby achieving a reduction in manufacturing cost of the product.
  • FIG. 1 is a schematic structural diagram of a chip package structure according to an embodiment of the present application.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated.
  • features defining “first” and “second” may include one or more of the features either explicitly or implicitly.
  • the meaning of "a plurality” is two or more unless specifically and specifically defined otherwise.
  • the terms “installation”, “connected”, “connected”, “fixed” and the like shall be understood broadly, and may be either a fixed connection or a detachable connection, unless otherwise explicitly stated and defined. , or integrated; can be mechanical connection, or can be electrical connection; can be directly connected, or can be indirectly connected through an intermediate medium, can be the internal communication of two elements or the interaction of two elements.
  • installation can be understood on a case-by-case basis.
  • an embodiment of the present application provides a chip package structure including a substrate 10 , a chip 20 , and an encapsulant 30 .
  • the substrate 10 includes an upper surface 11 and a lower surface 12 disposed opposite to each other.
  • the lower surface 12 is provided with a ball grid array 40.
  • the chip 20 is disposed on the upper surface 11 of the substrate 10 and electrically connected to the ball grid array 40 through the substrate 10, and the encapsulant 30 is coated on The chip 20 is externally mounted and the chip 20 is packaged and fixed to the upper surface 11 of the substrate 10.
  • the chip package structure of the embodiment of the present invention electrically connects the chip 20 packaged on the upper surface 11 of the substrate 10 and the ball grid array 40 disposed on the lower surface 12 of the substrate 10 through the arrangement of the substrate 10, and thus is disposed.
  • the ball grid array 40 can realize the conversion of the chip 20, thus eliminating the need to redesign the original printed circuit board, reducing the design time cost, quickly adapting to the market demand, and eliminating the need to redesign the circuit traces so as not to affect the signal. Transmission, which in turn ensures stable and reliable product performance.
  • the chip 20 is a DRAM chip.
  • the DRAM chip has a special ball position, then the above package structure can ensure that the printed circuit board does not need to be redesigned, the flexibility of product application is improved, and the introduction cost of the customer product is reduced.
  • the DRAM chip is a 366 ball LPDDR4 chip
  • the ball grid array 40 is a 200 ball ball grid array.
  • the 366 ball LPDDR4 chip with a special ball position is converted into a 200 Ball LPDDR4 chip through the substrate 10.
  • the supplier of the 366 ball LPDDR4 chip can Directly supply 200 Ball's LPDDR4 chip for customers to import, improve product application flexibility and reduce customer product introduction costs.
  • the DRAM chip is a 426 ball LPDDR3 chip
  • the ball grid array 40 is a 168 ball ball grid array.
  • the 426 ball LPDDR3 chip with a special ball position is converted into a 168 Ball LPDDR3 chip through the substrate 10.
  • the supplier of the 426 ball LPDDR3 chip can Direct supply of 168 Ball's LPDDR3 chip allows customers to import, increase product application flexibility and reduce customer product introduction costs.
  • the DRAM chip is a 426 ball LPDDR3 chip
  • the ball grid array 40 is a 178 ball ball grid array.
  • the 426 ball LPDDR3 chip with a special ball position is converted into a 178 Ball LPDDR3 chip through the substrate 10.
  • the supplier of the 426 ball LPDDR3 chip can Direct supply of 178 Ball's LPDDR3 chip allows customers to import, increase product application flexibility and reduce customer product introduction costs.
  • the DRAM chip is a 456 ball LPDDR3 chip
  • the ball grid array is a 168 ball ball grid array.
  • the 456 ball LPDDR3 chip with a special ball position is converted into a 168 Ball LPDDR3 chip through the substrate 10.
  • the supplier of the 456 ball LPDDR3 chip can Direct supply of 168 Ball's LPDDR3 chip allows customers to import, increase product application flexibility and reduce customer product introduction costs.
  • the ball grid array 40 includes a plurality of balls 41 , and each of the balls 41 is electrically connected to the lower surface 12 of the substrate 10 .
  • each of the spheres 41 of the ball grid array 40 is a solder ball, and can be electrically connected to the pads of the lower surface 12 of the substrate 10 by solder paste or solder paste, so that the respective spheres 41 and the substrate of the ball grid array 40 can be ensured. 10 connection stability, and can be electrically connected by solder.
  • the substrate 10 is a printed circuit board, and further, the printed circuit board is a hard printed circuit board.
  • the side end surface of the encapsulant 30 is flush with the side end surface of the substrate 10.
  • the design can make the entire chip package structure flat and regular, which is more advantageous for the installation of the chip package structure, and can save space occupied by the installation.
  • the encapsulant 30 is an epoxy resin.
  • the chip 20 is covered by the encapsulant 30, which improves the long-term stability and safety of the chip package structure provided by the embodiment of the present invention.
  • the embodiment of the present application provides a mobile terminal, which includes the chip package structure described above. Specifically, in the mobile terminal of the embodiment of the present application, since the above-mentioned chip package structure is used, the mobile terminal does not need to redesign a new printed circuit board to match the installation of different chips 20, thereby achieving a reduction in manufacturing cost of the product.
  • the mobile terminal can be a mobile phone or a tablet or other mobile electronic product.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Packaging Frangible Articles (AREA)

Abstract

一种移动终端及其芯片封装结构。芯片封装结构包括基板（10）、芯片（20）和封装胶体（30），基板（10）包括位置相对设置的上表面（11）和下表面（12），基板（10）的下表面（12）设置有球栅阵列（40），芯片（20）设置于基板（10）的上表面（11）并通过基板（10）与球栅阵列（40）电性连接，封装胶体（30）包覆于芯片（20）外并将芯片（20）封装固定于基板（10）的上表面（11）。通过基板的设置将封装在基板的上表面的芯片与设置在基板的下表面的球栅阵列电性连接，球栅阵列实现对芯片的转换，如此不需要重新设计原有的印刷电路板，减少设计时间成本，不需要重新设计电路的走线，不会影响信号的传输，进而确保产品的性能稳定可靠。

Description

移动终端及其芯片封装结构 技术领域
本申请属于芯片封装技术领域，尤其涉及一种移动终端及其芯片封装结构。
 背景技术
当前市场上有一些特殊球位封装的芯片，比如说DRAM芯片中的426ball的LPDDR3芯片。由于一般的LPDDR3芯片为168ball，如果要将426ball的LPDDR3芯片替代168ball的LPDDR3芯片使用，则需要重新设计印刷电路板用来适配426ball的特殊球位。而这样做的缺点是，重新设计印刷电路板需要付出一定的时间成本，导致不能够快速的适应市场需求；且因为需要重新设计印刷电路板，则电路的走线等需要重新设计，从而影响信号的传输，进而影响产品的性能。因此，对于特殊球位封装芯片的供应商来说，由于需要客户重新设计印刷电路板来适配特殊球位封装芯片，大大地提高产品的推广难度和门槛。
发明内容
本申请的目的在于提供一种芯片封装结构，旨在解决现有技术中针对特殊球位的芯片需要重新设计相适应的印刷线路板而导致无法快速适应市场需求以及影响芯片性能的技术问题。
为实现上述目的，本申请采用的技术方案是：一种芯片封装结构，包括基板、芯片和封装胶体，所述基板包括位置相对设置的上表面和下表面，所述基板的下表面设置有球栅阵列，所述芯片设于所述基板的上表面并通过所述基板与所述球栅阵列电性连接，所述封装胶体包覆于所述芯片外并将所述芯片封装固定于所述基板的上表面。
优选地，所述芯片为DRAM芯片。
优选地，所述DRAM芯片为366 ball LPDDR4芯片，所述球栅阵列为200 ball球栅阵列。
优选地，所述DRAM芯片为426 ball LPDDR3芯片，所述球栅阵列为168 ball球栅阵列。
优选地，所述DRAM芯片为426 ball LPDDR3芯片，所述球栅阵列为178 ball球栅阵列。
优选地，所述DRAM芯片为456 ball LPDDR3芯片，所述球栅阵列为168 ball球栅阵列。
优选地，所述球栅阵列包括若干个球体，各所述球体均焊接于所述基板的下表面。
优选地，所述封装胶体的侧端面与所述基板的侧端面齐平。
优选地，所述封装胶体为环氧树脂。
本申请的有益效果：本申请的芯片封装结构，通过基板的设置将封装在基板的上表面的芯片与设置在基板的下表面的球栅阵列电性连接，如此设置的球栅阵列可以实现对芯片的转换，如此不需要重新设计原有的印刷电路板，减少设计时间成本，快速适应市场需求，并且不需要重新设计电路的走线，从而不会影响信号的传输，进而确保产品的性能稳定可靠。
本申请采用的另一技术方案是：一种移动终端，其包括上述的芯片封装结构。
本申请的移动终端，由于使用上述的芯片封装结构，那么移动终端不需要重新设计新的印刷电路板匹配不同的芯片的安装，进而可以实现降低产品的制造成本。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的芯片封装结构的结构示意图。
其中，图中各附图标记：
10—基板;11—上表面;12—下表面;
20—芯片;30—封装胶体;40—球栅阵列;
41—球体。
具体实施方式
下面详细描述本申请的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，旨在用于解释本申请，而不能理解为对本申请的限制。
在本申请的描述中，需要理解的是，术语“长度”、“宽度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
如图1所示，本申请实施例提供了一种芯片封装结构，包括基板10、芯片20和封装胶体30，所述基板10包括位置相对设置的上表面11和下表面12，所述基板10的下表面12设置有球栅阵列40，所述芯片20设于所述基板10的上表面11并通过所述基板10与所述球栅阵列40电性连接，所述封装胶体30包覆于所述芯片20外并将所述芯片20封装固定于所述基板10的上表面11。具体地，本申请实施例的芯片封装结构，通过基板10的设置将封装在基板10的上表面11的芯片20与设置在基板10的下表面12的球栅阵列40电性连接，如此设置的球栅阵列40可以实现对芯片20的转换，如此不需要重新设计原有的印刷电路板，减少设计时间成本，快速适应市场需求，并且不需要重新设计电路的走线，从而不会影响信号的传输，进而确保产品的性能稳定可靠。
本实施例中，优选地，所述芯片20为DRAM芯片。其中，DRAM芯片具有特殊的球位，那么采用上述的封装结构可以确保不需要重新设计印刷电路板，提高产品应用的灵活性，降低客户产品导入成本。
本实施例中的第一种实施方式是，所述DRAM芯片为366 ball LPDDR4芯片，所述球栅阵列40为200 ball球栅阵列。具体地，通过基板10将具有特殊球位的366 ball LPDDR4芯片转换为200 Ball LPDDR4芯片，在对应的手机和平板市场分离式LPDDR4以200 ball为主的情况下，366 ball LPDDR4芯片的供应商可以直接供应200 Ball的LPDDR4芯片让客户进行导入，提高产品应用的灵活性，降低客户产品导入成本。
本实施例中的第二种实施方式是，所述DRAM芯片为426 ball LPDDR3芯片，所述球栅阵列40为168 ball球栅阵列。具体地，通过基板10将具有特殊球位的426 ball LPDDR3芯片转换为168 Ball LPDDR3芯片，在对应的手机和平板市场分离式LPDDR3以168 ball为主的情况下，426 ball LPDDR3芯片的供应商可以直接供应168 Ball的LPDDR3芯片让客户进行导入，提高产品应用的灵活性，降低客户产品导入成本。
本实施例中的第三种实施方式是，所述DRAM芯片为426 ball LPDDR3芯片，所述球栅阵列40为178 ball球栅阵列。具体地，通过基板10将具有特殊球位的426 ball LPDDR3芯片转换为178 Ball LPDDR3芯片，在对应的手机和平板市场分离式LPDDR3以178 ball为主的情况下，426 ball LPDDR3芯片的供应商可以直接供应178 Ball的LPDDR3芯片让客户进行导入，提高产品应用的灵活性，降低客户产品导入成本。
本实施例中的第四种实施方式是，所述DRAM芯片为456 ball LPDDR3芯片，所述球栅阵列为168 ball球栅阵列。具体地，通过基板10将具有特殊球位的456 ball LPDDR3芯片转换为168 Ball LPDDR3芯片，在对应的手机和平板市场分离式LPDDR3以168 ball为主的情况下，456 ball LPDDR3芯片的供应商可以直接供应168 Ball的LPDDR3芯片让客户进行导入，提高产品应用的灵活性，降低客户产品导入成本。
本实施例中，所述球栅阵列40包括若干个球体41，各所述球体41均电连接于所述基板10的下表面12。具体地，球栅阵列40的各个球体41为锡球，可以通过锡膏或者助焊膏电连接于基板10的下表面12的焊盘上，这样可以确保球栅阵列40的各个球体41与基板10连接的稳定性，并且可以通过焊锡实现电性连接。
优选地，所述基板10为印刷电路板，进一步地，所述印刷电路板为硬质印刷电路板。
本实施例中，所述封装胶体30的侧端面与所述基板10的侧端面齐平。具体地，如此设计可以使得整个芯片封装结构侧面平整规则，这样更加有利于芯片封装结构的安装，且可以节省占据安装的空间。
本实施例中，所述封装胶体30为环氧树脂。其中，通过封装胶体30将芯片20包覆，如此便提升了本发明实施例提供的芯片封装结构的长期使用稳定性和安全性。
本申请实施例提供了一种移动终端，其包括上述的芯片封装结构。具体地，本申请实施例的移动终端，由于使用上述的芯片封装结构，那么移动终端不需要重新设计新的印刷电路板匹配不同的芯片20的安装，进而可以实现降低产品的制造成本。
其中，移动终端可以是手机或者平板或者其他移动式电子产品。
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。

Claims (10)

  1. 一种芯片封装结构，其特征在于：包括基板、芯片和封装胶体，所述基板包括位置相对设置的上表面和下表面，所述基板的下表面设置有球栅阵列，所述芯片设于所述基板的上表面并通过所述基板与所述球栅阵列电性连接，所述封装胶体包覆于所述芯片外并将所述芯片封装固定于所述基板的上表面。
  2. 根据权利要求1所述的芯片封装结构，其特征在于：所述芯片为DRAM芯片。
  3. 根据权利要求2所述的芯片封装结构，其特征在于：所述DRAM芯片为366 ball LPDDR4芯片，所述球栅阵列为200 ball球栅阵列。
  4. 根据权利要求2所述的芯片封装结构，其特征在于：所述DRAM芯片为426 ball LPDDR3芯片，所述球栅阵列为168 ball球栅阵列。
  5. 根据权利要求2所述的芯片封装结构，其特征在于：所述DRAM芯片为426 ball LPDDR3芯片，所述球栅阵列为178 ball球栅阵列。
  6. 根据权利要求2所述的芯片封装结构，其特征在于：所述DRAM芯片为456 ball LPDDR3芯片，所述球栅阵列为168 ball球栅阵列。
  7. 根据权利要求1~6任一项所述的芯片封装结构，其特征在于：所述球栅阵列包括若干个球体，各所述球体均焊接于所述基板的下表面。
  8. 根据权利要求1~6任一项所述的芯片封装结构，其特征在于：所述封装胶体的侧端面与所述基板的侧端面齐平。
  9. 根据权利要求1~6任一项所述的芯片封装结构，其特征在于：所述封装胶体为环氧树脂。
  10. 一种移动终端，其特征在于：包括权利要求1~9任一项所述的芯片封装结构。
PCT/CN2017/117756 2017-08-31 2017-12-21 移动终端及其芯片封装结构 WO2019041674A1 (zh)

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CN102376666A (zh) * 2010-08-06 2012-03-14 三星半导体(中国)研究开发有限公司 一种球栅阵列封装结构及其制造方法
CN105009279A (zh) * 2013-03-13 2015-10-28 索尼公司 半导体器件及制造半导体器件的方法
KR101672967B1 (ko) * 2015-07-31 2016-11-04 송영희 에지에 사이드 패드를 포함하는 반도체 스택 패키지, 및 이를 포함하는 고밀도 메모리 모듈, 전자 회로 기기
CN106328604A (zh) * 2015-07-01 2017-01-11 珠海越亚封装基板技术股份有限公司 芯片封装

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CN102005435A (zh) * 2009-08-28 2011-04-06 马维尔国际贸易有限公司 用于电子组件的互连布局
CN102376666A (zh) * 2010-08-06 2012-03-14 三星半导体(中国)研究开发有限公司 一种球栅阵列封装结构及其制造方法
CN105009279A (zh) * 2013-03-13 2015-10-28 索尼公司 半导体器件及制造半导体器件的方法
CN106328604A (zh) * 2015-07-01 2017-01-11 珠海越亚封装基板技术股份有限公司 芯片封装
KR101672967B1 (ko) * 2015-07-31 2016-11-04 송영희 에지에 사이드 패드를 포함하는 반도체 스택 패키지, 및 이를 포함하는 고밀도 메모리 모듈, 전자 회로 기기

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