WO2019037435A1 - 栅极驱动单元电路、栅极驱动电路及液晶显示装置 - Google Patents

栅极驱动单元电路、栅极驱动电路及液晶显示装置 Download PDF

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WO2019037435A1
WO2019037435A1 PCT/CN2018/082360 CN2018082360W WO2019037435A1 WO 2019037435 A1 WO2019037435 A1 WO 2019037435A1 CN 2018082360 W CN2018082360 W CN 2018082360W WO 2019037435 A1 WO2019037435 A1 WO 2019037435A1
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Prior art keywords
thin film
film transistor
gate
unit circuit
pull
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PCT/CN2018/082360
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English (en)
French (fr)
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戴超
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南京中电熊猫平板显示科技有限公司
南京中电熊猫液晶显示科技有限公司
南京华东电子信息科技股份有限公司
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Publication of WO2019037435A1 publication Critical patent/WO2019037435A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a gate driving unit circuit, a gate driving circuit, and a liquid crystal display device.
  • LCD Liquid crystal display
  • PDAs personal digital assistants
  • digital cameras computer screens or laptop screens, etc.
  • FIG. 1 is a schematic circuit diagram of a gate driving unit circuit with a front and back scanning function applied to an in-cell touch display screen in the prior art, mainly having a front and back scanning control module 1, a pull-up module 2, and a touch
  • the module 3, the maintenance module, and other auxiliary modules 4 are maintained, as well as the bootstrap capacitor C1.
  • the forward/reverse scan function is mainly implemented by the forward scan control signal U2D and the reverse scan control signal D2U, and the first thin film transistor M1 and the ninth thin film transistor M9 element.
  • U2D is high, D2U is low, the first thin film transistor M1 is responsible for the pull-up precharge pull-up control node netAn, and the ninth thin film transistor M9 is responsible for clearing and resetting the pull-up control node netAn point;
  • U2D is low, D2U is high, the first thin film transistor M1 is responsible for emptying and resetting the pull-up control node netAn, and the ninth thin film transistor M9 is responsible for pulling up the pre-charged pull-up control node netAn.
  • the main disadvantages of this circuit are as follows:
  • the first thin film transistor M1 is in a long-term negative stress state, which is prone to a negative drift of the threshold voltage.
  • the M1 may leak seriously, causing the circuit to fail, and vice versa.
  • a gate driving unit circuit which is suitable for multi-level connection to form a gate driving circuit, including a forward and reverse scanning control module, a sustaining module, and a pull-up module;
  • the front and back scan control module includes a forward and reverse scan pull-up control module, and the forward and reverse scan pull-up control module is configured to receive a scan signal of a front-stage gate drive unit circuit and a scan signal of a subsequent-stage gate drive unit circuit, and
  • the startup circuit realizes forward and reverse scanning under the control of the scan signal of the front stage gate drive unit circuit and the scan signal of the subsequent stage gate drive unit circuit.
  • the forward and reverse scan pull-up control module includes a forward scan pull-up control sub-module and a reverse scan pull-up control sub-module; the forward scan pull-up control sub-module is used in the The start-up circuit realizes forward scanning under the control of the scan signal of the front-stage gate drive unit circuit; the reverse scan pull-up control sub-module is used to start under the control of the scan signal of the subsequent-stage gate drive unit circuit The circuit implements a reverse scan.
  • the forward scan pull-up control sub-module includes a first thin film transistor, a gate of the first thin film transistor is connected to a scan signal of the front-stage gate drive unit circuit, and a source is connected. High level, the drain is connected to the pull-up control node.
  • the reverse scan pull-up control sub-module includes an eleventh thin film transistor, and a gate of the eleventh thin film transistor is connected to a scan signal of the rear-stage gate driving unit circuit, a source The pole is connected high and the drain is connected to the pull-up control node.
  • the gate of the first thin film transistor in the first stage of the gate driving unit circuit is connected to a start pulse signal.
  • the gate of the eleventh thin film transistor in the gate drive unit circuit of the last stage is connected to the start pulse signal.
  • the forward and reverse scan control module further includes a pull-down clearing module for performing pull-down clearing of the pull-up control node under the control of the clock signal of the subsequent-stage gate drive unit circuit.
  • the pull-down emptying module includes a ninth thin film transistor; a gate of the ninth thin film transistor is connected to a clock signal of the rear-stage gate driving unit circuit, and a source is connected to the pull-up control node, and the drain Connect low.
  • the pull-up module includes a tenth thin film transistor, the gate of the tenth thin film transistor is connected to the pull-up control node, and the source is connected to the clock signal of the gate driving unit circuit of the current stage, and the drain Connect the scanning signal of this level.
  • the maintenance module includes a maintenance control node generation module for generating a maintenance control node, and a node maintenance module for maintaining a control node based on the maintenance The control is to maintain the internal node signal of the circuit at a low potential.
  • the sustain control node generating module includes a fifth thin film transistor, a sixth thin film transistor, a sixteenth thin film transistor, a twenty-sixth thin film transistor; a gate and a source of the fifth thin film transistor
  • the pole is connected to a high level, the drain connection is connected to the control node;
  • the gate of the sixth thin film transistor is connected to the pull-up control node, the source is connected to the sustain control node, and the drain is connected to the low level;
  • the sixteenth thin film transistor The gate is connected to the scan signal of the front-stage gate driving unit circuit, the source is connected to maintain the control node, and the drain is connected to the low level;
  • the gate of the twenty-sixth thin film transistor is connected to the scan of the subsequent-stage gate driving unit circuit Signal, the source is connected to maintain the control node, and the drain is connected low.
  • the sustain control node generating module includes a fifth thin film transistor, a sixth thin film transistor, a sixteenth thin film transistor, a twenty-sixth thin film transistor; and a gate connection of the fifth thin film transistor a clock signal of the stage gate driving unit circuit or a clock signal of a subsequent stage gate driving unit circuit, the source is connected to a high level, the drain is connected to maintain the control node; and the gate of the sixth thin film transistor is connected to the pull-up control node, The source is connected to the control node, and the drain is connected to the low level; the gate of the sixteenth thin film transistor is connected to the scan signal of the front stage gate driving unit circuit, the source is connected to maintain the control node, and the drain is connected to the low level; The gate of the twenty-sixth thin film transistor is connected to the scan signal of the subsequent stage gate driving unit circuit, the source is connected to maintain the control node, and the drain is connected to the low level.
  • the node maintenance module includes an eighth thin film transistor and a thirteenth thin film transistor; a gate of the eighth thin film transistor is connected to maintain a control node, a source is connected to a pull-up control node, and a drain connection is a low level for maintaining the pull-up control node during the inactive period; the gate connection of the thirteenth thin film transistor is maintained at the control node, the source is connected to the scan signal of the current stage, and the drain is connected to the low level for The scanning signal of this stage is maintained during the inactive period.
  • the node maintenance module includes an eighth thin film transistor and a thirteenth thin film transistor; a gate of the eighth thin film transistor is connected to a clock signal of the gate driving unit circuit of the current stage, and the source is connected Pulling the control node, the drain is connected to the scan signal of the current stage for maintaining the pull-up control node during the non-active period; the gate connection of the thirteenth thin film transistor is maintained at the control node, and the source is connected to the scan signal of the current stage, and the drain is connected The pole is connected low to maintain the scan signal of this stage during the inactive period.
  • the circuit further includes a clear reset module;
  • the clear reset module includes a second thin film transistor, a third thin film transistor; and a gate connection of the second thin film transistor clears a reset signal,
  • the source is connected to the pull-up control node, the drain is connected to the low level, and is used for clearing and resetting the pull-up control node;
  • the gate connection of the third thin film transistor is clearing the reset signal, the source is connected to maintain the control node, and the drain is connected. Low level, used to clear the reset maintenance control node.
  • the emptying reset module further includes a twelfth thin film transistor; the gate connection of the twelfth thin film transistor is emptied with a reset signal, the source is connected to the scan signal of the current stage, and the drain is connected to the low level. , used to clear and reset the scanning signal of this level.
  • the circuit further includes a touch maintaining module, and the touch maintaining module is configured to maintain the scan signal of the current level during the touch scan.
  • the touch control module includes a fourteenth thin film transistor; the gate of the fourteenth thin film transistor is connected to the touch sustain control signal, the source is connected to the scan signal of the current stage, and the drain connection is low. Level.
  • the circuit further includes a bootstrap capacitor, and one end of the bootstrap capacitor is connected to the pull-up control node, and the other end is connected to the scan signal of the current stage.
  • a gate drive circuit comprising a multi-level connection of a gate drive unit circuit as described in any of the preceding embodiments.
  • liquid crystal display device comprising the gate drive circuit as described in the foregoing embodiments.
  • the forward and reverse scan control module of the gate drive unit circuit of the embodiment of the present invention utilizes the scan signal of the front stage gate drive unit circuit and the scan signal of the subsequent stage gate drive unit circuit.
  • the timing control realizes the forward and reverse scanning function, and does not need to additionally increase the forward scanning control signal and the reverse scanning control signal to perform the forward and reverse scanning functions, which reduces the number of control signals, makes the circuit structure simpler, and can improve the control in the circuit. Negative drift of the threshold voltage of the reverse-scanned device causes a problem of circuit failure.
  • FIG. 1 is a circuit diagram of a gate driving unit circuit with a front and back scanning function of an in-cell touch display screen in the prior art
  • FIG. 2 is a circuit diagram of a gate driving unit circuit according to an embodiment of the invention.
  • FIG. 3 is a circuit diagram of a gate driving unit circuit according to another embodiment of the present invention.
  • FIG. 4 is a schematic diagram of driving waveforms of a gate driving unit circuit in forward scanning according to an embodiment of the invention
  • FIG. 5 is a schematic diagram of driving waveforms of a gate driving unit circuit in reverse scanning according to an embodiment of the invention.
  • 01 positive anti-sweep pull-up control module, 02, pull-down clear module, 03, pull-up module, 04, maintenance module, 05, clear reset module, 06, touch maintenance module;
  • M1A first thin film transistor, M1B, eleventh thin film transistor, M2, second thin film transistor, M3, third thin film transistor, M5, fifth thin film transistor, M6, sixth thin film transistor, M6A, sixteenth thin film transistor , M6B, twenty-sixth thin film transistor, M8, eighth thin film transistor, M9, ninth thin film transistor, M10, tenth thin film transistor, M12, twelfth thin film transistor, M13, thirteenth thin film transistor, M14, Fourteen thin film transistors, C1, bootstrap capacitors;
  • Gn scan signal of the driver circuit unit of this stage, netAn, pull-up control node, netBn, sustain control node, VGH, high level, VSS, low level, CKm, clock signal of the driver circuit unit of this stage, CKm+4 Clock signal of the rear stage driving circuit unit, Gn-2, scanning signal of the pre-drive circuit unit, Gn+2, scanning signal of the driving circuit unit of the rear stage, TC1, touch sustain control signal, CLR, clear reset signal .
  • FIG. 2 is a circuit diagram of a gate drive unit circuit in accordance with an embodiment of the present invention.
  • the gate driving unit circuit of the present embodiment is adapted to perform multi-stage connection to form a gate driving circuit, which includes a forward and reverse scanning control module, a pull-up module 03, and a maintenance module 04.
  • the forward and reverse scan control module includes a forward and reverse scan pull-up control module 01 and a pull-down clear module 02.
  • the forward and reverse scan pull-up control module 01 is configured to receive a scan signal of a previous stage gate drive unit circuit and a scan signal of a subsequent stage gate drive unit circuit, and scan signals of the front stage gate drive unit circuit and The start-up circuit performs forward and reverse scanning under the control of the scan signal of the subsequent stage gate drive unit circuit.
  • the forward and reverse scan pull-up control module 01 includes a forward scan pull-up control sub-module and a reverse scan pull-up control sub-module.
  • the forward scan pull-up control sub-module is configured to receive a scan signal of a front-stage gate drive unit circuit, and start a circuit to implement a forward scan under control of a scan signal of the front-stage gate drive unit circuit;
  • the reverse scan pull-up control sub-module is configured to receive a scan signal of the subsequent-stage gate drive unit circuit, and start the circuit to implement reverse scan under the control of the scan signal of the subsequent-stage gate drive unit circuit.
  • the forward scan pull-up control sub-module includes a first thin film transistor M1A
  • the reverse scan pull-up control sub-module includes an eleventh thin film transistor M1B.
  • the first thin film transistor M1A is configured to precharge the pull-up control node netAn during forward scanning, the gate thereof is connected to the scan signal Gn-2 of the previous stage gate driving unit circuit, and the source is connected to the high level VGH.
  • the drain connection pull-up control node netAn wherein the gate of the first thin film transistor M1A in the gate driving unit circuit of the first stage inputs a start pulse signal GSP1.
  • the eleventh thin film transistor M1B is used for pre-charging the pull-up control node netAn during the reverse scan, the gate thereof is connected to the scan signal Gn+2 of the subsequent-stage gate drive unit circuit, and the source is connected to the high-level VGH.
  • the pull-down emptying module 02 is configured to perform pull-down clearing of the pull-up control node netAn under the control of the clock signal of the subsequent-stage gate driving unit circuit.
  • the pull-down emptying module 02 includes a ninth thin film transistor M9 whose gate is connected to a clock signal of a subsequent stage gate driving unit circuit, a source connected to the pull-up control node netAn, and a drain connected to a low level VSS.
  • the clock signal of the subsequent stage gate drive unit circuit of the gate input of the ninth thin film transistor M9 is represented as CKm+4.
  • the pull-up module 03 is configured to perform a pull-up output and a pull-down clear on the scan signal Gn of the current stage, and includes a tenth thin film transistor M10.
  • the gate of the tenth thin film transistor M10 is connected to the pull-up control node netAn, the source is connected to the clock signal CKm of the gate drive unit circuit of the current stage, and the drain is connected to the scan signal Gn of the current stage.
  • the circuit of the first stage gate driving unit is The gate of the ninth thin film transistor M9 is connected to CK5, and the gate of the ninth thin film transistor M9 of the last-stage gate driving unit circuit is connected to CK3.
  • the clock signal output order is CK1, CK3, CK5, and CK7.
  • the current-stage circuit since CK1 is output before CK5, the current-stage circuit first drives the output of the tenth thin film transistor M10 through CK1.
  • the scan signal is generated, and the ninth thin film transistor M9 is driven by CK5 to clear the pull-up control node, that is, the output scan signal can be normally started; and for the last-stage gate drive unit circuit, since CK3 is output before CK7, that is, at this level
  • the clock signal CK7 does not drive M10 to generate the scan signal before CK3 has driven M9 to clear the pull-up control node of the last stage, that is, the output scan signal cannot be normally started, so that only the first-stage gate drive unit circuit can normally start the output scan signal. And then perform a forward scan in sequence. In the reverse scan, the clock signal output order is CK7, CK5, CK3, and CK1.
  • the circuit of this stage first drives the output of the tenth thin film transistor M10 through CK7 to generate the scan signal, and then drives the ninth thin film transistor M9 through CK3 to clear the pull-up control node, that is, the output scan signal can be normally started, so that only the last stage gate
  • the drive unit circuit can normally start the output scan signal and then perform reverse scan in sequence.
  • the maintenance module 04 is configured to maintain the internal node signal of the circuit during the non-active period, such as pulling the control node netAn and the local scanning signal Gn to maintain a stable low potential without interference from other signals to ensure that the circuit has a higher level. Reliability.
  • the maintenance module 04 includes a maintenance control node generation module and a node maintenance module.
  • the sustain control node generating module is configured to generate a sustain control node netBn, which mainly includes a fifth thin film transistor M5, a sixth thin film transistor M6, a sixteenth thin film transistor M6A, and a twenty-sixth thin film transistor M6B.
  • the node maintenance module is configured to maintain the internal node signal of the circuit at a low level under the control of the maintenance control node netBn, and mainly includes an eighth thin film transistor M8 and a thirteenth thin film transistor M13.
  • the gate and the source of the fifth thin film transistor M5 are both connected to the high level VGH, and the drain connection is connected to the control node netBn.
  • the fifth thin film transistor M5 is for charging the sustain control node netBn.
  • the fifth thin film transistor M5 may be modified, and the gate of the fifth thin film transistor M5 may be connected to the clock signal CKm of the gate driving unit circuit of the current stage or the gate of the subsequent stage.
  • the clock signal of the drive unit circuit, such as CKm+4 has the beneficial effect of avoiding a large loop current between the high level VGH and the low level VSS.
  • the gate of the sixth thin film transistor M6 is connected to the pull-up control node netAn, the source is connected to the sustain control node netBn, and the drain is connected to the low level VSS.
  • the sixth thin film transistor M6 is used to pull down the maintenance control node netBn by using the pull-up control node netAn to ensure that the maintenance control node netBn does not affect the pull-up control node netAn.
  • the gate of the sixteenth thin film transistor M6A is connected to the scan signal Gn-2 of the previous stage gate drive unit circuit, the source is connected to the sustain control node netBn, and the drain is connected to the low level VSS.
  • the sixteenth thin film transistor M6A is used for pulling down the maintenance control node netBn by using the scan signal Gn-2 of the previous stage gate driving unit circuit during forward scanning to ensure that the maintenance control node netBn does not affect the pull-up control node netAn pull high.
  • the gate of the twenty-sixth thin film transistor M6B is connected to the scan signal Gn+2 of the post-stage gate drive unit circuit, the source is connected to the sustain control node netBn, and the drain is connected to the low level VSS.
  • the twenty-sixth thin film transistor M6B is used to pull down the maintenance control node netBn by using the scan signal Gn+2 of the subsequent stage gate driving unit circuit in the reverse scanning to ensure that the maintenance control node netBn does not affect the pull-up control node netAn Pull up.
  • the gate of the eighth thin film transistor M8 is connected to the sustain control node netBn, the source is connected to the pull-up control node netAn, and the drain is connected to the low level VSS.
  • the eighth thin film transistor M8 is used to maintain the pull-up control node netAn during the inactive period.
  • the gate of the thirteenth thin film transistor M13 is connected to the sustain control node netBn, the source is connected to the scan signal Gn of the present stage, and the drain is connected to the low level VSS.
  • the thirteenth thin film transistor M13 is used to maintain the scanning signal of the current stage during the inactive period.
  • the gate drive unit circuit further includes an empty reset module 05.
  • the emptying reset module 05 uses the clear reset signal CLR to clear the pull-up control node netAn of the circuit, the maintenance control node netBn, and the local-level scan signal Gn at the end of each frame and when the machine is turned off.
  • the empty reset module 05 includes a second thin film transistor M2, a third thin film transistor M3, and a twelfth thin film transistor M12.
  • the gate of the second thin film transistor M2 is connected to clear the reset signal CLR, the source is connected to the pull-up control node netAn, and the drain is connected to the low level VSS for clearing and resetting the pull-up control node netAn.
  • the gate of the third thin film transistor M3 is connected to the clear reset signal CLR, the source is connected to the sustain control node netBn, and the drain is connected to the low level VSS for clearing the reset maintenance control node netBn.
  • the gate of the twelfth thin film transistor M12 is connected to clear the reset signal CLR, the source is connected to the scan signal Gn of the current stage, and the drain is connected to the low level VSS for clearing and resetting the scan signal Gn of the present stage.
  • the gate driving unit circuit further includes a bootstrap capacitor C1.
  • One end of the bootstrap capacitor C1 is connected to the pull-up control node netAn, and the other end is connected to the scan signal Gn of the current stage for scanning signals at the current level.
  • the potential of the pull-up control node netAn is raised during the output period so that the pull-up module 03 has a sufficient current region to drive the scanning signal of the current stage.
  • the gate driving unit circuit further includes a touch maintaining module 06.
  • the touch control module 06 includes a fourteenth thin film transistor M14.
  • the gate of the fourteenth thin film transistor M14 inputs a touch sustain control signal TC1, the source is connected to the scan signal Gn of the current stage, and the drain is connected to a low level VSS.
  • the touch signal is turned off, the normal driving signal is turned off, and the touch sustaining control signal TC1 is pulled high to maintain the scanning signal of the current level, so as to prevent the touch sensor from generating a large coupling effect on the gate scanning line, thereby affecting the screen display and Touch detection.
  • the touch-maintaining module 06 of the embodiment is applicable to the gate driving circuit of the in-cell touch display screen, and if the ordinary non-in-cell touch display screen is used, the touch maintenance can be removed. Module 06.
  • Gn+2 is a scan signal of the gate driving unit circuit of the latter two stages of the driving circuit unit of the current stage, in fact, as long as the scanning signal of the gate driving unit circuit after the gate driving unit circuit of the current stage is as Gn+1, Gn+3, Gn+5 and the like can be applied to the present invention.
  • the scanning signals of the gate driving unit circuit before the gate driving unit circuit of the present stage such as Gn-1, Gn-3, Gn-5, etc., may also be substituted for Gn-2 in this embodiment.
  • the clock signal CKm+4 in the gate driving unit circuit of the latter stage is the last four clock signals of the clock signal CKm of the gate driving unit circuit of the stage, in fact, the clock in the circuit of the other subsequent stage driving unit Signals such as CKm+1, CKm+2, CKm+3, etc. can be applied to the present invention.
  • the clearing reset module 05, the bootstrap capacitor C1, and the touch maintaining module 06 are functional modules that need to be added according to actual use, and whether the circuit includes the above modules is not limited, and in order to meet the actual situation. It is also necessary to add other functional modules, and the conventional functional improvements based on this should fall within the protection scope of the present invention.
  • the embodiment of the invention realizes the function of forward and reverse scanning of the gate driving circuit by circuit design and timing matching, and uses the clock signal to clear the pull-up control node netAn, which reduces the forward and reverse scanning control signals compared with the prior art.
  • the number, the circuit structure is simpler, and at the same time, it can improve the circuit failure caused by the negative drift of the threshold voltage of the device controlling the forward and reverse scanning in the circuit.
  • FIG. 3 is a circuit diagram of a gate drive unit circuit in accordance with another embodiment of the present invention. As shown in FIG. 3, the present embodiment is improved on the basis of the embodiment shown in FIG. 2, and the connection mode of the eighth thin film transistor M8 is improved.
  • the gate of the eighth thin film transistor M8 is connected to the clock signal CKm of the gate drive unit circuit of the current stage, the source is connected to the pull-up control node netAn, and the drain is connected to the scan signal Gn of the current stage.
  • the twelfth thin film transistor M12 can also be removed, and the function of the twelfth thin film transistor M12 can be realized by the fourteenth thin film transistor M14.
  • FIG. 4 is a schematic diagram of driving waveforms of a gate driving unit circuit in forward scanning according to an embodiment of the invention. Take the drive architecture of the left and right interleaved unilateral drive mode as an example. As shown in Figure 4, the signals are as follows:
  • GSP1 is the start pulse signal and is responsible for starting during forward scan and reverse scan;
  • CK1, CK3, CK5, and CK7 are driven clock signals, which are sequentially output during forward scanning;
  • the TC1 is a touch sustain control signal during touch, and is used to maintain the scan signal of the current level during the touch period;
  • VGH is a constant voltage high potential control signal, which is a high level in this embodiment
  • VSS is a constant voltage low potential control signal, which is the low level in this embodiment
  • the CLR is the clear reset signal, which is mainly responsible for the charge emptying of the internal nodes of the circuit at the end of each frame and when the machine is turned on and off.
  • waveforms such as netA1, netA2, netAlast-1, and netAlast are the output waveforms of the internal nodes of the circuit, and G1, G2, and Glast are the waveforms of the scan signals output by the drive unit circuits of each stage.
  • FIG. 5 is a schematic diagram of driving waveforms of a gate driving unit circuit in reverse scanning according to an embodiment of the present invention. Take the drive architecture of the left and right interleaved unilateral drive mode as an example. As shown in Figure 5, the signals are as follows:
  • GSP1 is the start pulse signal and is responsible for starting during forward scan and reverse scan;
  • CK1, CK3, CK5, and CK7 are driven clock signals, and are output in reverse order during reverse scanning;
  • the TC1 is a touch sustaining control signal during touch, and is used for maintaining the scanning signal line of the current level during the touch period;
  • VGH is a constant voltage high potential control signal, which is a high level in this embodiment
  • VSS is a constant voltage low potential control signal, which is the low level in this embodiment
  • the CLR is the clear reset signal, which is mainly responsible for the charge emptying of the internal nodes of the circuit at the end of each frame and when the machine is turned on and off.
  • waveforms such as netA1, netA2, netAlast-1, and netAlast are the output waveforms of the internal nodes of the circuit, and G1, G2, and Glast are the waveforms of the scan signals output by the drive unit circuits of each stage.
  • circuit diagrams in the foregoing embodiments are all single-stage circuits in the interlace driving architecture, that is, the left-right interleaved unilateral driving mode, but the application of the gate scanning driving circuit of the present invention is not limited to this mode, and can be applied. Drive architecture in any mode.
  • the embodiment of the invention further provides a gate driving circuit comprising N cascaded gate driving unit circuits according to the foregoing embodiments, wherein N is a positive integer greater than one.
  • the gate driving circuit can be applied to an in-cell or non-embedded touch screen display, which reduces the number of forward and reverse scanning control signals, has a simpler circuit structure, and can improve the circuit compared with the prior art.
  • the negative drift of the threshold voltage of the device controlling the forward and reverse scan causes the circuit to fail.
  • the embodiment of the invention further provides a liquid crystal display device comprising the above gate driving circuit.
  • the gate driving circuit may be a single-sided driving method or a bilateral driving method.

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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种栅极驱动单元电路，适于进行多级连接以形成栅极驱动电路，包括正反扫描控制模块、维持模块04以及上拉模块03；正反扫描控制模块包括正反扫描上拉控制模块01，用于接收前面级栅极驱动单元电路的扫描信号Gn-2和后面级栅极驱动单元电路的扫描信号Gn+2，并在扫描信号Gn-2和Gn+2的控制下启动电路实现正反扫描。栅极驱动单元电路利用时序控制实现电路的正反扫描功能，缩减了控制信号的数量，且能够改善电路中控制正反向扫描的器件阈值电压负向漂移导致电路失效的问题。

Description

栅极驱动单元电路、栅极驱动电路及液晶显示装置 技术领域
本发明涉及液晶显示技术领域，尤其涉及一种栅极驱动单元电路、栅极驱动电路及液晶显示装置。
背景技术
液晶显示器(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
在一些特殊的应用场合，液晶显示器需要具备正向和反向扫描的功能，例如手机屏的显示画面可以正常放置显示，也需要可以倒置显示，那么这就要求栅极扫描驱动电路既可以进行自上而下的扫描，也要可以进行自下而上的扫描。图1所示是现有技术中应用于内嵌式触控显示屏的具有正反扫描功能的栅极驱动单元电路的电路示意图，主要有正反扫描控制模块1、上拉模块2、触控维持模块3、维持模块以及其他辅助模块4，还有自举电容C1。其中，正反扫描功能主要通过正向扫描控制信号U2D和反向扫描控制信号D2U、以及第一薄膜晶体管M1和第九薄膜晶体管M9元件来实现。在正向扫描时，U2D是高电位，D2U是低电位，第一薄膜晶体管M1负责上拉预充上拉控制节点netAn，第九薄膜晶体管M9负责清空重置上拉控制节点netAn点；在反向扫描时，U2D是低电位，D2U是高电位，第一薄膜晶体管M1负责清空重置上拉控制节点netAn，第九薄膜晶体管M9负责上拉预充上拉控制节点netAn。该电路主要的缺点如下：
1.正向扫描时，第一薄膜晶体管M1处于长期的负压应力(stress)状态，容易产生阈值电压负向漂移，在切换到反向扫描时，M1会漏电严重导致电路失效，反之反向扫描时第九薄膜晶体管M9也存在同样的问题；
2.需要增加额外的U2D和D2U控制信号来进行正反扫描功能的控制。
发明内容
为解决上述技术问题，根据本发明的一方面，提出一种栅极驱动单元电路，适于进行多级连接以形成栅极驱动电路，包括正反扫描控制模块、维持模块以及上拉模块；所述正反扫描控制模块包括正反扫描上拉控制模块，所述正反扫描上拉控制模块用于接收前面级栅极驱动单元电路的扫描信号和后面级栅极驱动单元电路的扫描信号，并在所述前面级栅极驱动单元电路的扫描信号和后面级栅极驱动单元电路的扫描信号的控制下启动电路实现正反扫描。
根据本发明的优选实施方式，所述正反扫描上拉控制模块包括正向扫描上拉控制子模块和反向扫描上拉控制子模块；所述正向扫描上拉控制子模块用于在所述前面级栅极驱动单元电路的扫描信号的控制下启动电路实现正向扫描；所述反向扫描上拉控制子模块用于在所述后面级栅极驱动单元电路的扫描信号的控制下启动电路实现反向扫描。
根据本发明的优选实施方式，所述正向扫描上拉控制子模块包括第一薄膜晶体管，所述第一薄膜晶体管的栅极连接所述前面级栅极驱动单元电路的扫描信号，源极连接高电平，漏极连接上拉控制节点。
根据本发明的优选实施方式，所述反向扫描上拉控制子模块包括第十一薄膜晶体管，所述第十一薄膜晶体管的栅极连接所述后面级栅极驱动单元电路的扫描信号，源极连接高电平，漏极连接上拉控制节点。
根据本发明的优选实施方式，第一级所述栅极驱动单元电路中的所述第一薄膜晶体管的栅极连接启动脉冲信号。
根据本发明的优选实施方式，最后一级所述栅极驱动单元电路中的所述第十一薄膜晶体管的栅极连接启动脉冲信号。
根据本发明的优选实施方式，所述正反扫描控制模块还包括下拉清空模块，用于在后面级栅极驱动单元电路的时钟信号的控制下对上拉控制节点进行下拉清空。
根据本发明的优选实施方式，所述下拉清空模块包括第九薄膜晶体管；第九薄膜晶体管的栅极连接所述后面级栅极驱动单元电路的时钟信号，源极连接上拉控制节点，漏极连接低电平。
根据本发明的优选实施方式，所述上拉模块包括第十薄膜晶体管，所述第 十薄膜晶体管的栅极连接上拉控制节点，源极连接本级栅极驱动单元电路的时钟信号，漏极连接本级扫描信号。
根据本发明的优选实施方式，所述维持模块包括维持控制节点产生模块和节点维持模块，所述维持控制节点产生模块用于产生维持控制节点，所述节点维持模块用于基于所述维持控制节点的控制来维持电路的内部节点信号处于低电位。
根据本发明的优选实施方式，所述维持控制节点产生模块包括第五薄膜晶体管、第六薄膜晶体管、第十六薄膜晶体管、第二十六薄膜晶体管；所述第五薄膜晶体管的栅极和源极均连接高电平，漏极连接维持控制节点；所述第六薄膜晶体管的栅极连接上拉控制节点，源极连接维持控制节点，漏极接低电平；所述第十六薄膜晶体管的栅极连接前面级栅极驱动单元电路的扫描信号，源极连接维持控制节点，漏极连接低电平；所述第二十六薄膜晶体管的栅极连接后面级栅极驱动单元电路的扫描信号，源极连接维持控制节点，漏极连接低电平。
根据本发明的优选实施方式，所述维持控制节点产生模块包括第五薄膜晶体管、第六薄膜晶体管、第十六薄膜晶体管、第二十六薄膜晶体管；所述第五薄膜晶体管的栅极连接本级栅极驱动单元电路的时钟信号或后面级栅极驱动单元电路的时钟信号，源极连接高电平，漏极连接维持控制节点；所述第六薄膜晶体管的栅极连接上拉控制节点，源极连接维持控制节点，漏极接低电平；所述第十六薄膜晶体管的栅极连接前面级栅极驱动单元电路的扫描信号，源极连接维持控制节点，漏极连接低电平；所述第二十六薄膜晶体管的栅极连接后面级栅极驱动单元电路的扫描信号，源极连接维持控制节点，漏极连接低电平。
根据本发明的优选实施方式，所述节点维持模块包括第八薄膜晶体管和第十三薄膜晶体管；所述第八薄膜晶体管的栅极连接维持控制节点，源极连接上拉控制节点，漏极连接低电平，用于在非作用期间对上拉控制节点进行维持；所述第十三薄膜晶体管的栅极连接维持控制节点，源极连接本级扫描信号，漏极连接低电平，用于在非作用期间对本级扫描信号进行维持。
根据本发明的优选实施方式，所述节点维持模块包括第八薄膜晶体管和第十三薄膜晶体管；所述第八薄膜晶体管的栅极连接本级栅极驱动单元电路的时 钟信号，源极连接上拉控制节点，漏极连接本级扫描信号，用于在非作用期间对上拉控制节点进行维持；所述第十三薄膜晶体管的栅极连接维持控制节点，源极连接本级扫描信号，漏极连接低电平，用于在非作用期间对本级扫描信号进行维持。
根据本发明的优选实施方式，所述电路还包括清空重置模块；所述清空重置模块包括第二薄膜晶体管、第三薄膜晶体管；所述第二薄膜晶体管的栅极连接清空重置信号，源极连接上拉控制节点，漏极连接低电平，用于清空重置上拉控制节点；所述第三薄膜晶体管的栅极连接清空重置信号，源极连接维持控制节点，漏极连接低电平，用于清空重置维持控制节点。
根据本发明的优选实施方式，所述清空重置模块还包括第十二薄膜晶体管；第十二薄膜晶体管的栅极连接清空重置信号，源极连接本级扫描信号，漏极连接低电平，用于清空重置本级扫描信号。
根据本发明的优选实施方式，所述电路还包括触控维持模块，所述触控维持模块用于在触控扫描期间对本级扫描信号进行维持。
根据本发明的优选实施方式，所述触控维持模块包括第十四薄膜晶体管；所述第十四薄膜晶体管的栅极连接触控维持控制信号，源极连接本级扫描信号，漏极连接低电平。
根据本发明的优选实施方式，所述电路还包括自举电容，所述自举电容一端连接上拉控制节点，另一端连接本级扫描信号。
根据本发明的另一方面，提出一种栅极驱动电路，包括多级连接的如前述任一实施例所述的栅极驱动单元电路。
根据本发明的另一方面，提出一种液晶显示装置，包括如前述实施例所述的栅极驱动电路。
与现有技术相比，本发明实施例的栅极驱动单元电路的正反扫描控制模块在前面级栅极驱动单元电路的扫描信号和后面级栅极驱动单元电路的扫描信号的控制下，利用时序控制实现正反扫描功能，无需额外增加正向扫描控制信号和反向扫描控制信号来进行正反扫描功能，缩减了控制信号的数量，使得电路结构更为简单，而且能够改善电路中控制正反向扫描的器件阈值电压负向漂 移导致电路失效的问题。
附图说明
图1为现有技术中内嵌式触控显示屏的具有正反扫描功能的栅极驱动单元电路的电路示意图；
图2为根据本发明一实施例的栅极驱动单元电路的电路示意图；
图3为根据本发明另一实施例的栅极驱动单元电路的电路示意图；
图4为根据本发明一实施例的栅极驱动单元电路正向扫描时的驱动波形示意图；
图5为根据本发明一实施例的栅极驱动单元电路反向扫描时的驱动波形示意图。
附图标号说明：
01、正反扫上拉控制模块，02、下拉清空模块，03、上拉模块，04、维持模块，05、清空重置模块，06、触控维持模块；
M1A、第一薄膜晶体管，M1B、第十一薄膜晶体管，M2、第二薄膜晶体管，M3、第三薄膜晶体管，M5、第五薄膜晶体管，M6、第六薄膜晶体管，M6A、第十六薄膜晶体管，M6B、第二十六薄膜晶体管，M8、第八薄膜晶体管，M9、第九薄膜晶体管，M10、第十薄膜晶体管，M12、第十二薄膜晶体管，M13、第十三薄膜晶体管，M14、第十四薄膜晶体管，C1、自举电容；
Gn、本级驱动电路单元的扫描信号，netAn、上拉控制节点，netBn、维持控制节点，VGH、高电平，VSS、低电平，CKm、本级驱动电路单元的时钟信号，CKm+4、后级驱动电路单元的时钟信号，Gn-2、前级驱动电路单元的扫描信号，Gn+2、后级驱动电路单元的扫描信号，TC1、触控维持控制信号，CLR、清空重置信号。
具体实施方式
为了更清楚地说明本发明实施例的技术方案，下面将对照附图说明本发明的具体实施方式。显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这 些附图获得其他的附图，并获得其他的实施方式。
为使图面简洁，各图中只示意性地表示出了与本发明相关的部分，它们并不代表其作为产品的实际结构。另外，以使图面简洁便于理解，在有些图中具有相同结构或功能的部件，仅示意性地绘示了其中的一个，或仅标出了其中的一个。在本文中，“一个”不仅表示“仅此一个”，也可以表示“多于一个”的情形。
图2为根据本发明一实施例的栅极驱动单元电路的电路示意图。如图2所示，本实施例的栅极驱动单元电路适于进行多级连接以形成栅极驱动电路，其包括：正反扫描控制模块、上拉模块03、维持模块04。
所述正反扫描控制模块包括正反扫描上拉控制模块01和下拉清空模块02。所述正反扫描上拉控制模块01用于接收前面级栅极驱动单元电路的扫描信号和后面级栅极驱动单元电路的扫描信号，并在所述前面级栅极驱动单元电路的扫描信号和后面级栅极驱动单元电路的扫描信号的控制下启动电路实现正向和反向扫描。
正反扫描上拉控制模块01包括正向扫描上拉控制子模块和反向扫描上拉控制子模块。所述正向扫描上拉控制子模块用于接收前面级栅极驱动单元电路的扫描信号，并在所述前面级栅极驱动单元电路的扫描信号的控制下启动电路实现正向扫描；所述反向扫描上拉控制子模块用于接收后面级栅极驱动单元电路的扫描信号，并在所述后面级栅极驱动单元电路的扫描信号的控制下启动电路实现反向扫描。
具体的，所述正向扫描上拉控制子模块包括第一薄膜晶体管M1A，所述反向扫描上拉控制子模块包括第十一薄膜晶体管M1B。所述第一薄膜晶体管M1A用于在正向扫描时对上拉控制节点netAn进行预充，其栅极连接前面级栅极驱动单元电路的扫描信号Gn-2，源极连接高电平VGH，漏极连接上拉控制节点netAn；其中，第1级所述栅极驱动单元电路中的所述第一薄膜晶体管M1A的栅极输入启动脉冲信号GSP1。所述第十一薄膜晶体管M1B用于在反向扫描时对上拉控制节点netAn进行预充，其栅极连接后面级栅极驱动单元电路的扫描信号Gn+2，源极连接高电平VGH，漏极连接上拉控制节点netAn；其中，第N级 (最后一级)所述栅极驱动单元电路中的所述第十一薄膜晶体管M1B的栅极输入启动脉冲信号GSP1。
下拉清空模块02用于在后面级栅极驱动单元电路的时钟信号的控制下对上拉控制节点netAn进行下拉清空。下拉清空模块02包括第九薄膜晶体管M9，所述第九薄膜晶体管M9的栅极连接后面级栅极驱动单元电路的时钟信号，源极连接上拉控制节点netAn，漏极连接低电平VSS。在一些实施方式中，第九薄膜晶体管M9的栅极输入的后面级栅极驱动单元电路的时钟信号表示为CKm+4。
上拉模块03用于对本级扫描信号Gn进行上拉输出以及下拉清空，其包括第十薄膜晶体管M10。所述第十薄膜晶体管M10的栅极连接上拉控制节点netAn，源极连接本级栅极驱动单元电路的时钟信号CKm，漏极连接本级扫描信号Gn。
本实施例中，如果第一级栅极驱动单元电路的本级时钟信号表示为CK1，最后一级栅极驱动单元电路的本级时钟信号表示为CK7，那么第一级栅极驱动单元电路的第九薄膜晶体管M9的栅极连接CK5，而最后一级栅极驱动单元电路的第九薄膜晶体管M9的栅极连接CK3。在正向扫描时，时钟信号输出顺序依次为CK1、CK3、CK5、CK7，对于第一级栅极驱动单元电路，由于CK1先于CK5输出，本级电路先通过CK1驱动第十薄膜晶体管M10输出产生扫描信号，再通过CK5驱动第九薄膜晶体管M9将上拉控制节点清空，即能够正常启动输出扫描信号；而对于最后一级栅极驱动单元电路，由于CK3先于CK7输出，即在本级时钟信号CK7未驱动M10产生扫描信号之前CK3已经先驱动M9将最后一级的上拉控制节点清空，即无法正常启动输出扫描信号，这样只有第一级栅极驱动单元电路能正常启动输出扫描信号，然后依序执行正向扫描。在反向扫描时，时钟信号输出顺序依次是CK7、CK5、CK3、CK1，对于第一级栅极驱动单元电路，由于CK5先于CK1输出，即在本级时钟信号CK1未驱动第十薄膜晶体管M10产生扫描信号之前CK5已经先驱动第九薄膜晶体管M9将第一级的上拉控制节点清空，也就无法正常启动输出扫描信号；而对于最后一级栅极驱动单元电路，由于CK7先于CK3输出，本级电路先通过CK7驱动第十薄膜晶体管M10输出产 生扫描信号，再通过CK3驱动第九薄膜晶体管M9将上拉控制节点清空，即能够正常启动输出扫描信号，这样只有最后一级栅极驱动单元电路能正常启动输出扫描信号，然后依序执行反向扫描。
维持模块04用于在非作用期间维持电路的内部节点信号，如上拉控制节点netAn以及本级扫描信号Gn，使其维持在稳定的低电位而不受到其他信号的干扰，以确保电路具有较高的可靠性。维持模块04包括维持控制节点产生模块和节点维持模块。所述维持控制节点产生模块用于产生维持控制节点netBn，其主要包括第五薄膜晶体管M5、第六薄膜晶体管M6、第十六薄膜晶体管M6A、第二十六薄膜晶体管M6B。所述节点维持模块用于在维持控制节点netBn的控制下维持电路的内部节点信号处于低电位，其主要包括第八薄膜晶体管M8以及第十三薄膜晶体管M13。
第五薄膜晶体管M5的栅极和源极均连接高电平VGH，漏极连接维持控制节点netBn。第五薄膜晶体管M5用于对维持控制节点netBn进行充电。需要说明的是，在一些实施方式中，还可以对上述第五薄膜晶体管M5进行改进，可以将第五薄膜晶体管M5的栅极连接本级栅极驱动单元电路的时钟信号CKm或后面级栅极驱动单元电路的时钟信号，例如CKm+4，这种实施方式的有益效果是可以避免高电平VGH和低电平VSS之间产生较大的回路电流。
第六薄膜晶体管M6的栅极连接上拉控制节点netAn，源极连接维持控制节点netBn，漏极接低电平VSS。第六薄膜晶体管M6用于利用上拉控制节点netAn对维持控制节点netBn进行拉低作用，确保维持控制节点netBn不影响上拉控制节点netAn拉高。
第十六薄膜晶体管M6A的栅极连接前级栅极驱动单元电路的扫描信号Gn-2，源极连接维持控制节点netBn，漏极连接低电平VSS。第十六薄膜晶体管M6A用于在正向扫描时利用前面级栅极驱动单元电路的扫描信号Gn-2对维持控制节点netBn进行拉低作用，确保维持控制节点netBn不影响上拉控制节点netAn拉高。
第二十六薄膜晶体管M6B的栅极连接后级栅极驱动单元电路的扫描信号Gn+2，源极连接维持控制节点netBn，漏极连接低电平VSS。第二十六薄膜晶 体管M6B用于在反向扫描时利用后面级栅极驱动单元电路的扫描信号Gn+2对维持控制节点netBn进行拉低作用，确保维持控制节点netBn不影响上拉控制节点netAn拉高。
第八薄膜晶体管M8的栅极连接维持控制节点netBn，源极连接上拉控制节点netAn，漏极连接低电平VSS。第八薄膜晶体管M8用于在非作用期间对上拉控制节点netAn进行维持。
第十三薄膜晶体管M13的栅极连接维持控制节点netBn，源极连接本级扫描信号Gn，漏极连接低电平VSS。第十三薄膜晶体管M13用于在非作用期间对本级扫描信号进行维持。
在一些实施方式中，所述栅极驱动单元电路还包括清空重置模块05。所述清空重置模块05利用清空重置信号CLR在每帧结束以及开关机的时候清空电路的上拉控制节点netAn、维持控制节点netBn以及本级扫描信号Gn。
所述清空重置模块05包括第二薄膜晶体管M2、第三薄膜晶体管M3和第十二薄膜晶体管M12。所述第二薄膜晶体管M2的栅极连接清空重置信号CLR，源极连接上拉控制节点netAn，漏极连接低电平VSS，用于清空重置上拉控制节点netAn。所述第三薄膜晶体管M3的栅极连接清空重置信号CLR，源极连接维持控制节点netBn，漏极连接低电平VSS，用于清空重置维持控制节点netBn。第十二薄膜晶体管M12的栅极连接清空重置信号CLR，源极连接本级扫描信号Gn，漏极连接低电平VSS，用于清空重置本级扫描信号Gn。
在一些实施方式中，所述栅极驱动单元电路还包括自举电容C1，所述自举电容C1一端连接上拉控制节点netAn，另一端连接本级扫描信号Gn，用于在本级扫描信号输出期间对上拉控制节点netAn的电位进行抬升，以使上拉模块03具有足够的电流区驱动本级扫描信号。
在一些实施方式中，所述栅极驱动单元电路还包括触控维持模块06。所述触控维持模块06包括第十四薄膜晶体管M14，所述第十四薄膜晶体管M14的栅极输入触控维持控制信号TC1，源极连接本级扫描信号Gn，漏极连接低电平VSS，用于在触控扫描期间对本级扫描信号Gn进行维持。当触控扫描时正常的驱动信号会关闭，触控维持控制信号TC1会拉高对本级扫描信号进行维持，以防止 触控的传感器对栅极扫描线产生较大的耦合作用而影响画面显示和触控侦测。需要说明的是，本实施例的所述触控维持模块06适用于内嵌式触控显示屏的栅极驱动电路，若为普通的非内嵌式触控显示屏，则可以去除触控维持模块06。
在本实施例中，Gn+2为本级驱动电路单元的后两级栅极驱动单元电路的扫描信号，实际上，只要本级栅极驱动单元电路之后的栅极驱动单元电路的扫描信号如Gn+1、Gn+3、Gn+5等均可适用于本发明。同理，本级栅极驱动单元电路之前的栅极驱动单元电路的扫描信号如Gn-1、Gn-3、Gn-5等也可替代本实施例中Gn-2。同理，后面级栅极驱动单元电路中的时钟信号CKm+4为本级栅极驱动单元电路的时钟信号CKm的后四级时钟信号，实际上，其它后面级栅极驱动单元电路中的时钟信号如CKm+1、CKm+2、CKm+3等均可适用于本发明。
需要说明的是，本实施例中所述清空重置模块05、自举电容C1以及触控维持模块06是根据实际使用需要增设的功能模块，电路中是否包含上述模块不作限定，同时为了满足实际需要还可以增加其他功能模块，在此基础上的常规功能改进均应落入本发明的保护范围。
本发明实施例通过电路设计和时序搭配来实现栅极驱动电路的正反扫描的功能，利用时钟信号对上拉控制节点netAn进行清空，与现有技术相比，减少了正反扫描控制信号的数量，电路结构更为简单，同时能够改善电路中控制正反向扫描的器件阈值电压负向漂移导致电路失效的问题。
图3为根据本发明另一实施例的栅极驱动单元电路的电路示意图。如图3所示，本实施例在图2所示实施例的基础上进行改进，对上述第八薄膜晶体管M8的连接方式进行改进。其中，第八薄膜晶体管M8的栅极连接本级栅极驱动单元电路的时钟信号CKm，源极连接上拉控制节点netAn，漏极连接本级扫描信号Gn。
在一些实施方式中，还可以去除第十二薄膜晶体管M12，通过第十四薄膜晶体管M14来实现第十二薄膜晶体管M12的功能。
图4为根据本发明一实施例的栅极驱动单元电路正向扫描时的驱动波形示意图。以左右交错式单边驱动方式的驱动架构为例，如图4所示，各信号如下：
GSP1是启动脉冲信号，同时负责在正向扫描和反向扫描时进行启动；
CK1、CK3、CK5、CK7是驱动的时钟信号，正向扫描时依序输出；
TC1是触控期间的触控维持控制信号，用于在触控期间维持本级扫描信号；
VGH是恒压高电位控制信号，为本实施例中的高电平；
VSS是恒压低电位控制信号，为本实施例中的低电平；
CLR是清空重置信号，主要负责在每帧结束以及开关机时对电路内部节点进行电荷清空。
其他所示波形如netA1、netA2、netAlast-1、netAlast是电路内部节点的输出波形，G1、G2以及Glast分别为各级驱动单元电路输出的扫描信号的波形。
图5为本发明一实施例的栅极驱动单元电路反向扫描时的驱动波形示意图。以左右交错式单边驱动方式的驱动架构为例，如图5所示，各信号如下：
GSP1是启动脉冲信号，同时负责在正向扫描和反向扫描时进行启动；
CK1、CK3、CK5、CK7是驱动的时钟信号，反向扫描时倒序输出；
TC1是触控期间的触控维持控制信号，用于在触控期间维持本级扫描信号线；
VGH是恒压高电位控制信号，为本实施例中的高电平；
VSS是恒压低电位控制信号，为本实施例中的低电平；
CLR是清空重置信号，主要负责在每帧结束以及开关机时对电路内部节点进行电荷清空。
其他所示波形如netA1、netA2、netAlast-1、netAlast是电路内部节点的输出波形，G1、G2以及Glast分别为各级驱动单元电路输出的扫描信号的波形。
需要说明的是，上述实施例所涉及的电路图均为interlace驱动架构下单一级电路，即左右交错式单边驱动方式，但本发明所述栅极扫描驱动电路的应用不仅限于该方式，可以适用于任意模式的驱动架构。
本发明实施例还提出一种栅极驱动电路，包括N个级联的前述实施例所述的栅极驱动单元电路，其中N为大于1的正整数。所述栅极驱动电路可以应用于内嵌式或非内嵌式触控显示屏中，与现有技术相比，减少了正反扫描控制信 号的数量，电路结构更为简单，同时能够改善电路中控制正反向扫描的器件阈值电压负向漂移导致电路失效的问题。
本发明实施例还提出一种液晶显示装置，包括上述栅极驱动电路。在一些实施方式中，该栅极驱动电路可以是单边驱动方式，也可以是双边驱动方式。
应当说明的是，上述实施例均可根据需要自由组合。以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干变化和改进，这些变化和改进也应视为落入本发明的保护范围。

Claims (21)

  1. 一种栅极驱动单元电路，适于进行多级连接以形成栅极驱动电路，其特征在于，包括正反扫描控制模块、维持模块以及上拉模块；所述正反扫描控制模块包括正反扫描上拉控制模块，所述正反扫描上拉控制模块用于接收前面级栅极驱动单元电路的扫描信号和后面级栅极驱动单元电路的扫描信号，并在所述前面级栅极驱动单元电路的扫描信号和后面级栅极驱动单元电路的扫描信号的控制下启动电路实现正反扫描。
  2. 如权利要求1所述的栅极驱动单元电路，其特征在于，所述正反扫描上拉控制模块包括正向扫描上拉控制子模块和反向扫描上拉控制子模块；所述正向扫描上拉控制子模块用于在所述前面级栅极驱动单元电路的扫描信号的控制下启动电路实现正向扫描；所述反向扫描上拉控制子模块用于在所述后面级栅极驱动单元电路的扫描信号的控制下启动电路实现反向扫描。
  3. 如权利要求2所述的栅极驱动单元电路，其特征在于，所述正向扫描上拉控制子模块包括第一薄膜晶体管，所述第一薄膜晶体管的栅极连接所述前面级栅极驱动单元电路的扫描信号，源极连接高电平，漏极连接上拉控制节点。
  4. 如权利要求2所述的栅极驱动单元电路，其特征在于，所述反向扫描上拉控制子模块包括第十一薄膜晶体管，所述第十一薄膜晶体管的栅极连接所述后面级栅极驱动单元电路的扫描信号，源极连接高电平，漏极连接上拉控制节点。
  5. 如权利要求3所述的栅极驱动单元电路，其特征在于，第一级所述栅极驱动单元电路中的所述第一薄膜晶体管的栅极连接启动脉冲信号。
  6. 如权利要求4所述的栅极驱动单元电路，其特征在于，最后一级所述栅极驱动单元电路中的所述第十一薄膜晶体管的栅极连接启动脉冲信号。
  7. 如权利要求1所述的栅极驱动单元电路，其特征在于，所述正反扫描控制模块还包括下拉清空模块，用于在后面级栅极驱动单元电路的时钟信号的控制下对上拉控制节点进行下拉清空。
  8. 如权利要求7所述的栅极驱动单元电路，其特征在于，所述下拉清空模块包括第九薄膜晶体管；第九薄膜晶体管的栅极连接所述后面级栅极驱动 单元电路的时钟信号，源极连接上拉控制节点，漏极连接低电平。
  9. 如权利要求1所述的栅极驱动单元电路，其特征在于，所述上拉模块包括第十薄膜晶体管，所述第十薄膜晶体管的栅极连接上拉控制节点，源极连接本级栅极驱动单元电路的时钟信号，漏极连接本级扫描信号。
  10. 如权利要求1所述的栅极驱动单元电路，其特征在于，所述维持模块包括维持控制节点产生模块和节点维持模块，所述维持控制节点产生模块用于产生维持控制节点，所述节点维持模块用于基于所述维持控制节点的控制来维持电路的内部节点信号处于低电位。
  11. 如权利要求10所述的栅极驱动单元电路，其特征在于，所述维持控制节点产生模块包括第五薄膜晶体管、第六薄膜晶体管、第十六薄膜晶体管、第二十六薄膜晶体管；所述第五薄膜晶体管的栅极和源极均连接高电平，漏极连接维持控制节点；所述第六薄膜晶体管的栅极连接上拉控制节点，源极连接维持控制节点，漏极接低电平；所述第十六薄膜晶体管的栅极连接前面级栅极驱动单元电路的扫描信号，源极连接维持控制节点，漏极连接低电平；所述第二十六薄膜晶体管的栅极连接后面级栅极驱动单元电路的扫描信号，源极连接维持控制节点，漏极连接低电平。
  12. 如权利要求10所述的栅极驱动单元电路，其特征在于，所述维持控制节点产生模块包括第五薄膜晶体管、第六薄膜晶体管、第十六薄膜晶体管、第二十六薄膜晶体管；所述第五薄膜晶体管的栅极连接本级栅极驱动单元电路的时钟信号或后面级栅极驱动单元电路的时钟信号，源极连接高电平，漏极连接维持控制节点；所述第六薄膜晶体管的栅极连接上拉控制节点，源极连接维持控制节点，漏极接低电平；所述第十六薄膜晶体管的栅极连接前面级栅极驱动单元电路的扫描信号，源极连接维持控制节点，漏极连接低电平；所述第二十六薄膜晶体管的栅极连接后面级栅极驱动单元电路的扫描信号，源极连接维持控制节点，漏极连接低电平。
  13. 如权利要求10所述的栅极驱动单元电路，其特征在于，所述节点维持模块包括第八薄膜晶体管和第十三薄膜晶体管；所述第八薄膜晶体管的栅极连接维持控制节点，源极连接上拉控制节点，漏极连接低电平，用于在非 作用期间对上拉控制节点进行维持；所述第十三薄膜晶体管的栅极连接维持控制节点，源极连接本级扫描信号，漏极连接低电平，用于在非作用期间对本级扫描信号进行维持。
  14. 如权利要求10所述的栅极驱动单元电路，其特征在于，所述节点维持模块包括第八薄膜晶体管和第十三薄膜晶体管；所述第八薄膜晶体管的栅极连接本级栅极驱动单元电路的时钟信号，源极连接上拉控制节点，漏极连接本级扫描信号，用于在非作用期间对上拉控制节点进行维持；所述第十三薄膜晶体管的栅极连接维持控制节点，源极连接本级扫描信号，漏极连接低电平，用于在非作用期间对本级扫描信号进行维持。
  15. 如权利要求1所述的栅极驱动单元电路，其特征在于，还包括清空重置模块；所述清空重置模块包括第二薄膜晶体管、第三薄膜晶体管；所述第二薄膜晶体管的栅极连接清空重置信号，源极连接上拉控制节点，漏极连接低电平，用于清空重置上拉控制节点；所述第三薄膜晶体管的栅极连接清空重置信号，源极连接维持控制节点，漏极连接低电平，用于清空重置维持控制节点。
  16. 如权利要求15所述的栅极驱动单元电路，其特征在于，所述清空重置模块还包括第十二薄膜晶体管；第十二薄膜晶体管的栅极连接清空重置信号，源极连接本级扫描信号，漏极连接低电平，用于清空重置本级扫描信号。
  17. 如权利要求15所述的栅极驱动单元电路，其特征在于，还包括触控维持模块，所述触控维持模块用于在触控扫描期间对本级扫描信号进行维持。
  18. 如权利要求17所述的栅极驱动单元电路，其特征在于，所述触控维持模块包括第十四薄膜晶体管；所述第十四薄膜晶体管的栅极连接触控维持控制信号，源极连接本级扫描信号，漏极连接低电平。
  19. 如权利要求1所述的栅极驱动单元电路，其特征在于，还包括自举电容，所述自举电容一端连接上拉控制节点，另一端连接本级扫描信号。
  20. 一种栅极驱动电路，其特征在于，包括多级连接的如权利要求1-19任一项所述的栅极驱动单元电路。
  21. 一种液晶显示装置，其特征在于，包括如上述权利要求20所述的栅 极驱动电路。
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