WO2018161658A1 - 移位寄存器、栅极驱动电路及其驱动方法、显示装置 - Google Patents

移位寄存器、栅极驱动电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2018161658A1
WO2018161658A1 PCT/CN2017/114582 CN2017114582W WO2018161658A1 WO 2018161658 A1 WO2018161658 A1 WO 2018161658A1 CN 2017114582 W CN2017114582 W CN 2017114582W WO 2018161658 A1 WO2018161658 A1 WO 2018161658A1
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Prior art keywords
pull
node
module
transistor
signal input
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PCT/CN2017/114582
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English (en)
French (fr)
Inventor
孙静
刘金良
赵剑
张淼
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US16/064,834 priority Critical patent/US20210209993A1/en
Publication of WO2018161658A1 publication Critical patent/WO2018161658A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present disclosure belongs to the field of display technologies, and in particular, to a shift register, a gate driving circuit, a driving method thereof, and a display device.
  • a liquid crystal display panel is composed of a vertical and horizontal array pixel matrix.
  • a gate driving circuit is used to generate a gate scan voltage of a pixel, and a gate scan signal is output through a gate driving circuit to scan each pixel line by line. .
  • the driving circuit of the liquid crystal panel is realized by providing an integrated circuit (IC) on the periphery of the liquid crystal panel.
  • IC integrated circuit
  • GOA Gate On Array
  • Each GOA unit has a shift register composed of a plurality of thin film transistors and film capacitor devices to scan. The signals are sequentially transmitted to the next GOA unit, and the switches of the thin film transistors are turned on line by line to complete the data signal input of the pixel units.
  • the present disclosure provides a shift register, a gate driving circuit, a driving method thereof, and a display device.
  • the present disclosure provides a shift register including an input module, an output module, and a buck module;
  • the input module is connected to the signal input end and the pull-up node
  • the output module is connected to the first clock signal input end, the signal output end, the buck module and the pull-up node;
  • the buck module is further connected to the pull-up node and the signal output end;
  • the pull-up node is a node connected between an input module, an output module, and a buck module;
  • the input module is configured to charge the pull-up node to a first potential according to a signal input by the signal input end during an input phase
  • the output module is configured to pull up a potential of the pull-up node to an output stage to Second potential
  • the step-down module is configured to pull a potential of the pull-up node from the second potential to a third potential after the potential of the pull-up node is pulled up to a second potential in an output stage, wherein The third potential is greater than the first potential;
  • the output module is further configured to output, by the signal output end, the first clock signal input by the first clock signal input end under the control of the pull-up node in an output stage.
  • the buck module includes a switching transistor, a first pole of the switching transistor is connected to the output module and the pull-up node, and a second pole of the switching transistor is connected to a control electrode of the switching transistor, The output module and the signal output end, the control electrode of the switching transistor is connected to the output module and the signal output end.
  • the input module includes a first transistor, a first pole of the first transistor is connected to a signal input end, and a second pole of the first transistor is connected to a pull-up node.
  • the output module includes a third transistor and a storage capacitor
  • the first pole of the third transistor is connected to the first clock signal input end
  • the second pole of the third transistor is connected to the second end of the storage capacitor and the buck module
  • the control terminal of the third transistor is connected
  • the shift register further includes: an output reset module, a pull-up node reset module, a pull-down module, a pull-down control module, a noise reduction module, and a boost module;
  • the output reset module is connected to the reset signal input end, the first signal input end and the signal output end; the output reset module is configured to reset the signal output by the signal output end;
  • the pull-up node reset module is connected to the reset signal input end, the first signal input end, and the pull-up node; the pull-up node reset module is configured to reset the potential of the pull-up node;
  • the pull-down control module is connected to the pull-down node and the second clock signal input end, and the pull-down control module is configured to control a potential of the pull-down node according to the second clock signal input by the second clock signal input end, the pull-down a node is a connection point between the pull-down control module and the pull-down module;
  • the pull-down module is connected to the pull-down node, the pull-up node, a pull-down control module and a first signal input end, and the pull-down module is used for controlling the potential of the pull-up node Down, the potential of the pull-down node is pulled down by the first signal input by the first signal input end;
  • the noise reduction module is connected to the input module, the first signal input end, the pull-down node, the pull-up node, the output module, the signal output end and the second clock signal input end; the noise reduction module is configured to pass the first signal input end The input first signal reduces the output noise of the pull-up node and the signal output;
  • the boosting module is connected to the signal input end, the input module, the second clock signal input end, and the pull-up node; the boosting module is configured to use the second clock signal input by the second clock signal input end to the signal input end The input signal is boosted.
  • the output reset module includes a fourth transistor, a first pole of the fourth transistor is connected to the buck module, an output module, and a signal output end, and a second pole of the fourth transistor is connected to the first signal input end
  • the control electrode of the fourth transistor is connected to the reset signal input terminal.
  • the pull-up node reset module includes a second transistor, a first pole of the second transistor is connected to the pull-up node, and a second pole of the second transistor is connected to a first signal input end, The control electrode of the second transistor is connected to the reset signal input terminal.
  • the pull-down module includes a sixth transistor and an eighth transistor;
  • a first pole of the sixth transistor is connected to the pull-down node, a second pole of the sixth transistor is connected to the first signal input end, and a control pole of the sixth transistor is connected to the pull-up node;
  • the first pole of the eighth transistor is connected to the pull-down control module, the second pole of the eighth transistor is connected to the first signal input end, and the control pole of the eighth transistor is connected to the pull-up node.
  • the pull-down control module includes a fifth transistor, a ninth transistor, and a pull-down control node;
  • a first pole of the fifth transistor is connected to the first pole and the second clock signal input end of the ninth transistor, and a second pole of the fifth transistor is connected to the pull-down node, and a control pole of the fifth transistor Connecting the pull-down control node;
  • the second pole of the ninth transistor is connected to the pull-down control node, and the control pole of the ninth transistor is connected to the second clock signal input end.
  • the noise reduction module includes a tenth transistor, an eleventh transistor, and a twelfth transistor;
  • the first pole of the tenth transistor is connected to the input module and the pull-up node, the second pole of the tenth transistor is connected to the first signal input end, and the control pole of the tenth transistor is connected to the pull-down node;
  • a first pole of the eleventh transistor is connected to the output module and a signal output end, a second pole of the eleventh transistor is connected to the first signal input end, and a control pole of the eleventh transistor is connected to the pull-down node;
  • a first pole of the twelfth transistor is connected to the signal output end, a second pole of the twelfth transistor is connected to the first signal input end, and a control pole of the twelfth transistor is connected to the second signal Clock signal input.
  • the boosting module includes a thirteenth transistor
  • the first pole of the thirteenth transistor is connected to the signal input end
  • the second pole of the thirteenth transistor is connected to the pull-up node
  • the control pole of the thirteenth transistor is connected to the second clock signal input end.
  • the present disclosure also provides a gate driving circuit, the gate driving circuit comprising a plurality of stages of the shift register of any one of the above,
  • the signal output from the signal output terminal of each stage of the shift register is used to drive a gate line and a reset signal as a reset signal terminal of the shift register of the shift register.
  • the present disclosure also provides a display device including the above-described gate driving circuit.
  • the present disclosure further provides a driving method of a gate driving circuit, where the gate driving circuit includes the shift register of any one of the above steps, and the driving method includes:
  • the pull-up node is charged to a first potential by the input module according to a signal input by the signal input end;
  • the potential of the pull-up node is pulled up to a second potential by the output module, and the first clock input by the first clock signal input end is controlled under the control of the pull-up node a signal is output through the signal output terminal; the potential of the pull-up node is pulled from the second potential to a third potential by the buck module, wherein the third potential is greater than the first potential.
  • the driving method of the gate driving circuit further includes:
  • FIG. 1 is a schematic structural diagram of a shift register according to an embodiment of the present disclosure
  • FIG. 2 is a circuit schematic diagram of a shift register in accordance with an embodiment of the present disclosure
  • FIG. 3 is an operational timing diagram of a shift register in accordance with an embodiment of the present disclosure
  • FIG. 4 is a schematic structural diagram of a shift register according to an embodiment of the present disclosure.
  • FIG. 5 is a circuit schematic diagram of a shift register in accordance with an embodiment of the present disclosure.
  • FIG. 6 is an operational timing diagram of a shift register in accordance with an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 8 is a flow chart showing a driving method of a gate driving circuit according to an embodiment of the present disclosure.
  • a liquid crystal display panel is composed of a vertical and horizontal array pixel matrix.
  • a gate driving circuit is used to generate a gate scan voltage of a pixel, and a gate scan signal is output through a gate driving circuit to scan each pixel line by line. .
  • the driving circuit of the liquid crystal panel is set through the periphery of the liquid crystal panel.
  • An integrated circuit (IC) is realized.
  • GOA Gate On Array
  • Each GOA unit has a shift register composed of a plurality of thin film transistors and film capacitor devices to scan. The signals are sequentially transmitted to the next GOA unit, and the switches of the thin film transistors are turned on line by line to complete the data signal input of the pixel units.
  • the GOA driving circuit is used to directly form the GOA unit on the array substrate, which can save the Gate driving IC and reduce the production cost. At the same time, the Gate IC bonding process is omitted, the output of the product is improved, and the narrow frame is facilitated. Therefore, the GOA drive circuit has been more and more widely used.
  • the existing GOA unit realizes the shift output of each row of the array panel by the clock signal (CLK), the output signal of the previous row is used as the input signal of the next row, and the output signal of the next row is used as the reset signal of the previous row.
  • CLK clock signal
  • the bootstrap effect of the capacitor in the GOA driving circuit causes the potential of the pull-up node (PU) to instantaneously rise to about twice the output voltage, thereby connecting the gate to the PU point.
  • the characteristic curve of the TFT device drifts, which affects the normal operation of some TFT devices, and causes display defects such as abnormal display (AD) on the liquid crystal panel.
  • the present disclosure particularly provides a shift register, a gate drive circuit, a method of driving the same, and a display device that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
  • the transistor used in the embodiment of the present disclosure may be a thin film transistor or a field effect transistor or other device of the same characteristics. Since the source and the drain of the transistor used are symmetrical, the source and the drain are indistinguishable. .
  • one pole is referred to as a first pole
  • the other pole is referred to as a second pole
  • the gate is referred to as a gate.
  • the transistors can be classified into an N-type and a P-type according to the characteristics of the transistors, and the following embodiments are described as N-type transistors.
  • the source of the first very N-type transistor and the drain of the second N-type transistor are turned on.
  • the gate input is high, the source and the drain are turned on, and the P-type transistor is reversed. It is conceivable that the implementation of the P-type transistor is easily conceivable by those skilled in the art without any creative effort, and is therefore within the scope of protection of the embodiments of the present disclosure.
  • Embodiments of the present disclosure provide a shift register.
  • the shift register includes an input module 1, an output module 2, and a buck module 3.
  • FIG. 1 is a schematic structural diagram of a shift register according to an embodiment of the present disclosure.
  • the input module 1 is connected to the signal input terminal INPUT and the pull-up node PU;
  • the output module 2 is connected to the first clock signal input terminal CLKA, the signal output terminal OUTPUT, the buck module 3, and the pull-up node PU;
  • 3 is also connected to the pull-up node PU and the signal output terminal OUTPUT;
  • the pull-up node PU is a node connected between the input module 1, the output module 2 and the buck module 3.
  • the input module 1 is configured to charge the pull-up node PU to a first potential according to a signal input by the signal input terminal INPUT during the input phase.
  • the output module 2 is used to pull up the potential of the pull-up node PU to the second potential during the output phase.
  • the buck module 3 is configured to pull the potential of the pull-up node PU from the second potential to the third potential after the potential of the pull-up node PU is pulled up to the second potential in the output stage, wherein the third potential is greater than the third potential One potential.
  • the output module 2 is further configured to output the first clock signal input by the first clock signal input terminal CLKA through the signal output terminal OUTPUT under the control of the pull-up node PU in the output stage.
  • the input module 1, the output module 2, and the buck module 3 are all connected to the pull-up node PU.
  • the input module 1 transmits the signal input by the signal input terminal INPUT to the pull-up node PU to raise the potential of the pull-up node PU to the first potential; at the instant of the output phase, the output module 2 will pull up the node.
  • the potential of the PU is pulled up from the first potential to the second potential; subsequently (still in the output stage), the buck module 3 pulls the potential of the pull-up node PU from the second potential to the third potential, wherein the third potential is greater than The first potential.
  • the buck module 3 pulls down the potential of the pull-up node PU, the characteristic curve of the TFT device connected to the pull-up node can be prevented from drifting, and the TFT device can be normally operated to avoid the AD panel of the liquid crystal panel. Poor display.
  • the third potential is greater than the first potential, but if the output time of the signal output terminal OUTPUT is sufficiently long, the third potential may be equal to the first potential, and details are not described herein again.
  • the buck module 3 includes a switching transistor TFT1, the first electrode of the switching transistor TFT1 is connected to the output module 2 and the pull-up node PU, and the second electrode of the switching transistor TFT1 is connected to the switching transistor TFT1.
  • the control electrode, the output module 2 and the signal output terminal OUTPUT, the control electrode of the switching transistor TFT1 is connected to the output module 2 and the signal output terminal OUTPUT.
  • the input module 1 includes a first transistor M1, a first pole of the first transistor M1 is connected to the signal input terminal INPUT, and a second pole of the first transistor M1 is connected to the pull-up node PU.
  • the output module 2 includes a third transistor M3 and a storage capacitor C1; the first electrode of the third transistor M3 is connected to the first clock signal input terminal CLKA, and the second electrode of the third transistor M3 A second end of the storage capacitor C1 is connected to the buck module 3.
  • the control electrode of the third transistor M3 is connected to the pull-up node PU and the first end of the storage capacitor C1.
  • FIG. 3 is an operational timing diagram of a shift register in accordance with an embodiment of the present disclosure.
  • the signal input terminal INPUT inputs a high level
  • the first transistor M1 is turned on, the potential of the pull-up node PU is raised to the first potential, and at the same time, the storage capacitor C1 is charged;
  • the three-transistor M3 is turned on.
  • the first clock signal (low level) input from the first clock signal input terminal CLKA is output from the signal output terminal OUTPUT.
  • the signal input terminal INPUT inputs a low level
  • the first transistor M1 is turned off, but due to the existence of the storage capacitor C1, the potential of the pull-up node PU continues to rise to the second potential (V1),
  • the third transistor M3 remains open.
  • the first clock signal input terminal CLKA inputs the first clock signal (high level), and the first clock signal (high level) is output from the signal output terminal OUTPUT (ie, the signal input to the signal input terminal INPUT of the next row)
  • the voltage of the pull-up node PU rises to about twice the voltage outputted by the signal output terminal OUTPUT, and the switching transistor TFT1 is turned on, so that the pull-up node PU and the signal output terminal OUTPUT pass.
  • the switching transistor TFT1 constitutes a loop, so that the potential of the pull-up node PU rapidly drops to the third The potential (V1'), that is, V1' ⁇ V1.
  • the switching transistor TFT1 since the switching transistor TFT1 is turned on, the potential of the pull-up node PU at the beginning of the output phase is pulled down, thereby avoiding the TFT device characteristic curve of the gate connected to the pull-up node PU.
  • the drift occurs, and the TFT device operates normally to prevent the LCD panel from displaying defects such as AD.
  • the shift register of this embodiment includes an input module 1, an output module 2, and a buck module 3.
  • the buck module 3 can be pulled up after the potential of the pull-up node PU is pulled up to the second potential.
  • the potential of the pull node PU is pulled from the second potential to the third potential, so that the voltage of the pull-up node PU is rapidly lowered to prevent the characteristic curve of the TFT device connected to the pull-up node PU from drifting, thereby making the TFT
  • the device works normally to avoid display defects such as AD on the LCD panel.
  • Embodiments of the present disclosure also provide a shift register.
  • the shift register of this embodiment has a structure similar to that of the shift register of the embodiment shown in FIG. 1, and the difference is that the shift register of the embodiment further includes: an output reset module 4, and a pull-up The node reset module 5, the pull-down module 6, the pull-down control module 7, the noise reduction module 8, and the boost module 9.
  • FIG. 4 is a schematic structural diagram of a shift register according to an embodiment of the present disclosure
  • FIG. 5 is a circuit schematic diagram of a shift register according to an embodiment of the present disclosure
  • FIG. 6 is a shift register according to an embodiment of the present disclosure. Working timing diagram.
  • the output reset module 4 is connected to the reset signal input terminal RESET, the first signal input terminal VSS and the signal output terminal OUTPUT; and the output reset module 4 is configured to reset the signal output from the signal output terminal OUTPUT.
  • the output reset module 4 includes a fourth transistor M4, and the first electrode of the fourth transistor M4 is connected to the buck module 3, the output module 2, and the signal output terminal OUTPUT, and the fourth transistor M4
  • the second pole is connected to the first signal input terminal VSS, and the gate of the fourth transistor M4 is connected to the reset signal input terminal RESET.
  • the pull-up node reset module 5 is connected to the reset signal input terminal RESET, the first signal input terminal VSS and the pull-up node PU; and the pull-up node reset module 5 is configured to reset the potential of the pull-up node PU.
  • the pull-up node reset module 5 includes a second transistor M2, and the first pole of the second transistor M2 is connected to the pull-up node PU, and the second transistor M2 The second pole is connected to the first signal input terminal VSS, and the gate of the second transistor M2 is connected to the reset signal input terminal RESET.
  • the pull-down control module 7 is connected to the pull-down node PD and the second clock signal input terminal CLKB, and the pull-down control module 7 is configured to control the potential of the pull-down node PD according to the second clock signal input by the second clock signal input terminal CLKB.
  • the pull-down node PD is a connection point of the pull-down control module 7 and the pull-down module 6.
  • the pull-down control module 7 includes a fifth transistor M5, a ninth transistor M9, and a pull-down control node PD_CN.
  • the first pole of the fifth transistor M5 is connected to the first pole of the ninth transistor M9 and the second clock signal input terminal CLKB, the second pole of the fifth transistor M5 is connected to the pull-down node PD, and the gate of the fifth transistor M5 is connected to the pull-down control node. PD_CN.
  • the second pole of the ninth transistor M9 is connected to the pull-down control node PD_CN, and the gate of the ninth transistor M9 is connected to the second clock signal input terminal CLKB.
  • the pull-down module 6 is connected to the pull-down node PD, the pull-up node PU, the pull-down control module 7 and the first signal input terminal VSS, and the pull-down module 6 is used to pass the first under the control of the potential of the pull-up node PU.
  • the first signal input by the signal input terminal VSS pulls down the potential of the pull-down node PD.
  • the pull-down module 6 includes a sixth transistor M6 and an eighth transistor M8.
  • the first pole of the sixth transistor M6 is connected to the pull-down node PD, the second pole of the sixth transistor M6 is connected to the first signal input terminal VSS, and the gate of the sixth transistor M6 is connected to the pull-up node PU.
  • the first pole of the eighth transistor M8 is connected to the pull-down control module 7, the second pole of the eighth transistor M8 is connected to the first signal input terminal VSS, and the control pole of the eighth transistor M8 is connected to the pull-up node PU.
  • the noise reduction module 8 is connected to the input module 1, the first signal input terminal VSS, the pull-down node PD, the pull-up node PU, the output module 2, the signal output terminal OUTPUT, and the second clock signal input terminal CLKB;
  • the module 8 is configured to reduce the output noise of the pull-up node PU and the signal output terminal OUTPUT through the first signal input by the first signal input terminal VSS.
  • the noise reduction module 8 includes a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12.
  • the first pole of the tenth transistor M10 is connected to the input module 1 and the pull-up node PU, the second pole of the tenth transistor M10 is connected to the first signal input terminal VSS, and the gate of the tenth transistor M10 is connected to the pull-down node PD.
  • the first pole of the eleventh transistor M11 is connected to the output module 2 and the signal output terminal OUTPUT, the second pole of the eleventh transistor M11 is connected to the first signal input terminal VSS, and the gate of the eleventh transistor M11 is connected to the pull-down node PD.
  • the first pole of the twelfth transistor M12 is connected to the signal output terminal OUTPUT, the second pole of the twelfth transistor M12 is connected to the first signal input terminal VSS, and the control electrode of the twelfth transistor M12 is connected to the second clock signal input terminal CLKB.
  • the boosting module 9 is connected to the signal input terminal INPUT, the input module 1, the second clock signal input terminal CLKB, and the pull-up node PU; the boosting module 9 is configured to input according to the second clock signal input terminal CLKB.
  • the second clock signal boosts the signal input to the signal input terminal INPUT.
  • the boosting module 9 includes a thirteenth transistor M13, the first pole of the thirteenth transistor M13 is connected to the signal input terminal INPUT, and the second pole of the thirteenth transistor M13 is connected to the pullup.
  • the node PU, the control electrode of the thirteenth transistor M13 is connected to the second clock signal input terminal CLKB.
  • the shift register of the present embodiment (output reset module 4, pull-up node reset module 5, pull-down module 6, pull-down control module 7, noise reduction module 8, and boost module 9)
  • the working principle is explained.
  • the first signal input terminal VSS always outputs a low level in the shift register.
  • the second clock signal input terminal CLKB inputs a high level, and the thirteenth transistor M13 is turned on to boost the potential of the pull-up node PU.
  • the pull-up node PU is at a high level, and the sixth transistor M6 and the eighth transistor M8 are turned on, so that the pull-down node PD and the pull-down control node PD_CN are respectively connected to the first signal input terminal VSS, so that The potential of the pull-down node PD is pulled down to low
  • the level (the pull-down control node PD_CN is also pulled down to a low level to avoid affecting the potential of the pull-down node PD), turning off the tenth transistor M10 and the eleventh transistor M11, thereby avoiding the pull-up caused by the opening of the tenth transistor M10
  • the potential of the node PU is unstable and the signal output from the signal output terminal OUTPUT due to the opening of the eleventh transistor M11 is unstable.
  • a reset noise reduction phase is also included.
  • the reset signal input terminal RESET inputs a high level, the second transistor M2 is turned on, and the pull-up node PU is connected to the first signal input terminal VSS through the second transistor M2, so that the potential of the pull-up node PU is from the third potential V1' Pulled low to low level to reset the potential of the pull-up node PU;
  • the first clock signal input terminal CLKA inputs a low level. Since the pull-up node PU is at a low level, the third transistor M3 is turned off, and at the same time, the second clock signal input terminal CLKB is input to a high level, and the ninth transistor M9 is turned on. At this time, the second clock signal input terminal CLKB is in communication with the pull-down control node PD_CN, the potential of the pull-down control node PD_CN is raised, the fifth transistor M5 is turned on, and the pull-down node PD is connected to the second clock signal input terminal CLKB, and the pull-down node PD is The potential is high;
  • the potential of the pull-down node PD is at a high level, so that the eleventh transistor M11 is turned on, and the second clock signal input terminal CLKB is input to a high level, so that the twelfth transistor M12 is turned on.
  • the signal output terminal OUTPUT passes the first
  • the eleven transistor M11 and the twelfth transistor M12 are connected to the first signal input terminal VSS, so that the potential of the signal output terminal OUTPUT is pulled to a low level to reduce the output noise of the signal output terminal OUTPUT;
  • the potential of the pull-down node PD is at a high level, so that the tenth transistor M10 is turned on.
  • the pull-up node PU is connected to the first signal input terminal VSS through the tenth transistor M10, so that the potential of the pull-up node PU is pulled. Low level to reduce the output noise of the pull-up node PU.
  • the shift register of this embodiment includes an input module 1, an output module 2, and a buck module 3.
  • the buck module 3 can be pulled up after the potential of the pull-up node PU is pulled up to the second potential.
  • the potential of the pull node PU is pulled from the second potential to the third potential, so that the voltage of the pull-up node PU is rapidly lowered to prevent the characteristic curve of the TFT device connected to the pull-up node PU from drifting, thereby making the TFT
  • the device works normally to avoid display defects such as AD on the LCD panel.
  • FIG. 7 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • the gate drive circuit includes a plurality of stages of shift registers as shown in the embodiment of Figure 1 (shown in phantom in Figure 7).
  • the signal output by the gate drive signal generating unit of each stage shift register is used as an input signal of the signal input end of the shift register of the shift register; the signal outputted by the signal output end of each stage shift register A reset signal for driving a gate line and a reset signal terminal of the shift register of the shift register.
  • the signal outputted from the output of each stage of the shift register is used to drive a gate line connected to the display area (ie, the AA area) of the display panel.
  • the gate driving circuit of the embodiment includes a plurality of shift registers as shown in the embodiment of FIG. 1. For details, refer to the shift register of the embodiment shown in FIG. 1, and details are not described herein again.
  • the gate driving circuit of this embodiment includes a plurality of shift registers of the embodiment shown in FIG. 1.
  • the shift register includes an input module, an output module, and a buck module.
  • the buck module can be on the After the potential of the pull-up node is pulled up to the second potential, the potential of the pull-up node is pulled from the second potential to the third potential, so that the voltage of the pull-up node is rapidly lowered to prevent the gate from being connected to the pull-up node.
  • the characteristic curve of the TFT device drifts, so that the TFT device works normally to avoid display defects such as AD in the liquid crystal panel.
  • Embodiments of the present disclosure also provide a display device including a gate drive circuit as in the embodiment shown in FIG.
  • the display device can be any product or component having a display function, such as a liquid crystal display panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device of this embodiment includes a gate driving circuit of the embodiment shown in FIG.
  • the shift register includes an input module, an output module, and a buck module.
  • the buck module can pull the potential of the pull-up node from the second potential after the potential of the pull-up node is pulled up to the second potential. Pulling down to the third potential, so that the voltage of the pull-up node is rapidly reduced to prevent the characteristic curve of the TFT device connected to the pull-up node from drifting, thereby enabling the TFT device to work normally to avoid the AD panel of the liquid crystal panel. Poor display.
  • Embodiments of the present disclosure also provide a driving method of a gate driving circuit.
  • FIG. 8 is a flow chart showing a driving method of a gate driving circuit according to an embodiment of the present disclosure.
  • the gate driving circuit includes a plurality of stages of the embodiment or the shift register as shown in FIG. 1 or FIG. 4, as shown in FIG. 8, the driving method includes:
  • the input module charges the pull-up node to the first potential based on the signal input at the signal input.
  • the potential of the pull-up node is pulled up to the second potential through the output module, and under the control of the pull-up node, the first clock signal input by the first clock signal input end is output through the signal output end. Pulling the potential of the pull-up node from the second potential to the third potential through the buck module, wherein the third potential is greater than the first potential.
  • the driving method further includes:
  • the signal output from the signal output and the potential of the pull-up node are reset.
  • the shift register when the gate driving circuit of the embodiment shown in FIG. 4 is driven, the shift register includes an input module, an output module, and a buck module.
  • the buck module can pull the potential of the pull-up node from the second potential to the third potential after the potential of the pull-up node is pulled up to the second potential, so that the voltage of the pull-up node is rapidly lowered to avoid the gate.
  • the characteristic curve of the TFT device connected to the pull-up node is drifted, so that the TFT device works normally to avoid display defects such as AD in the liquid crystal panel.

Abstract

公开了一种移位寄存器、栅极驱动电路及其驱动方法、显示装置。该移位寄存器包括输入模块（1）、输出模块（2）、降压模块（3）；输入模块（1），用于在输入阶段，根据信号输入端（INPUT）所输入的信号，对上拉节点（PU）充电至第一电位；输出模块（2），用于在输出阶段，将上拉节点（PU）的电位上拉至第二电位；降压模块（3），用于在输出阶段，上拉节点（PU）的电位被上拉至第二电位后，将上拉节点（PU）的电位从第二电位拉低至第三电位，其中，第三电位大于第一电位；输出模块（3），还用于在输出阶段，在上拉节点（PU）的控制下，将第一时钟信号（CLK）输入端所输入的第一时钟信号，通过信号输出端（OUTPUT）进行输出。

Description

移位寄存器、栅极驱动电路及其驱动方法、显示装置 技术领域
本公开属于显示技术领域，具体涉及一种移位寄存器、栅极驱动电路及其驱动方法、显示装置。
背景技术
通常，液晶显示面板由垂直和水平阵列式像素矩阵组成，在显示过程中，栅极驱动电路用于产生像素的栅极扫描电压，通过栅极驱动电路输出栅极扫描信号，逐行扫描各像素。
在现有技术中，液晶面板的驱动电路通过在液晶面板外围设置集成电路(Integrated Circuit，IC)得以实现。相比之下，GOA(Gate On Array)是一种将栅极驱动电路集成于阵列基板上的技术，每个GOA单元均有一个由多个薄膜晶体管及薄膜电容器件构成的移位寄存器将扫描信号依次传递给下一GOA单元，逐行开启薄膜晶体管的开关，完成像素单元的数据信号输入。
发明内容
本公开提供了一种移位寄存器、栅极驱动电路及其驱动方法、显示装置。
一方面，本公开提供了一种移位寄存器，包括输入模块、输出模块、降压模块；
所述输入模块连接信号输入端和上拉节点；
所述输出模块连接第一时钟信号输入端、信号输出端、降压模块和上拉节点；
所述降压模块还连接上拉节点和信号输出端；
所述上拉节点为输入模块、输出模块和降压模块之间连接的节点；
所述输入模块，用于在输入阶段，根据所述信号输入端所输入的信号，对所述上拉节点充电至第一电位；
所述输出模块，用于在输出阶段，将所述上拉节点的电位上拉至 第二电位；
所述降压模块，用于在输出阶段，所述上拉节点的电位被上拉至第二电位后，将所述上拉节点的电位从所述第二电位拉低至第三电位，其中，第三电位大于第一电位；
所述输出模块，还用于在输出阶段，在所述上拉节点的控制下，将所述第一时钟信号输入端所输入的第一时钟信号，通过所述信号输出端进行输出。
可选地，所述降压模块包括开关晶体管，所述开关晶体管的第一极连接所述输出模块和所述上拉节点，所述开关晶体管的第二极连接所述开关晶体管的控制极、所述输出模块和所述信号输出端，所述开关晶体管的控制极连接所述输出模块和所述信号输出端。
可选地，所述输入模块包括第一晶体管，所述第一晶体管的第一极连接信号输入端，所述第一晶体管的第二极连接上拉节点。
可选地，所述输出模块包括第三晶体管和存储电容器；
所述第三晶体管的第一极连接第一时钟信号输入端，所述第三晶体管的第二极连接所述存储电容器的第二端和降压模块，所述第三晶体管的控制极连接所述上拉节点和所述存储电容器的第一端。
可选地，所述移位寄存器还包括：输出复位模块、上拉节点复位模块、下拉模块、下拉控制模块、降噪模块和升压模块；
所述输出复位模块连接复位信号输入端、第一信号输入端和信号输出端；所述输出复位模块用于将所述信号输出端输出的信号复位；
所述上拉节点复位模块连接复位信号输入端、第一信号输入端和所述上拉节点；所述上拉节点复位模块用于将所述上拉节点的电位复位；
所述下拉控制模块连接下拉节点和第二时钟信号输入端，所述下拉控制模块用于根据所述第二时钟信号输入端所输入的第二时钟信号控制所述下拉节点的电位，所述下拉节点为所述下拉控制模块与所述下拉模块的连接点；
所述下拉模块连接所述下拉节点、所述上拉节点、下拉控制模块和第一信号输入端，所述下拉模块用于在所述上拉节点的电位的控制 下，通过所述第一信号输入端所输入的第一信号将所述下拉节点的电位进行下拉；
所述降噪模块连接输入模块、第一信号输入端、下拉节点、上拉节点、输出模块、信号输出端和第二时钟信号输入端；所述降噪模块用于通过第一信号输入端所输入的第一信号降低上拉节点和信号输出端的输出噪声；
所述升压模块连接信号输入端、输入模块、第二时钟信号输入端和上拉节点；所述升压模块用于根据第二时钟信号输入端所输入的第二时钟信号对信号输入端所输入的信号进行升压。
可选地，所述输出复位模块包括第四晶体管，所述第四晶体管的第一极连接降压模块、输出模块和信号输出端，所述第四晶体管的第二极连接第一信号输入端，所述第四晶体管的控制极连接复位信号输入端。
可选地，所述上拉节点复位模块包括第二晶体管，所述第二晶体管的第一极连接所述上拉节点，所述第二晶体管的第二极连接第一信号输入端，所述第二晶体管的控制极连接复位信号输入端。
可选地，所述下拉模块包括第六晶体管和第八晶体管；
所述第六晶体管的第一极连接所述下拉节点，所述第六晶体管的第二极连接所述第一信号输入端，所述第六晶体管的控制极连接所述上拉节点；
所述第八晶体管的第一极连接所述下拉控制模块，所述第八晶体管的第二极连接所述第一信号输入端，所述第八晶体管的控制极连接所述上拉节点。
可选地，所述下拉控制模块包括第五晶体管、第九晶体管和下拉控制节点；
所述第五晶体管的第一极连接所述第九晶体管的第一极和第二时钟信号输入端，所述第五晶体管的第二极连接所述下拉节点，所述第五晶体管的控制极连接所述下拉控制节点；
所述第九晶体管的第二极连接所述下拉控制节点，所述第九晶体管的控制极连接所述第二时钟信号输入端。
可选地，所述降噪模块包括第十晶体管、第十一晶体管和第十二晶体管；
所述第十晶体管的第一极连接输入模块和上拉节点，所述第十晶体管的第二极连接所述第一信号输入端，所述第十晶体管的控制极连接所述下拉节点；
所述第十一晶体管的第一极连接输出模块和信号输出端，所述第十一晶体管的第二极连接所述第一信号输入端，所述第十一晶体管的控制极连接所述下拉节点；
所述第十二晶体管的第一极连接所述信号输出端，所述第十二晶体管的第二极连接所述第一信号输入端，所述第十二晶体管的控制极连接所述第二时钟信号输入端。
可选地，所述升压模块包括第十三晶体管；
所述第十三晶体管的第一极连接信号输入端，所述第十三晶体管的第二极连接上拉节点，所述第十三晶体管的控制极连接第二时钟信号输入端。
另一方面，本公开还提供一种栅极驱动电路，所述栅极驱动电路包括多级上述任意一项的所述移位寄存器，
每一级所述移位寄存器的栅极驱动信号生成单元所输出的信号作为该移位寄存器的下一级移位寄存器的信号输入端的输入信号；
每一级所述移位寄存器的信号输出端所输出的信号用于驱动一根栅线以及作为该移位寄存器的上一级移位寄存器的复位信号端的复位信号。
另一方面，本公开还提供一种显示装置，所述显示装置包括上述的栅极驱动电路。
另一方面，本公开还提供一种栅极驱动电路的驱动方法，所述栅极驱动电路包括多级上述任意一项的所述移位寄存器，所述驱动方法包括：
在输入阶段，通过所述输入模块根据所述信号输入端所输入的信号，对所述上拉节点充电至第一电位；
在输出阶段，通过所述输出模块将所述上拉节点的电位上拉至第二电位，并在所述上拉节点的控制下，将所述第一时钟信号输入端所输入的第一时钟信号，通过所述信号输出端进行输出；通过所述降压模块将所述上拉节点的电位从所述第二电位拉低至第三电位，其中，第三电位大于第一电位。
可选地，采用上述的移位寄存器时，所述栅极驱动电路的驱动方法还包括：
在复位降噪阶段：将信号输出端输出的信号和上拉节点的电位复位。
附图说明
图1为根据本公开的实施例的移位寄存器的结构示意图；
图2为根据本公开的实施例的移位寄存器的电路原理图；
图3为根据本公开的实施例的移位寄存器的工作时序图；
图4为根据本公开的实施例的移位寄存器的结构示意图；
图5为根据本公开的实施例的移位寄存器的电路原理图；
图6为根据本公开的实施例的移位寄存器的工作时序图；
图7为根据本公开的实施例的栅极驱动电路的结构示意图；
图8为根据本公开的实施例的栅极驱动电路的驱动方法的流程示意图。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施方式对本公开作进一步详细描述。
通常，液晶显示面板由垂直和水平阵列式像素矩阵组成，在显示过程中，栅极驱动电路用于产生像素的栅极扫描电压，通过栅极驱动电路输出栅极扫描信号，逐行扫描各像素。
在现有技术中，液晶面板的驱动电路通过在液晶面板外围设置集 成电路(Integrated Circuit，IC)得以实现。相比之下，GOA(Gate On Array)是一种将栅极驱动电路集成于阵列基板上的技术，每个GOA单元均有一个由多个薄膜晶体管及薄膜电容器件构成的移位寄存器将扫描信号依次传递给下一GOA单元，逐行开启薄膜晶体管的开关，完成像素单元的数据信号输入。
采用GOA驱动电路，将GOA单元直接制成在阵列基板上，能够节省Gate驱动IC，降低了生产成本，同时，省去Gate IC bonding工艺，提升了产品的产量，且便于实现窄边框。因而，GOA驱动电路得到了越来越广泛的应用。
现有的GOA单元通过时钟信号(CLK)实现阵列面板每一行的移位输出，上一行的输出信号作为下一行的输入信号，下一行的输出信号作为上一行的复位信号。但当每一行的信号输出时，因GOA驱动电路中的电容器的自举效应会导致上拉节点(PU)的电位瞬间升高为输出电压的约两倍，从而使栅极与PU点相连的TFT器件的特性曲线发生漂移，影响部分TFT器件的正常工作，进而造成液晶面板产生画面显示异常(AD)等显示不良。
因此，本公开特别提供了一种移位寄存器、栅极驱动电路及其驱动方法、显示装置，其实质上消除了由于现有技术的限制和缺陷而导致的问题中的一个或多个。
本公开实施例中的所采用的晶体管可以为薄膜晶体管或场效应管或相同特性的其它器件，由于采用的晶体管的源极和漏极是对称的，所以其源极、漏极是没有区别的。在本公开实施例中，为区分晶体管的源极和漏极，将其一极称为第一极，另一极称为第二极，栅极称为控制极。此外按照晶体管的特性区分可以将晶体管分为N型和P型，以下实施例中是以N型晶体管进行说明的。当采用N型晶体管时，第一极为N型晶体管的源极，第二极为N型晶体管的漏极，栅极输入高电平时，源、漏极导通，P型晶体管则相反。可以想到的是，采用P型晶体管实现是本领域技术人员可以在没有付出创造性劳动前提下轻易想到的，因此也是在本公开实施例的保护范围内的。
本公开实施例提供一种移位寄存器。参照图1至图3，所述移位寄存器包括输入模块1、输出模块2、降压模块3。
图1为根据本公开的实施例的移位寄存器的结构示意图。如图1所示，输入模块1连接信号输入端INPUT和上拉节点PU；输出模块2连接第一时钟信号输入端CLKA、信号输出端OUTPUT、降压模块3和上拉节点PU；降压模块3还连接上拉节点PU和信号输出端OUTPUT；上拉节点PU为输入模块1、输出模块2和降压模块3之间连接的节点。
输入模块1用于在输入阶段，根据信号输入端INPUT所输入的信号，对上拉节点PU充电至第一电位。
输出模块2用于在输出阶段，将上拉节点PU的电位上拉至第二电位。
降压模块3用于在输出阶段，上拉节点PU的电位被上拉至第二电位后，将上拉节点PU的电位从第二电位拉低至第三电位，其中，第三电位大于第一电位。
输出模块2还用于在输出阶段，在上拉节点PU的控制下，将第一时钟信号输入端CLKA所输入的第一时钟信号，通过信号输出端OUTPUT进行输出。
从图1中可以看出，输入模块1、输出模块2和降压模块3均与上拉节点PU连接。在输入阶段，输入模块1将信号输入端INPUT所输入的信号传输至上拉节点PU，以使上拉节点PU的电位上升至第一电位；在输出阶段开始的瞬间，输出模块2将上拉节点PU的电位由第一电位上拉至第二电位；随后(仍为输出阶段)，降压模块3将上拉节点PU的电位从第二电位拉低至第三电位，其中，第三电位大于第一电位。此时，由于降压模块3拉低了上拉节点PU的电位，能够避免栅极与上拉节点相连的TFT器件的特性曲线发生漂移，进而使TFT器件正常工作，以避免液晶面板产生AD等显示不良。
需要说明的是，在一般情况下，第三电位大于第一电位，但若信号输出端OUTPUT的输出时间足够长，第三电位有可能等于第一电位，在此不再赘述。
图2为根据本公开的实施例的移位寄存器的电路原理图。如图2所示，在本实施例中，降压模块3包括开关晶体管TFT1，开关晶体管TFT1的第一极连接输出模块2和上拉节点PU，开关晶体管TFT1的第二极连接开关晶体管TFT1的控制极、输出模块2和信号输出端OUTPUT，开关晶体管TFT1的控制极连接输出模块2和信号输出端OUTPUT。
如图2所示，在本实施例中，输入模块1包括第一晶体管M1，第一晶体管M1的第一极连接信号输入端INPUT，第一晶体管M1的第二极连接上拉节点PU。
如图2所示，在本实施例中，输出模块2包括第三晶体管M3和存储电容器C1；第三晶体管M3的第一极连接第一时钟信号输入端CLKA，第三晶体管M3的第二极连接存储电容器C1的第二端和降压模块3，第三晶体管M3的控制极连接上拉节点PU和存储电容器C1的第一端。
下面，参照图3对本实施例的移位寄存器的工作原理进行说明。图3为根据本公开的实施例的移位寄存器的工作时序图。
如图3所示，在输入阶段，信号输入端INPUT输入高电平，第一晶体管M1开启，使上拉节点PU的电位上升至第一电位，同时，对存储电容器C1进行充电；另外，第三晶体管M3开启，此时，第一时钟信号输入端CLKA输入的第一时钟信号(低电平)从信号输出端OUTPUT输出。
如图3所示，在输出阶段，信号输入端INPUT输入低电平，第一晶体管M1关闭，但由于存储电容器C1的存在，上拉节点PU的电位继续升高至第二电位(V1)，第三晶体管M3保持开启。此时，第一时钟信号输入端CLKA输入第一时钟信号(高电平)，第一时钟信号(高电平)从信号输出端OUTPUT输出(即为下一行的信号输入端INPUT输入的信号)，而由于存储电容器C1的自举作用，上拉节点PU的电压升高为信号输出端OUTPUT输出的电压的约两倍，同时将开关晶体管TFT1开启，使得上拉节点PU与信号输出端OUTPUT通过开关晶体管TFT1构成回路，使上拉节点PU的电位迅速下降至第三 电位(V1’)，即V1’＜V1。
也就是说，在输出阶段开始后的一段时间时，由于开关晶体管TFT1开启，拉低了输出阶段开始瞬间上拉节点PU的电位，从而避免了栅极与上拉节点PU相连的TFT器件特性曲线发生漂移，进而使TFT器件正常工作，以避免液晶面板产生AD等显示不良。
本实施例的移位寄存器，包括输入模块1、输出模块2、降压模块3，在输出阶段，该降压模块3能够在上拉节点PU的电位被上拉至第二电位后，将上拉节点PU的电位从第二电位拉低至第三电位，从而使上拉节点PU的电压被迅速降低，以避免栅极与上拉节点PU相连的TFT器件的特性曲线发生漂移，进而使TFT器件正常工作，以避免液晶面板产生AD等显示不良。
本公开实施例还提供一种移位寄存器。参照图4至图6，本实施例的移位寄存器具有与图1所示实施例的移位寄存器相似的结构，其区别在于本实施例的移位寄存器还包括：输出复位模块4、上拉节点复位模块5、下拉模块6、下拉控制模块7、降噪模块8和升压模块9。
图4为根据本公开的实施例的移位寄存器的结构示意图；图5为根据本公开的实施例的移位寄存器的电路原理图；以及图6为根据本公开的实施例的移位寄存器的工作时序图。
如图4所示，输出复位模块4连接复位信号输入端RESET、第一信号输入端VSS和信号输出端OUTPUT；输出复位模块4用于将信号输出端OUTPUT输出的信号复位。
如图5所示，在本实施例中，输出复位模块4包括第四晶体管M4，第四晶体管M4的第一极连接降压模块3、输出模块2和信号输出端OUTPUT，第四晶体管M4的第二极连接第一信号输入端VSS，第四晶体管M4的控制极连接复位信号输入端RESET。
如图4所示，上拉节点复位模块5连接复位信号输入端RESET、第一信号输入端VSS和上拉节点PU；上拉节点复位模块5用于将上拉节点PU的电位复位。
如图5所示，在本实施例中，上拉节点复位模块5包括第二晶体管M2，第二晶体管M2的第一极连接上拉节点PU，第二晶体管M2 的第二极连接第一信号输入端VSS，第二晶体管M2的控制极连接复位信号输入端RESET。
如图4所示，下拉控制模块7连接下拉节点PD和第二时钟信号输入端CLKB，下拉控制模块7用于根据第二时钟信号输入端CLKB所输入的第二时钟信号控制下拉节点PD的电位，下拉节点PD为下拉控制模块7与下拉模块6的连接点。
如图5所示，在本实施例中，下拉控制模块7包括第五晶体管M5、第九晶体管M9和下拉控制节点PD_CN。
第五晶体管M5的第一极连接第九晶体管M9的第一极和第二时钟信号输入端CLKB，第五晶体管M5的第二极连接下拉节点PD，第五晶体管M5的控制极连接下拉控制节点PD_CN。
第九晶体管M9的第二极连接下拉控制节点PD_CN，第九晶体管M9的控制极连接第二时钟信号输入端CLKB。
如图4所示，下拉模块6连接下拉节点PD、上拉节点PU、下拉控制模块7和第一信号输入端VSS，下拉模块6用于在上拉节点PU的电位的控制下，通过第一信号输入端VSS所输入的第一信号将下拉节点PD的电位进行下拉。
如图5所示，在本实施例中，下拉模块6包括第六晶体管M6和第八晶体管M8。
第六晶体管M6的第一极连接下拉节点PD，第六晶体管M6的第二极连接第一信号输入端VSS，第六晶体管M6的控制极连接上拉节点PU。
第八晶体管M8的第一极连接下拉控制模块7，第八晶体管M8的第二极连接第一信号输入端VSS，第八晶体管M8的控制极连接上拉节点PU。
如图4所示，降噪模块8连接输入模块1、第一信号输入端VSS、下拉节点PD、上拉节点PU、输出模块2、信号输出端OUTPUT和第二时钟信号输入端CLKB；降噪模块8用于通过第一信号输入端VSS所输入的第一信号降低上拉节点PU和信号输出端OUTPUT的输出噪声。
如图5所示，在本实施例中，降噪模块8包括第十晶体管M10、第十一晶体管M11和第十二晶体管M12。
第十晶体管M10的第一极连接输入模块1和上拉节点PU，第十晶体管M10的第二极连接第一信号输入端VSS，第十晶体管M10的控制极连接下拉节点PD。
第十一晶体管M11的第一极连接输出模块2和信号输出端OUTPUT，第十一晶体管M11的第二极连接第一信号输入端VSS，第十一晶体管M11的控制极连接下拉节点PD。
第十二晶体管M12的第一极连接信号输出端OUTPUT，第十二晶体管M12的第二极连接第一信号输入端VSS，第十二晶体管M12的控制极连接第二时钟信号输入端CLKB。
如图4所示，升压模块9连接信号输入端INPUT、输入模块1、第二时钟信号输入端CLKB和上拉节点PU；升压模块9用于根据第二时钟信号输入端CLKB所输入的第二时钟信号对信号输入端INPUT所输入的信号进行升压。
如图5所示，在本实施例中，升压模块9包括第十三晶体管M13，第十三晶体管M13的第一极连接信号输入端INPUT，第十三晶体管M13的第二极连接上拉节点PU，第十三晶体管M13的控制极连接第二时钟信号输入端CLKB。
由于本实施例的移位寄存器中的输入模块1、输出模块2和降压模块3的工作原理与图1所示实施例相同，故在此不再赘述。
下面，参照如图6所示的时序图，对本实施例的移位寄存器(输出复位模块4、上拉节点复位模块5、下拉模块6、下拉控制模块7、降噪模块8和升压模块9)的工作原理进行说明。在本实施例中，第一信号输入端VSS在移位寄存器中一直输出低电平。
如图6所示，在输入阶段，第二时钟信号输入端CLKB输入高电平，第十三晶体管M13开启，以对上拉节点PU的电位进行升压。
如图6所示，在输出阶段，上拉节点PU为高电平，第六晶体管M6和第八晶体管M8开启，使下拉节点PD和下拉控制节点PD_CN分别与第一信号输入端VSS连通，使下拉节点PD的电位被下拉至低 电平(下拉控制节点PD_CN也被下拉至低电平，以避免影响下拉节点PD的电位)，使第十晶体管M10和第十一晶体管M11关闭，从而避免因第十晶体管M10开启导致的上拉节点PU的电位不稳定和因第十一晶体管M11开启导致的信号输出端OUTPUT输出的信号不稳定。
如图6所示，在输出阶段之后，还包括复位降噪阶段。
在复位降噪阶段：
(1)复位信号输入端RESET输入高电平，第二晶体管M2开启，上拉节点PU通过第二晶体管M2与第一信号输入端VSS相连，使上拉节点PU的电位从第三电位V1’被拉低至低电平，以对上拉节点PU的电位进行复位；
(2)复位信号输入端RESET输入高电平，第四晶体管M4开启，信号输出端OUTPUT通过第四晶体管M4与第一信号输入端VSS相连，使信号输出端OUTPUT的电位被拉至低电平，以对信号输出端OUTPUT的电位进行复位；
(3)第一时钟信号输入端CLKA输入低电平，由于上拉节点PU为低电平，第三晶体管M3关闭，同时，第二时钟信号输入端CLKB输入高电平，第九晶体管M9开启，此时，第二时钟信号输入端CLKB与下拉控制节点PD_CN连通，下拉控制节点PD_CN的电位升高，使第五晶体管M5开启，下拉节点PD与第二时钟信号输入端CLKB连通，下拉节点PD的电位呈高电平；
(4)下拉节点PD的电位呈高电平，使第十一晶体管M11开启，第二时钟信号输入端CLKB输入高电平，使第十二晶体管M12开启，此时，信号输出端OUTPUT通过第十一晶体管M11和第十二晶体管M12与第一信号输入端VSS相连，使信号输出端OUTPUT输出的电位被拉至低电平，以降低信号输出端OUTPUT的输出噪声；
(5)下拉节点PD的电位呈高电平，使第十晶体管M10开启，此时，上拉节点PU通过第十晶体管M10与第一信号输入端VSS相连，使上拉节点PU的电位被拉至低电平，以降低上拉节点PU的输出噪声。
需要说明的是，在复位降噪阶段中，上述(1)-(5)是同时发生的，并不存在先后顺序。
本实施例的移位寄存器，包括输入模块1、输出模块2、降压模块3，在输出阶段，该降压模块3能够在上拉节点PU的电位被上拉至第二电位后，将上拉节点PU的电位从第二电位拉低至第三电位，从而使上拉节点PU的电压被迅速降低，以避免栅极与上拉节点PU相连的TFT器件的特性曲线发生漂移，进而使TFT器件正常工作，以避免液晶面板产生AD等显示不良。
图7为根据本公开的实施例的栅极驱动电路的结构示意图。参照图7，该栅极驱动电路包括多级如图1所示实施例的移位寄存器(如图7中虚线内所示)。
每一级移位寄存器的栅极驱动信号生成单元所输出的信号作为该移位寄存器的下一级移位寄存器的信号输入端的输入信号；每一级移位寄存器的信号输出端所输出的信号用于驱动一根栅线以及作为该移位寄存器的上一级移位寄存器的复位信号端的复位信号。
需要说明的是，每级移位寄存器的输出端所输出的信号用于驱动与显示面板的显示区域(即AA区域)连接的栅线。
本实施例的栅极驱动电路，包括多级如图1所示实施例的的移位寄存器，详细描述可参照如图1所示实施例的移位寄存器，在此不再赘述。
本实施例的栅极驱动电路，包括多级如图1所示实施例的移位寄存器，该移位寄存器包括输入模块、输出模块、降压模块，在输出阶段，该降压模块能够在上拉节点的电位被上拉至第二电位后，将上拉节点的电位从第二电位拉低至第三电位，从而使上拉节点的电压被迅速降低，以避免栅极与上拉节点相连的TFT器件的特性曲线发生漂移，进而使TFT器件正常工作，以避免液晶面板产生AD等显示不良。
本公开的实施例还提供了一种显示装置，显示装置包括如图4所示实施例的栅极驱动电路。该显示装置可以为：液晶显示面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本实施例的显示装置，包括如图4所示实施例的栅极驱动电路， 其中的移位寄存器包括输入模块、输出模块、降压模块，在输出阶段，该降压模块能够在上拉节点的电位被上拉至第二电位后，将上拉节点的电位从第二电位拉低至第三电位，从而使上拉节点的电压被迅速降低，以避免栅极与上拉节点相连的TFT器件的特性曲线发生漂移，进而使TFT器件正常工作，以避免液晶面板产生AD等显示不良。
本公开实施例还提供一种栅极驱动电路的驱动方法。图8为根据本公开的实施例的栅极驱动电路的驱动方法的流程示意图。栅极驱动电路包括多级如图1或图4所示的实施例实施例或的移位寄存器，如图8所示，所述驱动方法包括：
在输入阶段，输入模块根据信号输入端所输入的信号，对上拉节点充电至第一电位。
在输出阶段，通过输出模块将上拉节点的电位上拉至第二电位，并在上拉节点的控制下，将第一时钟信号输入端所输入的第一时钟信号，通过信号输出端进行输出；通过降压模块将上拉节点的电位从第二电位拉低至第三电位，其中，第三电位大于第一电位。
当栅极驱动电路包括多级如图4所示实施例的移位寄存器时，所述驱动方法还包括：
在复位降噪阶段，将信号输出端输出的信号和上拉节点的电位复位。
本实施例的栅极驱动电路的驱动方法，用于驱动如图4所示实施例的栅极驱动电路时，其中的移位寄存器包括输入模块、输出模块、降压模块，在输出阶段，该降压模块能够在上拉节点的电位被上拉至第二电位后，将上拉节点的电位从第二电位拉低至第三电位，从而使上拉节点的电压被迅速降低，以避免栅极与上拉节点相连的TFT器件的特性曲线发生漂移，进而使TFT器件正常工作，以避免液晶面板产生AD等显示不良。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出 各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (15)

  1. 一种移位寄存器，包括输入模块、输出模块、降压模块；
    所述输入模块，连接信号输入端和上拉节点，用于在输入阶段，根据所述信号输入端所输入的信号，对所述上拉节点充电至第一电位，所述上拉节点为输入模块、输出模块和降压模块之间连接的节点；
    所述输出模块连接第一时钟信号输入端、信号输出端、降压模块和上拉节点，用于在输出阶段，将所述上拉节点的电位上拉至第二电位；
    所述降压模块还连接上拉节点和信号输出端，用于在输出阶段，所述上拉节点的电位被上拉至第二电位后，将所述上拉节点的电位从所述第二电位拉低至第三电位，其中，第三电位大于第一电位；
    所述输出模块，还用于在输出阶段，在所述上拉节点的控制下，将所述第一时钟信号输入端所输入的第一时钟信号，通过所述信号输出端进行输出。
  2. 根据权利要求1所述的移位寄存器，其中，所述降压模块包括开关晶体管，所述开关晶体管的第一极连接所述输出模块和所述上拉节点，所述开关晶体管的第二极连接所述开关晶体管的控制极、所述输出模块和所述信号输出端，所述开关晶体管的控制极连接所述输出模块和所述信号输出端。
  3. 根据权利要求1所述的移位寄存器，其中，所述输入模块包括第一晶体管，所述第一晶体管的第一极连接信号输入端，所述第一晶体管的第二极连接上拉节点。
  4. 根据权利要求1所述的移位寄存器，其中，所述输出模块包括第三晶体管和存储电容器；
    所述第三晶体管的第一极连接第一时钟信号输入端，所述第三晶 体管的第二极连接所述存储电容器的第二端和降压模块，所述第三晶体管的控制极连接所述上拉节点和所述存储电容器的第一端。
  5. 根据权利要求1至4任意一项所述的移位寄存器，还包括：输出复位模块、上拉节点复位模块、下拉模块、下拉控制模块、降噪模块和升压模块；
    所述输出复位模块连接复位信号输入端、第一信号输入端和信号输出端；所述输出复位模块用于将所述信号输出端输出的信号复位；
    所述上拉节点复位模块连接复位信号输入端、第一信号输入端和所述上拉节点；所述上拉节点复位模块用于将所述上拉节点的电位复位；
    所述下拉控制模块连接下拉节点和第二时钟信号输入端，所述下拉控制模块用于根据所述第二时钟信号输入端所输入的第二时钟信号控制所述下拉节点的电位，所述下拉节点为所述下拉控制模块与所述下拉模块的连接点；
    所述下拉模块连接所述下拉节点、所述上拉节点、下拉控制模块和第一信号输入端，所述下拉模块用于在所述上拉节点的电位的控制下，通过所述第一信号输入端所输入的第一信号将所述下拉节点的电位进行下拉；
    所述降噪模块连接输入模块、第一信号输入端、下拉节点、上拉节点、输出模块、信号输出端和第二时钟信号输入端；所述降噪模块用于通过第一信号输入端所输入的第一信号降低上拉节点和信号输出端的输出噪声；
    所述升压模块连接信号输入端、输入模块、第二时钟信号输入端和上拉节点；所述升压模块用于根据第二时钟信号输入端所输入的第二时钟信号对信号输入端所输入的信号进行升压。
  6. 根据权利要求5所述的移位寄存器，其中，所述输出复位模块包括第四晶体管，所述第四晶体管的第一极连接降压模块、输出模块和信号输出端，所述第四晶体管的第二极连接第一信号输入端，所述 第四晶体管的控制极连接复位信号输入端。
  7. 根据权利要求5所述的移位寄存器，其中，所述上拉节点复位模块包括第二晶体管，所述第二晶体管的第一极连接所述上拉节点，所述第二晶体管的第二极连接第一信号输入端，所述第二晶体管的控制极连接复位信号输入端。
  8. 根据权利要求5所述的移位寄存器，其中，所述下拉模块包括第六晶体管和第八晶体管；
    所述第六晶体管的第一极连接所述下拉节点，所述第六晶体管的第二极连接所述第一信号输入端，所述第六晶体管的控制极连接所述上拉节点；
    所述第八晶体管的第一极连接所述下拉控制模块，所述第八晶体管的第二极连接所述第一信号输入端，所述第八晶体管的控制极连接所述上拉节点。
  9. 根据权利要求5所述的移位寄存器，其中，所述下拉控制模块包括第五晶体管、第九晶体管和下拉控制节点；
    所述第五晶体管的第一极连接所述第九晶体管的第一极和第二时钟信号输入端，所述第五晶体管的第二极连接所述下拉节点，所述第五晶体管的控制极连接所述下拉控制节点；
    所述第九晶体管的第二极连接所述下拉控制节点，所述第九晶体管的控制极连接所述第二时钟信号输入端。
  10. 根据权利要求5所述的移位寄存器，其中，所述降噪模块包括第十晶体管、第十一晶体管和第十二晶体管；
    所述第十晶体管的第一极连接输入模块和上拉节点，所述第十晶体管的第二极连接所述第一信号输入端，所述第十晶体管的控制极连接所述下拉节点；
    所述第十一晶体管的第一极连接输出模块和信号输出端，所述第 十一晶体管的第二极连接所述第一信号输入端，所述第十一晶体管的控制极连接所述下拉节点；
    所述第十二晶体管的第一极连接所述信号输出端，所述第十二晶体管的第二极连接所述第一信号输入端，所述第十二晶体管的控制极连接所述第二时钟信号输入端。
  11. 根据权利要求5所述的移位寄存器，其中，所述升压模块包括第十三晶体管；
    所述第十三晶体管的第一极连接信号输入端，所述第十三晶体管的第二极连接上拉节点，所述第十三晶体管的控制极连接第二时钟信号输入端。
  12. 一种栅极驱动电路，包括多级权利要求1至11中任意一项的移位寄存器，其中，
    每一级所述移位寄存器的栅极驱动信号生成单元所输出的信号作为该移位寄存器的下一级移位寄存器的信号输入端的输入信号；
    每一级所述移位寄存器的信号输出端所输出的信号用于驱动一根栅线以及作为该移位寄存器的上一级移位寄存器的复位信号端的复位信号。
  13. 一种显示装置，包括权利要求12的所述的栅极驱动电路。
  14. 一种栅极驱动电路的驱动方法，所述栅极驱动电路包括多级权利要求1至11中任意一项的移位寄存器，所述驱动方法包括：
    在输入阶段，通过所述输入模块根据所述信号输入端所输入的信号，对所述上拉节点充电至第一电位；
    在输出阶段，通过所述输出模块将所述上拉节点的电位上拉至第二电位，并在所述上拉节点的控制下，将所述第一时钟信号输入端所输入的第一时钟信号，通过所述信号输出端进行输出；通过所述降压模块将所述上拉节点的电位从所述第二电位拉低至第三电位，其中， 第三电位大于第一电位。
  15. 根据权利要求14所述的栅极驱动电路的驱动方法，其中，采用权利要求5所述的移位寄存器时，所述驱动方法还包括：
    在复位降噪阶段，将信号输出端输出的信号和上拉节点的电位复位。
PCT/CN2017/114582 2017-03-08 2017-12-05 移位寄存器、栅极驱动电路及其驱动方法、显示装置 WO2018161658A1 (zh)

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