WO2019033783A1 - 移位寄存器单元、驱动方法、栅极驱动电路和显示装置 - Google Patents

移位寄存器单元、驱动方法、栅极驱动电路和显示装置 Download PDF

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Publication number
WO2019033783A1
WO2019033783A1 PCT/CN2018/084489 CN2018084489W WO2019033783A1 WO 2019033783 A1 WO2019033783 A1 WO 2019033783A1 CN 2018084489 W CN2018084489 W CN 2018084489W WO 2019033783 A1 WO2019033783 A1 WO 2019033783A1
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WIPO (PCT)
Prior art keywords
pull
node
control
shift register
register unit
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PCT/CN2018/084489
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English (en)
French (fr)
Inventor
米磊
王世君
薛艳娜
包智颖
张勇
肖文俊
白璐
华刚
王景棚
方浩博
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/320,821 priority Critical patent/US11373613B2/en
Priority to EP18833817.2A priority patent/EP3477646A4/en
Publication of WO2019033783A1 publication Critical patent/WO2019033783A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit

Definitions

  • Embodiments of the present disclosure relate to the field of display driving technologies, and in particular, to a shift register unit, a driving method, a gate driving circuit, and a display device.
  • the in-box touch method integrates the touch function into an LCD (Liquid Crystal Display) panel, thereby reducing the cost of the touch.
  • LCD Liquid Crystal Display
  • Touch driving is performed in a blank time period. After inserting a blank time period between rows and rows, the interline display needs to be paused for a period of time, and strict requirements are imposed on the GOA (Gate On Array, gate driving circuit disposed on the array substrate). .
  • the potential of the pull-up node needs to be stable.
  • the LH Blanking touch drive mode may have different problems of horizontal and horizontal stripes.
  • the main reason is that the display time of one frame is divided into at least two touch time periods and at least three display time periods, and one touch time period is set between two display time periods, and the segment cannot be guaranteed to be normal. Display, there will be bad stripes.
  • the main reason is that the pull-up node in the shift register unit near the segment is difficult to maintain for a long time, affecting the gate output of the corresponding row, and there is a difference between the other normal rows, and the horizontal streak phenomenon may occur. Aggravated.
  • an embodiment of the present disclosure provides a shift register unit including: a pull-up node state maintaining circuit coupled to a pull-up node and a first control voltage input, configured to be pulled up according to the pull-up The potential of the node and the input potential of the first control voltage input terminal control whether the pull-up node is in communication with the first control voltage input terminal, thereby maintaining the potential state of the pull-up node unchanged.
  • the pull-up node refers to a connection point of an input circuit, an output circuit, and a reset circuit in the shift register unit.
  • the shift register unit may include: an input transistor, a gate of the input transistor is connected to the signal input end, the first pole is connected to the first level signal end; and an output transistor is the first of the output transistor The pole is connected to the clock signal input end, the second pole is connected to the gate drive signal output end; and a storage capacitor, the first end of the storage capacitor is connected to the gate of the output transistor, and the second end is The gate driving signal output terminal is connected, and a connection point between a source of the input transistor, a first end of the storage capacitor and a gate of the output transistor is a pull-up node.
  • the pull-up node state maintaining circuit includes:
  • a pull-up control node control sub-circuit connected to the pull-up node, the first control voltage input end and the pull-up control node, configured to control whether the pull-up control node is related to a potential of the pull-up node
  • the first control voltage input terminal is connected;
  • the pull-up control node control sub-circuit includes:
  • the pull-up control node controls the transistor, the gate is connected to the pull-up node, the first pole is connected to the first control voltage input terminal, and the second pole is connected to the pull-up control node.
  • the pull-up node state maintaining sub-circuit includes:
  • the pull-up node state maintains a transistor, the gate is connected to the pull-up control node, the first pole is connected to the first control voltage input terminal, and the second pole is connected to the pull-up node.
  • the pull-up node state maintaining sub-circuit further includes a switching circuit connected between the second pole of the pull-up node state maintaining transistor and the pull-up node; a control end of the circuit is connected to the pull-up control node;
  • the switching circuit is configured to control whether the second pole of the pull-up node state maintaining transistor is in communication with the pull-up node under control of the pull-up control node.
  • the switching circuit includes a switching transistor
  • a gate of the switching transistor is connected to the pull-up control node, a first pole of the switching transistor is connected to a second pole of the pull-up node state maintaining transistor, and a second pole of the switching transistor is Pull up the node connection.
  • the switching circuit includes a first switching transistor and a second switching transistor, where
  • a gate of the first switching transistor is connected to the pull-up control node, and a first pole of the first switching transistor is connected to a second pole of the pull-up node state maintaining transistor;
  • a gate of the second switching transistor is connected to the pull-up control node, a first pole of the second switching transistor is connected to a second pole of the first switching transistor, and a second of the second switching transistor The pole is connected to the pull-up node.
  • the switching circuit includes N switching transistors, and N is an integer greater than two;
  • a gate of the first switching transistor is connected to the pull-up control node, and a first pole of the first switching transistor is connected to a second pole of the pull-up node state maintaining transistor;
  • n is an integer greater than 1 and less than N ;
  • a gate of the Nth switching transistor is connected to the pull-up control node, a first pole of the Nth switching transistor is connected to a second pole of the N-1th switching transistor, and a second pole of the Nth switching transistor is The pull-up nodes are connected.
  • the pull-up node state maintaining circuit includes a transistor, a gate of the transistor and a drain of the transistor are connected to the pull-up node, a source of the transistor and the The first control voltage input is connected.
  • the shift register according to the embodiment of the present disclosure further includes:
  • a pull-down node state maintaining circuit coupled to the pull-down node, the second control voltage input terminal, and the first level input terminal, configured to control whether the pull-down node is different from the first according to an input potential of the second control voltage input terminal
  • the level inputs are connected.
  • the pull-down node state maintaining circuit includes: a pull-down node sustaining transistor, a gate connected to the second control voltage input terminal, a first pole connected to the pull-down node, and a second pole Connected to the first level input.
  • an embodiment of the present disclosure further provides a driving method of a shift register unit, which is applied to the above shift register unit, wherein the driving method of the shift register unit includes:
  • the pull-up node state maintaining circuit controls the pull-up node in the shift register unit corresponding to the turned-on gate line to communicate with the first control voltage input terminal.
  • the driving method of the shift register unit further includes: inputting a low voltage to the first control voltage input terminal during a display period, the pull-up node state maintaining circuit control and The pull-up nodes of the plurality of shift registers corresponding to all the row gate lines are not in communication with the first control voltage input terminal.
  • the shift register unit includes a pull-down node state maintaining circuit coupled to the pull-down node, the second control voltage input terminal, and the first level input terminal, configured to be according to the second Controlling an input potential of the voltage input terminal to control whether the pull-down node is in communication with the first level input terminal
  • the driving method of the shift register unit further comprises: loading a low-level DC signal to the first level input terminal Controlling, by the touch time period, a voltage input to the second control voltage input terminal, so that the pull-down node state maintaining circuit controls a pull-down node in the shift register unit corresponding to the turned-on gate line and the first A level input is connected.
  • the driving method of the shift register unit further includes: controlling a voltage input to the second control voltage input terminal during a display period to cause the pull-down node state maintaining circuit A pull-down node in the plurality of shift registers corresponding to all of the row gate lines is controlled to be out of communication with the first level input terminal.
  • the pull-down node state maintaining circuit includes an N-type transistor, and inputs the same control voltage to the first control voltage input terminal and the second control voltage input terminal.
  • each frame picture display time includes at least two touch time periods and at least two display time periods;
  • the at least two touch time periods and the at least two display time period intervals are set.
  • an embodiment of the present disclosure further provides a gate driving circuit including a plurality of cascaded shift register units as described above.
  • an embodiment of the present disclosure further provides a display device including the above-described gate drive circuit.
  • FIG. 1 is a schematic diagram showing a division of a frame display time in an LH blank touch driving mode
  • FIG. 2 is a structural diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 3 is a circuit diagram of a specific embodiment of a shift register unit according to an embodiment of the present disclosure
  • FIG. 4 is a timing chart showing the operation of a shift register unit according to an embodiment of the present disclosure.
  • the transistors employed in all embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other device having the same characteristics.
  • one of the poles is referred to as a first pole, and the other pole is referred to as a second pole.
  • the first pole may be a drain and the second pole may be a source.
  • the first pole may be a source and the second pole may be a drain.
  • FIG. 1 is a schematic diagram of a division of a frame display time in an LH blank touch driving mode.
  • TF1 is the first frame picture display time
  • TF2 is the second frame picture display time.
  • TD11 is the first display time period included in TF1
  • TT11 is the first blank time period included in TF1.
  • TD12 is the second display time period included in TF1, and TT12 is the second blank time period included in TF1.
  • TD21 is the first display time period included in TF2, and TT21 is the first blank time period included in TF2.
  • TD22 is the second display time period included in TF2, and TT22 is the second blank time period included in TF2.
  • the division manner shown in FIG. 1 is only one embodiment, and in actual operation, more segments can be divided in one frame display time.
  • Touch driving is performed in a blank time period. After inserting a blank time period between rows and rows, the interline display needs to be paused for a period of time, and strict requirements are imposed on the GOA (Gate On Array, gate driving circuit disposed on the array substrate). . Specifically, the potential of the pull-up node needs to be stable.
  • the LH Blanking touch drive mode may have different problems of horizontal and horizontal stripes. The main reason is that the display time of one frame is divided into at least two touch time periods and at least three display time periods, and one touch time period is set between two display time periods, and the segment cannot be guaranteed to be normal. Display, there will be bad stripes.
  • the main reason is that the pull-up node in the shift register unit near the segment is difficult to maintain for a long time, affecting the gate output of the corresponding row, and there is a difference between other normal rows, and there will be a bad horizontal grain phenomenon, and the degree of badness will be aggravated under high temperature conditions. .
  • a main object of the embodiments of the present disclosure is to provide a shift register unit, a driving method, a gate driving circuit, and a display device, which solve the problem that the pull-up node in the shift register unit in the related art is difficult to maintain for a long time, and the influence is affected.
  • the corresponding row gate output is different from other normal lines, and there will be a problem of horizontal streaks and aggravation of the degree of badness at high temperatures.
  • the shift register unit of the embodiment of the present disclosure includes, for example:
  • the input circuit 13 is connected to the pull-up node PU, the input terminal INPUT and the high voltage input terminal of the input high voltage VDD, and is configured to control whether the pull-up node PU and the input high voltage are according to the potential of the input terminal INPUT The high voltage input of VDD is connected;
  • a gate driving signal output circuit 17 connected to the pull-up node PU, the clock signal input terminal CLK and the gate driving signal output terminal OUTPUT, configured to control the gate driving signal according to the potential of the pull-up node PU Whether the output terminal OUTPUT is in communication with the clock signal input terminal CLK;
  • the reset circuit 14 is connected to the pull-up node PU, the reset terminal RESET, and the low voltage input terminal of the input low voltage VSS, and is configured to control whether the pull-up node PU and the input are according to the potential of the reset terminal RESET The low voltage input of the low voltage VSS is connected;
  • a gate drive signal reset circuit 19 connected to the first control voltage input terminal GCL, the gate drive signal output terminal OUTPUT and the first level input terminal VI1, configured to be according to the first control voltage
  • the input potential of the input terminal GCL controls whether the gate drive signal output terminal OUTPUT is in communication with the first level input terminal VI1.
  • the pull-up node state maintaining circuit 11 is connected to the pull-up node PU and the first control voltage input terminal GCL, and is configured to be controlled according to the potential of the pull-up node PU and the input potential of the first control voltage input terminal GCL. Whether the pull-up node PU is in communication with the first control voltage input terminal GCL;
  • a pull-down node state maintaining circuit 12 connected to the pull-down node PD, the third control voltage input terminal GCH and the first level input terminal VI1, configured to control the pull-down node according to an input potential of the third control voltage input terminal GCH Whether the PD is in communication with the first level input terminal VI1;
  • a pull-down node control circuit 16 connected to the third control voltage input terminal GCH, the pull-down node PD, the pull-up node PU, and the first level input terminal VI1, configured to be input according to the third control voltage Controlling an electric potential of the pull-down node PD by an input potential of the terminal GCH and a potential of the pull-up node PU;
  • a first pull-down circuit 15 connected to the pull-up node PU, the pull-down node PD, and the first level input terminal VI1, respectively, configured to control the pull-up node according to a potential of the pull-down node PD Whether the PU is in communication with the first level input terminal VI1;
  • a second pull-down circuit 18 connected to the pull-down node PD, the gate driving signal output terminal OUT and the first level input terminal VI1, configured to control the gate driving signal according to the potential of the pull-down node PD Whether the output terminal OUT is connected to the first level input terminal VI1;
  • the first level input terminal VI1 may be a low level input terminal of the input low level, but is not limited thereto.
  • the pull-up node state maintaining circuit 11 may include, for example:
  • the pull-up control node controls the transistor MU, the gate is connected to the pull-up node PU, the drain is connected to the first control voltage input terminal GCL, and the source is connected to the pull-up control node PUCN;
  • a pull-up node state maintaining transistor MUK a gate connected to the pull-up control node PUCN, a drain connected to the first control voltage input terminal GCL, and a source connected to the pull-up node PU;
  • the switching transistor MK has a gate connected to the pull-up control node PUCN, a drain connected to the first control voltage input terminal GCL, and a source connected to the pull-up node PU.
  • the pull-down node maintaining circuit 12 may include, for example, a pull-down node sustain transistor MDK, a gate connected to the first control voltage input terminal GCL, a drain connected to the pull-down node PD, and a source and the input low level.
  • the low level input of VGL is connected.
  • the input circuit 13 can include, for example:
  • the input transistor MI has a gate connected to the input terminal INPUT, a drain connected to a high voltage input terminal of the input high voltage VDD, and a source connected to the pull-up node PU.
  • the reset circuit 14 can include, for example:
  • the reset transistor MR has a gate connected to the reset terminal RESET, a drain connected to the pull-up node PU, and a source connected to a low voltage input terminal inputting a low voltage VSS.
  • the first pull-down circuit 15 may include, for example:
  • the first pull-down transistor MDC has a gate connected to the pull-down node PD, a drain connected to the pull-up node PU, and a source connected to a low-level input terminal of the input low level VGL.
  • the pull-down node control circuit 16 can include, for example:
  • the first pull-down control node controls the transistor MDC1, the gate and the drain are both connected to the third control voltage input terminal GCH, and the source is connected to the pull-down control node PDCN;
  • the second pull-down control node controls the transistor MDC2, the gate is connected to the pull-up node PU, the drain is connected to the pull-down control node PDCN, and the source is connected to the low-level input end of the input low level VGL;
  • a first pull-down node controls the transistor MD1, a gate is connected to the pull-down control node PDCN, a drain is connected to the third control voltage input terminal GCH, and a source is connected to the pull-down node PD;
  • the second pull-down node controls the transistor MD2, the gate is connected to the pull-up node PU, the drain is connected to the pull-down node PD, and the source is connected to the low-level input terminal of the input low level VGL.
  • the gate driving signal output circuit 17 may include, for example:
  • An output transistor MO a gate connected to the pull-up node PU, a drain connected to the clock signal input terminal CLK, and a source connected to the gate drive signal output terminal OUTPUT;
  • the storage capacitor C1 has a first end connected to the pull-up node PU and a second end connected to the gate drive signal output end OUTPUT.
  • the second pull-down circuit 18 can include, for example:
  • the second pull-down transistor MD has a gate connected to the pull-down node PD, a drain connected to the gate drive signal output terminal OUTPUT, and a source connected to the low-level input terminal of the input low level VGL.
  • the gate driving signal reset circuit 19 may include, for example:
  • the gate driving signal resets the transistor MOR, the gate is connected to the first control voltage input terminal GCL, the drain is connected to the gate driving signal output terminal OUTPUT, and the source and the low level input terminal of the input low level VGL connection.
  • all of the transistors are N-type transistors.
  • the above transistor may also be P-type, and the timing of the control signal may be changed accordingly, and the type of the transistor is not limited herein.
  • the gate of the MDK can be coupled to the first control voltage input.
  • the gate of the MDK needs to be connected to the second control voltage input terminal.
  • a specific embodiment of the 14T1C shift register unit as shown in FIG. 3 is added with four TFTs (thin film transistors), that is, a pull-up, compared to the conventional 10T1C shift register unit.
  • the control node controls the transistor MUC, the pull-up node state sustain transistor MUK, the switching transistor MK, and the pull-down node sustain transistor MDK.
  • the first control voltage input by the first control voltage input terminal GCL is a high voltage
  • the high voltage input by the GCL forces the potential of the pull-down node PD to be pulled low by the MDK to ensure that the MUC is at It is completely off, preventing the PU of the pull-up node from leaking a lot.
  • the pull-up node PU turns on the MUC, introduces the high voltage of the GCL input, and then turns on the MUK and MK, and transmits the high voltage of the GCL input to the pull-up node PU to maintain Pull the node high in the blank period.
  • the pull-up node of the 14T1C shift register unit shown in FIG. 3 has a stronger potential holding capability, and the specific embodiment of the 14T1C shift register unit is required after a blank pause. It is higher than the potential of the pull-up node of the 10T1C shift register unit. In the actual situation, the potential of the pull-up node of the 10T1C shift register unit decreases more after the blank time, and the 14T1C shift register unit described in the embodiment of the present disclosure can effectively prevent this phenomenon from occurring, thereby preventing the horizontal stripes from being bad. A phenomenon occurs.
  • the specific embodiment of the shift register unit shown in FIG. 3 provided by the embodiment of the present disclosure is in operation, in a blank time period (ie, a touch time period) TB, GCL input.
  • GCH inputs a low voltage.
  • the potential of the pull-up node PU is maintained at a high voltage
  • the potential of the pull-down node PD is a low voltage.
  • a GOA Gate On Array, a gate driving circuit provided on an array substrate
  • a shift register unit uses an 8 phase (phase) clock signal, and the left and right sides are alternately driven as an example.
  • the display panel adopts four clock signal input terminals on the left and right sides, and the clock signal input end does not output in the blank time period, the first control voltage of the GCL input and the third control voltage of the GCH input are mutually inverted, and the GCH is input in the blank time period.
  • GCL inputs a high voltage during the blank period
  • GCH inputs a high voltage during the display period
  • GCL inputs a low voltage during the display period.
  • the shift register unit disposed on the left side of the display panel may be connected to the odd-numbered gate lines, and the shift register unit disposed on the right side of the display panel may be connected with even lines. Grid connection. It is assumed that a specific embodiment of the shift register unit as shown in FIG.
  • n-th row shift register unit 3 is an n-th row shift register unit connected to an odd-numbered row gate line disposed on the left side of the display panel (n is a positive integer greater than 2, and n is an odd number)
  • the nth row shift register unit located on the left side is connected to the first clock signal input terminal CLK1
  • the n+1th shift register unit located on the right side is connected to the second clock signal input terminal CLK2, and is located at the nth side of the left side.
  • the first clock signal input by CLK1 continues to be at a high level for TG
  • the second clock signal input by CLK2 is delayed by TG/2 from the first clock signal input by CLK1
  • the second clock signal input from CLK2 is delayed by TG/2
  • the fourth clock signal input from CLK4 is delayed by TG/2 from the third clock signal input from CLK3.
  • the nth row shift register unit (the nth shift register unit)
  • the pull-up node PU in the first clock signal input by CLK1 is pre-charged, and the potential of the pull-up node PU reaches a certain high potential, after a long pause (ie, after a blank period of time TB), input at CLK1
  • the potential of the pull-up node PU of the n-th shift register unit (the potential of the PU in FIG. 4 is the potential of the pull-up node in the n-th shift register unit) is further pulled up by the bootstrap action.
  • the leakage current of the MI connected to the pull-up node PU, the leakage current of the MR connected to the pull-up node PU, and the leakage current of the MUC connected to the pull-up node PU increase, after the pause of the blank period TB, the pull-up is performed.
  • the potential of the node PU is greatly reduced, thereby affecting the amplitude of the secondary lift voltage of the pull-up node PU.
  • the embodiment of the present disclosure controls whether the pull-up node PU and the first one are controlled by the pull-up node state maintaining circuit 11 under the control of the pull-up node PU and the first control voltage input terminal GCL.
  • Controlling the voltage input terminal GCL, that is, the potential of the pull-up node PU by the pull-up node state maintaining circuit is at a second level (the second level can be, for example, a high level) and inputting the first control voltage input terminal At the second level, the control pull-up node PU is connected to the first control voltage input terminal GCL to better maintain the high potential of the pull-up node PU.
  • the shift register unit of the embodiment of the present disclosure is controlled by the pull-down node state maintaining circuit 12 under the control of the first control voltage input terminal GCL during a blank period (the blank period is the touch period).
  • the potential of the pull-down node PD is maintained at a first level (the first level may be, for example, a low level), thereby reducing the path of the pull-up node PU leakage, which is advantageous for maintaining the potential of the pull-up node PU.
  • the driving method of the shift register unit according to the embodiment of the present disclosure is applied to the above shift register unit, and the driving method of the shift register unit includes:
  • the pull-up node state maintaining circuit controls the pull-up node in the shift register unit corresponding to the turned-on gate line to communicate with the first control voltage input terminal.
  • the pull-up node state maintaining circuit controls the pull-up node in the shift register unit corresponding to the turned-on gate line to communicate with the first control voltage input terminal to maintain the upper
  • the potential of the pull node is at a high level to reduce the leakage path of the pull-up node, so that the segment of the gate driving circuit in the LH Blanking touch driving mode can be made (touch time period and display time period)
  • the potential of the pull-up node in the nearby shift register unit can be maintained at a high level for a long time.
  • the driving method of the shift register unit further includes: inputting a low voltage to the first control voltage input terminal during a display time period, and the pull-up node state maintaining circuit controls all rows The pull-up node of the plurality of shift register units corresponding to the gate line is not in communication with the first control voltage input terminal.
  • the pull-up node state maintaining circuit controls the disconnection between the pull-up node and the first control voltage input terminal so as not to affect the normal display.
  • the shift register unit includes a pull-down node state maintaining circuit, and is connected to the pull-down node, the second control voltage input end, and the first level input end, and is configured to be controlled according to an input potential of the second control voltage input end.
  • the driving method of the shift register unit according to the embodiment of the present disclosure further includes: loading a low-level DC signal to the first level input terminal, where the pull-down node is in communication with the first level input terminal, a touch time period, controlling a voltage input to the second control voltage input terminal, so that the pull-down node state maintaining circuit controls a pull-down node in the shift register unit corresponding to the turned-on gate line and the first power The flat input is connected.
  • the first level input terminal is connected to make the potential of the pull-down node low to reduce a leakage path of the pull-up node, so that the gate driving circuit in the LH Blanking touch driving mode can be
  • the potential of the pull-up node in the shift register unit near the segment can be maintained at a high level for a long time.
  • the driving method of the shift register unit further includes: controlling, during the display period, a voltage input to the second control voltage input terminal, so that the pull-down node state maintaining circuit control and The pull-down node of the plurality of shift registers corresponding to all the row gate lines is not connected to the first level input terminal so as not to affect the normal display.
  • the pull-down node state maintaining circuit includes a transistor that can be an N-type transistor, and inputs the same control voltage to the first control voltage input terminal and the second control voltage input terminal. That is, at this time, the first control voltage input terminal and the second control voltage input terminal may be one terminal, which can save space.
  • each frame display time may include at least two touch time periods and at least two display time periods;
  • the at least two touch time periods and the at least two display time period intervals are set.
  • a display time period is set after a touch time period, and a touch time period is set after a display time period.
  • the last time period of each frame picture display time is the touch time period, the next frame picture is displayed. The time can be displayed at the beginning of the time period.
  • At least two touch time periods are set within a frame display period to increase the touch frequency.
  • the above touch time period and the display time period are set by the LH Blanking touch driving mode, and at least two touch time periods are set within one frame display time period to increase the touch frequency.
  • the gate driving circuit of the embodiment of the present disclosure includes a plurality of cascaded shift register units.
  • the display device includes the above-described gate driving circuit.
  • the shift register unit, the driving method, the gate driving circuit, and the display device can maintain the potential of the pull-up node in the shift register unit corresponding to the turned-on gate line in the blank
  • the time period (the blank time period is the touch time period) is a high level, thereby maintaining the potential state of the pull-up node unchanged, so as to improve the potential holding capacity of the pull-up node, and solving the pull-up node in the related art.
  • the potential of the potential drop in the touch time period is large, which causes a technical problem of the occurrence of a bad horizontal grain phenomenon.

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Abstract

本公开实施例提供一种移位寄存器单元、驱动方法、栅极驱动电路和显示装置。所述移位寄存器单元包括：上拉节点状态维持电路，与上拉节点和第一控制电压输入端连接，被构造成根据所述上拉节点的电位和所述第一控制电压输入端的输入电位的控制下控制所述上拉节点是否与所述第一控制电压输入端连通。

Description

移位寄存器单元、驱动方法、栅极驱动电路和显示装置
相关申请的交叉引用
本申请主张在2017年8月16日在中国提交的中国专利申请号No.201710701895.5的优先权，其全部内容通过引用包含于此。
技术领域
本公开实施例涉及显示驱动技术领域，尤其涉及一种移位寄存器单元、驱动方法、栅极驱动电路和显示装置。
背景技术
盒内触控方式是将触控功能集成进入LCD(Liquid Crystal Display，液晶显示)面板中，进而降低触控成本。在盒内触控方式的实际操作时可以在一帧画面显示时间内分更多段。在空白时间段进行触控驱动，在行与行之间插入空白时间段后，行间显示需要停顿一段时间，对于GOA(Gate On Array，设置在阵列基板上的栅极驱动电路)提出严格要求。具体的，上拉节点的电位需要保持稳定，对于a-Si(非晶硅)Full in Cell(盒内)显示产品，LH Blanking触控驱动模式会出现不同轻重的横纹不良问题。主要原因为一帧画面显示时间被分成至少两个触控时间段和至少三个显示时间段，一所述触控时间段设置于两个所述显示时间段之间，分段处无法保证正常显示，会出现横纹不良现象。主要原因为分段处附近移位寄存器单元中的上拉节点长时间电位保持困难，影响相应行栅极输出，与其他正常行存在差异，会出现横纹不良现象，高温情况下不良程度可能会加重。
发明内容
在第一个方面中，本公开实施例提供了一种移位寄存器单元，包括：上拉节点状态维持电路，与上拉节点和第一控制电压输入端连接，被构造成根据所述上拉节点的电位和第一控制电压输入端的输入电位控制所述上拉节点是否与所述第一控制电压输入端连通，进而维持所述上拉节点的电位状态不 变。其中，所述上拉节点是指移位寄存器单元中输入电路、输出电路和复位电路的连接点。具体地，所述移位寄存器单元可以包括：一输入晶体管，该输入晶体管的栅极与信号输入端连接，第一极与第一电平信号端连接；一输出晶体管，该输出晶体管的第一极与时钟信号输入端连接，第二极与栅极驱动信号输出端连接；以及，一存储电容，所述存储电容的第一端与所述输出晶体管的栅极连接，第二端与所述栅极驱动信号输出端连接，所述输入晶体管的源极、所述存储电容的第一端与所述输出晶体管的栅极之间的连接点即为上拉节点。
在本公开的一个可行实施例中，所述上拉节点状态维持电路包括：
上拉控制节点控制子电路，与所述上拉节点、所述第一控制电压输入端和上拉控制节点连接，被构造成根据所述上拉节点的电位控制所述上拉控制节点是否与所述第一控制电压输入端连通；以及，
上拉节点状态维持子电路，与所述上拉控制节点、所述第一控制电压输入端和所述上拉节点连接，被构造成根据所述上拉控制节点的电位控制所述上拉节点是否与所述第一控制电压输入端连通。
在本公开的一个可行实施例中，所述上拉控制节点控制子电路包括：
上拉控制节点控制晶体管，栅极与所述上拉节点连接，第一极与所述第一控制电压输入端连接，第二极与所述上拉控制节点连接。
在本公开的一个可行实施例中，所述上拉节点状态维持子电路包括：
上拉节点状态维持晶体管，栅极与所述上拉控制节点连接，第一极与所述第一控制电压输入端连接，第二极与所述上拉节点连接。
在本公开的一个可行实施例中，所述上拉节点状态维持子电路还包括连接于所述上拉节点状态维持晶体管的第二极与所述上拉节点之间的开关电路；所述开关电路的控制端与所述上拉控制节点连接；
所述开关电路被构造成在所述上拉控制节点的控制下控制所述上拉节点状态维持晶体管的第二极是否与所述上拉节点连通。
在本公开的一个可行实施例中，所述开关电路包括一个开关晶体管；
所述开关晶体管的栅极与所述上拉控制节点连接，所述开关晶体管的第一极与所述上拉节点状态维持晶体管的第二极连接，所述开关晶体管的第二 极与所述上拉节点连接。
在本公开的一个可行实施例中，所述开关电路包括第一开关晶体管和第二开关晶体管，其中，
所述第一开关晶体管的栅极与所述上拉控制节点连接，所述第一开关晶体管的第一极与所述上拉节点状态维持晶体管的第二极连接；
所述第二开关晶体管的栅极与所述上拉控制节点连接，所述第二开关晶体管的第一极与所述第一开关晶体管的第二极连接，所述第二开关晶体管的第二极与所述上拉节点连接。
在本公开的一个可行实施例中，所述开关电路包括N个开关晶体管，N为大于2的整数；
第一开关晶体管的栅极与所述上拉控制节点连接，所述第一开关晶体管的第一极与所述上拉节点状态维持晶体管的第二极连接；
第n开关晶体管的栅极与所述上拉控制节点连接，所述第n开关晶体管的第一极与所述第n-1开关晶体管的第二极连接；n为大于1而小于N的整数；
第N开关晶体管的栅极与所述上拉控制节点连接，所述第N开关晶体管的第一极与第N-1开关晶体管的第二极连接，所述第N开关晶体管的第二极与所述上拉节点连接。
在本公开的一个可行实施例中，所述上拉节点状态维持电路包括一晶体管，该晶体管的栅极和该晶体管的漏极都与所述上拉节点连接，该晶体管的源极与所述第一控制电压输入端连接。
在本公开的一个可行实施例中，本公开实施例所述的移位寄存器还包括：
下拉节点状态维持电路，与下拉节点、第二控制电压输入端和第一电平输入端连接，被构造成根据所述第二控制电压输入端的输入电位控制所述下拉节点是否与所述第一电平输入端连通。
在本公开的一个可行实施例中，所述下拉节点状态维持电路包括：下拉节点维持晶体管，栅极与所述第二控制电压输入端连接，第一极与所述下拉节点连接，第二极与所述第一电平输入端连接。
在第二个方面中，本公开实施例还提供了一种移位寄存器单元的驱动方 法，应用于上述的移位寄存器单元，其中，所述移位寄存器单元的驱动方法包括：
在触控时间段，向第一控制电压输入端输入高电压，上拉节点状态维持电路控制与开启的栅线对应的移位寄存器单元中的上拉节点与所述第一控制电压输入端连通。
在本公开的一个可行实施例中，所述移位寄存器单元的驱动方法还包括：在显示时间段，向所述第一控制电压输入端输入低电压，所述上拉节点状态维持电路控制与所有行栅线对应的多个移位寄存器中的上拉节点与所述第一控制电压输入端之间不连通。
在本公开的一个可行实施例中，所述移位寄存器单元包括下拉节点状态维持电路，与下拉节点、第二控制电压输入端和第一电平输入端连接，被构造成根据所述第二控制电压输入端的输入电位控制所述下拉节点是否与所述第一电平输入端连通，所述移位寄存器单元的驱动方法还包括：向所述第一电平输入端加载低电平直流信号，在触控时间段，控制向所述第二控制电压输入端输入的电压，以使得所述下拉节点状态维持电路控制与开启的栅线对应的移位寄存器单元中的下拉节点与所述第一电平输入端连通。
在本公开的一个可行实施例中，所述移位寄存器单元的驱动方法还包括：在显示时间段，控制向所述第二控制电压输入端输入的电压，以使得所述下拉节点状态维持电路控制与所有行栅线对应的多个移位寄存器中的下拉节点与所述第一电平输入端不连通。
在本公开的一个可行实施例中，所述下拉节点状态维持电路包括N型晶体管，向所述第一控制电压输入端和所述第二控制电压输入端输入相同的控制电压。
在本公开的一个可行实施例中，每一帧画面显示时间包括至少两个触控时间段和至少两个显示时间段；
所述至少两个触控时间段和所述至少两个显示时间段间隔设置。
在第三个方面中，本公开实施例还提供了一种栅极驱动电路，包括多个级联的上述的移位寄存器单元。
在第四个方面中，本公开实施例还提供了一种显示装置，包括上述的栅 极驱动电路。
附图说明
为了更清楚地说明本公开文本实施例或相关技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开文本的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是LH空白触控驱动模式下的一帧画面显示时间的一种划分示意图；
图2是本公开实施例所述的移位寄存器单元的结构图；
图3是本公开实施例所述的移位寄存器单元的一具体实施例的电路图；以及
图4是本公开实施例所述的移位寄存器单元的工作时序图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一极，另一极称为第二极。在实际操作时，所述第一极可以为漏极，所述第二极可以为源极。或者，所述第一极可以为源极，所述第二极可以为漏极。
现有的常用的触控频率高的LH Blanking(空白)触控驱动模式是将空白时间段插在行与行之间。例如，图1是LH空白触控驱动模式下的一帧画面显示时间的一种划分示意图。在图1中，TF1为第一帧画面显示时间，TF2为第二帧画面显示时间。TD11为TF1包括的第一显示时间段，TT11为TF1包括的第一空白时间段。TD12为TF1包括的第二显示时间段，TT12为TF1包括的第二空白时间段。TD21为TF2包括的第一显示时间段，TT21为TF2 包括的第一空白时间段。TD22为TF2包括的第二显示时间段，TT22为TF2包括的第二空白时间段。这里，图1所示的划分方式仅为一种实施例，在实际操作时可以在一帧画面显示时间内分更多段。
在空白时间段进行触控驱动，在行与行之间插入空白时间段后，行间显示需要停顿一段时间，对于GOA(Gate On Array，设置在阵列基板上的栅极驱动电路)提出严格要求。具体的，上拉节点的电位需要保持稳定，对于a-Si(非晶硅)Full in Cell(盒内)显示产品，LH Blanking触控驱动模式会出现不同轻重的横纹不良问题。主要原因为一帧画面显示时间被分成至少两个触控时间段和至少三个显示时间段，一所述触控时间段设置于两个所述显示时间段之间，分段处无法保证正常显示，会出现横纹不良现象。主要原因为分段处附近移位寄存器单元中的上拉节点长时间电位保持困难，影响相应行栅极输出，与其他正常行存在差异，会出现横纹不良现象，高温情况下不良程度会加重。
相应的，本公开实施例的主要目的在于提供一种移位寄存器单元、驱动方法、栅极驱动电路和显示装置，解决相关技术中移位寄存器单元中的上拉节点长时间电位保持困难，影响相应行栅极输出，与其他正常行存在差异，会出现横纹不良现象，高温情况下不良程度加重的技术问题。
如图2所示，本公开实施例所述的移位寄存器单元例如包括：
输入电路13，与上拉节点PU、输入端INPUT和输入高电压VDD的高电压输入端连接，被构造成根据所述输入端INPUT的电位控制所述上拉节点PU是否与所述输入高电压VDD的高电压输入端连通；
栅极驱动信号输出电路17，与所述上拉节点PU、时钟信号输入端CLK和栅极驱动信号输出端OUTPUT连接，被构造成根据所述上拉节点PU的电位控制所述栅极驱动信号输出端OUTPUT是否与所述时钟信号输入端CLK连通；
复位电路14，与所述上拉节点PU、复位端RESET和输入低电压VSS的低电压输入端连接，被构造成根据所述复位端RESET的电位控制所述上拉节点PU是否与所述输入低电压VSS的低电压输入端连通；
栅极驱动信号复位电路19，与所述第一控制电压输入端GCL、所述栅极 驱动信号输出端OUTPUT和所述第一电平输入端VI1连接，被构造成根据所述第一控制电压输入端GCL的输入电位控制所述栅极驱动信号输出端OUTPUT是否与所述第一电平输入端VI1连通。
上拉节点状态维持电路11，与上拉节点PU和第一控制电压输入端GCL连接，被构造成根据所述上拉节点PU的电位和所述第一控制电压输入端GCL的输入电位，控制所述上拉节点PU是否与所述第一控制电压输入端GCL连通；
下拉节点状态维持电路12，与下拉节点PD、第三控制电压输入端GCH和第一电平输入端VI1连接，被构造成根据所述第三控制电压输入端GCH的输入电位控制所述下拉节点PD是否与所述第一电平输入端VI1连通；
下拉节点控制电路16，与第三控制电压输入端GCH、所述下拉节点PD、所述上拉节点PU和所述第一电平输入端VI1连接，被构造成根据所述第三控制电压输入端GCH的输入电位和所述上拉节点PU的电位，控制所述下拉节点PD的电位；
第一下拉电路15，分别与所述上拉节点PU、所述下拉节点PD和所述第一电平输入端VI1连接，被构造成根据所述下拉节点PD的电位控制所述上拉节点PU是否与所述第一电平输入端VI1连通；
第二下拉电路18，与所述下拉节点PD、所述栅极驱动信号输出端OUT和第一电平输入端VI1连接，被构造成根据所述下拉节点PD的电位控制所述栅极驱动信号输出端OUT是否与第一电平输入端VI1连通；以及，
在实际操作时，所述第一电平输入端VI1可以为输入低电平的低电平输入端，但不以此为限。
具体的，如图3所示，所述上拉节点状态维持电路11可以例如包括：
上拉控制节点控制晶体管MU，栅极与所述上拉节点PU连接，漏极与所述第一控制电压输入端GCL连接，源极与上拉控制节点PUCN连接；
上拉节点状态维持晶体管MUK，栅极与所述上拉控制节点PUCN连接，漏极与所述第一控制电压输入端GCL连接，源极与所述上拉节点PU连接；
开关晶体管MK，栅极与所述上拉控制节点PUCN连接，漏极与所述第一控制电压输入端GCL连接，源极与所述上拉节点PU连接。
所述下拉节点维持电路12可以例如包括：下拉节点维持晶体管MDK，栅极与所述第一控制电压输入端GCL连接，漏极与所述下拉节点PD连接，源极与所述输入低电平VGL的低电平输入端连接。
所述输入电路13可以例如包括：
输入晶体管MI，栅极与所述输入端INPUT连接，漏极与输入高电压VDD的高电压输入端连接，源极与所述上拉节点PU连接。
所述复位电路14可以例如包括：
复位晶体管MR，栅极与所述复位端RESET连接，漏极与所述上拉节点PU连接，源极与输入低电压VSS的低电压输入端连接。
所述第一下拉电路15可以例如包括：
第一下拉晶体管MDC，栅极与所述下拉节点PD连接，漏极与所述上拉节点PU连接，源极与输入低电平VGL的低电平输入端连接。
所述下拉节点控制电路16可以例如包括：
第一下拉控制节点控制晶体管MDC1，栅极和漏极都与所述第三控制电压输入端GCH连接，源极与所述下拉控制节点PDCN连接；以及，
第二下拉控制节点控制晶体管MDC2，栅极与所述上拉节点PU连接，漏极与所述下拉控制节点PDCN连接，源极与所述输入低电平VGL的低电平输入端连接；
第一下拉节点控制晶体管MD1，栅极与所述下拉控制节点PDCN连接，漏极与所述第三控制电压输入端GCH连接，源极与所述下拉节点PD连接；以及，
第二下拉节点控制晶体管MD2，栅极与所述上拉节点PU连接，漏极与所述下拉节点PD连接，源极与所述输入低电平VGL的低电平输入端连接。
所述栅极驱动信号输出电路17可以例如包括：
输出晶体管MO，栅极与所述上拉节点PU连接，漏极与所述时钟信号输入端CLK连接，源极与所述栅极驱动信号输出端OUTPUT连接；以及，
存储电容C1，第一端与所述上拉节点PU连接，第二端与所述栅极驱动信号输出端OUTPUT连接。
所述第二下拉电路18可以例如包括：
第二下拉晶体管MD，栅极与所述下拉节点PD连接，漏极与所述栅极驱动信号输出端OUTPUT连接，源极与所述输入低电平VGL的低电平输入端连接。
所述栅极驱动信号复位电路19可以例如包括：
栅极驱动信号复位晶体管MOR，栅极与所述第一控制电压输入端GCL连接，漏极与所述栅极驱动信号输出端OUTPUT连接，源极与输入低电平VGL的低电平输入端连接。
在图3所示的具体实施例中，所有的晶体管都为N型晶体管。然而，在实际操作时，以上晶体管也可以为P型，相应改变控制信号的时序即可，在此对晶体管的类型不作限定。
在图3所示的具体实施例中，由于MDK为N型晶体管，所以MDK的栅极可以与第一控制电压输入端连接。另外，当MDK为P型晶体管时，MDK的栅极需与第二控制电压输入端连接。
在本公开实施例中，如图3所示的14T1C移位寄存器单元的具体实施例在工作时，与传统的10T1C移位寄存器单元相比，增加了四个TFT(薄膜晶体管)，即上拉控制节点控制晶体管MUC、上拉节点状态维持晶体管MUK、开关晶体管MK和下拉节点维持晶体管MDK。在空白时间段(也即触控时间段)，第一控制电压输入端GCL输入的第一控制电压为高电压，GCL输入的高电压通过MDK强制将下拉节点PD的电位拉低，保证MUC处于完全关闭状态，防止上拉节点PU大幅度漏电。并且，在空白时间段(也即触控时间段)，上拉节点PU打开MUC，将GCL输入的高电压引入，进而打开MUK和MK，将GCL输入的高电压传导至上拉节点PU，维持上拉节点在空白时间段内的高电平。经过模拟发现，本公开实施例提供的如图3所示的14T1C移位寄存器单元的具体实施例的上拉节点电位保持能力更强，14T1C移位寄存器单元的具体实施例在经过空白停顿后要比10T1C移位寄存器单元的上拉节点的电位高。在实际情况下，10T1C移位寄存器单元的上拉节点的电位经过空白时间后下降幅度更大，本公开实施例所述的14T1C移位寄存器单元可有效防止这一现象发生，进而防止横纹不良现象发生。
在实际操作时，如图4所示，本公开实施例提供的如图3所示的移位寄 存器单元的具体实施例在工作时，在空白时间段(即触控时间段)TB，GCL输入高电压，GCH输入低电压，此时上拉节点PU的电位维持为高电压，下拉节点PD的电位为低电压。
在实际操作时，以包括本公开实施例所述的移位寄存器单元的GOA(Gate On Array，设置在阵列基板上的栅极驱动电路)使用8phase(相位)时钟信号，左右两边交替驱动为例，显示面板左右各采用4个时钟信号输入端，时钟信号输入端在空白时间段内不输出，GCL输入的第一控制电压和GCH输入的第三控制电压相互反相，GCH在空白时间段输入低电压，GCL在空白时间段输入高电压，GCH在显示时间段输入高电压，GCL在显示时间段输入低电压。
在具体实施时，根据一种具体实施方式，设置于所述显示面板左侧的移位寄存器单元可以与奇数行栅线连接，设置于所述显示面板右侧的移位寄存器单元可以与偶数行栅线连接。假设如图3所示的移位寄存器单元的具体实施例为设置于显示面板左侧的与奇数行栅线连接的第n行移位寄存器单元(n为大于2的正整数，n为奇数)；位于左侧的第n行移位寄存器单元与第一时钟信号输入端CLK1连接，位于右侧的第n+1移位寄存器单元与第二时钟信号输入端CLK2连接，位于左侧的第n-2行移位寄存器单元与第三时钟信号输入端CLK3连接，位于右侧的第n-1行移位寄存器单元与第四时钟信号输入端CLK4连接(位于左侧的奇数行移位寄存器单元相互级联，位于右侧的偶数行移位寄存器单元相互级联)。
如图4所示，CLK1输入的第一时钟信号持续为高电平的时间为TG，CLK2输入的第二时钟信号比CLK1输入的第一时钟信号推迟TG/2，CLK3输入的第三时钟信号比CLK2输入的第二时钟信号推迟TG/2，CLK4输入的第四时钟信号比CLK3输入的第三时钟信号推迟TG/2。第n-2行移位寄存器单元(该第n-2行移位寄存器单元接入由CLK3输入的第三时钟信号)输出后，第n行移位寄存器单元(该第n行移位寄存器单元接入由CLK1输入的第一时钟信号)中的上拉节点PU预充电，该上拉节点PU的电位达到一定高电位，经过长时间停顿后(即经过空白时间段TB后)，在CLK1输入高电压时由于自举作用将第n行移位寄存器单元的上拉节点PU(图4中的PU的电 位为第n行移位寄存器单元中的上拉节点的电位)的电位进一步拉升。如果与上拉节点PU连接的MI的漏电流、与上拉节点PU连接的MR的漏电流、与上拉节点PU连接的MUC的漏电流增大，经过空白时间段TB的停顿后，上拉节点PU的电位会大幅下降，从而影响上拉节点PU二次抬起电压的幅值。
针对上述技术问题，本公开实施例通过上拉节点状态维持电路11在所述上拉节点PU和所述第一控制电压输入端GCL的控制下控制所述上拉节点PU是否与所述第一控制电压输入端GCL连接，也即通过上拉节点状态维持电路在上拉节点PU的电位为第二电平(所述第二电平例如可以为高电平)并第一控制电压输入端输入第二电平时，控制上拉节点PU与第一控制电压输入端GCL连接，以更好的维持上拉节点PU的高电位。此外，本公开实施例所述的移位寄存器单元通过下拉节点状态维持电路12在第一控制电压输入端GCL的控制下在空白时间段(所述空白时间段即为触控时间段)控制将下拉节点PD的电位维持为第一电平(所述第一电平例如可以为低电平)，从而减少上拉节点PU漏电的路径，利于维持上拉节点PU的电位。
本公开实施例所述的移位寄存器单元的驱动方法，应用于上述的移位寄存器单元，所述移位寄存器单元的驱动方法包括：
在触控时间段，向第一控制电压输入端输入高电压，上拉节点状态维持电路控制与开启的栅线对应的移位寄存器单元中的上拉节点与所述第一控制电压输入端连通。
在触控时间段(即空白时间段)，上拉节点状态维持电路控制与开启的栅线对应的移位寄存器单元中的上拉节点与所述第一控制电压输入端连通，以维持该上拉节点的电位为高电平，以减少该上拉节点的漏电路径，这样，可以使得处于LH Blanking触控驱动模式下的栅极驱动电路的分段处(触控时间段和显示时间段分段处)附近的移位寄存器单元中的上拉节点的电位能长时间保持为高电平。
具体的，本公开实施例所述的移位寄存器单元的驱动方法还包括：在显示时间段，向所述第一控制电压输入端输入低电压，所述上拉节点状态维持电路控制与所有行栅线对应的多个移位寄存器单元中的上拉节点与所述第一控制电压输入端之间不连通。
在显示时间段，上拉节点状态维持电路控制所述上拉节点与所述第一控制电压输入端之间不连通，以不影响正常显示。
具体的，所述移位寄存器单元包括下拉节点状态维持电路，与下拉节点、第二控制电压输入端和第一电平输入端连接，被构造成根据所述第二控制电压输入端的输入电位控制所述下拉节点是否与所述第一电平输入端连通，本公开实施例所述的移位寄存器单元的驱动方法还包括：向所述第一电平输入端加载低电平直流信号，在触控时间段，控制向所述第二控制电压输入端输入的电压，以使得所述下拉节点状态维持电路控制与开启的栅线对应的移位寄存器单元中的下拉节点与所述第一电平输入端连通。
在触控时间段(即空白时间段)，向所述第一电平输入端加载低电平直流信号，下拉节点状态维持电路控制与开启的栅线对应的移位寄存器单元中的下拉节点与所述第一电平输入端连通，以使得该下拉节点的电位为低电平，以减少该上拉节点的漏电路径，这样，可以使得处于LH Blanking触控驱动模式下的栅极驱动电路的分段处(触控时间段和显示时间段分段处)附近的移位寄存器单元中的上拉节点的电位能长时间保持为高电平。
具体的，本公开实施例所述的移位寄存器单元的驱动方法还包括：在显示时间段，控制向所述第二控制电压输入端输入的电压，以使得所述下拉节点状态维持电路控制与所有行栅线对应的多个移位寄存器中的下拉节点与所述第一电平输入端不连通，以不影响正常显示。
具体的，所述下拉节点状态维持电路包括的晶体管可以是N型晶体管，向所述第一控制电压输入端和所述第二控制电压输入端输入相同的控制电压。也即，此时第一控制电压输入端和所述第二控制电压输入端可以为一个端子，这样可以节省空间。
具体的，每一帧画面显示时间可以包括至少两个触控时间段和至少两个显示时间段；
所述至少两个触控时间段和所述至少两个显示时间段间隔设置。
也即，一触控时间段后面设置一显示时间段，一显示时间段后面设置一触控时间段，当每一帧画面显示时间最后一时间段为触控时间段时，下一帧画面显示时间最开始可以为显示时间段。
相应的，在一帧画面显示时间段之内设置至少两个触控时间段，以提高触控频率。
以上触控时间段和显示时间段的设置即为LH Blanking(空白)触控驱动模式，在一帧画面显示时间段之内设置至少两个触控时间段，以提高触控频率。
本公开实施例所述的栅极驱动电路包括多个级联的上述的移位寄存器单元。
本公开实施例所述的显示装置包括上述的栅极驱动电路。
与相关技术相比，本公开实施例所述的移位寄存器单元、驱动方法、栅极驱动电路和显示装置可以维持与开启的栅线对应的移位寄存器单元中的上拉节点的电位在空白时间段(所述空白时间段即为触控时间段)为高电平，进而维持所述上拉节点的电位状态不变，以提升上拉节点电位保持能力，解决相关技术中上拉节点的电位在触控时间段下降幅度大，从而导致横纹不良现象发生的技术问题。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (19)

  1. 一种移位寄存器单元，包括：
    上拉节点状态维持电路，与上拉节点和第一控制电压输入端连接，被构造成根据所述上拉节点的电位和第一控制电压输入端的输入电位控制所述上拉节点是否与所述第一控制电压输入端连通，进而维持所述上拉节点的电位状态不变。
  2. 如权利要求1所述的移位寄存器单元，其中，所述上拉节点状态维持电路包括：
    上拉控制节点控制子电路，与所述上拉节点、所述第一控制电压输入端和上拉控制节点连接，被构造成根据所述上拉节点的电位控制所述上拉控制节点是否与所述第一控制电压输入端连通；以及，
    上拉节点状态维持子电路，与所述上拉控制节点、所述第一控制电压输入端和所述上拉节点连接，被构造成根据所述上拉控制节点的电位控制所述上拉节点是否与所述第一控制电压输入端连通。
  3. 如权利要求2所述的移位寄存器单元，其中，所述上拉控制节点控制子电路包括：
    上拉控制节点控制晶体管，栅极与所述上拉节点连接，第一极与所述第一控制电压输入端连接，第二极与所述上拉控制节点连接。
  4. 如权利要求2所述的移位寄存器单元，其中，所述上拉节点状态维持子电路包括：
    上拉节点状态维持晶体管，栅极与所述上拉控制节点连接，第一极与所述第一控制电压输入端连接，第二极与所述上拉节点连接。
  5. 如权利要求4所述的移位寄存器单元，其中，所述上拉节点状态维持子电路还包括连接于所述上拉节点状态维持晶体管的第二极与所述上拉节点之间的开关电路；所述开关电路的控制端与所述上拉控制节点连接；
    所述开关电路被构造成在所述上拉控制节点的控制下控制所述上拉节点状态维持晶体管的第二极是否与所述上拉节点连通。
  6. 如权利要求5所述的移位寄存器单元，其中，所述开关电路包括一个 开关晶体管；
    所述开关晶体管的栅极与所述上拉控制节点连接，所述开关晶体管的第一极与所述上拉节点状态维持晶体管的第二极连接，所述开关晶体管的第二极与所述上拉节点连接。
  7. 如权利要求5所述的移位寄存器单元，其中，所述开关电路包括第一开关晶体管和第二开关晶体管，其中，
    所述第一开关晶体管的栅极与所述上拉控制节点连接，所述第一开关晶体管的第一极与所述上拉节点状态维持晶体管的第二极连接；
    所述第二开关晶体管的栅极与所述上拉控制节点连接，所述第二开关晶体管的第一极与所述第一开关晶体管的第二极连接，所述第二开关晶体管的第二极与所述上拉节点连接。
  8. 如权利要求5所述的移位寄存器单元，其中，所述开关电路包括N个开关晶体管，N为大于2的整数；
    第一开关晶体管的栅极与所述上拉控制节点连接，所述第一开关晶体管的第一极与所述上拉节点状态维持晶体管的第二极连接；
    第n开关晶体管的栅极与所述上拉控制节点连接，所述第n开关晶体管的第一极与所述第n-1开关晶体管的第二极连接；n为大于1而小于N的整数；
    第N开关晶体管的栅极与所述上拉控制节点连接，所述第N开关晶体管的第一极与第N-1开关晶体管的第二极连接，所述第N开关晶体管的第二极与所述上拉节点连接。
  9. 如权利要求1所述的移位寄存器单元，其中，所述上拉节点状态维持电路包括一晶体管，该晶体管的栅极和该晶体管的漏极都与所述上拉节点连接，该晶体管的源极与所述第一控制电压输入端连接。
  10. 如权利要求1至9中任一权利要求所述的移位寄存器单元，其中，所述移位寄存器单元还包括：
    下拉节点状态维持电路，与下拉节点、第二控制电压输入端和第一电平输入端连接，被构造成根据所述第二控制电压输入端的输入电位控制所述下拉节点是否与所述第一电平输入端连通。
  11. 如权利要求10所述的移位寄存器单元，其中，所述下拉节点状态维持电路包括：下拉节点维持晶体管，栅极与所述第二控制电压输入端连接，第一极与所述下拉节点连接，第二极与所述第一电平输入端连接。
  12. 一种移位寄存器单元的驱动方法，应用于如权利要求1至11中任一权利要求所述的移位寄存器单元，所述移位寄存器单元的驱动方法包括：
    在触控时间段，向第一控制电压输入端输入高电压，上拉节点状态维持电路控制与开启的栅线对应的移位寄存器单元中的上拉节点与所述第一控制电压输入端连通。
  13. 如权利要求12所述的移位寄存器单元的驱动方法，其中，所述移位寄存器单元的驱动方法还包括：在显示时间段，向所述第一控制电压输入端输入低电压，所述上拉节点状态维持电路控制与所有行栅线对应的多个移位寄存器中的上拉节点与所述第一控制电压输入端之间不连通。
  14. 如权利要求12或13所述的移位寄存器单元的驱动方法，其中，所述移位寄存器单元包括下拉节点状态维持电路，与下拉节点、第二控制电压输入端和第一电平输入端连接，被构造成根据所述第二控制电压输入端的输入电位控制所述下拉节点是否与所述第一电平输入端连通，所述移位寄存器单元的驱动方法还包括：向所述第一电平输入端加载低电平直流信号，在所述触控时间段，控制向所述第二控制电压输入端输入的电压，以使得所述下拉节点状态维持电路控制与开启的栅线对应的移位寄存器单元中的下拉节点与所述第一电平输入端连通。
  15. 如权利要求14所述的移位寄存器单元的驱动方法，其中，所述移位寄存器单元的驱动方法还包括：在所述显示时间段，控制向所述第二控制电压输入端输入的电压，以使得所述下拉节点状态维持电路控制与所有行栅线对应的多个移位寄存器中的下拉节点与所述第一电平输入端不连通。
  16. 如权利要求11至15中任一权利要求所述的移位寄存器单元的驱动方法，其中，所述下拉节点状态维持电路包括N型晶体管，向所述第一控制电压输入端和所述第二控制电压输入端输入相同的控制电压。
  17. 如权利要求12或13所述的移位寄存器单元的驱动方法，其中，每一帧画面显示时间包括至少两个触控时间段和至少两个显示时间段；
    所述至少两个触控时间段和所述至少两个显示时间段间隔设置。
  18. 一种栅极驱动电路，包括多个级联的如权利要求1至11中任一权利要求所述的移位寄存器单元。
  19. 一种显示装置，包括如权利要求18所述的栅极驱动电路。
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