WO2019033549A1 - 一种goa电路及液晶显示装置 - Google Patents

一种goa电路及液晶显示装置 Download PDF

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Publication number
WO2019033549A1
WO2019033549A1 PCT/CN2017/107543 CN2017107543W WO2019033549A1 WO 2019033549 A1 WO2019033549 A1 WO 2019033549A1 CN 2017107543 W CN2017107543 W CN 2017107543W WO 2019033549 A1 WO2019033549 A1 WO 2019033549A1
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Prior art keywords
thin film
film transistor
electrically connected
clock signal
node
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PCT/CN2017/107543
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English (en)
French (fr)
Inventor
石龙强
陈书志
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US15/739,783 priority Critical patent/US10453414B2/en
Publication of WO2019033549A1 publication Critical patent/WO2019033549A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to a GOA circuit and a liquid crystal display device.
  • the liquid crystal display device has advantages of high display quality, low price, and convenient portability, and has become a display device for mobile communication devices, PCs, TVs, and the like.
  • the liquid crystal display device driving technology tends to adopt GOA technology.
  • the GOA technology can simplify the manufacturing process of the flat display panel, eliminating the bonding process in the horizontal scanning line direction, which can increase the productivity, reduce the product cost, and can improve the display panel.
  • the integration makes it more suitable for making narrow border or borderless display products, satisfying the visual pursuit of modern people.
  • the existing GOA circuit includes a plurality of cascaded GOA units, FIG. 1 is a circuit diagram of a conventional N-th stage GOA unit, and FIG. 2 is a waveform of each node or each output end of the present invention. Please refer to FIG. 1 and FIG.
  • the N-stage GOA unit includes a pull-up control unit 110, a pull-up unit 120, a pull-down unit 130, a pull-down maintaining unit 140, a downlink unit 150, and a bootstrap capacitor unit 160.
  • the pull-up unit 120 is mainly responsible for outputting the clock signal CK to the N-th horizontal scanning line G(N) of the display region, including the third transistor T3.
  • the pull-up control unit 110 is responsible for controlling the turn-on time of the pull-up unit 120, including the first transistor T1, the downlink signal ST(N-1) of the previous stage or the start signal STV is input to the gate and source of the first transistor T1.
  • the drain of the first transistor T1 is connected to the first node Q(N).
  • the pull-down unit 130 is responsible for pulling the horizontal scan signal on the Nth horizontal scanning line G(N) to a low level, that is, turning off the horizontal scanning signal, including the transistors T4 and T5, and the downlink signal ST(N+1) of the latter stage.
  • the pull-down maintaining unit 140 is responsible for maintaining the horizontal scanning signal on the Nth horizontal scanning line G(N) and the first node Q(N) in a closed state (ie, a negative potential).
  • the bootstrap capacitor unit 160 is responsible for the secondary rise of the potential of the first node Q(N), which facilitates the output of the pull up unit 120.
  • the downlink unit 150 is configured to output the downlink transmission signal ST(N) of the present stage.
  • VSS stands for DC low voltage.
  • the clock signal CK suddenly disappears in one cycle, and the disappearance of the clock signal CK causes the downlink signal ST(N+1) of the next-stage GOA unit to be output. Because the normal high-potential effect of the output of the downlink signal ST(N+1) of the next-stage GOA unit is to lower the high potential of the first node Q(N) of the GOA unit of the present stage, and when the next-level GOA unit When the downlink signal ST(N+1) has no output, the high potential of the first node Q(N) of the current stage is maintained at all times. Please refer to FIG. 3, which may cause a large current, and the liquid crystal display device may be damaged.
  • a technical problem to be solved by embodiments of the present invention is to provide a GOA circuit and a liquid crystal display device.
  • the clock signal fails, the potential of the first node can be pulled down, thereby preventing damage of the liquid crystal display device.
  • the first aspect of the present invention provides a GOA circuit, which includes a plurality of cascaded GOA units, and outputs a gate driving signal to the display area in accordance with the Nth stage GOA unit.
  • the Nth stage GOA unit includes a pull-up unit, a pull-up control unit, a pull-down unit, a pull-down maintaining unit, a downlink unit, and a bootstrap capacitor unit; the pull-up unit, the pull-down unit, and the The pull-down maintaining unit and the bootstrap capacitor unit are respectively electrically connected to the first node and the N-th horizontal scanning line, and the pull-up control unit and the downlink unit are electrically connected to the first node, where N is a positive integer
  • the GOA unit also includes:
  • a forced pull down unit is used to force the first node to be low when the clock signal disappears.
  • the forced pull-down unit includes a twelfth thin film transistor, and a gate of the twelfth thin film transistor is connected to a reset signal, and a source thereof is electrically connected to the first node, and a drain thereof is connected to the first low level.
  • the reset signal changes from a low level to a high level when the clock signal disappears.
  • the pull-down maintaining unit includes a sixth thin film transistor, a seventh thin film transistor, and an eighth thin a film transistor, a ninth thin film transistor, a tenth thin film transistor, and an eleventh thin film transistor, wherein a source of the sixth thin film transistor is electrically connected to the first node, and a drain thereof is connected to the first low level, and the gate thereof is The Nth second node is electrically connected, the source of the seven thin film transistor is electrically connected to the Nth horizontal scanning line, the drain thereof is connected to the first low level, and the gate thereof is electrically connected to the Nth second node.
  • the gate and the source of the eighth thin film transistor are electrically connected to a high level, and the drain thereof is electrically connected to a gate of the ninth thin film transistor and a source of the eleventh thin film transistor, respectively, and a source of the ninth thin film transistor.
  • the pole is electrically connected to the high level, the drain thereof is electrically connected to the second node of the Nth stage, the source of the tenth thin film transistor is electrically connected to the second node of the Nth stage, and the drain thereof is connected to the first low level,
  • the gate is electrically connected to the first node, the drain of the eleventh thin film transistor is connected to the first low level, and the gate thereof is electrically connected to the first node.
  • the forced pull-down unit includes a thirteenth thin film transistor, and a gate of the thirteenth thin film transistor is connected to a reset signal, and a source thereof is electrically connected to a high level, and a drain thereof and a second node of the Nth stage Electrically connected, the reset signal transitions from a low level to a high level when the clock signal disappears.
  • the clock signal includes a first clock signal and a second clock signal, and the first clock signal and the second clock signal have the same frequency, and the phases are opposite in time except for the blanking time in one cycle;
  • the forced pull-down unit includes The eighteenth thin film transistor, the nineteenth thin film transistor, the twentieth thin film transistor, and the twenty first thin film transistor, wherein the source and the gate of the eighteenth thin film transistor are electrically connected to a high level, and the drains thereof are respectively a gate of the nineteenth thin film transistor, a source of the twentieth thin film transistor, and a source of the twenty first thin film transistor are electrically connected, and a source of the nineteenth thin film transistor is electrically connected to a high level, and a drain thereof Electrically connecting with the second node of the Nth stage, the gate of the twentieth thin film transistor is electrically connected to the first clock signal, the drain thereof is electrically connected to the first low level, and the gate of the second eleventh thin film transistor is The pole is electrically connected to the second clock signal, and the drain thereof is
  • the clock signal includes a first clock signal and a second clock signal, and the first clock signal and the second clock signal have the same frequency, and the phases are opposite in time except for the blanking time in one cycle;
  • the forced pull-down unit includes a fourteenth thin film transistor, a fifteenth thin film transistor, a sixteenth thin film transistor, and a seventeenth thin film transistor, wherein a source and a gate of the fourteenth thin film transistor are electrically connected to a high level, and a drain thereof is respectively
  • the gate of the fifteen thin film transistor, the source of the sixteenth thin film transistor, and the source of the seventeenth thin film transistor are electrically connected, and the source of the fifteenth thin film transistor is electrically connected to the first node, and the drain and the a low-level electrical connection, a gate of the sixteenth thin film transistor is electrically connected to the first clock signal, a drain thereof is electrically connected to the first low level, and a gate of the seventeenth thin film transistor is connected to the second Clock letter
  • the number is electrically connected,
  • one cycle of the GOA driving circuit includes a blanking time
  • the forced pull-down unit forces the first node to be low when the clock signal disappears at a time other than the blanking time of the GOA driving circuit.
  • the pull-up unit includes a third thin film transistor, the source of the third thin film transistor is connected to the first clock signal, the gate thereof is electrically connected to the first node, and the drain thereof is connected to the Nth horizontal scan line. connection.
  • the pull-down unit includes a fourth thin film transistor and a fifth thin film transistor, the source of the fourth thin film transistor is electrically connected to the first node, and the drain thereof is connected to the first low level, and the fifth thin film transistor is The source is electrically connected to the Nth horizontal scanning line, the drain thereof is connected to the first low level, and the gate of the fourth thin film transistor and the gate of the fifth thin film transistor are used to be connected to the N+1th stage. Signal.
  • a second aspect of the present invention provides a liquid crystal display device including the above GOA driving circuit.
  • the GOA unit includes a forced pull-down unit, it is used to force the first node to be low when the clock signal disappears, so that when the clock signal suddenly disappears in one cycle due to signal interference, the forced pull-down unit will The first node is forced to be at a low level so as not to cause a large current, and the liquid crystal display device is not damaged.
  • 1 is a circuit diagram of a prior art Nth stage GOA unit
  • FIG. 2 is a signal timing diagram of a prior art Nth stage GOA unit
  • FIG. 3 is a signal timing diagram of an Nth stage GOA unit when a prior art clock signal fails
  • FIG. 5 is a signal timing diagram of an Nth stage GOA unit when a clock signal fails in the first embodiment of the present invention
  • Figure 6 is a circuit diagram of an Nth stage GOA unit of a second embodiment of the present invention.
  • FIG. 7 is a signal timing diagram of an Nth stage GOA unit when a clock signal fails in the second embodiment of the present invention.
  • Figure 8 is a circuit diagram of an Nth stage GOA unit of a third embodiment of the present invention.
  • Figure 9 is a circuit diagram of an Nth stage GOA unit of a fourth embodiment of the present invention.
  • An embodiment of the present invention provides a GOA driving circuit, where the GOA driving circuit includes a plurality of cascaded GOA units, for example, including M GOA units, and the second level GOA unit is electrically connected to the first level GOA unit, and the third level GOA
  • the unit is electrically connected to the second stage GOA unit, ..., the Mth stage GOA unit is electrically connected to the M-1th stage GOA unit, and each GOA unit outputs a gate driving signal to the horizontal scanning line G corresponding to the display area, for example, the first The stage GOA unit outputs a gate driving signal to the first level horizontal scanning line G(1), the second stage GOA unit outputs a gate driving signal to the second level horizontal scanning line G(2), and the third stage GOA unit output gate Drive signal to the third level horizontal scanning line G(3),..., The M-level GOA unit outputs a gate drive signal to the M-th horizontal scanning line G(M).
  • the GOA driving circuit sequentially outputs gate driving signals to the first horizontal scanning line G(1), the second horizontal scanning line G(2), the third horizontal scanning line G(3), ..., the Mth horizontal scanning line G ( M), after a while, the GOA driving circuit sequentially outputs the gate driving signal to the first horizontal scanning line G(1), the second horizontal scanning line G(2), and the third horizontal scanning line G(3).
  • the Mth horizontal scanning line G(M) that is, the GOA driving circuit outputs the gate driving signal in cycles
  • one cycle of the GOA driving circuit includes a blanking time
  • the blanking time is the Mth level GOA unit
  • M is a positive integer.
  • the GO stage unit of the Nth stage includes a pull-up control unit 210, a pull-up unit 220, a pull-down unit 230, a pull-down maintaining unit 240, a downlink unit 250, and a bootstrap capacitor unit. 260, where N is a positive integer and N is less than or equal to M.
  • the pull-up unit 220, the pull-down unit 230, the pull-down maintaining unit 240, and the bootstrap capacitor unit 260 are respectively electrically connected to the first node Q(N) and the N-th horizontal scanning line G(N), and the pull-up control Unit 210 and downlink unit 250 are electrically coupled to first node Q(N).
  • the GOA unit further includes a forced pull-down unit 270 for forcing the first node Q(N) to be low when the clock signal disappears.
  • the forced pull-down unit 270 forces the first node Q(N) to be low when the clock signal disappears at a time other than the blanking time of one cycle of the GOA driving circuit.
  • the first node Q(N) may be the first node Q(N) of the Nth stage GOA driving unit, or may be the first node Q(N) common to the GOA driving circuit.
  • the forced pull-down unit 270 forces the first node Q(N) to be low, see FIG. 5, which does not cause a large current.
  • the liquid crystal display device is also not damaged.
  • the forced pull-down unit 270 includes a twelfth thin film transistor T12.
  • the gate of the twelfth thin film transistor T12 is connected to the reset signal Reset, and the source thereof is electrically connected to the first node Q(N).
  • the drain thereof is connected to the first low level Vss
  • the first low level Vss is a low voltage DC power source
  • the potential is -7V
  • the reset signal Reset is changed from low level to high when the clock signal disappears.
  • Level the clock signal includes a first clock signal CK and a second clock signal XCK
  • the first clock signal CK and the second clock signal XCK have the same frequency, and the blanking time is divided in one cycle.
  • the outer time phase is opposite.
  • the first clock signal CK and the second clock signal XCK are both low, and the first clock signal CK and the second clock signal XCK disappear simultaneously.
  • the reset signal Reset is triggered to be turned from a low level to a high level, so that the twelfth thin film transistor T12 is turned on, thereby the first node Q(N) Pulled down to the first low level Vss, please refer to the waveform diagram of Figure 5, which will not cause a large current, and the liquid crystal display device will not be damaged.
  • the reset signal Reset turns to a low level again at the beginning of the next cycle, that is, the reset signal Reset turns to a low level when the start signal STV is turned to a high level.
  • the pull-down maintaining unit 240 includes a sixth thin film transistor T6 and a seventh thin film transistor T7.
  • the source of the sixth thin film transistor T6 is electrically connected to the first node Q(N), and the drain terminal thereof is connected.
  • the first low level Vss is connected, the gate thereof is electrically connected to the second node K(N), and the source of the seventh thin film transistor T7 is electrically connected to the Nth horizontal scanning line G(N), and the drain is connected
  • the first low level Vss is entered, and its gate is electrically connected to the second node K(N).
  • the pull-down maintaining unit 240 further includes an eighth thin film transistor T8, a ninth thin film transistor T9, a tenth thin film transistor T10, and an eleventh thin film transistor T11.
  • the gate and the source of the eighth thin film transistor T8 are the first high.
  • the level DCH is electrically connected, the first high level DCH is a high voltage direct current power source, the potential of the first high level DCH is 28V, and the drain of the eighth thin film transistor T8 and the ninth thin film transistor T9 are respectively
  • the gate is electrically connected to the source of the eleventh thin film transistor T11
  • the source of the ninth thin film transistor T9 is electrically connected to the first high level DCH
  • the drain thereof is electrically connected to the second node K(N)
  • the source of the transistor T10 is electrically connected to the second node K(N), the drain thereof is connected to the first low level Vss, the gate thereof is electrically connected to the first node Q(N), and the drain of the eleventh thin film transistor T11 is The pole is connected to the first low level Vss, and its gate is electrically connected to the first node Q(N).
  • the pull-up unit 220 includes a third thin film transistor T3.
  • the source of the third thin film transistor T3 is connected to the first clock signal CK, and the gate thereof is electrically connected to the first node Q(N).
  • the drain thereof is electrically connected to the Nth horizontal scanning line G(N).
  • the downlink unit 250 includes a second thin film transistor T2.
  • the source of the second thin film transistor T2 is connected to the first clock signal CK, and the gate thereof is electrically connected to the first node Q(N).
  • the drain is used to output the Nth stage down signal ST(N).
  • the pull-down unit 230 includes a fourth thin film transistor T4 and a fifth thin film transistor T5.
  • the source of the fourth thin film transistor T4 is electrically connected to the first node Q(N), and the drain thereof is connected.
  • a low level Vss, a source of the fifth thin film transistor T5 and an Nth horizontal scanning line G(N) Electrically connected, the drain of which is connected to the first low level Vss, the gate of the fourth thin film transistor T4 and the gate of the fifth thin film transistor T5 are used to connect the N+1th down signal ST(N+ 1).
  • the pull-up control unit 210 includes a first thin film transistor T1, and the gate and source of the first thin film transistor T1 receive the N-1th-level downlink signal ST(N-1) or The start signal STV has its drain electrically connected to the first node Q(N).
  • the bootstrap capacitor unit 260 includes a capacitor Cb, one end of which is electrically connected to the first node Q(N), and the other end is electrically connected to the Nth horizontal scan line G(N).
  • an embodiment of the present invention further provides a liquid crystal display device including the above GOA driving circuit.
  • FIG. 6 is a circuit diagram of an Nth-level GOA unit according to a second embodiment of the present invention.
  • the circuit of FIG. 6 is similar to the circuit of FIG. 4, and thus the same component symbols represent the same components.
  • the clock signal includes a first clock signal CK and a second clock signal XCK, and the first clock signal CK and the second clock signal XCK have the same frequency, and the time phase other than the blanking time in one cycle In contrast, the first clock signal CK and the second clock signal XCK are both at a low level during the blanking time.
  • the forced pull-down unit 370 includes a fourteenth thin film transistor T14 , a fifteenth thin film transistor T15 , a sixteenth thin film transistor T16 , and a seventeenth thin film transistor T17 , and the fourteenth thin film transistor
  • the source and the gate of T14 are electrically connected to the first high level DCH, and the drain thereof is respectively connected to the gate of the fifteenth thin film transistor T15, the source of the sixteenth thin film transistor T16, and the source of the seventeenth thin film transistor T17.
  • the source of the fifteenth thin film transistor T15 is electrically connected to the first node Q(N), and the drain thereof is electrically connected to the first low level Vss, and the gate of the sixteenth thin film transistor T16 Electrically connected to the first clock signal CK, the drain thereof is electrically connected to the first low level Vss, the gate of the seventeenth thin film transistor T17 is electrically connected to the second clock signal XCK, and the drain and the first low voltage Flat Vss electrical connection.
  • the clock signal suddenly disappears in one cycle due to signal interference, that is, when the first clock signal CK and the second clock signal XCK suddenly disappear, the sixteenth thin film transistor T16 and the seventeenth thin film transistor T17 are turned off.
  • the fourteenth thin film transistor T14 is turned on, thereby The three-node S(N) is at a high level, so that the fifteenth thin film transistor T15 is turned on, thereby pulling the first node Q(N) low to the first low level Vss, see FIG. 7, which does not cause High current, liquid crystal display device will not be damaged.
  • FIG. 8 is a circuit diagram of an Nth-level GOA unit according to a second embodiment of the present invention.
  • the circuit of FIG. 8 is similar to the circuit of FIG. 4, and thus the same component symbols represent the same components.
  • the forced pull-down unit 470 includes a thirteenth thin film transistor T13.
  • the gate of the thirteenth thin film transistor T13 is connected to the reset signal Reset, and the source thereof is electrically connected to the first high level DCH.
  • the drain thereof is electrically connected to the Nth stage second node K(N), and the reset signal Reset changes from a low level to a high level when the clock signal disappears.
  • the reset signal Reset changes from a low level to a high level, so that the thirteenth thin film transistor T13 is turned on when the first node Q(N) is high.
  • the eighth thin film transistor T8, the tenth thin film transistor T10, and the eleventh thin film transistor T11 are turned on, and the ninth thin film transistor T9 is turned off. Since the thirteenth thin film transistor T13 is turned on, the second node K (N) Is pulled high to the sixth thin film transistor T6, so that the first node Q(N) is pulled down to the first low level Vss, which does not cause a large current, and the liquid crystal display device does not Suffered from damage.
  • FIG. 9 is a circuit diagram of an Nth-level GOA unit according to a fourth embodiment of the present invention.
  • the circuit of FIG. 9 is similar to the circuit of FIG. 8. Therefore, the same component symbols represent the same components.
  • the clock signal includes a first clock signal CK and a second clock signal XCK, and the first clock signal CK and the second clock signal XCK have the same frequency, and the time phase other than the blanking time in one cycle In contrast, the first clock signal CK and the second clock signal XCK are both at a low level during the blanking time.
  • the forced pull-down unit 570 includes an eighteenth thin film transistor T18, a nineteenth thin film transistor T19, a twentieth thin film transistor, and a twenty-first thin film transistor, and the eighteenth thin film.
  • the source and the gate of the transistor T18 are electrically connected to the first high level DCH, and the drain thereof is respectively connected to the gate of the nineteenth thin film transistor T19, the source of the twentieth thin film transistor, and the source of the twenty first thin film transistor.
  • the source of the nineteenth thin film transistor T19 is electrically connected to a high level, and the drain thereof is electrically connected to the Nth second node K(N), and the gate of the twentieth thin film transistor is
  • the first clock signal CK is electrically connected, the drain thereof is electrically connected to the first low level Vss, the gate of the 21st thin film transistor is electrically connected to the second clock signal XCK, and the drain thereof and the first low level Vss is electrically connected.
  • the twentieth thin film transistor and the twenty-first thin film transistor are turned off,
  • the eighteenth thin film transistor T18 is turned on, so that the third node S(N) is at a high level, so that the nineteenth thin film transistor T19 is turned on, so that the second node K(N) is pulled high, and thus the sixth
  • the thin film transistor T6 is turned on, so that the first node Q(N) is pulled down to the first low level Vss, so that a large current is not caused, and the liquid crystal display device is not damaged.
  • the present invention has the following advantages:
  • the GOA unit includes a forced pull-down unit, it is used to force the first node to be low when the clock signal disappears, so that when the clock signal suddenly disappears in one cycle due to signal interference, the forced pull-down unit will The first node is forced to be at a low level so as not to cause a large current, and the liquid crystal display device is not damaged.

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Abstract

公开了一种GOA驱动电路，该GOA驱动电路包括多个级联的GOA单元，按照第N级GOA单元输出栅极驱动信号给显示区域第N级水平扫描线G(N)，该第N级GOA单元包括上拉单元(220)、上拉控制单元(210)、下拉单元(230)、下拉维持单元(240)、下传单元(250)以及自举电容单元(260)；该上拉单元(220)、该下拉单元(230)、该下拉维持单元(240)及该自举电容单元(260)均分别与第一节点Q(N)以及第N级水平扫描线G(N)电连接，该上拉控制单元(210)以及该下传单元(250)与第一节点Q(N)电连接，其中N为正整数；该GOA单元还包括：强制下拉单元(270)，其用于时钟信号(CK)消失时强迫该第一节点Q(N)为低电平。还公开了一种液晶显示装置。该驱动电路具有当时钟信号(CK)失效时可以拉低第一节点Q(N)的电位，从而可以防止液晶显示装置损伤的优点。

Description

一种GOA电路及液晶显示装置
本发明要求2017年8月16日递交的发明名称为“一种GOA电路及液晶显示装置”的申请号CN 201710702450.9的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及液晶显示技术领域，特别是涉及一种GOA电路以及液晶显示装置。
背景技术
液晶显示装置以其显示品质高、价格低廉、携带方便等优点，成为移动通讯设备、PC、TV等的显示装置。目前液晶显示装置驱动技术逐渐趋向于采用GOA技术，GOA技术能简化平板显示面板的制作工序，省去水平扫描线方向的接合(bonding)工艺，可提升产能、降低产品成本，同时可以提升显示面板的集成度使之更适合制作窄边框或无边框显示产品，满足现代人们的视觉追求。
GOA技术，即Gate Driver on Array技术，也就是利用现有薄膜晶体管液晶显示器Array制程将Gate行扫描驱动信号电路制作在Array基板上，实现对Gate逐行扫描的驱动方式。现有的GOA电路包括多个级联的GOA单元，图1是现有的第N级GOA单元的电路图，图2是本发明各个节点或者各个输出端的波形，请参照图1和图2，第N级的GOA单元包括上拉控制单元110、上拉单元120、下拉单元130、下拉维持单元140、下传单元150和自举电容单元160。
上拉单元120主要负责将时钟信号CK输出给显示区域第N级水平扫描线G(N)，包括第三晶体管T3。上拉控制单元110负责控制上拉单元120的打开时间，包括第一晶体管T1，前一级的下传信号ST(N-1)或者起始信号STV输入到第一晶体管T1的栅极和源极，第一晶体管T1的漏极连接到第一节点Q(N)。下拉单元130负责将第N级水平扫描线G(N)上的水平扫描信号拉低为低电位，即关闭水平扫描信号，包括晶体管T4和T5，后一级的下传信号ST(N+1) 输入到晶体管T4和T5的栅极。下拉维持单元140则负责将第N级水平扫描线G(N)上的水平扫描信号和第一节点Q(N)维持在关闭状态(即负电位)。自举电容单元160则负责所述第一节点Q(N)电位的二次抬升，这样有利于上拉单元120的输出。下传单元150用于输出本级下传信号ST(N)。VSS表示直流低电压。
在日常应用中，由于信号干扰等环境影响，时钟信号CK在一个周期中突然消失，时钟讯号CK的消失导致下一级GOA单元的下传信号ST(N+1)没有输出。因为下一级GOA单元的下传信号ST(N+1)的输出正常的高电位作用是将本级GOA单元的第一节点Q(N)的高电位拉低，而当下一级GOA单元的下传信号ST(N+1)没有输出时，本级的第一节点Q(N)的高电位会一直维持，请参见图3,这样会导致大电流，液晶显示装置有可能受到损伤。
发明内容
本发明实施例所要解决的技术问题在于，提供一种GOA电路及液晶显示装置。当时钟信号失效时可以拉低第一节点的电位，从而可以防止液晶显示装置损伤。
为了解决上述技术问题，本发明第一方面实施例提供了一种GOA电路，该GOA驱动电路包括多个级联的GOA单元，按照第N级GOA单元输出栅极驱动信号给显示区域第N级水平扫描线，该第N级GOA单元包括上拉单元、上拉控制单元、下拉单元、下拉维持单元、下传单元以及自举电容单元；所述上拉单元、所述下拉单元以、所述下拉维持单元及所述自举电容单元均分别与第一节点以及第N级水平扫描线电连接，所述上拉控制单元以及所述下传单元与第一节点电连接，其中N为正整数；该GOA单元还包括：
强制下拉单元，其用于时钟信号消失时强迫所述第一节点为低电平。
其中，所述强制下拉单元包括第十二薄膜晶体管，所述第十二薄膜晶体管的栅极接入重置信号，其源极与第一节点电连接，其漏极接入第一低电平，所述重置信号在时钟信号消失时由低电平转为高电平。
其中，所述下拉维持单元包括第六薄膜晶体管、第七薄膜晶体管、第八薄 膜晶体管、第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管，所述第六薄膜晶体管的源极与第一节点电连接，其漏极接入第一低电平，其栅极与第N级第二节点电连接，所述七薄膜晶体管的源极与第N级水平扫描线电连接，其漏极接入第一低电平，其栅极与第N级第二节点电连接，所述第八薄膜晶体管的栅极与源极与高电平电连接，其漏极分别与第九薄膜晶体管的栅极和第十一薄膜晶体管的源极电连接，第九薄膜晶体管的源极与高电平电连接，其漏极与第N级第二节点电连接，第十薄膜晶体管的源极与第N级第二节点电连接，其漏极接入第一低电平，其栅极与第一节点电连接，第十一薄膜晶体管的漏极接入第一低电平，其栅极与第一节点电连接。
其中，所述强制下拉单元包括第十三薄膜晶体管，所述第十三薄膜晶体管的栅极接入重置信号，其源极与高电平电连接，其漏极与第N级第二节点电连接，所述重置信号在时钟信号消失时由低电平转为高电平。
其中，所述时钟信号包括第一时钟信号和第二时钟信号，所述第一时钟信号和第二时钟信号频率相同，在一个周期除消隐时间以外的时间相位相反；所述强制下拉单元包括第十八薄膜晶体管、第十九薄膜晶体管、第二十薄膜晶体管、第二十一薄膜晶体管，所述第十八薄膜晶体管的源极和栅极与高电平电连接，其漏极分别与第十九薄膜晶体管的栅极、第二十薄膜晶体管的源极、第二十一薄膜晶体管的源极电连接，所述第十九薄膜晶体管的源极与高电平电连接，其漏极与第N级第二节点电连接，所述第二十薄膜晶体管的栅极与第一时钟信号电连接，其漏极与第一低电平电连接，所述第二十一薄膜晶体管的栅极与第二时钟信号电连接，其漏极与第一低电平电连接。
其中，所述时钟信号包括第一时钟信号和第二时钟信号，所述第一时钟信号和第二时钟信号频率相同，在一个周期除消隐时间以外的时间相位相反；所述强制下拉单元包括第十四薄膜晶体管、第十五薄膜晶体管、第十六薄膜晶体管、第十七薄膜晶体管，所述第十四薄膜晶体管的源极和栅极与高电平电连接，其漏极分别与第十五薄膜晶体管的栅极、第十六薄膜晶体管的源极、第十七薄膜晶体管的源极电连接，所述第十五薄膜晶体管的源极与第一节点电连接，其漏极与第一低电平电连接，所述第十六薄膜晶体管的栅极与第一时钟信号电连接，其漏极与第一低电平电连接，所述第十七薄膜晶体管的栅极与第二时钟信 号电连接，其漏极与第一低电平电连接。
其中，所述GOA驱动电路的一个周期包括消隐时间，所述强制下拉单元在GOA驱动电路的一个周期除消隐时间以外的时间用于时钟信号消失时强迫所述第一节点为低电平。
其中，所述上拉单元包括第三薄膜晶体管，所述第三薄膜晶体管的源极接入第一时钟信号，其栅极与第一节点电连接，其漏极与第N级水平扫描线电连接。
其中，所述下拉单元包括第四薄膜晶体管和第五薄膜晶体管，所述第四薄膜晶体管的源极与第一节点电连接，其漏极接第一低电平，所述第五薄膜晶体管的源极与第N级水平扫描线电连接，其漏极接第一低电平，所述第四薄膜晶体管的栅极和所述第五薄膜晶体管的栅极用于接第N+1级下传信号。
本发明第二方面实施例提供了一种液晶显示装置，包括上述的GOA驱动电路。
实施本发明实施例，具有如下有益效果：
由于所述GOA单元包括强制下拉单元，其用于时钟信号消失时强迫所述第一节点为低电平，从而，当由于信号干扰而导致时钟信号在一个周期中突然消失时，强制下拉单元会强迫所述第一节点为低电平，这样不会导致大电流，液晶显示装置也不会受到损伤。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术第N级GOA单元的电路图；
图2是现有技术第N级GOA单元的信号时序图；
图3是现有技术时钟信号失效时第N级GOA单元的信号时序图；
图4是本发明第一实施例第N级GOA单元的电路图；
图5是本发明第一实施例时钟信号失效时第N级GOA单元的信号时序图；
图6是本发明第二实施例第N级GOA单元的电路图；
图7是本发明第二实施例时钟信号失效时第N级GOA单元的信号时序图；
图8是本发明第三实施例第N级GOA单元的电路图；
图9是本发明第四实施例第N级GOA单元的电路图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本申请说明书、权利要求书和附图中出现的术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。此外，术语“第一”、“第二”和“第三”等是用于区别不同的对象，而并非用于描述特定的顺序。
第一实施例
本发明实施例提供一种GOA驱动电路，所述GOA驱动电路包括多个级联的GOA单元，例如包括M个GOA单元，第二级GOA单元与第一级GOA单元电连接，第三级GOA单元与第二级GOA单元电连接，…，第M级GOA单元与第M-1级GOA单元电连接，每个GOA单元输出栅极驱动信号给显示区域对应的水平扫描线G，例如第一级GOA单元输出栅极驱动信号给第一级水平扫描线G(1)，第二级GOA单元输出栅极驱动信号给第二级水平扫描线G(2)，第三级GOA单元输出栅极驱动信号给第三级水平扫描线G(3)，…，第 M级GOA单元输出栅极驱动信号给第M级水平扫描线G(M)。GOA驱动电路依序输出栅极驱动信号给第一水平扫描线G(1)、第二水平扫描线G(2)、第三水平扫描线G(3)、…、第M水平扫描线G(M)，其后过一段时间，GOA驱动电路再次依序输出栅极驱动信号给第一水平扫描线G(1)、第二水平扫描线G(2)、第三水平扫描线G(3)、…、第M水平扫描线G(M)，也即GOA驱动电路按周期输出栅极驱动信号，所述GOA驱动电路的一个周期包括消隐时间，所述消隐时间为第M级GOA单元输出栅极驱动信号给第M级水平扫描线G(M)之后的时间到下一个周期开始之间的时间间隔，该消隐时间包括同步前沿时间、同步时间和同步后沿时间。其中M为正整数。
请参见图4和图5，在本实施例中，第N级的GOA单元包括上拉控制单元210、上拉单元220、下拉单元230、下拉维持单元240、下传单元250、自举电容单元260，其中N为正整数，N小于或等于M。所述上拉单元220、下拉单元230、下拉维持单元240及自举电容单元260均分别与第一节点Q(N)以及第N级水平扫描线G(N)电连接，所述上拉控制单元210以及下传单元250与第一节点Q(N)电连接。
在本实施例中，该GOA单元还包括强制下拉单元270，其用于时钟信号消失时强迫所述第一节点Q(N)为低电平。具体说来，所述强制下拉单元270在GOA驱动电路的一个周期除消隐时间以外的时间用于时钟信号消失时强迫所述第一节点Q(N)为低电平。所述第一节点Q(N)可以为第N级GOA驱动单元的第一节点Q(N)，也可以是GOA驱动电路共通的第一节点Q(N)。从而，当由于信号干扰而导致时钟信号在一个周期中突然消失时，强制下拉单元270会强迫所述第一节点Q(N)为低电平，请参见图5，这样不会导致大电流，液晶显示装置也不会受到损伤。
请继续参见图4，所述强制下拉单元270包括第十二薄膜晶体管T12，所述第十二薄膜晶体管T12的栅极接入重置信号Reset，其源极与第一节点Q(N)电连接，其漏极接入第一低电平Vss，所述第一低电平Vss为低压直流电源，电位为-7V，所述重置信号Reset在时钟信号消失时由低电平转为高电平。在本实施中，所述时钟信号包括第一时钟信号CK和第二时钟信号XCK，所述第一时钟信号CK和第二时钟信号XCK频率相同，在一个周期除消隐时间以 外的时间相位相反，在消隐时间所述第一时钟信号CK和第二时钟信号XCK都为低电平，第一时钟信号CK和第二时钟信号XCK会同时消失。当由于信号干扰而导致时钟信号在一个周期中突然消失时，会触发重置信号Reset由低电平转为高电平，从而第十二薄膜晶体管T12导通，从而第一节点Q(N)被拉低至第一低电平Vss，请参见图5的波形图，这样不会导致大电流，液晶显示装置也不会受到损伤。所述重置信号Reset在下一个周期开始时又会转为低电平，也即所述重置信号Reset在接到起始信号STV转为高电平时又转为低电平。
在本实施例中，所述下拉维持单元240包括第六薄膜晶体管T6、第七薄膜晶体管T7，所述第六薄膜晶体管T6的源极与第一节点Q(N)电连接，其漏极接入第一低电平Vss，其栅极与第二节点K(N)电连接，所述第七薄膜晶体管T7的源极与第N级水平扫描线G(N)电连接，其漏极接入第一低电平Vss，其栅极与第二节点K(N)电连接。所述下拉维持单元240还包括第八薄膜晶体管T8、第九薄膜晶体管T9、第十薄膜晶体管T10、第十一薄膜晶体管T11，所述第八薄膜晶体管T8的栅极与源极与第一高电平DCH电连接，所述第一高电平DCH为高压直流电源，所述第一高电平DCH的电位为28V，所述第八薄膜晶体管T8的漏极分别与第九薄膜晶体管T9的栅极和第十一薄膜晶体管T11的源极电连接，第九薄膜晶体管T9的源极与第一高电平DCH电连接，其漏极与第二节点K(N)电连接，第十薄膜晶体管T10的源极与第二节点K(N)电连接，其漏极接入第一低电平Vss，其栅极与第一节点Q(N)电连接，第十一薄膜晶体管T11的漏极接入第一低电平Vss，其栅极与第一节点Q(N)电连接。
在本实施例中，所述上拉单元220包括第三薄膜晶体管T3，所述第三薄膜晶体管T3的源极接入第一时钟信号CK，其栅极与第一节点Q(N)电连接，其漏极与第N级水平扫描线G(N)电连接。
在本实施例中，所述下传单元250包括第二薄膜晶体管T2，所述第二薄膜晶体管T2的源极接入第一时钟信号CK，其栅极与第一节点Q(N)电连接，其漏极用于输出第N级下传信号ST(N)。
在本实施例中，所述下拉单元230包括第四薄膜晶体管T4和第五薄膜晶体管T5，所述第四薄膜晶体管T4的源极与第一节点Q(N)电连接，其漏极接第一低电平Vss，所述第五薄膜晶体管T5的源极与第N级水平扫描线G(N) 电连接，其漏极接第一低电平Vss，所述第四薄膜晶体管T4的栅极和所述第五薄膜晶体管T5的栅极用于接第N+1级下传信号ST(N+1)。
在本实施例中，所述上拉控制单元210包括第一薄膜晶体管T1，所述第一薄膜晶体管T1的栅极和源极接收第N-1级下传信号ST(N-1)或者起始信号STV，其漏极与第一节点Q(N)电连接。
在本实施例中，所述自举电容单元260包括电容Cb，所述电容Cb的一端与第一节点Q(N)电连接，另一端与第N级水平扫描线G(N)电连接。
另外，本发明实施例还提供一种液晶显示装置，其包括上述的GOA驱动电路。
第二实施例
图6为本发明第二实施例提供的一种第N级GOA单元的电路图，图6的电路与图4的电路相似，因此相同的元件符号代表相同的元件，本实施例与第一实施例的主要不同点为强制下拉单元。
在本实施例中，所述时钟信号包括第一时钟信号CK和第二时钟信号XCK，所述第一时钟信号CK和第二时钟信号XCK频率相同，在一个周期除消隐时间以外的时间相位相反，在消隐时间所述第一时钟信号CK和第二时钟信号XCK都为低电平。
请参见图6和图7，所述强制下拉单元370包括第十四薄膜晶体管T14、第十五薄膜晶体管T15、第十六薄膜晶体管T16、第十七薄膜晶体管T17，所述第十四薄膜晶体管T14的源极和栅极与第一高电平DCH电连接，其漏极分别与第十五薄膜晶体管T15的栅极、第十六薄膜晶体管T16的源极、第十七薄膜晶体管T17的源极电连接，所述第十五薄膜晶体管T15的源极与第一节点Q(N)电连接，其漏极与第一低电平Vss电连接，所述第十六薄膜晶体管T16的栅极与第一时钟信号CK电连接，其漏极与第一低电平Vss电连接，所述第十七薄膜晶体管T17的栅极与第二时钟信号XCK电连接，其漏极与第一低电平Vss电连接。当由于信号干扰而导致时钟信号在一个周期中突然消失时，也即第一时钟信号CK和第二时钟信号XCK突然消失时，此时第十六薄膜晶体管T16和第十七薄膜晶体管T17截止，第十四薄膜晶体管T14导通，从而第 三节点S(N)为高电平，从而第十五薄膜晶体管T15导通，从而将第一节点Q(N)被拉低为第一低电平Vss，请参见图7，这样不会导致大电流，液晶显示装置也不会受到损伤。
第三实施例
图8为本发明第二实施例提供的一种第N级GOA单元的电路图，图8的电路与图4的电路相似，因此相同的元件符号代表相同的元件，本实施例与第一实施例的主要不同点为强制下拉单元。
请参见图8，所述强制下拉单元470包括第十三薄膜晶体管T13，所述第十三薄膜晶体管T13的栅极接入重置信号Reset，其源极与第一高电平DCH电连接，其漏极与第N级第二节点K(N)电连接，所述重置信号Reset在时钟信号消失时由低电平转为高电平。当由于信号干扰而导致时钟信号在一个周期中突然消失时，重置信号Reset由低电平转为高电平，从而第十三薄膜晶体管T13导通，当第一节点Q(N)是高电平时，所述第八薄膜晶体管T8、第十薄膜晶体管T10、第十一薄膜晶体管T11导通，第九薄膜晶体管T9截止，由于第十三薄膜晶体管T13导通，从而第二节点K(N)被拉升为高电平，从而第六薄膜晶体管T6导通，从而第一节点Q(N)被拉低为第一低电平Vss，这样不会导致大电流，液晶显示装置也不会受到损伤。
第四实施例
图9为本发明第四实施例提供的一种第N级GOA单元的电路图，图9的电路与图8的电路相似，因此相同的元件符号代表相同的元件，本实施例与第一实施例的主要不同点为强制下拉单元。
在本实施例中，所述时钟信号包括第一时钟信号CK和第二时钟信号XCK，所述第一时钟信号CK和第二时钟信号XCK频率相同，在一个周期除消隐时间以外的时间相位相反，在消隐时间所述第一时钟信号CK和第二时钟信号XCK都为低电平。
请参见图9，所述强制下拉单元570包括第十八薄膜晶体管T18、第十九薄膜晶体管T19、第二十薄膜晶体管、第二十一薄膜晶体管，所述第十八薄膜 晶体管T18的源极和栅极与第一高电平DCH电连接，其漏极分别与第十九薄膜晶体管T19的栅极、第二十薄膜晶体管的源极、第二十一薄膜晶体管的源极电连接，所述第十九薄膜晶体管T19的源极与高电平电连接，其漏极与第N级第二节点K(N)电连接，所述第二十薄膜晶体管的栅极与第一时钟信号CK电连接，其漏极与第一低电平Vss电连接，所述第二十一薄膜晶体管的栅极与第二时钟信号XCK电连接，其漏极与第一低电平Vss电连接。当由于信号干扰而导致时钟信号在一个周期中突然消失时，也即第一时钟信号CK和第二时钟信号XCK突然消失时，此时第二十薄膜晶体管和第二十一薄膜晶体管截止，第十八薄膜晶体管T18导通，从而第三节点S(N)为高电平，从而第十九薄膜晶体管T19导通，从而第二节点K(N)被拉升为高电平，从而第六薄膜晶体管T6导通，从而第一节点Q(N)被拉低为第一低电平Vss，这样不会导致大电流，液晶显示装置也不会受到损伤。
需要说明的是，本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其它实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。对于装置实施例而言，由于其与方法实施例基本相似，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。
通过上述实施例的描述，本发明具有以下优点：
由于所述GOA单元包括强制下拉单元，其用于时钟信号消失时强迫所述第一节点为低电平，从而，当由于信号干扰而导致时钟信号在一个周期中突然消失时，强制下拉单元会强迫所述第一节点为低电平，这样不会导致大电流，液晶显示装置也不会受到损伤。
以上所揭露的仅为本发明较佳实施例而已，当然不能以此来限定本发明之权利范围，因此依本发明权利要求所作的等同变化，仍属本发明所涵盖的范围。

Claims (20)

  1. 一种GOA驱动电路，其中，该GOA驱动电路包括多个级联的GOA单元，按照第N级GOA单元输出栅极驱动信号给显示区域第N级水平扫描线，该第N级GOA单元包括上拉单元、上拉控制单元、下拉单元、下拉维持单元、下传单元以及自举电容单元；所述上拉单元、所述下拉单元以、所述下拉维持单元及所述自举电容单元均分别与第一节点以及第N级水平扫描线电连接，所述上拉控制单元以及所述下传单元与第一节点电连接，其中N为正整数；该GOA单元还包括：
    强制下拉单元，其用于时钟信号消失时强迫所述第一节点为低电平。
  2. 如权利要求1所述的GOA驱动电路，其中，所述强制下拉单元包括第十二薄膜晶体管，所述第十二薄膜晶体管的栅极接入重置信号，其源极与第一节点电连接，其漏极接入第一低电平，所述重置信号在时钟信号消失时由低电平转为高电平。
  3. 如权利要求1所述的GOA驱动电路，其中，所述下拉维持单元包括第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管，所述第六薄膜晶体管的源极与第一节点电连接，其漏极接入第一低电平，其栅极与第N级第二节点电连接，所述七薄膜晶体管的源极与第N级水平扫描线电连接，其漏极接入第一低电平，其栅极与第N级第二节点电连接，所述第八薄膜晶体管的栅极与源极与高电平电连接，其漏极分别与第九薄膜晶体管的栅极和第十一薄膜晶体管的源极电连接，第九薄膜晶体管的源极与高电平电连接，其漏极与第N级第二节点电连接，第十薄膜晶体管的源极与第N级第二节点电连接，其漏极接入第一低电平，其栅极与第一节点电连接，第十一薄膜晶体管的漏极接入第一低电平，其栅极与第一节点电连接。
  4. 如权利要求3所述的GOA驱动电路，其中，所述强制下拉单元包括 第十三薄膜晶体管，所述第十三薄膜晶体管的栅极接入重置信号，其源极与高电平电连接，其漏极与第N级第二节点电连接，所述重置信号在时钟信号消失时由低电平转为高电平。
  5. 如权利要求3所述的GOA驱动电路，其中，所述时钟信号包括第一时钟信号和第二时钟信号，所述第一时钟信号和第二时钟信号频率相同，在一个周期除消隐时间以外的时间相位相反；所述强制下拉单元包括第十八薄膜晶体管、第十九薄膜晶体管、第二十薄膜晶体管、第二十一薄膜晶体管，所述第十八薄膜晶体管的源极和栅极与高电平电连接，其漏极分别与第十九薄膜晶体管的栅极、第二十薄膜晶体管的源极、第二十一薄膜晶体管的源极电连接，所述第十九薄膜晶体管的源极与高电平电连接，其漏极与第N级第二节点电连接，所述第二十薄膜晶体管的栅极与第一时钟信号电连接，其漏极与第一低电平电连接，所述第二十一薄膜晶体管的栅极与第二时钟信号电连接，其漏极与第一低电平电连接。
  6. 如权利要求1所述的GOA驱动电路，其中，所述时钟信号包括第一时钟信号和第二时钟信号，所述第一时钟信号和第二时钟信号频率相同，在一个周期除消隐时间以外的时间相位相反；所述强制下拉单元包括第十四薄膜晶体管、第十五薄膜晶体管、第十六薄膜晶体管、第十七薄膜晶体管，所述第十四薄膜晶体管的源极和栅极与高电平电连接，其漏极分别与第十五薄膜晶体管的栅极、第十六薄膜晶体管的源极、第十七薄膜晶体管的源极电连接，所述第十五薄膜晶体管的源极与第一节点电连接，其漏极与第一低电平电连接，所述第十六薄膜晶体管的栅极与第一时钟信号电连接，其漏极与第一低电平电连接，所述第十七薄膜晶体管的栅极与第二时钟信号电连接，其漏极与第一低电平电连接。
  7. 如权利要求1所述的GOA驱动电路，其中，所述GOA驱动电路的一个周期包括消隐时间，所述强制下拉单元在GOA驱动电路的一个周期除消隐时间以外的时间用于时钟信号消失时强迫所述第一节点为低电平。
  8. 如权利要求2所述的GOA驱动电路，其中，所述GOA驱动电路的一个周期包括消隐时间，所述强制下拉单元在GOA驱动电路的一个周期除消隐时间以外的时间用于时钟信号消失时强迫所述第一节点为低电平。
  9. 如权利要求3所述的GOA驱动电路，其中，所述GOA驱动电路的一个周期包括消隐时间，所述强制下拉单元在GOA驱动电路的一个周期除消隐时间以外的时间用于时钟信号消失时强迫所述第一节点为低电平。
  10. 如权利要求4所述的GOA驱动电路，其中，所述GOA驱动电路的一个周期包括消隐时间，所述强制下拉单元在GOA驱动电路的一个周期除消隐时间以外的时间用于时钟信号消失时强迫所述第一节点为低电平。
  11. 如权利要求5所述的GOA驱动电路，其中，所述GOA驱动电路的一个周期包括消隐时间，所述强制下拉单元在GOA驱动电路的一个周期除消隐时间以外的时间用于时钟信号消失时强迫所述第一节点为低电平。
  12. 如权利要求6所述的GOA驱动电路，其中，所述GOA驱动电路的一个周期包括消隐时间，所述强制下拉单元在GOA驱动电路的一个周期除消隐时间以外的时间用于时钟信号消失时强迫所述第一节点为低电平。
  13. 如权利要求1所述的GOA驱动电路，其中，所述上拉单元包括第三薄膜晶体管，所述第三薄膜晶体管的源极接入第一时钟信号，其栅极与第一节点电连接，其漏极与第N级水平扫描线电连接。
  14. 如权利要求1所述的GOA驱动电路，其中，所述下拉单元包括第四薄膜晶体管和第五薄膜晶体管，所述第四薄膜晶体管的源极与第一节点电连接，其漏极接第一低电平，所述第五薄膜晶体管的源极与第N级水平扫描线电连接，其漏极接第一低电平，所述第四薄膜晶体管的栅极和所述第五薄膜晶 体管的栅极用于接第N+1级下传信号。
  15. 一种液晶显示装置，其中，包括一种GOA驱动电路，该GOA驱动电路包括多个级联的GOA单元，按照第N级GOA单元输出栅极驱动信号给显示区域第N级水平扫描线，该第N级GOA单元包括上拉单元、上拉控制单元、下拉单元、下拉维持单元、下传单元以及自举电容单元；所述上拉单元、所述下拉单元以、所述下拉维持单元及所述自举电容单元均分别与第一节点以及第N级水平扫描线电连接，所述上拉控制单元以及所述下传单元与第一节点电连接，其中N为正整数；该GOA单元还包括：
    强制下拉单元，其用于时钟信号消失时强迫所述第一节点为低电平。
  16. 如权利要求15所述的液晶显示装置，其中，所述强制下拉单元包括第十二薄膜晶体管，所述第十二薄膜晶体管的栅极接入重置信号，其源极与第一节点电连接，其漏极接入第一低电平，所述重置信号在时钟信号消失时由低电平转为高电平。
  17. 如权利要求15所述的液晶显示装置，其中，所述下拉维持单元包括第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管，所述第六薄膜晶体管的源极与第一节点电连接，其漏极接入第一低电平，其栅极与第N级第二节点电连接，所述七薄膜晶体管的源极与第N级水平扫描线电连接，其漏极接入第一低电平，其栅极与第N级第二节点电连接，所述第八薄膜晶体管的栅极与源极与高电平电连接，其漏极分别与第九薄膜晶体管的栅极和第十一薄膜晶体管的源极电连接，第九薄膜晶体管的源极与高电平电连接，其漏极与第N级第二节点电连接，第十薄膜晶体管的源极与第N级第二节点电连接，其漏极接入第一低电平，其栅极与第一节点电连接，第十一薄膜晶体管的漏极接入第一低电平，其栅极与第一节点电连接。
  18. 如权利要求17所述的液晶显示装置，其中，所述强制下拉单元包括 第十三薄膜晶体管，所述第十三薄膜晶体管的栅极接入重置信号，其源极与高电平电连接，其漏极与第N级第二节点电连接，所述重置信号在时钟信号消失时由低电平转为高电平。
  19. 如权利要求17所述的液晶显示装置，其中，所述时钟信号包括第一时钟信号和第二时钟信号，所述第一时钟信号和第二时钟信号频率相同，在一个周期除消隐时间以外的时间相位相反；所述强制下拉单元包括第十八薄膜晶体管、第十九薄膜晶体管、第二十薄膜晶体管、第二十一薄膜晶体管，所述第十八薄膜晶体管的源极和栅极与高电平电连接，其漏极分别与第十九薄膜晶体管的栅极、第二十薄膜晶体管的源极、第二十一薄膜晶体管的源极电连接，所述第十九薄膜晶体管的源极与高电平电连接，其漏极与第N级第二节点电连接，所述第二十薄膜晶体管的栅极与第一时钟信号电连接，其漏极与第一低电平电连接，所述第二十一薄膜晶体管的栅极与第二时钟信号电连接，其漏极与第一低电平电连接。
  20. 如权利要求15所述的液晶显示装置，其中，所述时钟信号包括第一时钟信号和第二时钟信号，所述第一时钟信号和第二时钟信号频率相同，在一个周期除消隐时间以外的时间相位相反；所述强制下拉单元包括第十四薄膜晶体管、第十五薄膜晶体管、第十六薄膜晶体管、第十七薄膜晶体管，所述第十四薄膜晶体管的源极和栅极与高电平电连接，其漏极分别与第十五薄膜晶体管的栅极、第十六薄膜晶体管的源极、第十七薄膜晶体管的源极电连接，所述第十五薄膜晶体管的源极与第一节点电连接，其漏极与第一低电平电连接，所述第十六薄膜晶体管的栅极与第一时钟信号电连接，其漏极与第一低电平电连接，所述第十七薄膜晶体管的栅极与第二时钟信号电连接，其漏极与第一低电平电连接。
PCT/CN2017/107543 2017-08-16 2017-10-24 一种goa电路及液晶显示装置 Ceased WO2019033549A1 (zh)

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