WO2019026295A1 - 電源装置、および、電源装置の制御方法 - Google Patents
電源装置、および、電源装置の制御方法 Download PDFInfo
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- WO2019026295A1 WO2019026295A1 PCT/JP2017/028487 JP2017028487W WO2019026295A1 WO 2019026295 A1 WO2019026295 A1 WO 2019026295A1 JP 2017028487 W JP2017028487 W JP 2017028487W WO 2019026295 A1 WO2019026295 A1 WO 2019026295A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
- H03K17/0826—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in bipolar transistor switches
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J3/00—Circuit arrangements for ac mains or ac distribution networks
- H02J3/10—Constant-current supply systems
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
- G01R19/16528—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values using digital techniques or performing arithmetic operations
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/26—Modifications for temporary blocking after receipt of control pulses
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
- H03K19/01806—Interface arrangements
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/12—Regulating voltage or current wherein the variable actually regulated by the final control device is ac
- G05F1/40—Regulating voltage or current wherein the variable actually regulated by the final control device is ac using discharge tubes or semiconductor devices as final control devices
- G05F1/44—Regulating voltage or current wherein the variable actually regulated by the final control device is ac using discharge tubes or semiconductor devices as final control devices semiconductor devices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0045—Full bridges, determining the direction of the current through the load
Definitions
- the present invention relates to a power supply device and a control method of the power supply device.
- the overcurrent detection circuit XA detects an overcurrent of the output circuit OCA (for example, a bridge circuit) of the power supply apparatus 100A (FIG. 9) whose output waveform is configured by the control unit CPU based on the overcurrent threshold THO.
- the timing (period) to turn off the output circuit OCA is determined with the CR time constant by the time constant circuit TA which is hardware. (FIG. 10) (see, for example, Patent Document 1).
- the conventional power supply device 100A is greatly affected by the temperature and accuracy.
- the processing load of the control unit can be reduced even when the switching cycle is high by counting the period in which the output circuit is turned off when the output circuit is over current by the CPU and performing other processing with hardware. It aims to provide a possible power supply.
- a power supply apparatus comprising: An output circuit that is supplied with power from the power supply and outputs a current; A drive circuit for controlling an output operation of the current of the output circuit; An overcurrent detection circuit which outputs a detection signal to a first node when an overcurrent of the output circuit is detected; An off fixed signal for forcibly turning off the output operation of the output circuit regardless of the control signal based on the detection signal input to the first node is output from the output node to the drive circuit Fixed circuit, By outputting a control signal for controlling the output operation of the output circuit to the drive circuit, the drive circuit controls the output operation of the output circuit, and the detection signal is input.
- the control unit and The drive circuit forcibly turns off the output operation of the output circuit regardless of the control signal in response to the off-fixing signal.
- the control unit outputs a release signal for releasing the forcible turning off of the output operation of the output circuit to the off-fixing circuit after a lapse of an off period since the detection signal is input.
- the off-fixing circuit stops the output of the off-fixing signal in response to the release signal, and returns the normal operation in which the drive circuit controls the output operation of the output circuit based on the control signal. It features.
- the off fixed circuit is The detection signal input to the first node is output to the drive circuit as the off fixed signal, Thereafter, in response to the input of the release signal, the potential of the first node is controlled to stop the output of the off-fixing signal.
- the control unit Feedback the release signal that has been output, and detect whether or not there is an abnormality in the release signal that is fed back; When an abnormality in the release signal is detected, the drive circuit is controlled by the control signal to stop the output operation of the output circuit.
- the overcurrent detection circuit is When the overcurrent due to the output operation is not detected in the output circuit, the detection signal is not output to the first node.
- the control unit After the release signal is output, when the detection signal is not input, the drive circuit outputs the control signal for controlling the output operation of the output circuit, whereby the drive circuit outputs the output. And controlling the output operation of the circuit.
- the drive circuit is A logic circuit that outputs a logic signal obtained by computing the control signal and a signal based on the potential of the first node; And a driver for controlling the output operation of the current of the output circuit based on the logic signal.
- the output circuit is a bridge circuit that controls and outputs power supplied from the power supply.
- the bridge circuit is A first output transistor having one end connected to the power supply and the other end connected to the first output terminal; A second output transistor having one end connected to the power supply and the other end connected to the second output terminal; A third output transistor having one end connected to the first output terminal and the other end connected to a fixed potential; A fourth output transistor, one end of which is connected to the second output terminal and the other end of which is connected to a fixed potential; A first detection resistor having one end connected to the other end of the third output transistor and the other end connected to the fixed potential; And a second detection resistor whose one end is connected to the other end of the fourth output transistor and whose other end is connected to the fixed potential.
- the over-current detection circuit detects an over-current of the current output from the bridge circuit by detecting the current flowing through the first and second detection resistors, and outputs the detection signal according to the detection result. .
- the drive circuit controls the operation of outputting power of the bridge circuit by controlling the operation of the first to fourth output transistors based on the control signal.
- the control unit is characterized by setting the off period for forcibly turning off the output operation of the output circuit by software.
- the output node is connected to the first node
- the off fixed circuit is A first PNP bipolar transistor having an emitter connected to the power supply, A first control resistor having one end connected to the collector of the first PNP bipolar transistor; A first NPN bipolar transistor having a collector connected to the other end of the first control resistor, an emitter connected to the fixed potential, and a base to which the release signal is input from the control unit; , A second control resistor having one end connected to the power supply and the other end connected to the base of the first PNP bipolar transistor; A third control resistor having one end connected to the other end of the second control resistor and the other end connected to the first node; And a second NPN bipolar transistor having a collector connected to the other end of the third control resistor, an emitter connected to the fixed potential, and a base connected to the other end of the first control resistor.
- the off fixed circuit is According to the detection signal output from the overcurrent detection circuit, a signal based on the potential of the first node is output to the drive circuit as the off-fixing signal. On the other hand, it is characterized in that the output of the off-fixing signal to the drive circuit is stopped according to the release signal output from the control unit.
- the overcurrent detection circuit is When the current output from the output circuit becomes equal to or greater than a preset overcurrent threshold, the detection signal is output, When the current output from the output circuit is less than the overcurrent threshold, the detection signal is not output.
- the drive circuit is When an overcurrent is detected by the overcurrent detection circuit, the first to fourth outputs according to the off-fixing signal output by the off-fixing circuit based on the detection signal of the first node. Stop the operation of the transistor, Thereafter, the stop of the operation of the first to fourth output transistors is released in response to the output stop of the off-fixing signal from the off-fixing circuit based on the release signal. Thereafter, the operation of the first to fourth output transistors is controlled based on the control signal.
- the output node is connected to the first node
- the off fixed circuit is A first control resistor having one end connected to the power supply and the other end connected to the first node; A second control resistor, one end of which is connected to the power supply, A capacitor whose one end is connected to the first node and whose other end is connected to a fixed potential, A PNP bipolar transistor having an emitter connected to the first node, the other end connected to the fixed potential, and a base connected to the other end of the second control resistor; And a NPN bipolar transistor having a collector connected to the other end of the second control resistor, an emitter connected to the fixed potential, and a base to which the release signal is input from the control unit.
- the output node is connected to the first node,
- the off fixed circuit is According to the detection signal output from the overcurrent detection circuit, a signal based on the potential of the first node is output to the drive circuit as the off-fixing signal.
- the output of the off-fixing signal to the drive circuit is stopped according to the release signal output from the control unit.
- the off fixed circuit is A first control resistor having one end connected to the power supply and the other end connected to the output node; A second control resistor, one end of which is connected to the power supply, A third control resistor having one end connected to the other end of the second control resistor and the other end connected to the first node; A first capacitor having one end connected to the other end of the first control resistor and the other end connected to a fixed potential; A second capacitor having one end connected to one end of the second control resistor and the other end connected to the fixed potential; A third capacitor whose one end is connected to the other end of the second control resistor and whose other end is connected to the fixed potential; A fourth control resistor having one end connected to the other end of the second control resistor; An NPN bipolar transistor in which a collector is connected to the other end of the second capacitor, an emitter is connected to the fixed potential, and the release signal is input to the base from the control unit; When one end is connected to the other end of the first control resistor, the other end is connected to
- a control method of a power supply device is An output circuit supplied with power from a power supply and outputting a current, a drive circuit controlling output operation of the current of the output circuit, and an overcurrent outputting a detection signal to the first node when an overcurrent of the output circuit is detected
- a detection circuit and an off-fixing signal for forcibly turning off the output operation of the output circuit regardless of the control signal based on the detection signal input to the first node from the output node to the drive circuit
- a control signal for controlling the output operation of the output circuit to control the output operation of the output circuit by the drive circuit.
- a control method of a power supply device comprising: a control unit adapted to receive a signal.
- the drive circuit forcibly turns off the output operation of the output circuit regardless of the control signal according to the off-fixing signal
- the control unit outputs, to the off fixing circuit, a release signal for releasing the forcible turning off of the output operation of the output circuit after a lapse of an off period since the detection signal is input.
- the output of the off-fixing signal is stopped by the off-fixing circuit in response to the release signal, and the drive circuit returns to the normal operation of controlling the output operation of the output circuit based on the control signal.
- a power supply device detects an over current of an output circuit which is supplied with power from a power supply and which outputs current, a drive circuit which controls the current output operation of the output circuit, and an output circuit. Based on the overcurrent detection circuit which outputs a signal to the first node, and based on the detection signal inputted to the first node, an off-fixing signal for forcibly turning off the output operation of the output circuit regardless of the control signal is driven.
- the drive circuit controls the output operation of the output circuit and the detection signal is input.
- a control unit CPU a control unit CPU.
- the drive circuit forcibly turns off the output operation of the output circuit regardless of the control signal in response to the off-fixing signal, and the control unit outputs the detection signal after a lapse of a preset off period.
- the release circuit outputs the release signal for releasing the forced OFF of the output operation of the output circuit to the OFF fixed circuit, and the OFF fixed circuit stops the output of the OFF fixed signal according to the release signal, and the drive circuit controls It returns to the normal operation that controls the output operation of the output circuit based on the signal.
- the output circuit is forcibly turned off based on the detection result of the overcurrent detection circuit, and the output circuit is normally output based on the release signal output after the off period set by the control unit CPU.
- control unit CPU counts a period during which the output circuit is turned off in the event of an overcurrent in the output circuit and performs other processing with hardware, thereby reducing the processing load on the control unit CPU even when the switching cycle is high. it can.
- control unit CPU sets a period during which the output circuit is turned off at the time of an overcurrent, the setting can be easily changed by communication without being influenced by temperature and accuracy.
- FIG. 1 is a diagram illustrating an example of the configuration of the power supply device 100 according to the first embodiment.
- FIG. 2 is a waveform diagram showing an example of the relationship between the current Iac output from the output circuit OC (bridge circuit BC) shown in FIG. 1 and the drive signals SD1 to SD4 output from the drive circuit DC.
- FIG. 3 is a diagram showing an example of a circuit configuration of the off fixing circuit Y shown in FIG. 4 shows the current Iac output from the output circuit OC (bridge circuit BC) shown in FIG. 1, the drive signals SD1 to SD4 output from the drive circuit DC, and the signals of the off-fixing circuit Y shown in FIG. It is a wave form diagram showing an example of a relation.
- FIG. 1 is a diagram illustrating an example of the configuration of the power supply device 100 according to the first embodiment.
- FIG. 2 is a waveform diagram showing an example of the relationship between the current Iac output from the output circuit OC (bridge circuit BC) shown in FIG. 1 and the drive signals SD1
- FIG. 5 is a diagram showing another example of the circuit configuration of the off-fixing circuit Y shown in FIG. 1 according to the first modification.
- 6 shows the current Iac output from the output circuit OC (bridge circuit BC) shown in FIG. 1, the drive signals SD1 to SD4 output from the drive circuit DC, and the signals of the off-fixing circuit Y shown in FIG. It is a wave form diagram which shows the other example of a relation.
- FIG. 7 is a diagram showing still another example of the circuit configuration of the off-fixing circuit Y shown in FIG. 1 according to the second modification. 8 shows the current Iac output from the output circuit OC (bridge circuit BC) shown in FIG.
- FIG. 9 is a diagram showing an example of a configuration of a conventional power supply device 100A.
- FIG. 10 is a waveform diagram showing an example of the relationship between the current Iac output from the output circuit OCA shown in FIG. 9 and the drive signal SD output from the drive circuit DCA.
- FIG. 1 is a diagram illustrating an example of the configuration of the power supply device 100 according to the first embodiment.
- FIG. 2 is a waveform diagram showing an example of the relationship between the current Iac output from the output circuit OC (bridge circuit BC) shown in FIG. 1 and the drive signals SD1 to SD4 output from the drive circuit DC.
- FIG. 3 is a diagram showing an example of the circuit configuration of the off-fixing circuit Y shown in FIG. 4 shows the current Iac output from the output circuit OC (bridge circuit BC) shown in FIG. 1, the drive signals SD1 to SD4 output from the drive circuit DC, and the respective signals of the off-fixing circuit Y shown in FIG. It is a wave form diagram showing an example of a relation of. In the examples of FIGS. 2 and 4, the waveforms of the drive signals SD1 to SD4 are expressed as one waveform for the sake of simplicity.
- the power supply device 100 constitutes, for example, an inverter or a converter.
- the power supply device 100 includes an output circuit OC, a drive circuit DC, an overcurrent detection circuit X, an off fixing circuit Y, and a control unit (microcomputer) CPU.
- the output circuit OC is supplied with power from the power supply Vcc, and outputs a predetermined current Iac to the first and second output terminals TO1 and TO2.
- the output circuit OC is, for example, a bridge circuit BC that controls and outputs the power supplied from the power supply Vcc, as shown in FIG.
- the bridge circuit BC includes a first output transistor Tr1, a second output transistor Tr2, a third output transistor Tr3, a fourth output transistor Tr4, and a first output transistor Tr1. And a second detection resistor R2.
- one end (collector) of the first output transistor Tr1 is connected to the power supply Vcc, the other end (emitter) is connected to the first output terminal TO1, and the drive signal SD1 is transmitted to the base. It is an NPN type bipolar transistor to be input.
- An NPN bipolar transistor having one end (collector) connected to the power supply Vcc, the other end (emitter) connected to the second output terminal TO2, and a drive signal SD2 input to the base of the second output transistor Tr2 It is.
- the third output transistor Tr3 has one end (collector) connected to the first output terminal TO1, the other end (emitter) connected to the fixed potential (ground), and an NPN to which the drive signal SD3 is input to the base.
- Type bipolar transistor Type bipolar transistor.
- the fourth output transistor Tr4 has one end (collector) connected to the second output terminal TO2, the other end (emitter) connected to the fixed potential (ground), and an NPN to which the drive signal SD3 is input to the base.
- Type bipolar transistor Type bipolar transistor.
- one end of the first detection resistor R1 is connected to the other end (emitter) of the third output transistor Tr3, and the other end is connected to a fixed potential (ground).
- one end of the second detection resistor R2 is connected to the other end (emitter) of the fourth output transistor Tr4, and the other end is connected to the fixed potential (ground).
- the drive circuit DC shown in FIG. 1 is adapted to control the output operation of the current of the output circuit OC.
- the drive circuit DC includes a first high side logic circuit AH1, a second high side logic circuit AH2, a first low side logic circuit AL1, and a second low side logic circuit. It comprises AL2, a high side driver DCH, and a low side driver DCL.
- the first high side logic circuit AH1 outputs a logic signal SH1 obtained by computing the first control signal SC1 and a signal based on the potential of the first node IN1.
- the second high side logic circuit AH2 outputs a logic signal SH2 obtained by calculating the second control signal SC2 and a signal based on the potential of the first node IN1.
- the first low side logic circuit AL1 outputs a logic signal SL1 obtained by computing the third control signal SC3 and a signal based on the potential of the first node IN1.
- the second low side logic circuit AL2 outputs a logic signal SL2 obtained by computing the fourth control signal SC4 and a signal based on the potential of the first node IN1.
- the high side driver DCH controls the output operation of the current of the output circuit OC according to the drive signals SD1 and SD2 based on the logic signals SH1 and SH2 (controls the first and second output transistors Tr1 and Tr2). ) Is supposed to.
- the low side driver DCL controls the output operation of the current of the output circuit OC by the drive signals SD3 and SD4 based on the logic signals SL1 and SL2 (controls the third and fourth output transistors Tr3 and Tr4). It is supposed to be.
- the drive circuit DC controls the operation of the first to fourth output transistors Tr1 to Tr4 based on the first to fourth control signals SC1 to SC4 in the normal operation to set the power of the bridge circuit BC. It is designed to control the output operation.
- the first and second output transistors Tr1 and Tr2 are complementarily turned on / off according to the drive signals SD1 to SD4 so that no through current flows.
- the third and fourth output transistors Tr3 and Tr4 are complementarily turned on / off.
- the output circuit OC outputs a predetermined current to the first and second output terminals TO1 and TO2 based on the power supplied from the power supply Vcc.
- the drive circuit DC responds to the OFF fixation signal OUT2 output from the OFF fixation circuit Y based on the detection signal SX of the first node IN1.
- the operation of the first to fourth output transistors Tr1 to Tr4 is stopped.
- the drive circuit DC cancels the stop of the operation of the first to fourth output transistors Tr1 to Tr4 in response to the stop of the output of the off-fixing signal OUT2 from the off-fixing circuit Y based on the release signal OUT1. ing.
- the drive circuit DC controls the operation of the first to fourth output transistors Tr1 to Tr4 based on the first to fourth control signals SC1 to SC4.
- the overcurrent detection circuit X shown in FIG. 1 outputs a detection signal SX (for example, a “Low” level signal) to the first node IN1 when the overcurrent of the output circuit OC is detected.
- a detection signal SX for example, a “Low” level signal
- the overcurrent detection circuit X does not detect the overcurrent due to the output operation in the output circuit OC
- the overcurrent detection circuit X does not output the "Low” level detection signal SX to the first node IN1 (ie, "High” level). Output a signal).
- the overcurrent detection circuit X is configured to output the detection signal SX when the current output from the output circuit OC becomes equal to or higher than the preset overcurrent threshold THO.
- the overcurrent detection circuit X is configured not to output the detection signal SX when the current output from the output circuit OC becomes less than the overcurrent threshold THO.
- the overcurrent detection circuit X detects the current value of the current flowing through the first detection resistor R1 and the second detection resistor R2, and based on the detection result, the output circuit OC Is designed to detect over current.
- the over-current detection circuit X detects an over-current of the current Iac output from the bridge circuit BC by detecting the current flowing through the first and second detection resistors R1 and R2.
- the detection signal SX (for example, a "Low" level signal) is output.
- the off-fixing circuit Y shown in FIG. 1 forcibly outputs the output operation of the output circuit OC regardless of the first to fourth control signals SC1 to SC4 based on the detection signal SX input to the first node IN1.
- the off fixed signal OUT2 for turning off is outputted from the output node NY to the drive circuit DC.
- the off-fixing circuit Y includes a first PNP bipolar transistor Tra, a first NPN bipolar transistor Trb, a first control resistor Ra, and a second control resistor Rb. , A third control resistor Rc, and a second NPN bipolar transistor Trc.
- the output node NY is connected to the first node IN1.
- the emitter of the first PNP bipolar transistor Tra is connected to the power supply Vcc.
- one end of the first control resistor Ra is connected to the collector of the first PNP bipolar transistor.
- the collector is connected to the other end of the first control resistor, the emitter is connected to a fixed potential (ground), and the release signal OUT1 is input to the base from the control unit CPU It is supposed to be.
- one end of the second control resistor Rb is connected to the power supply Vcc, and the other end is connected to the base of the first PNP bipolar transistor Tra.
- one end of the third control resistor Rc is connected to the other end of the second control resistor Rb, and the other end is connected to the first node IN1.
- the second NPN bipolar transistor Trc has a collector connected to the other end of the third control resistor Rc, an emitter connected to a fixed potential (ground), and a base connected to the other end of the first control resistor Ra. It is connected.
- the off-fixing circuit Y outputs the detection signal SX ("Low” level) input to the first node IN1 to the drive circuit DC as the off-fixing signal OUT2 (latches the potential of the first node IN1 to "Low” level) After that, in response to the input of the release signal OUT1 (“High” level), the potential of the first node IN1 is controlled to stop the output of the off-fixing signal OUT2 (latched at “High” level).
- the off-fixing circuit Y outputs a signal based on the potential of the first node IN1 as the off-fixing signal OUT2 to the drive circuit DC in response to the detection signal SX output from the overcurrent detection circuit X. It has become.
- the off-fixing circuit Y is configured to stop the output of the off-fixing signal OUT2 to the drive circuit DC in response to the release signal OUT1 output from the control unit CPU.
- control unit CPU outputs the first to fourth control signals (PWM signals) SC1 to SC4 for controlling the output operation of the output circuit OC to the drive circuit DC.
- the drive circuit DC controls the output operation of the output circuit OC, and the detection signal SX is input (via the second node IN2).
- the drive circuit DC is configured to forcibly turn off the output operation of the output circuit OC regardless of the first to fourth control signals SC1 to SC4 in response to the off-fixing signal OUT2.
- control unit CPU receives release signal OUT1 (for example, “High” level) for releasing the forcible turning off of the output operation of output circuit OC after the lapse of the off period TGF after the detection signal SX is input. It is designed to output to the off-fixing circuit Y.
- release signal OUT1 for example, “High” level
- the off-fixing circuit Y described above stops the output of the off-fixing signal OUT2 in response to the release signal OUT1 (for example, “High” level), and the drive circuit DC generates the first to fourth control signals SC1.
- the normal operation for controlling the output operation of the output circuit OC is restored based on .about.SC4.
- control unit CPU controls the output operation of output circuit OC when detection signal SX (“Low” level) is not input to second node N2.
- the output operation of the output circuit OC is controlled by the drive circuit DC by outputting the first to fourth control signals SC1 to SC4 to the drive circuit DC.
- control unit CPU feedbacks the output release signal OUT1, detects whether or not there is an abnormality (such as a predetermined signal is not output) in the feedback release signal, and detects an abnormality in the release signal.
- the drive circuit DC is controlled by the first to fourth control signals SC1 to SC4 to stop the output operation of the output circuit OC.
- the output operation of the output circuit OC can be stopped to suppress a malfunction or the like of the power supply device 100.
- the control unit CPU sets, for example, by software, the off period TGF during which the output operation of the output circuit OC is forcibly turned off.
- control unit CPU drives first to fourth control signals (PWM signals) SC1 to SC4 for controlling the output operation of output circuit OC during normal operation, as shown in FIG.
- PWM signals pulse width modulation signals
- the overcurrent detection circuit X does not detect an overcurrent due to the output operation in the output circuit OC (if the current output from the output circuit OC is less than the overcurrent threshold THO), the "Low” level Is not output to the first node IN1 (ie, a signal of "High” level is output).
- the off-fixing circuit Y stops the output of the off-fixing signal OUT2 to the drive circuit DC in response to the signal (signal of “Low” level) output from the output node Na during normal operation from the control unit CPU (“ It outputs a "High” level signal).
- the drive circuit DC controls the operation of the first to fourth output transistors Tr1 to Tr4 based on the first to fourth control signals SC1 to SC4 to obtain the bridge circuit BC. Control the power output operation.
- the overcurrent detection circuit X detects an overcurrent due to the output operation in the output circuit OC (the current Iac output from the output circuit OC reaches the overcurrent threshold THO), the detection signal SX (corresponding to the detection result) Output “Low” level signal).
- the off-fixing circuit Y outputs the detection signal SX input to the first node IN1 as the off-fixing signal OUT2 to the drive circuit DC (latches the potential of the first node IN1 to the “Low” level).
- the drive circuit DC stops the operation of the first to fourth output transistors Tr1 to Tr4 in response to the off-fixing signal OUT2 output from the off-fixing circuit Y, to perform the output operation of the output circuit OC. It is forcibly turned off regardless of the fourth control signals SC1 to SC4.
- control unit CPU receives release signal OUT1 (for example, “High” level) for releasing the forcible turning off of the output operation of output circuit OC after lapse of off period TGF after the detection signal SX is input. Output to the off fixing circuit Y.
- release signal OUT1 for example, “High” level
- the off-fixing circuit Y controls the potential of the first node IN1 to stop the output of the off-fixing signal OUT2 in response to the input of the release signal OUT1 (a signal of “high” level) (“high” level Latch).
- the drive circuit DC controls the output operation of the output circuit OC based on the first to fourth control signals SC1 to SC4. Return to normal operation.
- the output operation of the output circuit OC is performed when the detection signal SX (“Low” level) is not input to the second node N2.
- the driving circuit DC controls the output operation of the output circuit OC.
- the power supply apparatus 100 can properly return to the normal operation when the overcurrent is not detected.
- the power supply device includes the output circuit OC which is supplied with power from the power supply and outputs the current, the drive circuit DC which controls the output operation of the current of the output circuit, and When the overcurrent is detected, the output operation of the output circuit is first to fourth based on the overcurrent detection circuit X which outputs the detection signal SX to the first node IN1, and the detection signal SX input to the first node.
- An off-fixing circuit Y which outputs an off-fixing signal OUT2 for forcibly turning off regardless of the control signals SC1 to SC4 to the drive circuit, and first to fourth control signals SC1 to control the output operation of the output circuit.
- the control circuit CPU is configured to control the output operation of the output circuit by the drive circuit and to output the detection signal SX by outputting the signal SC1 to SC4 to the drive circuit.
- the drive circuit forcibly turns off the output operation of the output circuit regardless of the first to fourth control signals SC1 to SC4 in response to the off-fixing signal, and the control unit receives the detection signal SX.
- a release signal for releasing the forced OFF of the output operation of the output circuit is output to the OFF fixing circuit, and the OFF fixing circuit is turned off in response to the release signal.
- the drive circuit returns to the normal operation of controlling the output operation of the output circuit based on the first to fourth control signals SC1 to SC4.
- the output circuit is forcibly turned off based on the detection result of the overcurrent detection circuit, and the output circuit is output based on the release signal output after the lapse of the off period TGF set by the control unit CPU. Return to normal operation.
- control unit CPU counts a period during which the output circuit is turned off in the event of an overcurrent in the output circuit and performs other processing with hardware, thereby reducing the processing load on the control unit CPU even when the switching cycle is high. it can.
- control unit CPU sets a period during which the output circuit is turned off at the time of an overcurrent, the setting can be easily changed by communication without being influenced by temperature and accuracy.
- Modification 1 In the first embodiment described above, the output operation of the output circuit OC is forcibly turned off irrespective of the first to fourth control signals SC1 to SC4 based on the detection signal SX input to the first node IN1.
- An example of the circuit configuration of the off-fixing circuit Y that outputs the off-fixing signal OUT2 to the drive circuit DC from the output node NY has been described.
- FIG. 5 is a diagram showing another example of the circuit configuration of the off-fixing circuit Y shown in FIG. 1 according to the first modification. 6 shows the current Iac output from the output circuit OC (bridge circuit BC) shown in FIG. 1, the drive signals SD1 to SD4 output from the drive circuit DC, and each signal of the off-fixing circuit Y shown in FIG. It is a wave form diagram showing another example of a relation of. In the example of FIG. 6, the waveforms of the drive signals SD1 to SD4 are expressed as one waveform for the sake of simplicity. Further, in FIG. 5, the same reference numerals as the reference numerals in FIG. 1 indicate the same configurations as in the first embodiment.
- the off-fixing circuit Y includes a first control resistor Re, a second control resistor Rf, a capacitor C, a PNP bipolar transistor Trf, and an NPN bipolar transistor Tre. Prepare.
- one end of the first control resistor Re is connected to the power supply Vcc, and the other end is connected to the first node IN1 (output node NY).
- one end of the second control resistor Rf is connected to the power supply Vcc.
- One end of the capacitor C is connected to the first node IN1, and the other end is connected to the fixed potential (ground).
- the emitter of the PNP bipolar transistor Trf is connected to the first node IN1, the other end is connected to the fixed potential (ground), and the base is connected to the other end of the second control resistor Rf.
- the NPN bipolar transistor Tre has a collector connected to the other end of the second control resistor Rf, an emitter connected to a fixed potential (ground), and a release signal from the output node Na of the control unit CPU connected to the base. It is input via the node IN3.
- the base of the NPN bipolar transistor Tre is connected to the output node Na of the control unit CPU via the third node IN3.
- an output node NY for outputting the off-fixing signal is connected to the first node IN1.
- the off-fixing circuit Y outputs a signal based on the potential of the first node IN1 as the off-fixing signal OUT2 to the drive circuit DCA in response to the detection signal SX output from the overcurrent detection circuit X. ing.
- the off-fixing circuit Y is configured to stop the output of the off-fixing signal OUT2 to the drive circuit DC in response to the release signal OUT1 output from the control unit CPU.
- control unit CPU drives first to fourth control signals (PWM signals) SC1 to SC4 for controlling the output operation of output circuit OC during normal operation, as shown in FIG.
- PWM signals pulse width modulation signals
- the overcurrent detection circuit X does not detect an overcurrent due to the output operation in the output circuit OC (if the current output from the output circuit OC is less than the overcurrent threshold THO), the "Low” level Is not output to the first node IN1 (ie, a signal of "High” level is output).
- the off-fixing circuit Y stops the output of the off-fixing signal OUT2 to the drive circuit DC in response to the signal (signal of “Low” level) output from the output node Na during normal operation from the control unit CPU (“ It outputs a "High” level signal).
- the drive circuit DC controls the operation of the first to fourth output transistors Tr1 to Tr4 based on the first to fourth control signals SC1 to SC4 to obtain the bridge circuit BC. Control the power output operation.
- the overcurrent detection circuit X detects an overcurrent due to the output operation in the output circuit OC (the current Iac output from the output circuit OC reaches the overcurrent threshold THO), the detection signal SX (corresponding to the detection result) Output “Low” level signal).
- the off-fixing circuit Y outputs the detection signal SX input to the first node IN1 as the off-fixing signal OUT2 to the drive circuit DC (according to the “High” level signal output by the control unit CPU from the output node Na). Latch the potential of the first node IN1 to "Low” level).
- the drive circuit DC stops the operation of the first to fourth output transistors Tr1 to Tr4 in response to the off-fixing signal OUT2 output from the off-fixing circuit Y, to perform the output operation of the output circuit OC. It is forcibly turned off regardless of the fourth control signals SC1 to SC4.
- control unit CPU sets release signal OUT1 (in this case, “Low” level) to release the forcible turning off of the output operation of output circuit OC after elapse of off period TGF after detection signal SX is input. Signal) to the off fixing circuit Y.
- release signal OUT1 in this case, “Low” level
- the off-fixing circuit Y controls the potential of the first node IN1 so as to stop the output of the off-fixing signal OUT2 in response to the input of the release signal OUT1 (signal of “low” level) (“high” level Latch).
- the drive circuit DC controls the output operation of the output circuit OC based on the first to fourth control signals SC1 to SC4. Return to normal operation.
- the output operation of the output circuit OC is performed when the detection signal SX (“Low” level) is not input to the second node N2.
- the driving circuit DC controls the output operation of the output circuit OC.
- the power supply apparatus 100 can properly return to the normal operation when the overcurrent is not detected.
- the drive circuit DC forcibly turns off the output operation of the output circuit OC regardless of the first to fourth control signals SC1 to SC4 in response to the off-fixing signal OUT2.
- the control unit CPU sets the release signal OUT1 for releasing the forcible turning off of the output operation of the output circuit OC to the off fixing circuit Y after the lapse of the preset off period TGF after the detection signal SX is input.
- the off-fixing circuit Y stops the output of the off-fixing signal OUT2 in response to the release signal OUT1, and the driving circuit DC outputs the output circuit OC based on the first to fourth control signals SC1 to SC4.
- the output circuit is forcibly turned off based on the detection result of the overcurrent detection circuit, and the lapse of the off period TGF set by the control unit CPU.
- the output circuit is returned to the normal operation based on the release signal to be output later.
- control unit CPU counts a period during which the output circuit is turned off when an overcurrent occurs in the output circuit and performs other processing by hardware, thereby reducing the processing load on the control unit CPU even when the switching cycle is high.
- FIG. 7 is a diagram showing still another example of the circuit configuration of the off-fixing circuit Y shown in FIG. 1 according to the second modification.
- 8 shows the current Iac output from the output circuit OC (bridge circuit BC) shown in FIG. 1, the drive signals SD1 to SD4 output from the drive circuit DC, and the respective signals of the off-fixing circuit Y shown in FIG.
- It is a wave form diagram showing another example of a relation of.
- the waveforms of the drive signals SD1 to SD4 are expressed as one waveform for the sake of simplicity.
- the same reference numerals as the reference numerals in FIG. 1 indicate the same configurations as in the first embodiment.
- the configuration of the power supply apparatus 100 other than the off fixing circuit Y according to the second modification is the same as that of the first embodiment.
- the off-fixing circuit Y includes a first control resistor Rg, a second control resistor Rh, a third control resistor Ri, a first capacitor Cg, and a second capacitor. And Ch, a third capacitor Ci, a fourth control resistor Rj, an NPN bipolar transistor Trg, and a reset circuit Z.
- One end of the first control resistor Rg is connected to the power supply Vcc, and the other end is connected to the output node NY.
- One end of the second control resistor Rh is connected to the power supply Vcc.
- One end of the third control resistor Ri is connected to the other end of the second control resistor Rh, and the other end is connected to the first node IN1.
- One end of the first capacitor Cg is connected to the other end of the first control resistor Rg, and the other end is connected to a fixed potential (ground).
- One end of the second capacitor Ch is connected to one end of the second control resistor Rh, and the other end is connected to a fixed potential (ground).
- One end of the third capacitor Ci is connected to the other end of the second control resistor Rh, and the other end is connected to a fixed potential (ground).
- One end of the fourth control resistor Rj is connected to the other end of the second control resistor Rh.
- the NPN bipolar transistor Trg has a collector connected to the other end of the fourth control resistor Rj, an emitter connected to a fixed potential (ground), and a release signal OUT1 input from the control unit CPU to the base. There is. For example, as shown in FIG. 7, the base of the NPN bipolar transistor Trg is connected to the output node Na of the control unit CPU via the third node IN3.
- One end of the reset circuit Z is connected to the other end of the first control resistor Rg, and the other end is connected to a fixed potential (ground).
- the potential of the other end of the second control resistor Rh is less than a preset reset threshold (an npn bipolar transistor Trg corresponding to a “high” level signal output by the control unit CPU). Is turned on, the first capacitor Cg is electrically connected between one end and the other end to discharge the charge of the first capacitor Cg.
- the off-fixing circuit Y outputs the detection signal SX input to the first node IN1 as the off-fixing signal OUT2 to the drive circuit DC (latches the potential of the first node IN1 to the “Low” level).
- the potential at the other end of the second control resistor Rh becomes equal to or higher than the reset threshold (the NPN bipolar transistor Trg is turned off in response to the "Low" level signal output by the control unit CPU).
- the NPN bipolar transistor Trg is turned off in response to the "Low" level signal output by the control unit CPU.
- the first capacitor Cg is disconnected between one end and the other end.
- the off-fixing circuit Y controls the potential of the first node IN1 to stop the output of the off-fixing signal OUT2 in response to the input of the release signal OUT1 (a signal of “high” level) (“high” Latch to the level).
- the off-fixing circuit Y outputs a signal based on the potential of the first node IN1 as the off-fixing signal OUT2 to the drive circuit DC in response to the detection signal X output from the overcurrent detection circuit X. It has become.
- the off-fixing circuit Y is configured to stop the output of the off-fixing signal OUT2 to the drive circuit DC in response to the release signal OUT1 output from the control unit CPU.
- control unit CPU drives first to fourth control signals (PWM signals) SC1 to SC4 for controlling the output operation of output circuit OC during normal operation, as shown in FIG.
- PWM signals pulse width modulation signals
- the overcurrent detection circuit X does not detect an overcurrent due to the output operation in the output circuit OC (if the current output from the output circuit OC is less than the overcurrent threshold THO), the "Low” level Is not output to the first node IN1 (ie, a signal of "High” level is output).
- the off-fixing circuit Y stops the output of the off-fixing signal OUT2 to the drive circuit DC in response to the signal (signal of “Low” level) output from the output node Na during normal operation from the control unit CPU (“ It outputs a "High” level signal).
- the drive circuit DC controls the operation of the first to fourth output transistors Tr1 to Tr4 based on the first to fourth control signals SC1 to SC4 to obtain the bridge circuit BC. Control the power output operation.
- the potential at the other end of the second control resistor Rh becomes equal to or higher than the reset threshold (the NPN bipolar transistor Trg is turned off in response to the “Low” level signal output by the control unit CPU)
- the NPN bipolar transistor Trg is turned off in response to the “Low” level signal output by the control unit CPU.
- the off-fixing circuit Y controls the potential of the first node IN1 to stop the output of the off-fixing signal OUT2 in response to the input of the release signal OUT1 (here, a “Low” level signal) (“ Latch to high level).
- the overcurrent detection circuit X detects an overcurrent due to the output operation in the output circuit OC (the current Iac output from the output circuit OC reaches the overcurrent threshold THO), the detection signal SX (corresponding to the detection result) Output “Low” level signal).
- the potential of the other end of the second control resistor Rh is less than a preset reset threshold (in response to the “High” level signal output by the control unit CPU in response to the detection signal SX).
- a preset reset threshold in response to the “High” level signal output by the control unit CPU in response to the detection signal SX.
- the off-fixing circuit Y outputs the detection signal SX input to the first node IN1 as the off-fixing signal OUT2 to the drive circuit DC (latches the potential of the first node IN1 to the “Low” level).
- the drive circuit DC stops the operation of the first to fourth output transistors Tr1 to Tr4 in response to the off-fixing signal OUT2 output from the off-fixing circuit Y, to perform the output operation of the output circuit OC. It is forcibly turned off regardless of the fourth control signals SC1 to SC4.
- control unit CPU sets release signal OUT1 (in this case, “Low” level) to release the forcible turning off of the output operation of output circuit OC after elapse of off period TGF after detection signal SX is input. Signal) to the off fixing circuit Y.
- release signal OUT1 in this case, “Low” level
- the off-fixing circuit Y controls the potential of the first node IN1 so as to stop the output of the off-fixing signal OUT2 in response to the input of the release signal OUT1 (signal of “low” level) (“high” level Latch).
- the drive circuit DC controls the output operation of the output circuit OC based on the first to fourth control signals SC1 to SC4. Return to normal operation.
- the output operation of the output circuit OC is performed when the detection signal SX (“Low” level) is not input to the second node N2.
- the driving circuit DC controls the output operation of the output circuit OC.
- the power supply apparatus 100 can properly return to the normal operation when the overcurrent is not detected.
- the drive circuit DC forcibly turns off the output operation of the output circuit OC regardless of the first to fourth control signals SC1 to SC4 in response to the off-fixing signal OUT2.
- the control unit CPU sets the release signal OUT1 for releasing the forcible turning off of the output operation of the output circuit OC to the off fixing circuit Y after the lapse of the preset off period TGF after the detection signal SX is input.
- the off-fixing circuit Y stops the output of the off-fixing signal OUT2 in response to the release signal OUT1, and the driving circuit DC outputs the output circuit OC based on the first to fourth control signals SC1 to SC4.
- the output circuit is forcibly turned off based on the detection result of the overcurrent detection circuit, and the off period set by the control unit CPU The output circuit is returned to the normal operation based on the release signal output after the lapse of TGF.
- control unit CPU counts a period during which the output circuit is turned off in the event of an overcurrent in the output circuit and performs other processing with hardware, thereby reducing the processing load on the control unit CPU even when the switching cycle is high. it can.
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Abstract
Description
電源から電力を供給され、電流を出力する出力回路と、
前記出力回路の電流の出力動作を制御する駆動回路と、
前記出力回路の過電流を検出すると検出信号を第1ノードに出力する過電流検出回路と、
前記第1ノードに入力された前記検出信号に基づいて、前記出力回路の前記出力動作を前記制御信号に拘わらず強制的にオフするためのオフ固定信号を出力ノードから前記駆動回路に出力するオフ固定回路と、
前記出力回路の前記出力動作を制御するための制御信号を前記駆動回路に出力することで、前記駆動回路により前記出力回路の前記出力動作を制御するとともに、前記検出信号が入力されるようになっている制御部と、を備え、
前記駆動回路は、前記オフ固定信号に応じて、前記出力回路の前記出力動作を前記制御信号に拘わらず強制的にオフにし、
前記制御部は、前記検出信号が入力されてからオフ期間の経過後に、前記出力回路の前記出力動作の強制的なオフを解除するための解除信号を前記オフ固定回路に出力し、
前記オフ固定回路は、前記解除信号に応じて前記オフ固定信号の出力を停止して、前記駆動回路が前記制御信号に基づいて前記出力回路の前記出力動作を制御する通常動作に復帰させることを特徴とする。
前記オフ固定回路は、
前記第1ノードに入力された前記検出信号を前記オフ固定信号として前記駆動回路に出力し、
その後、前記解除信号の入力に応じて、前記オフ固定信号の出力を停止するように前記第1ノードの電位を制御する
ことを特徴とする。
前記制御部は、
出力した前記解除信号をフィードバックし、フィードバックされた前記解除信号に異常があるか否かを検出し、
前記解除信号の異常を検出した場合には、前記制御信号により前記駆動回路を制御して、前記出力回路の前記出力動作を停止させる
ことを特徴とする。
前記過電流検出回路は、
前記出力回路に前記出力動作による過電流を検出しない場合には、前記検出信号を前記第1ノードに出力しない
ことを特徴とする。
前記制御部は、
前記解除信号を出力した後、前記検出信号が入力されていない場合には、前記出力回路の前記出力動作を制御するための制御信号を前記駆動回路に出力することで、前記駆動回路により前記出力回路の前記出力動作を制御する
ことを特徴とする。
前記駆動回路は、
前記制御信号と前記第1ノードの電位に基づいた信号とを演算した論理信号を出力する論理回路と、
前記論理信号に基づいて前記出力回路の電流の出力動作を制御するドライバと、を備える
ことを特徴とする。
前記出力回路は、前記電源から供給される電力を制御して出力するブリッジ回路であることを特徴とする。
前記ブリッジ回路は、
一端が前記電源に接続され、他端が第1の出力端子に接続された第1の出力トランジスタと、
一端が前記電源に接続され、他端が第2の出力端子に接続された第2の出力トランジスタと、
一端が前記第1の出力端子に接続され、他端が固定電位に接続された第3の出力トランジスタと、
一端が前記第2の出力端子に接続され、他端が固定電位に接続され、第4の出力トランジスタと、
一端が前記第3の出力トランジスタの他端に接続され、他端が前記固定電位に接続された第1の検出抵抗と、
一端が前記第4の出力トランジスタの他端に接続され、他端が前記固定電位に接続された第2の検出抵抗と、を備え、
前記過電流検出回路は、前記第1及び第2の検出抵抗に流れる電流を検出することで前記ブリッジ回路が出力する電流の過電流を検出し、この検出結果に応じた前記検出信号を出力し、
前記駆動回路は、通常動作時は、前記制御信号に基づいて前記第1ないし第4の出力トランジスタの動作を制御することで、前記ブリッジ回路の電力の出力動作を制御する
ことを特徴とする。
前記制御部は、前記出力回路の前記出力動作を強制的にオフする前記オフ期間をソフトウエアで設定する
ことを特徴とする。
前記出力ノードが前記第1ノードに接続され、
前記オフ固定回路は、
エミッタが前記電源に接続された第1のPNP型バイポーラトランジスタと、
一端が前記第1のPNP型バイポーラトランジスタのコレクタに接続された第1の制御抵抗と、
コレクタが前記第1の制御抵抗の他端に接続され、エミッタが前記固定電位に接続され、ベースに前記制御部から前記解除信号が入力されるようになっている第1のNPN型バイポーラトランジスタと、
一端が前記電源に接続され、他端が前記第1のPNP型バイポーラトランジスタのベースに接続された第2の制御抵抗と、
一端が前記第2の制御抵抗の他端に接続され、他端が前記第1ノードに接続された第3の制御抵抗と、
コレクタが前記第3の制御抵抗の他端に接続され、エミッタが前記固定電位に接続され、ベースが前記第1の制御抵抗の他端に接続された第2のNPN型バイポーラトランジスタと、を備え、
前記オフ固定回路は、
前記過電流検出回路から出力された前記検出信号に応じて、前記第1ノードの電位に基づいた信号を、前記オフ固定信号として、前記駆動回路に出力し、
一方、前記制御部から出力された前記解除信号に応じて、前記駆動回路への前記オフ固定信号の出力を停止する
ことを特徴とする。
前記過電流検出回路は、
前記出力回路が出力する電流が予め設定された過電流閾値以上になった場合には、前記検出信号を出力し、
前記出力回路が出力する電流が前記過電流閾値未満になった場合には、前記検出信号を出力しない
ことを特徴とする。
前記駆動回路は、
前記過電流検出回路により過電流が検出された場合には、前記第1ノードの前記検出信号に基づいて前記オフ固定回路が出力する前記オフ固定信号に応じて、前記第1ないし第4の出力トランジスタの動作を停止させ、
その後、前記解除信号に基づいた前記オフ固定回路からの前記オフ固定信号の出力停止に応じて前記第1ないし第4の出力トランジスタの動作の停止を解除し、
その後、前記制御信号に基づいて前記第1ないし第4の出力トランジスタの動作を制御することを特徴とする。
前記出力ノードが前記第1ノードに接続され、
前記オフ固定回路は、
一端が前記電源に接続され、他端が前記第1ノードに接続された第1の制御抵抗と、
一端が前記電源に接続された第2の制御抵抗と、
一端が前記第1ノードに接続され、他端が固定電位に接続されたキャパシタと、
エミッタが前記第1ノードに接続され、他端が前記固定電位に接続され、ベースが前記第2の制御抵抗の他端に接続されたPNP型バイポーラトランジスタと、
コレクタが前記第2の制御抵抗の他端に接続され、エミッタが前記固定電位に接続され、 ベースに前記制御部から前記解除信号が入力されるようになっているNPN型バイポーラトランジスタと、を備え、
前記出力ノードが前記第1ノードに接続され、
前記オフ固定回路は、
前記過電流検出回路から出力された前記検出信号に応じて、前記第1ノードの電位に基づいた信号を、前記オフ固定信号として、前記駆動回路に出力し、
一方、前記制御部から出力された前記解除信号に応じて、前記駆動回路への前記オフ固定信号の出力を停止する
ことを特徴とする。
前記オフ固定回路は、
一端が前記電源に接続され、他端が前記出力ノードに接続された第1の制御抵抗と、
一端が前記電源に接続された第2の制御抵抗と、
一端が前記第2の制御抵抗の他端に接続され、他端が前記第1ノードに接続された第3の制御抵抗と、
一端が前記第1の制御抵抗の他端に接続され、他端が固定電位に接続された第1のキャパシタと、
一端が前記第2の制御抵抗の一端に接続され、他端が前記固定電位に接続された第2のキャパシタと、
一端が前記第2の制御抵抗の他端に接続され、他端が前記固定電位に接続された第3のキャパシタと、
一端が前記第2の制御抵抗の他端に接続された第4の制御抵抗と、
コレクタが前記第2のキャパシタの他端に接続され、エミッタが前記固定電位に接続され、 ベースに前記制御部から前記解除信号が入力されるようになっているNPN型バイポーラトランジスタと、
一端が前記第1の制御抵抗の他端に接続され、他端が前記固定電位に接続され、前記第2の制御抵抗の他端の電位が予め設定されたリセット閾値未満である場合には、前記第1のキャパシタの一端と他端との間を導通して前記第1のキャパシタの電荷を放電させ、一方、前記第2の制御抵抗の他端の前記電位が前記リセット閾値以上である場合には、前記第1のキャパシタの一端と他端との間を遮断するリセット回路と、を備え、
前記オフ固定回路は、
前記過電流検出回路から出力された前記検出信号に応じて、前記第1ノードの電位に基づいた信号を、前記オフ固定信号として、前記駆動回路に出力し、
一方、前記制御部から出力された前記解除信号に応じて、前記駆動回路への前記オフ固定信号の出力を停止する
ことを特徴とする。
電源から電力を供給され、電流を出力する出力回路と、前記出力回路の電流の出力動作を制御する駆動回路と、前記出力回路の過電流を検出すると検出信号を第1ノードに出力する過電流検出回路と、前記第1ノードに入力された前記検出信号に基づいて、前記出力回路の前記出力動作を前記制御信号に拘わらず強制的にオフするためのオフ固定信号を出力ノードから前記駆動回路に出力するオフ固定回路と、前記出力回路の前記出力動作を制御するための制御信号を前記駆動回路に出力することで、前記駆動回路により前記出力回路の前記出力動作を制御するとともに、前記検出信号が入力されるようになっている制御部と、を備えた電源装置の制御方法であって、
前記駆動回路により、前記オフ固定信号に応じて、前記出力回路の前記出力動作を前記制御信号に拘わらず強制的にオフにし、
前記制御部により、前記検出信号が入力されてからオフ期間の経過後に、前記出力回路の前記出力動作の強制的なオフを解除するための解除信号を前記オフ固定回路に出力し、
前記オフ固定回路により、前記解除信号に応じて前記オフ固定信号の出力を停止して、前記駆動回路が前記制御信号に基づいて前記出力回路の前記出力動作を制御する通常動作に復帰させる
ことを特徴とする。
そして、例えば、図1に示すように、ブリッジ回路BCは、第1の出力トランジスタTr1と、第2の出力トランジスタTr2と、第3の出力トランジスタTr3と、第4の出力トランジスタTr4と、第1の検出抵抗R1と、第2の検出抵抗R2と、を備える。
このオフ固定回路Yは、例えば、図3に示すように、第1のPNP型バイポーラトランジスタTraと、第1のNPN型バイポーラトランジスタTrbと、第1の制御抵抗Raと、第2の制御抵抗Rbと、第3の制御抵抗Rcと、第2のNPN型バイポーラトランジスタTrcと、を備える。
既述の第1の実施形態では、第1ノードIN1に入力された検出信号SXに基づいて、出力回路OCの出力動作を第1ないし第4の制御信号SC1~SC4に拘わらず強制的にオフするためのオフ固定信号OUT2を出力ノードNYから駆動回路DCに出力するオフ固定回路Yの回路構成の一例について説明した。
ここで、図5は、変形例1に係る、図1に示すオフ固定回路Yの回路構成の他の例を示す図である。また、図6は、図1に示す出力回路OC(ブリッジ回路BC)が出力する電流Iacと、駆動回路DCが出力する駆動信号SD1~SD4と、図5に示すオフ固定回路Yの各信号と、の関係の他の例を示す波形図である。なお、図6の例においては、駆動信号SD1~SD4の波形を簡単のため、1つの波形として表現している。また、図5において、図1の符号と同じ符号は、第1の実施形態と同様の構成を示す。
本変形例2では、オフ固定回路Yの回路構成のさらに他の例について説明する。
ここで、図7は、変形例2に係る、図1に示すオフ固定回路Yの回路構成のさらに他の例を示す図である。また、図8は、図1に示す出力回路OC(ブリッジ回路BC)が出力する電流Iacと、駆動回路DCが出力する駆動信号SD1~SD4と、図7に示すオフ固定回路Yの各信号と、の関係の他の例を示す波形図である。なお、図8の例においては、駆動信号SD1~SD4の波形を簡単のため、1つの波形として表現している。また、図7において、図1の符号と同じ符号は、第1の実施形態と同様の構成を示す。なお、本変形例2に係る当該オフ固定回路Y以外の電源装置100の構成は、第1の実施形態と同様である。
OC 出力回路
DC 駆動回路
X 過電流検出回路
Y オフ固定回路
CPU 制御部(マイコン)
BC ブリッジ回路
Tr1 第1の出力トランジスタ
Tr2 第2の出力トランジスタ
Tr3 第3の出力トランジスタ
Tr4 第4の出力トランジスタ
R1 第1の検出抵抗
R2 第2の検出抵抗
AH1 第1のハイサイド論理回路
AH2 第2のハイサイド論理回路
AL1 第1のローサイド論理回路
AL2 第2のローサイド論理回路
DCH ハイサイドドライバ
DCL ローサイドドライバ
Claims (15)
- 電源から電力を供給され、電流を出力する出力回路と、
前記出力回路の電流の出力動作を制御する駆動回路と、
前記出力回路の過電流を検出すると検出信号を第1ノードに出力する過電流検出回路と、
前記第1ノードに入力された前記検出信号に基づいて、前記出力回路の前記出力動作を前記制御信号に拘わらず強制的にオフするためのオフ固定信号を出力ノードから前記駆動回路に出力するオフ固定回路と、
前記出力回路の前記出力動作を制御するための制御信号を前記駆動回路に出力することで、前記駆動回路により前記出力回路の前記出力動作を制御するとともに、前記検出信号が入力されるようになっている制御部と、を備え、
前記駆動回路は、前記オフ固定信号に応じて、前記出力回路の前記出力動作を前記制御信号に拘わらず強制的にオフにし、
前記制御部は、前記検出信号が入力されてからオフ期間の経過後に、前記出力回路の前記出力動作の強制的なオフを解除するための解除信号を前記オフ固定回路に出力し、
前記オフ固定回路は、前記解除信号に応じて前記オフ固定信号の出力を停止して、前記駆動回路が前記制御信号に基づいて前記出力回路の前記出力動作を制御する通常動作に復帰させることを特徴とする電源装置。 - 前記オフ固定回路は、
前記第1ノードに入力された前記検出信号を前記オフ固定信号として前記駆動回路に出力し、
その後、前記解除信号の入力に応じて、前記オフ固定信号の出力を停止するように前記第1ノードの電位を制御する
ことを特徴とする請求項1に記載の電源装置。 - 前記制御部は、
出力した前記解除信号をフィードバックし、フィードバックされた前記解除信号に異常があるか否かを検出し、
前記解除信号の異常を検出した場合には、前記制御信号により前記駆動回路を制御して、前記出力回路の前記出力動作を停止させる
ことを特徴とする請求項2に記載の電源装置。 - 前記過電流検出回路は、
前記出力回路に前記出力動作による過電流を検出しない場合には、前記検出信号を前記第1ノードに出力しない
ことを特徴とする請求項2に記載の電源装置。 - 前記制御部は、
前記解除信号を出力した後、前記検出信号が入力されていない場合には、前記出力回路の前記出力動作を制御するための制御信号を前記駆動回路に出力することで、前記駆動回路により前記出力回路の前記出力動作を制御する
ことを特徴とする請求項4に記載の電源装置。 - 前記駆動回路は、
前記制御信号と前記第1ノードの電位に基づいた信号とを演算した論理信号を出力する論理回路と、
前記論理信号に基づいて前記出力回路の電流の出力動作を制御するドライバと、を備える
ことを特徴とする請求項1に記載の電源装置。 - 前記出力回路は、前記電源から供給される電力を制御して出力するブリッジ回路であることを特徴とする請求項2に記載の電源装置。
- 前記ブリッジ回路は、
一端が前記電源に接続され、他端が第1の出力端子に接続された第1の出力トランジスタと、
一端が前記電源に接続され、他端が第2の出力端子に接続された第2の出力トランジスタと、
一端が前記第1の出力端子に接続され、他端が固定電位に接続された第3の出力トランジスタと、
一端が前記第2の出力端子に接続され、他端が固定電位に接続され、第4の出力トランジスタと、
一端が前記第3の出力トランジスタの他端に接続され、他端が前記固定電位に接続された第1の検出抵抗と、
一端が前記第4の出力トランジスタの他端に接続され、他端が前記固定電位に接続された第2の検出抵抗と、を備え、
前記過電流検出回路は、前記第1及び第2の検出抵抗に流れる電流を検出することで前記ブリッジ回路が出力する電流の過電流を検出し、この検出結果に応じた前記検出信号を出力し、
前記駆動回路は、通常動作時は、前記制御信号に基づいて前記第1ないし第4の出力トランジスタの動作を制御することで、前記ブリッジ回路の電力の出力動作を制御する
ことを特徴とする請求項7に記載の電源装置。 - 前記制御部は、前記出力回路の前記出力動作を強制的にオフする前記オフ期間をソフトウエアで設定する
ことを特徴とする請求項1に記載の電源装置。 - 前記出力ノードが前記第1ノードに接続され、
前記オフ固定回路は、
エミッタが前記電源に接続された第1のPNP型バイポーラトランジスタと、
一端が前記第1のPNP型バイポーラトランジスタのコレクタに接続された第1の制御抵抗と、
コレクタが前記第1の制御抵抗の他端に接続され、エミッタが前記固定電位に接続され、ベースに前記制御部から前記解除信号が入力されるようになっている第1のNPN型バイポーラトランジスタと、
一端が前記電源に接続され、他端が前記第1のPNP型バイポーラトランジスタのベースに接続された第2の制御抵抗と、
一端が前記第2の制御抵抗の他端に接続され、他端が前記第1ノードに接続された第3の制御抵抗と、
コレクタが前記第3の制御抵抗の他端に接続され、エミッタが前記固定電位に接続され、ベースが前記第1の制御抵抗の他端に接続された第2のNPN型バイポーラトランジスタと、を備え、
前記オフ固定回路は、
前記過電流検出回路から出力された前記検出信号に応じて、前記第1ノードの電位に基づいた信号を、前記オフ固定信号として、前記駆動回路に出力し、
一方、前記制御部から出力された前記解除信号に応じて、前記駆動回路への前記オフ固定信号の出力を停止する
ことを特徴とする請求項5に記載の電源装置。 - 前記過電流検出回路は、
前記出力回路が出力する電流が予め設定された過電流閾値以上になった場合には、前記検出信号を出力し、
前記出力回路が出力する電流が前記過電流閾値未満になった場合には、前記検出信号を出力しない
ことを特徴とする請求項2に記載の電源装置。 - 前記駆動回路は、
前記過電流検出回路により過電流が検出された場合には、前記第1ノードの前記検出信号に基づいて前記オフ固定回路が出力する前記オフ固定信号に応じて、前記第1ないし第4の出力トランジスタの動作を停止させ、
その後、前記解除信号に基づいた前記オフ固定回路からの前記オフ固定信号の出力停止に応じて前記第1ないし第4の出力トランジスタの動作の停止を解除し、
その後、前記制御信号に基づいて前記第1ないし第4の出力トランジスタの動作を制御することを特徴とする請求項8に記載の電源装置。 - 前記出力ノードが前記第1ノードに接続され、
前記オフ固定回路は、
一端が前記電源に接続され、他端が前記第1ノードに接続された第1の制御抵抗と、
一端が前記電源に接続された第2の制御抵抗と、
一端が前記第1ノードに接続され、他端が固定電位に接続されたキャパシタと、
エミッタが前記第1ノードに接続され、他端が前記固定電位に接続され、ベースが前記第2の制御抵抗の他端に接続されたPNP型バイポーラトランジスタと、
コレクタが前記第2の制御抵抗の他端に接続され、エミッタが前記固定電位に接続され、 ベースに前記制御部から前記解除信号が入力されるようになっているNPN型バイポーラトランジスタと、を備え、
前記出力ノードが前記第1ノードに接続され、
前記オフ固定回路は、
前記過電流検出回路から出力された前記検出信号に応じて、前記第1ノードの電位に基づいた信号を、前記オフ固定信号として、前記駆動回路に出力し、
一方、前記制御部から出力された前記解除信号に応じて、前記駆動回路への前記オフ固定信号の出力を停止する
ことを特徴とする請求項5に記載の電源装置。 - 前記オフ固定回路は、
一端が前記電源に接続され、他端が前記出力ノードに接続された第1の制御抵抗と、
一端が前記電源に接続された第2の制御抵抗と、
一端が前記第2の制御抵抗の他端に接続され、他端が前記第1ノードに接続された第3の制御抵抗と、
一端が前記第1の制御抵抗の他端に接続され、他端が固定電位に接続された第1のキャパシタと、
一端が前記第2の制御抵抗の一端に接続され、他端が前記固定電位に接続された第2のキャパシタと、
一端が前記第2の制御抵抗の他端に接続され、他端が前記固定電位に接続された第3のキャパシタと、
一端が前記第2の制御抵抗の他端に接続された第4の制御抵抗と、
コレクタが前記第2のキャパシタの他端に接続され、エミッタが前記固定電位に接続され、 ベースに前記制御部から前記解除信号が入力されるようになっているNPN型バイポーラトランジスタと、
一端が前記第1の制御抵抗の他端に接続され、他端が前記固定電位に接続され、前記第2の制御抵抗の他端の電位が予め設定されたリセット閾値未満である場合には、前記第1のキャパシタの一端と他端との間を導通して前記第1のキャパシタの電荷を放電させ、一方、前記第2の制御抵抗の他端の前記電位が前記リセット閾値以上である場合には、前記第1のキャパシタの一端と他端との間を遮断するリセット回路と、を備え、
前記オフ固定回路は、
前記過電流検出回路から出力された前記検出信号に応じて、前記第1ノードの電位に基づいた信号を、前記オフ固定信号として、前記駆動回路に出力し、
一方、前記制御部から出力された前記解除信号に応じて、前記駆動回路への前記オフ固定信号の出力を停止する
ことを特徴とする請求項5に記載の電源装置。 - 電源から電力を供給され、電流を出力する出力回路と、前記出力回路の電流の出力動作を制御する駆動回路と、前記出力回路の過電流を検出すると検出信号を第1ノードに出力する過電流検出回路と、前記第1ノードに入力された前記検出信号に基づいて、前記出力回路の前記出力動作を前記制御信号に拘わらず強制的にオフするためのオフ固定信号を出力ノードから前記駆動回路に出力するオフ固定回路と、前記出力回路の前記出力動作を制御するための制御信号を前記駆動回路に出力することで、前記駆動回路により前記出力回路の前記出力動作を制御するとともに、前記検出信号が入力されるようになっている制御部と、を備えた電源装置の制御方法であって、
前記駆動回路により、前記オフ固定信号に応じて、前記出力回路の前記出力動作を前記制御信号に拘わらず強制的にオフにし、
前記制御部により、前記検出信号が入力されてからオフ期間の経過後に、前記出力回路の前記出力動作の強制的なオフを解除するための解除信号を前記オフ固定回路に出力し、
前記オフ固定回路により、前記解除信号に応じて前記オフ固定信号の出力を停止して、前記駆動回路が前記制御信号に基づいて前記出力回路の前記出力動作を制御する通常動作に復帰させる
ことを特徴とする電源装置の制御方法。
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JP2013247821A (ja) * | 2012-05-29 | 2013-12-09 | Sharp Corp | 過電圧保護回路及び電源装置 |
JP3193936U (ja) * | 2014-06-20 | 2014-10-30 | 群光電能科技股▲ふん▼有限公司 | 出力短絡保護装置 |
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JP2000295878A (ja) * | 1999-04-01 | 2000-10-20 | Koyo Seiko Co Ltd | 電動パワーステアリング装置 |
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JP6308519B2 (ja) | 2013-11-29 | 2018-04-11 | 株式会社東芝 | モータ駆動装置及びモータ制御方法 |
JP6409982B2 (ja) * | 2015-09-30 | 2018-10-24 | 富士電機株式会社 | 多相電力変換装置の制御回路 |
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JPS6149614A (ja) * | 1984-08-17 | 1986-03-11 | 富士通株式会社 | 過電流制御回路 |
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JP2007252165A (ja) * | 2006-03-20 | 2007-09-27 | Mitsubishi Electric Corp | インバータ |
JP2008118834A (ja) * | 2006-11-08 | 2008-05-22 | Toyota Industries Corp | サージ低減回路およびサージ低減回路を備えたインバータ装置 |
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JP2013247821A (ja) * | 2012-05-29 | 2013-12-09 | Sharp Corp | 過電圧保護回路及び電源装置 |
JP3193936U (ja) * | 2014-06-20 | 2014-10-30 | 群光電能科技股▲ふん▼有限公司 | 出力短絡保護装置 |
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Also Published As
Publication number | Publication date |
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JPWO2019026295A1 (ja) | 2019-08-08 |
CN109804564B (zh) | 2023-01-06 |
CN109804564A (zh) | 2019-05-24 |
EP3664272A4 (en) | 2020-08-12 |
JP6445192B1 (ja) | 2018-12-26 |
US20190089157A1 (en) | 2019-03-21 |
EP3664272A1 (en) | 2020-06-10 |
US10333303B2 (en) | 2019-06-25 |
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