WO2019015309A1 - 移位寄存器单元及其驱动方法、栅极驱动电路、阵列基板、显示装置 - Google Patents

移位寄存器单元及其驱动方法、栅极驱动电路、阵列基板、显示装置 Download PDF

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Publication number
WO2019015309A1
WO2019015309A1 PCT/CN2018/075745 CN2018075745W WO2019015309A1 WO 2019015309 A1 WO2019015309 A1 WO 2019015309A1 CN 2018075745 W CN2018075745 W CN 2018075745W WO 2019015309 A1 WO2019015309 A1 WO 2019015309A1
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Prior art keywords
signal
reset
output
circuit
sub
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PCT/CN2018/075745
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English (en)
French (fr)
Inventor
苏秋杰
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US16/304,738 priority Critical patent/US20190189233A1/en
Publication of WO2019015309A1 publication Critical patent/WO2019015309A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to the field of display technologies, and in particular to a shift register unit and a driving method thereof, a gate driving circuit, an array substrate, and a display device.
  • the GOA Gate Driver On Array
  • the current display panel industry based on cost considerations, began to use the GOA structure to drive the display panel. This trend has become more apparent in recent years.
  • the GOA structure is to form a gate driving circuit by using a plurality of TFTs (thin film transistors) and capacitors on the array substrate, which is essentially a shift register, which sequentially outputs a high level with the clock signal, thereby opening the corresponding gate line. .
  • TFTs thin film transistors
  • an object of the present disclosure is to provide a shift register unit and a driving method thereof, a gate driving circuit, an array substrate, and a display device.
  • a shift register unit including:
  • An input sub-circuit having a first end connected to the input end and a second end connected to the pull-up node, the input sub-circuit for receiving an input signal from the input terminal and outputting the input signal to the pull-up a node, and outputting a pull-up signal via the pull-up node;
  • a first output sub-circuit the first end of which is connected to the first output signal end, the second end is connected to the first clock signal end, the third end is connected to the pull-up node, and the first output sub-circuit is used for receiving Pulling up the signal and the first clock signal, and outputting the first output signal from the first output signal end according to the pull-up signal and the first clock signal;
  • a second output sub-circuit the first end of which is connected to the second output signal end, the second end is connected to the second clock signal end, the third end is connected to the pull-up node, and the second output sub-circuit is used for receiving And the second output signal is output from the second output signal end according to the pull-up signal and the second clock signal;
  • a storage subcircuit having a first end coupled to the pull up node and a second end coupled to the second output subcircuit, the memory subcircuit being configured to store the pull up signal.
  • the shift register unit as described above further includes: a first reset sub-circuit having a first end connected to the pull-up node, a second end connected to the first reset end, and a third end connected And to the reset voltage terminal, the first reset sub-circuit is configured to receive a first reset signal from the first reset terminal, and reset the pull-up node according to the first reset signal.
  • the shift register unit as described above further includes: a second reset sub-circuit having a first end connected to the first output sub-circuit, a second end connected to the second reset end, and a third The terminal is connected to the reset voltage terminal, and the second reset sub-circuit is configured to receive a second reset signal from the second reset terminal, and reset the first output sub-circuit according to the second reset signal.
  • the shift register unit as described above further includes: a third reset sub-circuit having a first end connected to the second output sub-circuit, a second end connected to the third reset end, and a third The terminal is connected to the reset voltage terminal, and the third reset sub-circuit is configured to receive a third reset signal from the third reset terminal, and reset the second output sub-circuit according to the third reset signal.
  • the input subcircuit includes an input transistor having a control electrode and a first pole coupled to the input and receiving the input signal via the input, the input transistor A second pole is coupled to the pull up node.
  • the first output sub-circuit includes a first output transistor, a control electrode of the first output is coupled to the pull-up node, and a first pole of the first output transistor is coupled to the a clock signal terminal and receiving the first clock signal, a second pole of the first output transistor being connected to the first output signal terminal and outputting the first output signal.
  • the second output sub-circuit includes a second output transistor, a control electrode of the second output transistor is coupled to the pull-up node, and a first pole of the second output transistor is coupled to a second
  • the clock signal terminal receives the second clock signal, and the second electrode of the second output transistor is connected to the second output signal terminal and outputs the second output signal.
  • the storage subcircuit includes a capacitor, a first end of the capacitor coupled to the pull up node, and a second end of the capacitor coupled to the second output signal terminal.
  • the first reset sub-circuit includes a first reset transistor, a control electrode of the first reset transistor is coupled to the first reset terminal and receives the first reset signal, the first reset a first pole of the transistor is coupled to the memory subcircuit, a second pole of the first reset transistor is coupled to a reset voltage terminal and receives a reset voltage signal; and/or the second reset subcircuit includes a second reset transistor a control pole of the second reset transistor is coupled to the second reset terminal and receives the second reset signal, a first pole of the second reset transistor is coupled to the first output signal terminal, and the second reset a second pole of the transistor is coupled to the reset voltage terminal and receives a reset voltage signal; and/or, the third reset subcircuit includes a third reset transistor, and a control electrode of the third reset transistor is coupled to the third reset terminal And receiving the third reset signal, a first pole of the third reset transistor is connected to the second output signal terminal, and a second pole of the third reset transistor is connected to the reset Voltage terminal and receives the reset signal
  • a first noise reduction sub-circuit is disposed between the input sub-circuit and the first output sub-circuit, and/or between the input sub-circuit and the second output sub-circuit There is a second noise reduction subcircuit.
  • the first reset signal and the third reset signal are the same reset signal.
  • a driving method of a shift register unit for driving the shift register unit according to any of the above comprising:
  • the pull-up signal When the input signal is turned on, the pull-up signal is output to the first output sub-circuit and the second output sub-circuit via the input sub-circuit;
  • the first clock signal is at an on level, and the first output sub-circuit outputs a first output signal
  • the first clock signal and the second clock signal are at an on level
  • the second output sub-circuit outputs a second output signal
  • the first output sub-circuit continues to output the first output signal
  • the driving method further includes, during a third time period, the second reset signal is at an on level, and the first output signal is reset.
  • the driving method further includes: in the fourth period, the first reset signal and the third reset signal are at an on level, and the pull-up signal and the second output signal are reset.
  • the first reset signal and the third reset signal are the same reset signal.
  • a gate driving circuit comprising at least two cascaded shift register units according to any of the above.
  • the input signal terminal of the shift register unit of the Nth stage is connected to the second output signal terminal of the shift register unit of the N-1th stage, and the first clock signal terminal and the second clock signal of the shift register unit of the Nth stage
  • the terminal respectively accesses the first clock signal and the second clock signal, and the first reset signal end and the third reset signal end of the shift register unit of the Nth stage and the second output signal of the shift register unit of the (N+1)th stage
  • the terminal is connected, and the second reset signal terminal of the shift register unit of the Nth stage is connected to the first output signal terminal of the shift register unit of the (N+1)th stage.
  • the input signal terminal of the shift register unit of the (N+1)th stage is connected to the second output signal terminal of the shift register unit of the Nth stage, and the first of the shift register units of the (N+1)th stage
  • the clock signal end and the second clock signal end respectively access the third clock signal and the fourth clock signal, and the first reset signal end and the third reset signal end of the shift register unit of the (N+1)th stage are combined with the N+2th stage
  • the second output signal terminal of the shift register unit is connected, and the second reset signal terminal of the shift register unit of the (N+1)th stage is connected to the first output signal terminal of the shift register unit of the N+2th stage.
  • the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are sequentially separated by 1/4 cycle.
  • an array substrate comprising the gate drive circuit of any of the above.
  • a display device comprising the array substrate as described above.
  • 1a is a schematic structural view of a gate driving circuit in the prior art and a timing diagram of an output signal thereof;
  • 1b is a schematic structural diagram of a shift register unit in the prior art
  • 1c is a signal timing diagram of a shift register unit in the prior art
  • FIG. 2 is a schematic structural diagram of an embodiment of a shift register unit provided by the present disclosure
  • 3a is a schematic structural diagram of a circuit of an embodiment of a shift register unit provided by the present disclosure
  • 3b is a schematic structural diagram of a circuit of another embodiment of a shift register unit provided by the present disclosure.
  • FIG. 4 is a signal timing diagram of one embodiment of a shift register unit provided by the present disclosure.
  • 5a is an equivalent circuit diagram of one embodiment of a shift register unit provided by the present disclosure.
  • Figure 5b is an equivalent circuit diagram of one embodiment of a shift register unit provided by the present disclosure.
  • Figure 5c is an equivalent circuit diagram of one embodiment of a shift register unit provided by the present disclosure.
  • 5d is an equivalent circuit diagram of one embodiment of a shift register unit provided by the present disclosure.
  • 5e is an equivalent circuit diagram of one embodiment of a shift register unit provided by the present disclosure.
  • FIG. 6 is a schematic flowchart diagram of an embodiment of a method for driving a shift register unit according to the present disclosure
  • FIG. 7 is a schematic structural diagram of an embodiment of a gate driving circuit provided by the present disclosure.
  • FIG. 8 is a schematic diagram of an embodiment of a display device provided by the present disclosure.
  • FIG. 1a Shown in FIG. 1a is a schematic structural diagram of a gate driving circuit in the prior art and an output signal timing diagram of each stage of the shift register.
  • the example shown in Figure 1 is a 4CLK pre-charge gate drive circuit.
  • the prior art 4CLK precharge gate drive circuit includes four clock CLK signal lines: CLK1-CLK4; and a reset voltage VSS signal line.
  • the gate driving circuit in FIG. 1 is, in order from the top to the bottom, the N-2th shift register unit GOA_N-2, the N-1th shift register unit GOA_N-1, the Nth shift register unit GOA_N, and the N+1 stage shift register unit GOA_N+1, N+2 stage shift register unit GOA_N+2, where N is a positive integer greater than 2; output terminals OUT_N-2, OUT_N-1 of each shift register unit, OUT_N, OUT_N+1, and OUT_N+2 sequentially output a high level signal.
  • Shown in Figure 1b is a schematic diagram of the structure of a prior art shift register unit in which a single shift register cell contains four main working TFTs: T1', T2', T3', T4' and a capacitor C'.
  • the signal of the input terminal INPUT is input to the pull-up node PU' via T1', and T3' is turned on under the control of PU', and outputs a signal to the output terminal OUT_N when the signal is input by CLK3.
  • Transistors T2' and T4' are used to reset the pull-up node PU' and the output terminal PUT_N, respectively.
  • a single shift register unit generally includes five signal input and output terminals: an input terminal INPUT, a clock signal terminal CLK3, a reset terminal RESET, an output terminal OUT_N, and a reset voltage terminal VSS.
  • Shown in Figure 1c is a signal timing diagram of a prior art shift register unit.
  • the access signals of the clock signal terminal CLK3 and the reset voltage terminal VSS can be provided by the PCB (circuit board) signal source, respectively, the clock signal and the low level DC signal; the input terminal INPUT, the reset terminal RESET, and the output terminal OUT_N signal Both are cascaded signals between shift register units, and more importantly, the signal at the output terminal OUT_N also acts as a gate drive signal.
  • the signal of the input terminal INPUT of the Nth stage shift register unit is provided by the signal of the output terminal OUT_N-2 of the N-2th stage, and the shift of the Nth stage
  • the signal of the reset terminal RESET of the bit register unit is provided by the signal of the OUT_N+2 of the N+2 stage; and the signal of the output terminal OUT_N of the Nth stage is also used as the signal of the reset terminal RESET of the N-2th stage and the Nth +2 level input signal of INPUT.
  • the pull-up signal timing at the pull-up node PU' is also shown in Figure 1c.
  • each gate drive signal needs to be provided by a shift register unit. This makes the gate drive circuit occupy a large overall space, which is disadvantageous for the realization of smaller-sized electronic devices (for example, narrow-frame electronic devices).
  • the vertical direction (the short border of the display panel) is small
  • the horizontal direction (the long border of the display panel) is required to be larger, that is, the width of the border of the panel is increased.
  • an embodiment of a shift register unit is provided that can implement a narrow bezel.
  • FIG. 2 Shown in FIG. 2 is a block diagram showing an embodiment of a shift register unit provided by the present disclosure.
  • the shift register unit 100 includes:
  • the input sub-circuit 101 has a first end connected to the input signal end, a second end connected to the pull-up node, the input sub-circuit 101 for receiving an input signal from the input end, and outputting the input signal to the pull-up node, and A pull-up signal is output via the pull-up node.
  • the input sub-circuit 101 is connected to the input signal terminal INPUT, and the input signal is output to the pull-up node PU via the input sub-circuit 101.
  • the first output sub-circuit 102 is connected to the input sub-circuit 101 for receiving the pull-up signal and the first clock signal, and outputs the first output signal according to the pull-up signal and the first clock signal.
  • the first end of the first output sub-circuit 102 is connected to the first clock signal terminal CLK1, and the second terminal is connected to the first output signal terminal OUT.
  • the first clock signal is input to the first output sub-circuit 102 via the first clock signal terminal CLK1, and the first output signal terminal OUT is connected to the gate scan line (for example, the Nth-th scan line) of the corresponding TFT for the corresponding TFT.
  • the gate outputs the first output signal as a corresponding scan signal.
  • the second output sub-circuit 103 is connected to the input sub-circuit 101 for receiving the pull-up signal and the second clock signal, and outputting the second output signal according to the pull-up signal and the second clock signal.
  • the first end of the second output sub-circuit 103 is connected to the second clock signal terminal CLK2, and the second terminal is connected to the second output signal terminal OUT(+1).
  • the second clock signal is input to the second output sub-circuit 103 via the second clock signal terminal CLK2, and the second output signal terminal OUT(+1) is connected to the gate scan line (for example, the N+1th scan line) of the corresponding TFT. And for outputting the second output signal to a gate of the corresponding TFT as a corresponding scan signal.
  • the storage sub-circuit 104 is connected to the input sub-circuit 101 and the second output sub-circuit 103, respectively, for storing the pull-up signal. As shown in FIG. 2, for example, the first end of the storage sub-circuit 104 is connected to the pull-up node PU, and the second end is connected to the second output sub-circuit 103.
  • shift register unit 100 further includes:
  • the first reset sub-circuit 105 is connected to the storage sub-circuit 104 for receiving the first reset signal and resetting the pull-up node PU according to the first reset signal.
  • the first terminal of the first reset sub-circuit 105 is connected to the first reset signal terminal RESET1
  • the second terminal is connected to the pull-up node PU
  • the third terminal is connected to the reset voltage terminal VSS.
  • the first reset sub-circuit 105 receives the first reset signal from the first reset terminal RESET1, and resets the pull-up node PU under the control of the first reset signal.
  • the second reset sub-circuit 106 is coupled to the first output sub-circuit 102 for receiving the second reset signal and resetting the first output signal according to the second reset signal.
  • the first terminal of the second reset sub-circuit 106 is connected to the second reset signal terminal RESET2
  • the second terminal is connected to the first output sub-circuit
  • the third terminal is connected to the reset voltage terminal VSS.
  • the second reset sub-circuit 106 receives the second reset signal from the second reset terminal RESET2, and resets the first output sub-circuit under the control of the second reset signal.
  • the third reset sub-circuit 107 is connected to the second output sub-circuit 103 for receiving the third reset signal and resetting the second output signal according to the third reset signal.
  • the first terminal of the third reset sub-circuit 107 is connected to the third reset signal terminal RESET3, the second terminal is connected to the second output sub-circuit, and the third terminal is connected to the reset voltage terminal VSS.
  • the third reset sub-circuit 107 receives the third reset signal from the third reset terminal RESET3, and resets the second output sub-circuit under the control of the third reset signal.
  • the shift register unit provides only one set of output sub-circuits (such as the second output sub-circuit and the third reset sub-increment) by adding only one set of output sub-circuits in the original shift register unit circuit. Circuit), so that one shift register unit can output two adjacent output signals, thereby greatly reducing the number of TFTs required for the gate driving circuit, reducing the space required for layout, and facilitating design of products with smaller sizes. .
  • applying the shift register unit in the above embodiment to the GOA product can greatly reduce the number of TFTs required for the GOA product, reduce the space required for layout, and facilitate the design of the narrow-frame GOA product.
  • FIG. 3a illustrates a circuit configuration diagram of a shift register unit in accordance with an embodiment of the present disclosure.
  • the input sub-circuit 101 includes an input transistor T1 having a control electrode and a first pole connected to the input terminal INPUT and receiving an input signal from the input.
  • the second electrode of the input transistor T1 is connected to the pull-up node PU and is connected to the first output sub-circuit 102 and the second output sub-circuit 103 via the pull-up node PU, respectively.
  • the first output sub-circuit 102 includes a first output transistor T2, wherein a control electrode of the first output transistor T2 is coupled to the input sub-circuit 101, and a first pole of the first output transistor T2 receives the first The clock signal, the second pole of the first output transistor T2 outputs a first output signal.
  • the first pole of the first output transistor T2 is coupled to the first clock signal terminal CLK1 for receiving the first clock signal.
  • the second electrode of the first output transistor T2 is connected to the first output signal terminal OUT for outputting the first output signal from the first output signal terminal OUT.
  • the control electrode of the first output transistor T2 is connected to the pull-up node PU, and outputs the first clock signal as a first output signal to the first output terminal under the control of the pull-up node PU.
  • the first output sub-circuit 102 is implemented by the first output transistor T2, and the control of the first output signal can be realized.
  • the second output sub-circuit 103 includes a second output transistor T3.
  • the control electrode of the second output transistor T3 is connected to the input sub-circuit 101, the first electrode of the second output transistor T3 receives the second clock signal, and the second electrode of the second output transistor T3 outputs the second output signal.
  • the first pole of the second output transistor T3 is coupled to the second clock signal terminal CLK2 for receiving the second clock signal.
  • the second electrode of the second output transistor T3 is coupled to the second output signal terminal OUT(+1) for outputting the second output signal from the second output signal terminal OUT(+1).
  • the control electrode of the second output transistor T3 is connected to the pull-up node PU, and outputs the second clock signal as a second output signal to the second output terminal under the control of the pull-up node PU.
  • the second output sub-circuit is implemented by the second output transistor T3, and the control of the second output signal can be realized.
  • the memory sub-circuit 104 includes a capacitor C having a first end coupled to the input sub-circuit 101 and a second end coupled to the second output sub-circuit 103.
  • the first end of the capacitor C is connected to the pull-up node PU, and the second end is connected to the second output signal terminal OUT(+1).
  • Capacitor C is used to store the pull-up signal.
  • the input west circuit 101 inputs an input signal to the pull-up node PU
  • the pull-up node PU since the pull-up node PU is connected to the capacitor C, the input signal can charge the capacitor C and maintain the potential at the pull-up node PU through the capacitor C.
  • the storage sub-circuit 104 is realized by the capacitor C, and the lifting and holding of the pull-up signal can be realized.
  • the first reset sub-circuit 105 includes a first reset transistor T4.
  • the control electrode of the first reset transistor T4 receives the first reset signal
  • the first pole of the first reset transistor T4 is connected to the memory sub-circuit 104
  • the second pole of the first reset transistor T4 receives the reset voltage signal.
  • the control electrode of the first reset transistor T4 is connected to the first reset signal terminal RESET1 for receiving the first reset signal
  • the first pole of the first reset transistor T4 is connected to the pull-up node PU
  • the first reset transistor T4 is The diode is connected to the reset voltage terminal VSS for receiving a reset voltage signal (optionally, the reset voltage signal is a low level DC signal, which is provided by the PCB signal source).
  • the first reset sub-circuit 105 is implemented by using the first reset transistor T4, and the reset of the pull-up node PU can be controlled by the first reset signal.
  • the second reset sub-circuit 106 includes a second reset transistor T5, the control electrode of the second reset transistor T5 receives the second reset signal, and the first and first outputs of the second reset transistor T5
  • the sub-circuit 102 is connected, and the second pole of the second reset transistor T5 receives the reset voltage signal.
  • the control electrode of the second reset transistor T5 is connected to the second reset signal terminal RESET2 for receiving the second reset signal.
  • the first pole of the second reset transistor T5 is connected to the first output signal terminal OUT.
  • the second pole of the second reset transistor T5 is coupled to the reset voltage terminal VSS for receiving a reset voltage signal (optionally, the reset voltage signal is a low level DC signal, provided by the PCB signal source).
  • the second reset sub-circuit 106 is implemented by the second reset transistor T5, and the reset of the first output signal terminal OUT can be controlled by the second reset signal.
  • the third reset sub-circuit 107 includes a third reset transistor T6, the control electrode of the third reset transistor T6 receives a third reset signal, and the first and second output sub-circuits of the third reset transistor T6 103 is connected, and the second pole of the third reset transistor T6 receives the reset voltage signal.
  • the control electrode of the third reset transistor T6 is connected to the third reset signal terminal RESET3 for receiving the third reset signal, and the first pole of the third reset transistor T6 is connected to the second output signal terminal OUT(+1).
  • the second pole of the triple reset transistor T6 is coupled to the reset voltage terminal VSS for receiving a reset voltage signal (optionally, the reset voltage signal is a low level DC signal, provided by the PCB signal source).
  • the third reset sub-circuit 107 is implemented by the third reset transistor T6, and the reset of the second output signal terminal OUT(+1) can be controlled by the third reset signal.
  • the shift register unit includes nine input/output terminals: an input signal terminal INPUT, a reset voltage terminal VSS, a first clock signal terminal CLK1, a second clock signal terminal CLK2, and a first output signal terminal OUT.
  • the second output signal terminal OUT (+1), the first reset signal terminal RESET1, the second reset signal terminal RESET2, and the third reset signal terminal RESET3.
  • the signals of the first clock signal terminal CLK1, the second clock signal terminal CLK2 and the reset voltage terminal VSS are respectively a clock signal and a low-level DC signal, and the signals may be provided by a PCB signal source;
  • the input signal terminal INPUT, the first output The signal terminal OUT, the second output signal terminal OUT(+1), the first reset signal terminal RESET1, the second reset signal terminal RESET2, and the third reset signal terminal RESET3 are cascade signals between the cascaded shift register units,
  • the first output signal terminal OUT and the second output signal terminal OUT(+1) are also gate drive signals of the adjacent two rows of gates, respectively.
  • the first reset signal and the third reset signal are the same reset signal.
  • the first reset signal terminal RESET1 inputting the first reset signal and the third reset signal terminal RESET3 inputting the third reset signal are connected to the reset signal terminal of the same reset signal.
  • the shift register unit has a total of 6 TFTs and a capacitor C, wherein the input transistor T1, the first output transistor T2, the first reset transistor T4, and the second reset transistor T5 can be used in the existing shift.
  • a similar specification for the transistor in the bit register may be the same as that of the first output transistor T2, and the specification of the third reset transistor T6 may be the same as that of the second reset transistor T5, and the size of the capacitor C may be different from that in the existing shift register unit.
  • Capacitor C' is the same (see Figure 1b).
  • the shift register unit provided by the embodiment of the present disclosure, the number of TFTs required for the gate driving circuit can be reduced, the space required for layout can be reduced, and the design of a product with a smaller size can be realized.
  • FIG. 3b illustrates a circuit configuration diagram of a shift register unit in accordance with an embodiment of the present disclosure.
  • the input sub-circuit 101, the first output sub-circuit 102, the second output sub-circuit 103, the storage sub-circuit 104, the first reset sub-circuit 105, the second reset sub-circuit 106, and the third reset sub-circuit 107 are shown in FIG. 3b.
  • the structure is the same as that shown in FIG. 3a, and details are not described herein again.
  • a first noise reduction sub-circuit may be disposed between the input sub-circuit 101 and the first output sub-circuit 102, and/or the input sub-circuit 101 and the second output sub-circuit 103 may be disposed.
  • the functions of the first noise reduction sub-circuit and the second noise reduction sub-circuit described above are simultaneously implemented by providing a noise reduction sub-circuit 108.
  • the noise reduction sub-circuit can be designed by referring to the noise reduction circuit in the prior art.
  • the circuit structure of the noise reduction sub-circuit may include a plurality of TFTs, and the internal structure of the noise reduction circuit is not limited herein.
  • the first reset signal and the third reset signal are the same reset signal.
  • the first reset signal terminal RESET1 inputting the first reset signal and the third reset signal terminal RESET3 inputting the third reset signal are connected to the reset signal terminal of the same reset signal.
  • FIGS. 3a, 3b and 4 illustrates a signal timing diagram for each input/output terminal in one embodiment of a shift register unit provided in accordance with the present disclosure, wherein.
  • the high level of the clock signal connected to the first clock signal terminal CLK1 and the second clock signal terminal CLK2 lasts for 2 units of time, respectively.
  • the operation of the shift register unit in accordance with the principles of the present disclosure will now be described in conjunction with FIGS. 3a, 3b and 4.
  • the input signal terminal INPUT receives an input signal of a high level, and the input sub-circuit 101 inputs the input signal to the pull-up node PU, and pulls the potential of the PU point high.
  • the control terminal and the first pole of the input transistor T1 are both connected to the input terminal INPUT, so that the input transistor T1 will be turned on under the control of the input signal, and the input signal is input thereto.
  • Pull the node PU The high level of the pull-up node PU point turns on the first output transistor T2 and the second output transistor T3.
  • Figure 5a shows an equivalent circuit diagram of the shift register during the t1 period.
  • the input transistor T1, the first output transistor T2, and the second output transistor T3 are turned on.
  • the first reset transistor T4, the second reset transistor T5, and the third reset transistor T6 are turned off.
  • the time of one unit (t2 period), the high level of the first clock signal accessed by the first clock signal terminal CLK1 comes, and the first output signal terminal OUT is charged through the first output transistor T2.
  • the first output signal terminal OUT starts to output a high level.
  • Figure 5b shows an equivalent circuit diagram of the shift register during the t2 period.
  • the input transistor T1, the first output transistor T2, and the second output transistor T3 are turned on.
  • the first reset transistor T4, the second reset transistor T5, and the third reset transistor T6 are turned off.
  • the first output signal terminal OUT outputs a high level.
  • the input terminal INPUT no longer inputs a high level input signal, and the input transistor T1 is turned off.
  • the high potential of the second clock signal connected to the second clock signal terminal CLK2 comes, the second output signal terminal OUT(+1) is charged through the second output transistor T3, and the second output signal terminal OUT(+1) starts to output high.
  • Figure 5c shows an equivalent circuit diagram of the shift register during the t3 period.
  • input transistor T1 is turned off.
  • the first output transistor T2 and the second output transistor T3 are turned on.
  • the first reset transistor T4, the second reset transistor T5, and the third reset transistor T6 are turned off.
  • the first output signal terminal OUT and the second output signal terminal OUT(+1) output a high level.
  • the first output signal terminal OUT outputs a total of two high levels of unit time, in the period of t4, the high level of the second reset signal of the second reset signal terminal RESET2 comes, and the second reset transistor T5 is The second reset signal is turned on under control, and the first output signal segment OUT is reset according to the low-level reset signal of the reset voltage terminal VSS, and the high level of the output of the first output signal terminal OUT ends.
  • Figure 5d shows an equivalent circuit diagram of the shift register during the t4 period.
  • input transistor T1 is turned off.
  • the first output transistor T2 and the second output transistor T3 are turned on.
  • the first reset transistor T4 and the third reset transistor T6 are turned off.
  • the second reset transistor T5 is turned on.
  • the second output signal terminal OUT(+1) outputs a high level, and the first output signal terminal OUT is reset under the control of the second reset signal.
  • the time of one unit (t5 period), the high level of the third reset signal of the third reset signal terminal RESET3 comes, and the third reset transistor T6 utilizes the reset voltage terminal under the control of the third reset signal.
  • the low-level reset voltage signal of the VSS access resets the second output signal terminal.
  • the high level of the first reset signal of the first reset signal terminal RESET1 comes, and the first reset transistor T4 uses the low-level reset voltage signal connected to the reset voltage terminal VSS under the control of the first reset signal to the pull-up node PU. Reset.
  • one shift register unit can be Output two adjacent output signals for driving the gates of adjacent rows, thereby greatly reducing the number of TFTs required for the gate driving circuit, reducing the space required for layout, and facilitating realization of products of smaller size. design.
  • the transistors in the above embodiments may be any type of transistors that are currently applicable or can be applied to a shift register, for example, a polysilicon thin film transistor, an amorphous silicon thin film transistor, an oxide thin film transistor, and an organic thin film transistor.
  • a polysilicon thin film transistor for example, a polysilicon thin film transistor, an amorphous silicon thin film transistor, an oxide thin film transistor, and an organic thin film transistor.
  • the type of transistor used is not limited in this disclosure.
  • the "control electrode” referred to in this embodiment may specifically refer to the gate or the base of the transistor, and the "first pole” may specifically refer to the source or emitter of the transistor, and the corresponding "second pole” may specifically Refers to the drain or collector of a transistor.
  • the "first pole” and “second pole” are interchangeable.
  • the input transistor T1, the first output transistor T2, the second output transistor T3, the first reset transistor T4, the second reset transistor T5, and the third reset transistor T6 are all N-type transistors, which is the embodiment.
  • the technical solutions for performing the same on or off operation for each transistor in the examples are all within the scope of the present application. For details, no more examples are given here.
  • FIG. 6 is a schematic flow chart of an embodiment of a method for driving a shift register unit according to the present disclosure.
  • the driving method of the shift register unit for driving the shift register unit in the foregoing embodiment includes:
  • Step 201 When the input signal is high level, the pull-up signal is output to the first output sub-circuit 102 and the second output sub-circuit 103 via the input sub-circuit 101;
  • Step 202 In the first period, the first clock signal is at a high level, and the first output sub-circuit 102 outputs a first output signal.
  • Step 203 In the second period, the first clock signal and the second clock signal are at a high level, the second output sub-circuit 103 outputs a second output signal, and the first output sub-circuit 102 continues to output the first output signal;
  • Step 204 In the third period, the second reset signal is at a high level, and the first output signal is reset.
  • Step 205 In the fourth period, the first reset signal and the third reset signal are at a high level, and the pull-up signal and the second output signal are reset.
  • the driving method of the shift register unit makes a signal design of each input terminal of the mobile register unit, so that the circuit of the shift register unit is improved.
  • the shift register unit can output two adjacent output signals for respectively driving the gates of adjacent rows, thereby greatly reducing the number of TFTs required for the gate driving circuit, reducing the space required for layout, and facilitating implementation.
  • the design of small size products are very small size products.
  • the first reset signal and the third reset signal are the same reset signal, and by sharing the reset signal, the device can be reduced, and the structural design of the shift register unit is simplified.
  • FIG. 7 is a schematic structural diagram of an embodiment of a gate driving circuit provided by the present disclosure.
  • the gate drive circuit includes any one of at least two cascaded shift register units as previously described.
  • the input signal terminal INPUT of the shift register unit GOA_N, N+1 of the Nth stage is connected to the second output signal terminal OUT(+1) of the shift register unit GOA_N-2, N-1 of the N-1th stage,
  • the first clock signal terminal CLK and the second clock signal terminal CLK(+1) of the N-stage shift register unit GOA_N, N+1 are respectively connected to the first clock signal CLK1 and the second clock signal CLK2, and the Nth stage shift
  • the input signal terminal INPUT of the shift register unit GOA_N+2, N+3 of the N+1th stage is connected to the second output signal terminal OUT(+1) of the shift register unit GOA_N, N+1 of the Nth stage
  • the first clock signal terminal CLK and the second clock signal terminal CLK (+1) of the N+1 stage shift register unit GOA_N+2, N+3 are respectively connected to the third clock signal CLK3 and the fourth clock signal CLK4, respectively N+1 stage shift register unit GOA_N+2, N+3 first reset signal terminal and third reset signal terminal RESET(+1) and N+2 stage shift register unit (not shown)
  • the second output signal terminal OUT(+1) is connected, the second reset signal terminal RESET of the shift register unit of the (N+1)th stage and the first output signal of the shift register unit (not shown) of the N+2th stage
  • the terminal OUT is connected.
  • the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are sequentially separated by 1/4 cycle. Meanwhile, the signal timing of the shift register unit of each stage can be referred to the timing in FIG.
  • the gate driving circuit provided by the embodiment of the present disclosure can design two shifting register units to output two adjacent terminals through the connection design of the clock signal line and the signal terminal of the cascaded shift register unit.
  • the output signal greatly reduces the number of TFTs required for GOA products, reduces the space required for layout, and facilitates the design of smaller-sized GOA products.
  • FIG. 8 is a schematic diagram of an embodiment of a display device provided by the present disclosure.
  • the display device shown in FIG. 8 may include an array substrate, wherein the array substrate may include the gate driving circuit as described in any of the previous embodiments.
  • the display device in this embodiment may be any product or component having a display function, such as an electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, and the like.
  • a shift register unit is made by merely adding the second output sub-circuit and the third reset sub-circuit in the original shift register unit circuit. Two adjacent output signals can be output, thereby greatly reducing the number of TFTs required for the gate driving circuit, reducing the space required for layout, and facilitating the design of products of smaller size.
  • the existing shift register unit contains M (M>4, common values 9, 10, 12, 16, etc.) TFTs, one capacitor C, then an ultra-high resolution display + single gate gate drive circuit structure It usually contains 2160*M TFTs and 2016 capacitors.
  • the gate driving circuit provided by the embodiment of the present disclosure for the internal structure of the shift register unit, no change is made to the noise reduction structure, only the circuit structure needs to be adjusted, and two TFTs are added in one shift register unit. It is possible to output two output signals, that is, the original shift register unit structure needs to output 2*M TFTs and 2 capacitors C for two adjacent gate signals, and the shift register unit structure of the present disclosure only needs M +2 TFTs and one capacitor C can be realized, so that the ultra-high-resolution display + single-gate gate drive circuit structure only needs to include 1080*(M+2) TFTs and 1080 capacitors.
  • the shift register unit, the gate driving circuit, and the corresponding array substrate and display device including the gate driving circuit provided by the embodiments of the present disclosure can greatly reduce the number of TFTs and the number of capacitors. By reducing it by half, it greatly saves the wiring space of the gate drive circuit, which is conducive to achieving a smaller product design.
  • DRAM dynamic RAM
  • the present invention can be implemented by means of software plus the necessary general hardware, and of course also by dedicated hardware, but in many cases the former may be a preferred embodiment.
  • the technical solution of the present invention is embodied in the form of software, hardware, firmware or any combination thereof, the computer software product being stored in a readable storage medium, such as a magnetic storage medium (such as a hard disk) or Electronic storage media (e.g., ROM, flash memory) and the like, including instructions to cause a computing device (which may be a computer, server or network device, etc.) to perform the methods described in various embodiments of the present invention.

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Abstract

一种移位寄存器单元(100)及其驱动方法、栅极驱动电路、阵列基板和显示装置，移位寄存器单元(100)包括：输入子电路(101)，其第一端连接到输入端(INPUT)，第二端连接到上拉节点(PU)，用于从输入端(INPUT)接收输入信号，并将其输出到上拉节点(PU)，并经由上拉节点(PU)输出上拉信号；第一输出子电路(102)，其第一端连接到第一输出信号端(OUT)，第二端连接到第一时钟信号端(CLK1)，第三端连接到上拉节点(PU)，用于接收上拉信号和第一时钟信号，并根据上拉信号和第一时钟信号从第一输出信号端(OUT)输出第一输出信号；第二输出子电路(103)，其第一端连接到第二输出信号端(OUT(+1))，第二端连接到第二时钟信号端(CLK2)，第三端连接到上拉节点(PU)，用于接收上拉信号和第二时钟信号，并根据上拉信号和第二时钟信号从第二输出信号端(OUT(+1))输出第二输出信号；存储子电路(104)，其第一端连接到上拉节点(PU)，第二端连接第二输出子电路(103)，用于存储上拉信号。

Description

移位寄存器单元及其驱动方法、栅极驱动电路、阵列基板、显示装置
相关申请的交叉引用
本公开要求于2017年7月21日递交的中国专利申请第201710601007.2号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及显示技术领域，特别是指一种移位寄存器单元及其驱动方法、栅极驱动电路、阵列基板、显示装置。
背景技术
GOA(Gate Driver On Array，阵列基板上栅极驱动)技术，是一种将栅极驱动电路集成于阵列基板，从而取代栅极驱动芯片以降低功耗和成本的技术。目前的显示面板产业，基于成本因素的考虑，开始采用GOA结构来实现显示面板的驱动，近年来这种趋势越加明显。
GOA结构就是在阵列基板上用若干TFT(薄膜晶体管)和电容制作出栅极驱动电路，本质是一种移位寄存器，其随着时钟信号会依次输出高电平，从而打开相应的栅极线。
发明内容
有鉴于此，本公开的目的在于提出一种移位寄存器单元及其驱动方法、栅极驱动电路、阵列基板和显示装置。
基于上述目的本公开实施例的第一个方面，提供了一种移位寄存器单元，包括：
输入子电路，其第一端连接到输入端，第二端连接到上拉节点，所述输入子电路用于从所述输入端接收输入信号，并将所述输入信号输出到所述上拉节点，并经由所述上拉节点输出上拉信号；
第一输出子电路，其第一端连接到第一输出信号端，第二端连接到第一 时钟信号端，第三端连接到所述上拉节点，所述第一输出子电路用于接收所述上拉信号和第一时钟信号，并根据所述上拉信号和所述第一时钟信号，从所述第一输出信号端输出第一输出信号；
第二输出子电路，其第一端连接到第二输出信号端，第二端连接到第二时钟信号端，第三端连接到所述上拉节点，所述第二输出子电路用于接收所述上拉信号和第二时钟信号，并根据所述上拉信号和所述第二时钟信号，从所述第二输出信号端输出第二输出信号；
存储子电路，其第一端连接到所述上拉节点，第二端连接到所述第二输出子电路，所述存储子电路用于存储所述上拉信号。
在一些实施例中，如前所述的移位寄存器单元还包括：第一复位子电路，其第一端连接到所述上拉节点，第二端连接到第一复位端，第三端连接到复位电压端，所述第一复位子电路用于从所述第一复位端接收第一复位信号，并根据所述第一复位信号对所述上拉节点进行复位。
在一些实施例中，如前所述的移位寄存器单元还包括：第二复位子电路，其第一端连接到所述第一输出子电路，第二端连接到第二复位端，第三端连接到复位电压端，所述第二复位子电路用于从所述第二复位端接收第二复位信号，并根据所述第二复位信号对所述第一输出子电路进行复位。
在一些实施例中，如前所述的移位寄存器单元还包括：第三复位子电路，其第一端连接到所述第二输出子电路，第二端连接到第三复位端，第三端连接到复位电压端，所述第三复位子电路用于从所述第三复位端接收第三复位信号，并根据所述第三复位信号对所述第二输出子电路进行复位。
在一些实施例中，所述输入子电路包括输入晶体管，所述输入晶体管的控制极和第一极连接到所述输入端，并经由所述输入端接收所述输入信号，所述输入晶体管的第二极连接到所述上拉节点。
在一些实施例中，所述第一输出子电路包括第一输出晶体管，所述第一输出的控制极连接到所述上拉节点，所述第一输出晶体管的第一极连接到所述第一时钟信号端并接收所述第一时钟信号，所述第一输出晶体管的第二极连接到所述第一输出信号端并输出所述第一输出信号。
在一些实施例中，所述第二输出子电路包括第二输出晶体管，所述第二 输出晶体管的控制极连接到所述上拉节点，所述第二输出晶体管的第一极连接到第二时钟信号端并接收所述第二时钟信号，所述第二输出晶体管的第二极连接到第二输出信号端并输出所述第二输出信号。
在一些实施例中，所述存储子电路包括电容，所述电容的第一端连接到所述上拉节点，所述电容的第二端连接到所述第二输出信号端。
在一些实施例中，所述第一复位子电路包括第一复位晶体管，所述第一复位晶体管的控制极连接到所述第一复位端并接收所述第一复位信号，所述第一复位晶体管的第一极连接到所述存储子电路，所述第一复位晶体管的第二极连接到复位电压端并接收复位电压信号；和/或，所述第二复位子电路包括第二复位晶体管，所述第二复位晶体管的控制极连接到第二复位端并接收所述第二复位信号，所述第二复位晶体管的第一极连接到所述第一输出信号端，所述第二复位晶体管的第二极连接到所述复位电压端并接收复位电压信号；和/或，所述第三复位子电路包括第三复位晶体管，所述第三复位晶体管的控制极连接到第三复位端并接收所述第三复位信号，所述第三复位晶体管的第一极连接到所述第二输出信号端，所述第三复位晶体管的第二极连接到所述复位电压端并接收复位电压信号。
在一些实施例中，所述输入子电路与所述第一输出子电路之间设置有第一降噪子电路，和/或，所述输入子电路与所述第二输出子电路之间设置有第二降噪子电路。
在一些实施例中，所述第一复位信号和第三复位信号为同一个复位信号。
根据本公开实施例的第二个方面，提供了一种移位寄存器单元的驱动方法，用于驱动如上任一项所述的移位寄存器单元，包括：
当输入信号为导通电平时，经由输入子电路输出上拉信号到第一输出子电路和第二输出子电路；
在第一时段，第一时钟信号处于导通电平，第一输出子电路输出第一输出信号；
在第二时段，第一时钟信号和第二时钟信号处于导通电平，第二输出子电路出第二输出信号，且第一输出子电路继续输出第一输出信号。
在一些实施例中，所述驱动方法还包括：在第三时段，第二复位信号处 于导通电平，第一输出信号完成复位。
在一些实施例中，所述驱动方法还包括：在第四时段，第一复位信号和第三复位信号处于导通电平，上拉信号和第二输出信号完成复位。
在一些实施例中，所述第一复位信号和第三复位信号为同一个复位信号。
根据本公开实施例的第三个方面，提供了一种栅极驱动电路，包括至少两个级联的如上任一项所述的移位寄存器单元。
第N级的移位寄存器单元的输入信号端与第N-1级的移位寄存器单元的第二输出信号端连接，第N级的移位寄存器单元的第一时钟信号端和第二时钟信号端分别接入第一时钟信号和第二时钟信号，第N级的移位寄存器单元的第一复位信号端和第三复位信号端与第N+1级的移位寄存器单元的第二输出信号端连接，第N级的移位寄存器单元的第二复位信号端与第N+1级的移位寄存器单元的第一输出信号端连接。
在一些实施例中，第N+1级的移位寄存器单元的输入信号端与第N级的移位寄存器单元的第二输出信号端连接，第N+1级的移位寄存器单元的第一时钟信号端和第二时钟信号端分别接入第三时钟信号和第四时钟信号，第N+1级的移位寄存器单元的第一复位信号端和第三复位信号端与第N+2级的移位寄存器单元的第二输出信号端连接，第N+1级的移位寄存器单元的第二复位信号端与第N+2级的移位寄存器单元的第一输出信号端连接。
在一些实施例中，所述第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号，依次相差1/4周期。
根据本公开实施例的第四个方面，提供了一种阵列基板，包括如上任一项所述的栅极驱动电路。
根据本公开实施例的第五个方面，提供了一种显示装置，包括如前所述的阵列基板。
附图说明
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全 部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
图1a为现有技术中栅极驱动电路的结构示意图及其输出信号时序图；
图1b为现有技术中移位寄存器单元的结构示意图；
图1c为现有技术中移位寄存器单元的信号时序图；
图2为本公开提供的移位寄存器单元的一个实施例的结构示意图；
图3a为本公开提供的移位寄存器单元的一个实施例的电路结构示意图；
图3b为本公开提供的移位寄存器单元的另一个实施例的电路结构示意图；
图4为本公开提供的移位寄存器单元的一个实施例的信号时序图；
图5a为本公开提供的移位寄存器单元的一个实施例的等效电路图；
图5b为本公开提供的移位寄存器单元的一个实施例的等效电路图；
图5c为本公开提供的移位寄存器单元的一个实施例的等效电路图；
图5d为本公开提供的移位寄存器单元的一个实施例的等效电路图；
图5e为本公开提供的移位寄存器单元的一个实施例的等效电路图；
图6为本公开提供的移位寄存器单元的驱动方法的一个实施例的流程示意图；
图7为本公开提供的栅极驱动电路的一个实施例的结构示意图；以及
图8为本公开提供的显示装置的一个实施例的示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本公开进一步详细说明。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或 者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。图1a中示出的是现有技术中栅极驱动电路的结构示意图以及每一级移位寄存器的输出信号时序图。图1中示出的示例是4CLK预充电栅极驱动电路。
如图1a所示，现有技术的4CLK预充电栅极驱动电路中包括四根时钟CLK信号线：CLK1-CLK4；一根复位电压VSS信号线。图1中的栅极驱动电路从上至下依次为第N-2级移位寄存器单元GOA_N-2、第N-1级移位寄存器单元GOA_N-1、第N级移位寄存器单元GOA_N、第N+1级移位寄存器单元GOA_N+1、第N+2级移位寄存器单元GOA_N+2，其中N是大于2的正整数；各移位寄存器单元的输出端OUT_N-2、OUT_N-1、OUT_N、OUT_N+1、OUT_N+2则依次输出高电平信号。
图1b中示出的是现有技术中移位寄存器单元的结构示意图，其中单个移位寄存器单元中包含4个主工作TFT：T1’、T2’、T3’、T4’及一个电容C’。其中，输入端INPUT的信号经由T1’输入到上拉节点PU’，T3’在PU’的控制下导通，并在CLK3输入信号时将信号输出到输出端OUT_N。晶体管T2’和T4’分别用于对上拉节点PU’和输出端PUT_N进行复位。
根据现有技术的单个移位寄存器单元一般包含五个信号输入输出端子：输入端INPUT、时钟信号端CLK3、复位端RESET、输出端OUT_N、复位电压端VSS。图1c中示出的是现有技术中移位寄存器单元的信号时序图。其中时钟信号端CLK3和复位电压端VSS的接入信号均可以由PCB(电路板)信号源提供，分别为时钟信号和低电平直流信号；输入端INPUT、复位端RESET、输出端OUT_N的信号均为移位寄存器单元之间的级联信号，更重要的是，输出端OUT_N的信号也作为栅极驱动信号。
对于现有技术的4CLK预充电栅极驱动电路结构，第N级的移位寄存器单元的输入端INPUT的信号是由第N-2级的输出端OUT_N-2的信号提供，第N级的移位寄存器单元的复位端RESET的信号是由第N+2级的OUT_N+2的信号提供；同时第N级的输出端OUT_N的信号也作为第N-2级的复位端RESET的信号及第N+2级的输入端INPUT的信号。此外，图1c中还示出了上拉节点PU’处的上拉信号时序。
由此可见，现有技术的栅极驱动电路，每个栅极驱动信号都需需要一个移位寄存器单元来提供。这使得栅极驱动电路整体占用空间较大，不利于更小尺寸的电子设备(例如，窄边框的电子设备)的实现。
并且，本公开的发明人在实现本公开时，发现现有技术的GOA结构至少具有以下问题：
在高分辨率的GOA产品布局时，由于垂直方向(显示面板的短边框)的尺寸较小，往往水平方向(显示面板的长边框)就需要更大尺寸，即面板的边框宽度会增大。
因此，本公开实施例的第一个方面，提供了一种移位寄存器单元的一个实施例，可以实现窄边框。
图2中示出的是本公开提供的移位寄存器单元的一个实施例的结构示意图。
所述移位寄存器单元100，包括：
输入子电路101，其第一端连接到输入信号端，第二端连接到上拉节点，输入子电路101用于从输入端接收输入信号，并将输入信号输出到所述上拉节点，并经由所述上拉节点输出上拉信号。例如，如图2所示，输入子电路101与输入信号端INPUT连接，输入信号经由输入子电路101输出到上拉节点PU。
第一输出子电路102，与输入子电路101连接，用于接收上拉信号和第一时钟信号，并根据所述上拉信号和第一时钟信号，输出第一输出信号。例如，如图2所示，所述第一输出子电路102的第一端连接到第一时钟信号端CLK1，第二端连接到第一输出信号端OUT。第一时钟信号经第一时钟信号端CLK1输入第一输出子电路102，第一输出信号端OUT与相应的TFT的栅极扫描线(例如第N行扫描线)连接，用于向相应TFT的栅极输出所述第一输出信号作为相应的扫描信号。
第二输出子电路103，与输入子电路101连接，用于接收上拉信号和第二时钟信号，并根据上拉信号和第二时钟信号输出第二输出信号。例如，如图2所示，第二输出子电路103的第一端连接到第二时钟信号端CLK2，第二端连接到第二输出信号端OUT(+1)。第二时钟信号经由第二时钟信号端CLK2输入到第二输出子电路103，第二输出信号端OUT(+1)与相应的TFT 的栅极扫描线(例如第N+1行扫描线)连接，用于向相应TFT的栅极输出所述第二输出信号作为相应的扫描信号。
存储子电路104，分别与输入子电路101和第二输出子电路103连接，用于存储所述上拉信号。如图2所示，例如，存储子电路104的第一端连接上拉节点PU，第二端连接到第二输出子电路103。
在一些实施例中，移位寄存器单元100还包括：
第一复位子电路105，与存储子电路104连接，用于接收第一复位信号，并根据第一复位信号对上拉节点PU进行复位。例如，如图2所示，第一复位子电路105的第一端与第一复位信号端RESET1连接，第二端连接到上拉节点PU，第三端连接到复位电压端VSS。其中，第一复位子电路105从第一复位端RESET1接收第一复位信号，并在第一复位信号的控制下对上拉节点PU进行复位。
第二复位子电路106，与第一输出子电路102连接，用于接收第二复位信号，并根据第二复位信号对第一输出信号进行复位。例如，如图2所示，第二复位子电路106的第一端与第二复位信号端RESET2连接，第二端连接到第一输出子电路，第三端连接到复位电压端VSS。其中，第二复位子电路106从第二复位端RESET2接收第二复位信号，并在第二复位信号的控制下对第一输出子电路进行复位。
第三复位子电路107，与第二输出子电路103连接，用于接收第三复位信号，并根据第三复位信号对第二输出信号进行复位。例如，如图2所示，第三复位子电路107的第一端与第三复位信号端RESET3连接，第二端连接到第二输出子电路，第三端连接到复位电压端VSS。其中，第三复位子电路107从第三复位端RESET3接收第三复位信号，并在第三复位信号的控制下对第二输出子电路进行复位。
从上述实施例可以看出，根据本公开实施例提供的移位寄存器单元，通过在原有的移位寄存器单元电路中仅增加设置一组输出子电路(如第二输出子电路和第三复位子电路)，使得一个移位寄存器单元可以输出两个相邻的输出信号，从而大大缩减了栅极驱动电路所需的TFT数目，减小布局所需空间，有利于实现更小尺寸的产品的设计。
例如，将上述实施例中的移位寄存器单元应用到GOA产品中，能够大 大缩减GOA产品需要的TFT数目，减小布局所需空间，有利于实现窄边框GOA产品的设计。
图3a示出了根据本公开实施例的一种移位寄存器单元的电路结构图。
在一些可选实施方式中，输入子电路101包括输入晶体管T1，输入晶体管T1的控制极和第一极连接到输入端INPUT，并从输入端接收输入信号。输入晶体管T1的第二极连接到上拉节点PU，并通过上拉节点PU分别与第一输出子电路102和第二输出子电路103连接。这样，通过采用输入晶体管T1实现输入子电路101的功能，能实现控制将输入信号输入到上拉节点PU。
在一些可选实施方式中，第一输出子电路102包括第一输出晶体管T2，其中，第一输出晶体管T2的控制极与输入子电路101连接，第一输出晶体管T2的第一极接收第一时钟信号，第一输出晶体管T2的第二极输出第一输出信号。例如，第一输出晶体管T2的第一极与第一时钟信号端CLK1连接，用于接收所述第一时钟信号。第一输出晶体管T2的第二极与第一输出信号端OUT连接，用于从第一输出信号端OUT输出第一输出信号。第一输出晶体管T2的控制极连接到上拉节点PU，并在上拉节点PU的控制下将第一时钟信号作为第一输出信号输出到第一输出端。这样，采用第一输出晶体管T2实现第一输出子电路102，能实现对第一输出信号的控制。
在一些可选实施方式中，第二输出子电路103包括第二输出晶体管T3。第二输出晶体管T3的控制极与输入子电路101连接，第二输出晶体管T3的第一极接收第二时钟信号，第二输出晶体管T3的第二极输出第二输出信号。例如，第二输出晶体管T3的第一极与第二时钟信号端CLK2连接，用于接收第二时钟信号。第二输出晶体管T3的第二极与第二输出信号端OUT(+1)连接，用于从第二输出信号端OUT(+1)输出所述第二输出信号。第二输出晶体管T3的控制极连接到上拉节点PU，并在上拉节点PU的控制下将第二时钟信号作为第二输出信号输出到第二输出端。这样，采用第二输出晶体管T3实现第二输出子电路，能实现对第二输出信号的控制。
在一些可选实施方式中，存储子电路104包括电容C，电容C的第一端与输入子电路101连接，电容C的第二端与第二输出子电路103连接。例如，如图3a中所示出的，电容C的第一端与上拉节点PU相连，第二端与第二输出信号端OUT(+1)连接。电容C用于存储上拉信号。例如，当输入西电路101 将输入信号输入到上拉节点PU时，由于上拉节点PU连接电容C，因此输入信号可以对电容C进行充电，并通过电容C保持上拉节点PU处的电位。这样，采用电容C实现存储子电路104，能实现上拉信号的抬升和保持。
在一些可选实施方式中，第一复位子电路105包括第一复位晶体管T4。第一复位晶体管T4的控制极接收第一复位信号，第一复位晶体管T4的第一极与存储子电路104连接，第一复位晶体管T4的第二极接收复位电压信号。例如，第一复位晶体管T4的控制极与第一复位信号端RESET1连接，用于接收第一复位信号，第一复位晶体管T4的第一极与上拉节点PU连接，第一复位晶体管T4的第二极与复位电压端VSS连接，用于接收复位电压信号(可选的，所述复位电压信号为低电平直流信号，由PCB信号源提供)。这样，采用第一复位晶体管T4实现第一复位子电路105，能实现通过第一复位信号控制上拉节点PU的复位。
在一些可选实施方式中，第二复位子电路106包括第二复位晶体管T5，第二复位晶体管T5的控制极接收所述第二复位信号，第二复位晶体管T5的第一极与第一输出子电路102连接，第二复位晶体管T5的第二极接收复位电压信号。例如，第二复位晶体管T5的控制极与第二复位信号端RESET2连接，用于接收第二复位信号。第二复位晶体管T5的第一极与第一输出信号端OUT连接。第二复位晶体管T5的第二极与复位电压端VSS连接，用于接收复位电压信号(可选的，所述复位电压信号为低电平直流信号，由PCB信号源提供)。这样，采用第二复位晶体管T5实现第二复位子电路106，能实现通过第二复位信号控制第一输出信号端OUT的复位。
在一些可选实施方式中，第三复位子电路107包括第三复位晶体管T6，第三复位晶体管T6的控制极接收第三复位信号，第三复位晶体管T6的第一极与第二输出子电路103连接，第三复位晶体管T6的第二极接收复位电压信号。例如，第三复位晶体管T6的控制极与第三复位信号端RESET3连接，用于接收第三复位信号，第三复位晶体管T6的第一极与第二输出信号端OUT(+1)连接，第三复位晶体管T6的第二极与复位电压端VSS连接，用于接收复位电压信号(可选的，所述复位电压信号为低电平直流信号，由PCB信号源提供)。这样，采用第三复位晶体管T6实现第三复位子电路107，能实现通过第三复位信号控制第二输出信号端OUT(+1)的复位。
如图3a所示，所述移位寄存器单元包含九个输入/输出端子：输入信号端INPUT、复位电压端VSS、第一时钟信号端CLK1、第二时钟信号端CLK2、第一输出信号端OUT、第二输出信号端OUT(+1)、第一复位信号端RESET1、第二复位信号端RESET2和第三复位信号端RESET3。其中，第一时钟信号端CLK1、第二时钟信号端CLK2和复位电压端VSS的信号分别为时钟信号和低电平直流信号，上述信号均可由PCB信号源提供；输入信号端INPUT、第一输出信号端OUT、第二输出信号端OUT(+1)、第一复位信号端RESET1、第二复位信号端RESET2和第三复位信号端RESET3为级联的移位寄存器单元之间的级联信号，同时第一输出信号端OUT和第二输出信号端OUT(+1)也分别是相邻两行栅极的栅极驱动信号。
在一些可选实施方式中，参考图4，上述第一复位信号和第三复位信号是同一个复位信号。例如，输入第一复位信号的第一复位信号端RESET1和输入第三复位信号的第三复位信号端RESET3连接的是同一个复位信号的复位信号端。这样，通过共用复位信号，能够减少移位寄存器单元中使用的器件数量，简化移位寄存器单元的结构设计。
如图3a所示，所述移位寄存器单元共有6个TFT和一个电容C，其中输入晶体管T1、第一输出晶体管T2、第一复位晶体管T4和第二复位晶体管T5可以使用在现有的移位寄存器中晶体管相似的规格。此外，第二输出晶体管T3的规格可与第一输出晶体管T2相同，第三复位晶体管T6的规格可与第二复位晶体管T5相同，电容C的尺寸大小可与现有的移位寄存器单元中的电容C’相同(参见附图1b)。
利用本公开实施例提供的移位寄存器单元，可以减少栅极驱动电路所需的TFT数目，减小布局所需空间，有利于实现更小尺寸的产品的设计。
图3b示出了根据本公开实施例的一种移位寄存器单元的电路结构图。图3b中示出的输入子电路101、第一输出子电路102、第二输出子电路103、存储子电路104、第一复位子电路105、第二复位子电路106以及第三复位子电路107的结构与图3a中示出的结构相同，在此不再赘述。
在一些可选实施方式中，输入子电路101与第一输出子电路102之间可以设置有第一降噪子电路，和/或，输入子电路101与第二输出子电路103之间可以设置有第二降噪子电路。例如，如图3b中所示出的，通过设置一个降 噪子电路108同时实现上述第一降噪子电路和第二降噪子电路的功能。通过设置降噪子电路能够更好地实现PU节点处的上拉信号的降噪，保证栅极驱动电路的电路信赖性。可选的，可参考现有技术中的降噪电路设计降噪子电路。降噪子电路的电路结构中可包含若干TFT，这里不对降噪电路的内部结构加以限制。
在一些可选实施方式中，参考图4，上述第一复位信号和第三复位信号是同一个复位信号。例如，输入第一复位信号的第一复位信号端RESET1和输入第三复位信号的第三复位信号端RESET3连接的是同一个复位信号的复位信号端。这样，通过共用复位信号，能够减少移位寄存器单元中使用的器件数量，简化移位寄存器单元的结构设计。
图4图示了根据本公开提供的移位寄存器单元的一个实施例中各输入/输出端的信号时序示意图，其中。第一时钟信号端CLK1和第二时钟信号端CLK2接入的时钟信号的高电平分别持续2个单位的时间。现在结合图3a、图3b和4阐述根据本公开的原理的该移位寄存器单元的工作原理。
在如图4所示的t1时段，输入信号端INPUT接收高电平的输入信号，输入子电路101将输入信号输入到上拉节点PU，并将PU点的电位拉高。例如，如图3a中所示出的，输入晶体管T1的控制端和第一极均连接到输入端INPUT，因此，输入晶体管T1将在输入信号的控制下导通，并将输入信号输入到上拉节点PU。上拉节点PU点的高电平将第一输出晶体管T2与第二输出晶体管T3打开。
图5a示出了t1时段期间移位寄存器的等效电路图。在t1时段期间，输入晶体管T1、第一输出晶体管T2、第二输出晶体管T3是导通的。第一复位晶体管T4、第二复位晶体管T5、第三复位晶体管T6是关断的。
回到图4，随后1个单位的时间(t2时段)，第一时钟信号端CLK1接入的第一时钟信号的高电平来临，通过第一输出晶体管T2给第一输出信号端OUT充电，第一输出信号端OUT开始输出高电平。
图5b示出了t2时段期间移位寄存器的等效电路图。在t2时段期间，输入晶体管T1、第一输出晶体管T2、第二输出晶体管T3是导通的。第一复位晶体管T4、第二复位晶体管T5、第三复位晶体管T6是关断的。第一输出信号端OUT输出高电平。
回到图4，随后1个单位的时间(t3时段)，输入端INPUT不再输入高电平的输入信号，输入晶体管T1关断。第二时钟信号端CLK2接入的第二时钟信号的高电位来临，通过第二输出晶体管T3给第二输出信号端OUT(+1)充电，第二输出信号端OUT(+1)开始输出高电平，此时，由于电容C的自举作用，PU点高电位会被抬高至将近原来的2倍，第一输出信号端OUT也将会继续输出1个单位时间的高电平。
图5c示出了t3时段期间移位寄存器的等效电路图。在t3时段期间，输入晶体管T1是关断的。第一输出晶体管T2、第二输出晶体管T3是导通的。第一复位晶体管T4、第二复位晶体管T5、第三复位晶体管T6是关断的。第一输出信号端OUT和第二输出信号端OUT(+1)输出高电平。
回到图4，第一输出信号端OUT总共输出2个单位时间的高电平后，在t4时段，第二复位信号端RESET2的第二复位信号的高电平来临，第二复位晶体管T5在第二复位信号的控制下导通，并根据复位电压端VSS的低电平复位信号对第一输出信号段OUT进行复位，第一输出信号端OUT输出的高电平结束。
图5d示出了t4时段期间移位寄存器的等效电路图。在t4时段期间，输入晶体管T1是关断的。第一输出晶体管T2、第二输出晶体管T3是导通的。第一复位晶体管T4、第三复位晶体管T6是关断的。第二复位晶体管T5是导通的。此时，第二输出信号端OUT(+1)输出高电平，第一输出信号端OUT在第二复位信号的控制下被复位。
回到图4，随后1个单位的时间(t5时段)，第三复位信号端RESET3的第三复位信号的高电平来临，第三复位晶体管T6在第三复位信号的控制下利用复位电压端VSS接入的低电平复位电压信号对第二输出信号端进行复位。同时第一复位信号端RESET1的第一复位信号的高电平来临，第一复位晶体管T4在第一复位信号的控制下利用复位电压端VSS接入的低电平复位电压信号对上拉节点PU进行复位。
从上述实施例可以看出，根据本公开实施例提供的移位寄存器单元，通过在原有的移位寄存器单元电路中仅增加设置第二输出晶体管和第三复位晶体管，使得一个移位寄存器单元可以输出两个相邻的输出信号，分别用于驱动相邻行的栅极，从而大大缩减了栅极驱动电路所需的TFT数目，减小布局 所需空间，有利于实现更小尺寸的产品的设计。
需要说明的是，上述各实施例中的晶体管可以是任何目前或将来可应用于移位寄存器的晶体管的类型，例如，多晶硅薄膜晶体管、非晶硅薄膜晶体管、氧化物薄膜晶体管以及有机薄膜晶体管中的一种或多种。在本公开中不对使用的晶体管类型加以限制。在本实施例中涉及到的“控制极”具体可以是指晶体管的栅极或基极，“第一极”具体可以是指晶体管的源极或发射极，相应的“第二极”具体可以是指晶体管的漏极或集电极。当然，本领域的技术人员应该知晓的是，该“第一极”与“第二极”可进行互换。
此外，上述实施例中输入晶体管T1、第一输出晶体管T2、第二输出晶体管T3、第一复位晶体管T4、第二复位晶体管T5和第三复位晶体管T6均为N型晶体管，为本实施例中便于实施的一种优选方案，其不会对本公开的技术方案产生限制。本领域技术人员应该知晓的是，简单的对各晶体管的类型(N型或P型)进行改变，以及对各电源端和控制信号线输出电压的正负极性进行改变，以实现与本实施例中对各晶体管执行相同的导通或截止操作的技术方案，其均属于本申请保护范围。具体情况，此处不再一一举例说明。
图6为本公开提供的移位寄存器单元的驱动方法的一个实施例的流程示意图。
如图6所示，结合参照附图4，所述移位寄存器单元的驱动方法，用于驱动前述实施例中的移位寄存器单元，包括：
步骤201：当输入信号为高电平时，经由输入子电路101输出上拉信号到第一输出子电路102和第二输出子电路103；
步骤202：在第一时段，第一时钟信号处于高电平，第一输出子电路102输出第一输出信号；
步骤203：在第二时段，第一时钟信号和第二时钟信号处于高电平，第二输出子电路103输出第二输出信号，且第一输出子电路102继续输出第一输出信号；
步骤204：在第三时段，第二复位信号处于高电平，第一输出信号完成复位；
步骤205：在第四时段，第一复位信号和第三复位信号处于高电平，上拉信号和第二输出信号完成复位。
从上述实施例可以看出，本公开实施例提供的移位寄存器单元的驱动方法，在移位寄存器单元的电路进行改进的前提下，通过对移动寄存器单元的各输入端子的信号设计，使得一个移位寄存器单元可以输出两个相邻的输出信号，分别用于驱动相邻行的栅极，从而大大缩减了栅极驱动电路所需的TFT数目，减小布局所需空间，有利于实现更小尺寸的产品的设计。
可选的，所述第一复位信号和第三复位信号为同一个复位信号，通过共用复位信号，能够减少器件，简化移位寄存器单元的结构设计。
图7为本公开提供的栅极驱动电路的一个实施例的结构示意图。
所述栅极驱动电路，包括至少两个级联的如前所述的移位寄存器单元的任一实施例。
第N级的移位寄存器单元GOA_N,N+1的输入信号端INPUT与第N-1级的移位寄存器单元GOA_N-2,N-1的第二输出信号端OUT(+1)连接，第N级的移位寄存器单元GOA_N,N+1的第一时钟信号端CLK和第二时钟信号端CLK(+1)分别接入第一时钟信号CLK1和第二时钟信号CLK2，第N级的移位寄存器单元GOA_N,N+1的第一复位信号端和第三复位信号端RESET(+1)与第N+1级的移位寄存器单元GOA_N+2,N+3的第二输出信号端OUT(+1)连接，第N级的移位寄存器单元GOA_N,N+1的第二复位信号端RESET与第N+1级的移位寄存器单元GOA_N+2,N+3的第一输出信号端OUT连接。
第N+1级的移位寄存器单元GOA_N+2,N+3的输入信号端INPUT与第N级的移位寄存器单元GOA_N,N+1的第二输出信号端OUT(+1)连接，第N+1级的移位寄存器单元GOA_N+2,N+3的第一时钟信号端CLK和第二时钟信号端CLK(+1)分别接入第三时钟信号CLK3和第四时钟信号CLK4，第N+1级的移位寄存器单元GOA_N+2,N+3的第一复位信号端和第三复位信号端RESET(+1)与第N+2级的移位寄存器单元(未示出)的第二输出信号端OUT(+1)连接，第N+1级的移位寄存器单元的第二复位信号端RESET与第N+2级的移位寄存器单元(未示出)的第一输出信号端OUT连接。
其中，所述第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号，依次相差1/4周期。同时，每一级的移位寄存器单元的信号时序都可参照参考附图4中的时序。
从上述实施例可以看出，本公开实施例提供的栅极驱动电路，通过时钟 信号线和级联的移位寄存器单元的信号端的连接设计，使得一个移位寄存器单元可以输出两个相邻的输出信号，从而大大缩减GOA产品需要的TFT数目，减小布局所需空间，有利于实现更小尺寸的GOA产品的设计。
图8为本公开提供的显示装置的一个实施例的示意图。
图8中示出的显示装置可以包括阵列基板，其中阵列基板可以包括如前任一实施例所述的栅极驱动电路。
需要说明的是，本实施例中的显示装置可以为：电子纸、手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
从上述实施例可以看出，根据本公开提供的阵列基板和显示装置，通过在原有的移位寄存器单元电路中仅增加设置第二输出子电路和第三复位子电路，使得一个移位寄存器单元可以输出两个相邻的输出信号，从而大大缩减了栅极驱动电路所需的TFT数目，减小布局所需空间，有利于实现更小尺寸的产品的设计。
下面简要对比一下本公开实施例与现有技术的区别，以明晰本公开所能带来的技术效果。
假设现有的移位寄存器单元包含M(M＞4，常见值9、10、12、16等)个TFT，一个电容C，那么一个超高分辨率显示器+单栅极的栅极驱动电路结构中通常要包含2160*M个TFT和2016个电容。
在采用本公开实施例提供的栅极驱动电路之后，针对移位寄存器单元内部结构，不对降噪结构做变更，只需要对电路结构做调整，同时在一个移位寄存器单元内增加两个TFT，就可以实现输出两个输出信号，即：原有移位寄存器单元结构输出两个相邻的栅极信号需要2*M个TFT和2个电容C，本公开的移位寄存器单元结构只需要M+2个TFT和一个电容C即可实现，这样，超高分辨率显示器+单栅极的栅极驱动电路结构中则只需要包含1080*(M+2)个TFT和1080个电容。
通过对比可以看出，采用本公开实施例提供的移位寄存器单元、栅极驱动电路以及相应的包含该栅极驱动电路的阵列基板和显示装置，能够极大减少TFT的个数且电容数量能够减少一半，极大节省了栅极驱动电路的布线空间，有利于实现更小尺寸的产品设计。
所属领域的普通技术人员应当理解：以上任何实施例的讨论仅为示例性的，并非旨在暗示本公开的范围(包括权利要求)被限于这些例子；在本公开的思路下，以上实施例或者不同实施例中的技术特征之间也可以进行组合，步骤可以以任意顺序实现，并存在如上所述的本公开的不同方面的许多其它变化，为了简明它们没有在细节中提供。
另外，为简化说明和讨论，并且为了不会使本公开难以理解，在所提供的附图中可以示出或可以不示出与集成电路(IC)芯片和其它部件的公知的电源/接地连接。此外，可以以框图的形式示出装置，以便避免使本公开难以理解，并且这也考虑了以下事实，即关于这些框图装置的实施方式的细节是高度取决于将要实施本公开的平台的(即，这些细节应当完全处于本领域技术人员的理解范围内)。在阐述了具体细节(例如，电路)以描述本公开的示例性实施例的情况下，对本领域技术人员来说显而易见的是，可以在没有这些具体细节的情况下或者这些具体细节有变化的情况下实施本公开。因此，这些描述应被认为是说明性的而不是限制性的。
尽管已经结合了本公开的具体实施例对本公开进行了描述，但是根据前面的描述，这些实施例的很多替换、修改和变型对本领域普通技术人员来说将是显而易见的。例如，其它存储器架构(例如，动态RAM(DRAM))可以使用所讨论的实施例。
所属领域的技术人员可以清楚地了解到本发明可借助软件加必需的通用硬件的方式来实现，当然也可以通过专用的硬件，但很多情况下前者可能是优选的实施方式。基于这样的理解，本发明的技术方案本质上以软件、硬件、固件或它们的任意组合的方式体现，该计算机软件产品存储在可读取的存储介质中，如磁性存储介质(例如硬盘)或电子存储介质(例如ROM、闪存)等，包括若干指令用以使得一台计算设备(可以是计算机、服务器或者网络设备等)执行本发明各个实施例所述的方法。
本公开的实施例旨在涵盖落入所附权利要求的宽泛范围之内的所有这样的替换、修改和变型。因此，凡在本公开的精神和原则之内，所做的任何省略、修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (20)

  1. 一种移位寄存器单元，包括：
    输入子电路，其第一端连接到输入端，第二端连接到上拉节点，所述输入子电路用于从所述输入端接收输入信号，并将所述输入信号输出到所述上拉节点，并经由所述上拉节点输出上拉信号；
    第一输出子电路，其第一端连接到第一输出信号端，第二端连接到第一时钟信号端，第三端连接到所述上拉节点，所述第一输出子电路用于接收所述上拉信号和第一时钟信号，并根据所述上拉信号和所述第一时钟信号，从所述第一输出信号端输出第一输出信号；
    第二输出子电路，其第一端连接到第二输出信号端，第二端连接到第二时钟信号端，第三端连接到所述上拉节点，所述第二输出子电路用于接收所述上拉信号和第二时钟信号，并根据所述上拉信号和所述第二时钟信号，从所述第二输出信号端输出第二输出信号；
    存储子电路，其第一端连接到所述上拉节点，第二端连接到所述第二输出子电路，所述存储子电路用于存储所述上拉信号。
  2. 根据权利要求1所述的移位寄存器单元，还包括：
    第一复位子电路，其第一端连接到所述上拉节点，第二端连接到第一复位端，第三端连接到复位电压端，所述第一复位子电路用于从所述第一复位端接收第一复位信号，并根据所述第一复位信号对所述上拉节点进行复位。
  3. 根据权利要求2所述的移位寄存器单元，还包括：
    第二复位子电路，其第一端连接到所述第一输出子电路，第二端连接到第二复位端，第三端连接到复位电压端，所述第二复位子电路用于从所述第二复位端接收第二复位信号，并根据所述第二复位信号对所述第一输出子电路进行复位。
  4. 根据权利要求3所述的移位寄存器单元，还包括：
    第三复位子电路，其第一端连接到所述第二输出子电路，第二端连接到第三复位端，第三端连接到复位电压端，所述第三复位子电路用于从所述第三复位端接收第三复位信号，并根据所述第三复位信号对所述第二输出子电 路进行复位。
  5. 根据权利要求1-4中任一项所述的移位寄存器单元，其中，所述输入子电路包括输入晶体管，所述输入晶体管的控制极和第一极连接到所述输入端，并经由所述输入端接收所述输入信号，所述输入晶体管的第二极连接到所述上拉节点。
  6. 根据权利要求1-5中任一项所述的移位寄存器单元，其中，所述第一输出子电路包括第一输出晶体管，所述第一输出的控制极连接到所述上拉节点，所述第一输出晶体管的第一极连接到所述第一时钟信号端并接收所述第一时钟信号，所述第一输出晶体管的第二极连接到所述第一输出信号端并输出所述第一输出信号。
  7. 根据权利要求1-6中任一项所述的移位寄存器单元，其中，所述第二输出子电路包括第二输出晶体管，所述第二输出晶体管的控制极连接到所述上拉节点，所述第二输出晶体管的第一极连接到第二时钟信号端并接收所述第二时钟信号，所述第二输出晶体管的第二极连接到第二输出信号端并输出所述第二输出信号。
  8. 根据权利要求1-7中任一项所述的移位寄存器单元，其中，所述存储子电路包括电容，所述电容的第一端连接到所述上拉节点，所述电容的第二端连接到所述第二输出信号端。
  9. 根据权利要求4-8中任一项所述的移位寄存器单元，其中，所述第一复位子电路包括第一复位晶体管，所述第一复位晶体管的控制极连接到所述第一复位端并接收所述第一复位信号，所述第一复位晶体管的第一极连接到所述存储子电路，所述第一复位晶体管的第二极连接到复位电压端并接收复位电压信号；
    和/或，
    所述第二复位子电路包括第二复位晶体管，所述第二复位晶体管的控制极连接到第二复位端并接收所述第二复位信号，所述第二复位晶体管的第一极连接到所述第一输出信号端，所述第二复位晶体管的第二极连接到所述复位电压端并接收复位电压信号；
    和/或，
    所述第三复位子电路包括第三复位晶体管，所述第三复位晶体管的控制极连接到第三复位端并接收所述第三复位信号，所述第三复位晶体管的第一极连接到所述第二输出信号端，所述第三复位晶体管的第二极连接到所述复位电压端并接收复位电压信号。
  10. 根据权利要求1-9中任一项所述的移位寄存器单元，其中，所述输入子电路与所述第一输出子电路之间设置有第一降噪子电路，和/或，所述输入子电路与所述第二输出子电路之间设置有第二降噪子电路。
  11. 根据权利要求4-10中任一项所述的移位寄存器单元，其中，所述第一复位信号和第三复位信号为同一个复位信号。
  12. 一种用于驱动如权利要求1-11中任一项所述的移位寄存器单元的驱动方法，包括：
    当输入信号为导通电平时，经由输入子电路输出上拉信号到第一输出子电路和第二输出子电路；
    在第一时段，第一时钟信号处于导通电平，第一输出子电路输出第一输出信号；
    在第二时段，第一时钟信号和第二时钟信号处于导通电平，第二输出子电路输出第二输出信号，且第一输出子电路继续输出第一输出信号。
  13. 根据权利要求12所述的驱动方法，还包括：
    在第三时段，第二复位信号处于导通电平，第一输出信号完成复位。
  14. 根据权利要求13所述的驱动方法，还包括：
    在第四时段，第一复位信号和第三复位信号处于导通电平，上拉信号和第二输出信号完成复位。
  15. 根据权利要求14所述的驱动方法，其中，所述第一复位信号和第三复位信号为同一个复位信号。
  16. 一种栅极驱动电路，包括至少两个级联的如权利要求1-11任一项所述的移位寄存器单元；
    第N级的移位寄存器单元的输入信号端与第N-1级的移位寄存器单元的第二输出信号端连接，第N级的移位寄存器单元的第一时钟信号端和第二时钟信号端分别接入第一时钟信号和第二时钟信号，第N级的移位寄存器单元 的第一复位信号端和第三复位信号端与第N+1级的移位寄存器单元的第二输出信号端连接，第N级的移位寄存器单元的第二复位信号端与第N+1级的移位寄存器单元的第一输出信号端连接。
  17. 根据权利要求16所述的栅极驱动电路，其中，第N+1级的移位寄存器单元的输入信号端与第N级的移位寄存器单元的第二输出信号端连接，第N+1级的移位寄存器单元的第一时钟信号端和第二时钟信号端分别接入第三时钟信号和第四时钟信号，第N+1级的移位寄存器单元的第一复位信号端和第三复位信号端与第N+2级的移位寄存器单元的第二输出信号端连接，第N+1级的移位寄存器单元的第二复位信号端与第N+2级的移位寄存器单元的第一输出信号端连接。
  18. 根据权利要求17所述的栅极驱动电路，其中，所述第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号，依次相差1/4周期。
  19. 一种阵列基板，包括如权利要求16-18中任一项所述的栅极驱动电路。
  20. 一种显示装置，包括如权利要求19所述阵列基板。
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