WO2019007347A1 - 沟槽隔离结构及其制造方法 - Google Patents

沟槽隔离结构及其制造方法 Download PDF

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WO2019007347A1
WO2019007347A1 PCT/CN2018/094369 CN2018094369W WO2019007347A1 WO 2019007347 A1 WO2019007347 A1 WO 2019007347A1 CN 2018094369 W CN2018094369 W CN 2018094369W WO 2019007347 A1 WO2019007347 A1 WO 2019007347A1
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trench
silicon oxide
manufacturing
forming
nitrogen
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French (fr)
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祁树坤
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/114—PN junction isolations
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/61—Formation of materials, e.g. in the shape of layers or pillars of insulating materials using masks
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
    • H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6322—Formation by thermal treatments
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
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    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
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    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
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    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/06—Planarisation of inorganic insulating materials
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0145—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0145—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape
    • H10W10/0147—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape the shapes being altered by a local oxidation of silicon process, e.g. trench corner rounding by LOCOS
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0148—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising introducing impurities in side walls or bottom walls of trenches, e.g. for forming channel stoppers
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    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
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    • H10W10/031—Manufacture or treatment of isolation regions comprising PN junctions
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    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
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    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
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    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/30—Isolation regions comprising PN junctions

Definitions

  • the present application relates to the field of semiconductor manufacturing, and in particular to a method for fabricating a trench isolation structure, and to a trench isolation structure.
  • the high-voltage power field also derives different types such as LDMOS (transverse double-diffused metal oxide semiconductor field effect transistor), LIGBT (transverse insulated gate bipolar transistor), and power-DMOS (power-diffused metal oxide semiconductor field effect transistor). Voltage levels, device structures with different structures, and withstand voltages from tens of volts to hundreds of volts, so various field structures such as field plates and field rings and RESURF (surface-reduction electric field) technology have been developed to assist these high-voltage powers.
  • the device guarantees a low specific on-resistance, which places high demands on device isolation techniques.
  • DTI deep trench isolation
  • the performance of high-voltage power devices is quite dependent on isolation technology, especially when avalanche breakdown of devices forms a large number of hot electrons/holes, some of which overcome the Si/SiO 2 barrier into the oxide layer of DTI, and the oxide layer in DTI/
  • the trap at the polysilicon interface (the surface density of the trap is approximately E+10/cm 2 ) is captured and is affected by the electric field drift in the polysilicon, causing cross-talk between the devices, which easily leads to isolation failure.
  • the pressure resistance is reduced. Therefore, continuous improvement of the process technology of deep trench isolation is one of the focuses in the field of high voltage power devices.
  • a trench isolation structure and a method of fabricating the same are provided.
  • a method for fabricating a trench isolation structure includes: forming a first trench having a width and a narrow width on a surface of the wafer; filling the first trench with silicon oxide by deposition; and removing the first trench by etching a portion of the surface of the silicon oxide in the trench; a silicon oxide corner structure formed at a corner of the top of the first trench by thermal oxidation, the silicon oxide corner structure being gradually degraded from the corner and located inside the first trench a thickened structure; depositing a nitrogen-containing compound on the surface of the wafer to cover the surface of the silicon oxide in the first trench and the surface of the silicon oxide corner structure; dry etching the nitrogen-containing compound to form the first trench The nitrogen-containing compound on the surface of the silicon oxide in the trench is removed, and the surface of the silicon oxide corner structure forms a sidewall of the nitrogen-containing compound extending in the trench; and the sidewall of the nitrogen-containing compound remains as a mask, and continues to be engraved downward Etching the silicon oxide and the wafer to form a second trench
  • a trench isolation structure comprising a trench, silicon oxide filled in the trench, and polysilicon in the trench surrounded by the silicon oxide, wherein the trench includes an upper width A narrow neck finish and a body structure extending downwardly from the finish structure.
  • FIG. 1 is a flow chart showing a method of fabricating a trench isolation structure in an embodiment
  • FIGS. 2 to 7 are cross-sectional views showing a device manufactured by a manufacturing method using a trench isolation structure in an embodiment.
  • the vocabulary of the semiconductor field used herein is a technical vocabulary commonly used by those skilled in the art, for example, for P-type and N-type impurities, to distinguish the doping concentration, the simple P+ type represents a heavily doped concentration of the P-type, and the P-type represents P type with doping concentration, P-type represents P type with light doping concentration, N+ type represents N type with heavy doping concentration, N type represents N type with medium doping concentration, and N type represents light doping concentration N type.
  • FIG. 1 is a flow chart of a method of fabricating a trench isolation structure in an embodiment, including the following steps:
  • the first trench (shallow trench) having a narrow width and a narrow width may be etched on the surface of the wafer (in this embodiment, a silicon wafer) by a process known in the art.
  • a silicon nitride film may be formed on the surface of the wafer before etching to form the first trench, and then an etched window is patterned on the silicon nitride film by photoresist, and then etched.
  • the window is inscribed through the silicon nitride film to form a first trench, and after the etching is completed, a silicon nitride layer is formed around the top of the first trench.
  • the etching of the first trench is performed by using CHCl 3 and/or CH 2 Cl 2 as an etchant for dry etching, and in other embodiments, other trenches known in the art may be used.
  • the etching process is performed by etching.
  • the upper portion of the first trench has a wider width such that the resulting trench isolation structure can reduce the likelihood of leakage due to high voltage traces over the trench isolation structure relative to the narrow trench.
  • the first trench has a depth of 1 to 2 microns.
  • a low doping concentration epitaxial layer is epitaxially grown on a highly doped concentration substrate by an epitaxial process, and the trench etched in step S110 is formed in the epitaxial layer.
  • step S120 is a deposition of silicon oxide by a high density plasma chemical vapor deposition (HDPCVD) process to obtain a better morphology.
  • a silicon oxide layer may also be deposited by other deposition processes known in the art according to actual needs.
  • the excess silicon oxide layer can be removed by chemical mechanical polishing (CMP), that is, the silicon oxide layer exposed outside the trench is removed.
  • CMP is to polish the silicon oxide layer to the silicon nitride layer.
  • the method before step S120, further includes the step of sidewall oxidation of the first trench to form the sidewall oxide layer 204.
  • the sidewall oxidation may serve to repair the defects generated in the trench etched in the inner wall of the first trench and the silicon surface of the bottom trench (for example, defects caused by the collision of high-energy particles by reactive ion etching), and eliminate the defect.
  • the negative effects of gate oxide may serve to repair the defects generated in the trench etched in the inner wall of the first trench and the silicon surface of the bottom trench (for example, defects caused by the collision of high-energy particles by reactive ion etching), and eliminate the defect.
  • FIG. 2 is a cross-sectional view of the device after completion of step S130 in the present embodiment.
  • step S130 is performed by a high density plasma etching process.
  • a special corner morphology is formed by oxidation after etching, that is, the surface of the silicon oxide in the trench is similar to a hemispherical shape. Concave. From the corner, the silicon oxide inside the trench gradually thickens to form a rounded corner, as shown in FIG.
  • a first trench is formed on the surface of the silicon wafer, the first trench is filled with silicon oxide 202, and a silicon nitride layer 302 is formed around the top of the first trench.
  • the silicon oxide corner structure is obtained by low temperature oxidation of 800 to 950 degrees Celsius.
  • Low temperature oxidation is used because the inventors have found that if a higher temperature (for example, sacrificial oxidation of 1000 degrees Celsius) is used, the doping ions in the high concentration substrate of the wafer are easily de-amplified into the low concentration epitaxial layer 102, the device Performance has a negative impact.
  • a higher temperature for example, sacrificial oxidation of 1000 degrees Celsius
  • a thin layer of nitrogen-containing compound is formed by chemical vapor deposition, followed by a hard mask for etching.
  • the nitrogen-containing compound may be silicon nitride, silicon oxynitride, boron nitride, titanium nitride or the like, and silicon nitride which is commonly used in the art may be employed in view of universality.
  • the nitrogen-containing compound on the surface of the silicon oxide 202 in the trench is removed by the anisotropy of the dry etching, and the sidewall of the nitrogen-containing compound extending in the trench is formed on the surface of the silicon oxide corner structure.
  • the nitrogen-containing compound sidewall residue 304 serves as a sidewall structure of the trench together with a portion of the silicon oxide 202 in the trench.
  • the nitrogen-containing compound sidewall residue 304 only covers a portion of the first trench, so that the region not covered by the nitrogen-containing compound sidewall residue 304 is etched down (ie, a portion of the silicon oxide 202, side).
  • the wall oxide layer 204 and the epitaxial layer 102 are etched away to form a second trench 201 (deep trench).
  • the width of the second trench 201 is limited by the nitrogen-containing compound sidewall residue 304, and obviously, the width of the second trench 201 is smaller than the width of the upper portion of the first trench.
  • the second trench 201 has a depth of 10 microns or more.
  • the silicon oxide layer 206 is formed by a thermal oxidation process, and the silicon oxide layer 206 is not formed at the position covered by the nitrogen-containing compound sidewall residue 304, see FIG.
  • a step of respectively implanting N-type ions and P-type ions into the second trench 201 and forming an N-type ring 104 and a P-type ring 106 around the bottom of the second trench 201 is further included.
  • the N-type ions are implanted first, the implantation depth is deep, and the N-type ring 104 is formed; after the P-type ions are implanted, the implantation depth is shallow, and the P-type ring 106 is formed above the N-type ring 104.
  • the implanted N-type ions are phosphorus ions and the implanted P-type ions are boron ions.
  • the P-type ring 106 is wider than the N-type ring 104 due to the faster diffusion rate of boron ions.
  • the N-ring 104 and the P-ring 106 are capable of forming a longitudinal depletion while the shallower P-ring 106 serves to reduce leakage from the P-well regions on both sides of the trench isolation structure.
  • the deposition is stopped after the polysilicon is deposited to the desired thickness.
  • etching is performed using the nitrogen-containing compound residue 304 as a mask, and the polysilicon 404 is etched to a desired thickness, for example, under the nitrogen-containing compound residue 304, as shown in FIG. Shown.
  • the etched polysilicon 404 the residual caused by the polysilicon process of the device can be avoided as much as possible, thereby reducing the possibility of surface leakage.
  • the deposited polysilicon is intrinsic polysilicon.
  • wet etching may be employed, for example, etching with concentrated phosphoric acid as an etchant.
  • etching with concentrated phosphoric acid as an etchant.
  • the silicon nitride layer 302 and the nitrogen-containing compound sidewall residue 304 are removed together by concentrated phosphoric acid.
  • the deposition of silicon oxide is performed using a high density plasma chemical vapor deposition (HDPCVD) process.
  • HDPCVD high density plasma chemical vapor deposition
  • the silicon oxide exposing the first trench may be planarized by chemical mechanical polishing, see FIG.
  • the method for manufacturing the trench isolation structure adopts a structure of a first trench + a second trench, and an upper portion of the trench isolation structure has a larger size (ie, a first trench), so that the finally formed trench isolation structure is relatively
  • the narrow trenches reduce the likelihood of leakage due to high voltage traces above the trench isolation structure.
  • the use of a nitrogen-containing compound residue as a hard mask to etch deep trenches saves the number of lithography masks required to achieve equivalent isolation.
  • the above described trench isolation structure fabrication method is applicable to a variety of semiconductor devices that are isolated using deep trench isolation structures.
  • the present application also provides a trench isolation structure accordingly.
  • a trench is included, silicon oxide 206 filled in the trench, and polysilicon 404 located within the trench surrounded by silicon oxide 206.
  • the groove includes an upper wide and a narrow finish structure and a bottle structure extending downward from the finish structure.
  • the trench isolation structure further includes an N-ring 104 and a P-ring 106 located around the bottom of the bottle structure, the P-ring 106 being located above the N-ring 104.

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Abstract

一种沟槽隔离结构的制造方法，包括：在晶圆表面形成上宽下窄的浅槽；通过淀积向浅槽内填充氧化硅；通过刻蚀去除掉一部分氧化硅；通过热氧化在浅槽顶部的拐角处形成氧化硅拐角结构；在晶圆表面淀积氮化硅，覆盖浅槽内的氧化硅表面及氧化硅拐角结构表面；干法刻蚀氮化硅，将浅槽内的氧化硅表面的氮化硅去除，氧化硅拐角结构表面形成向沟槽内延伸的氮化硅残留；以氮化硅残留为掩膜，继续向下刻蚀形成深槽；在深槽的侧壁和底部形成氧化硅层；向浅槽和深槽内淀积多晶硅；去除氮化硅；在浅槽内形成氧化硅将多晶硅覆盖。

Description

沟槽隔离结构及其制造方法 技术领域
本申请涉及半导体制造领域，特别是涉及一种沟槽隔离结构的制造方法，还涉及一种沟槽隔离结构。
背景技术
在智能电源管理、显示以及马达驱动和汽车电子等领域，对高效、节能的要求日趋提高。高压功率领域也衍生出诸如LDMOS(横向双扩散金属氧化物半导体场效应管)、LIGBT(横向绝缘栅双极型晶体管)、power-DMOS(功率-双扩散金属氧化物半导体场效应管)等不同电压等级、不同结构的器件结构，耐压由几十伏至上百伏，因此各种各样的场板、场环等终端结构和RESURF(降低表面电场)技术被开发出来，以辅助这些高压功率器件能保证较低的比导通电阻，这对器件隔离技术提出了很高的要求。
这其中，深槽隔离(DTI)技术作为通用的技术，以其尺寸小、低漏电、双向隔离得以广泛应用。但由于高压功率器件的性能相当依赖于隔离技术，特别是器件雪崩击穿时形成大量的热电子/空穴，其中一部分克服Si/SiO 2势垒进入DTI的氧化层、被DTI中氧化层/多晶硅界面处的陷阱(陷阱的面密度大概为E+10/cm 2量级)俘获，并在多晶硅中受电场影响漂移，使得器件之间发生互扰(cross-talk)，极易导致隔离失效、耐压性能降低。因此持续改进深槽隔离的工艺技术，是高压功率器件领域的重点之一。
发明内容
根据本申请的各种实施例，提供一种沟槽隔离结构及其制造方法。
一种沟槽隔离结构的制造方法，包括：在晶圆表面形成上宽下窄的第一 沟槽；通过淀积向所述第一沟槽内填充氧化硅；通过刻蚀去除掉第一沟槽内的氧化硅表面的一部分；通过热氧化在第一沟槽顶部的拐角处形成氧化硅拐角结构，所述氧化硅拐角结构为从拐角处往下、位于第一沟槽内部的氧化硅逐渐变厚的结构；在晶圆表面淀积含氮化合物，覆盖所述第一沟槽内的氧化硅表面及所述氧化硅拐角结构表面；干法刻蚀所述含氮化合物，将第一沟槽内的氧化硅表面的含氮化合物去除，所述氧化硅拐角结构表面形成向沟槽内延伸的含氮化合物侧壁残留；以所述含氮化合物侧壁残留为掩膜，继续向下刻蚀氧化硅和晶圆形成第二沟槽；在所述第二沟槽的侧壁和底部形成氧化硅层；向所述第一沟槽和第二沟槽内淀积多晶硅；去除所述含氮化合物；在第一沟槽内形成氧化硅将多晶硅覆盖。
一种沟槽隔离结构，包括沟槽，填充于所述沟槽内的氧化硅，以及位于所述沟槽内、被所述氧化硅包围的多晶硅，其特征在于，所述沟槽包括上宽下窄的瓶口结构和从所述瓶口结构向下延伸的瓶身结构。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1是一实施例中沟槽隔离结构的制造方法的流程图；
图2至图7是一实施例中采用沟槽隔离结构的制造方法制造的器件在制造过程中的剖视图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。 附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
图1是一实施例中沟槽隔离结构的制造方法的流程图，包括下列步骤：
S110，在晶圆表面形成上宽下窄的第一沟槽。
可以采用本领域习知的工艺在晶圆(本实施例中为硅片)表面刻蚀出上宽下窄的第一沟槽(浅槽)。在本实施例中，刻蚀形成第一沟槽之前可以先在晶圆表面形成一层氮化硅膜，再于氮化硅膜上通过光刻胶图案化出刻蚀窗口，再通过刻蚀窗口刻穿氮化硅膜形成第一沟槽，刻蚀完成后第一沟槽顶部的周围形成有氮化硅层。在本实施例中，第一沟槽的刻蚀是采用CHCl 3和/或CH 2Cl 2作为刻蚀剂进行干法刻蚀，在其他实施例中也可以采用其他本领域习知的沟槽刻蚀工艺进行刻蚀。
第一沟槽的上部的宽度较宽，这样最终形成的沟槽隔离结构相对于窄沟槽能够降低沟槽隔离结构上方的高压走线导致的漏电可能性。在一个实施例中，第一沟槽的深度为1～2微米。
在一个实施例中，通过外延工艺在高掺杂浓度的衬底上外延出低掺杂浓度的外延层，步骤S110刻蚀得到的沟槽是形成于外延层中。
S120，通过淀积向第一沟槽内填充氧化硅。
通过淀积工艺形成氧化硅(SiO x)层的速度远大于传统的通过热氧化生长氧化硅层的速度。在本实施例中，步骤S120是采用高密度等离子化学气相淀积(HDPCVD)工艺进行氧化硅的淀积，可以获得较好的形貌。在其他实施例中也可以根据实际需求采用其他本领域习知的淀积工艺淀积氧化硅层。
淀积完后可以通过化学机械研磨(CMP)将多余的氧化硅层去除，即将露出于沟槽外面的氧化硅层去除。对于步骤S110采用氮化硅作为硬掩膜刻蚀出第一沟槽的实施例，CMP是将氧化硅层研磨至该氮化硅层。
在一个实施例中，步骤S120之前还包括对第一沟槽进行侧壁氧化，形成侧壁氧化层204的步骤。侧壁氧化可以起到修复步骤S110的沟槽刻蚀在第一沟槽内壁和底部的硅表面产生的缺陷(例如因反应离子刻蚀的高能粒子撞击产生的缺陷)的作用，消除该缺陷对栅氧产生的负面影响。
S130，通过刻蚀去除掉第一沟槽内的氧化硅表面的一部分。
可以采用干法刻蚀，利用其各向异性获得合适的形貌。图2是本实施例中步骤S130完成后器件的剖视图。在其中一个实施例中，步骤S130选用高密度等离子刻蚀的工艺进行刻蚀。
S140，通过氧化在第一沟槽顶部的拐角处形成氧化硅拐角结构。
为了后续步骤中得到的含氮化合物侧壁残留能形成本方案所需的形貌，在刻蚀后通过氧化形成特殊的拐角形貌，即在沟槽内的氧化硅表面形成类似于半球形的凹面。从拐角处往下、位于沟槽内部的氧化硅逐渐变厚，从而形成圆滑的拐角，如图3所示。图3中在硅片的表面形成有第一沟槽，第一沟槽内填充有氧化硅202，第一沟槽顶部的周围形成有氮化硅层302。在本实施例中通过800～950摄氏度的低温氧化来得到该氧化硅拐角结构。采用低温氧化是因为发明人发现若采用较高的温度(例如1000摄氏度的牺牲氧化)，则晶圆的高浓度衬底中的掺杂离子容易反扩至低浓度的外延层102中，对器件性能产生负面影响。
S150，在晶圆表面淀积氮化硅，覆盖第一沟槽内的氧化硅表面及氧化硅 拐角结构表面。
在本实施例中是通过化学气相淀积形成一层薄的含氮化合物，后续作为刻蚀的硬掩膜。该含氮化合物可以是氮化硅、氮氧化硅、氮化硼、氮化钛等，考虑到普适性，可以采用本领域常用的氮化硅。
S160，干法刻蚀含氮化合物，氧化硅拐角结构表面形成向第一沟槽内延伸的含氮化合物侧壁残留。
参见图3，利用干法刻蚀的各向异性，将沟槽内的氧化硅202表面的含氮化合物去除，同时在氧化硅拐角结构表面形成向沟槽内延伸的含氮化合物侧壁残留304。含氮化合物侧壁残留304与沟槽内的一部分氧化硅202共同作为沟槽的侧壁结构。
S170，以含氮化合物侧壁残留为掩膜，继续向下刻蚀氧化硅和晶圆形成第二沟槽。
参见图4，含氮化合物侧壁残留304只会覆盖第一沟槽的一部分，因此没被含氮化合物侧壁残留304覆盖的区域就会被向下刻蚀掉(即部分氧化硅202、侧壁氧化层204及外延层102被刻蚀去除)形成第二沟槽201(深槽)。第二沟槽201的宽度受含氮化合物侧壁残留304限制，显然地，第二沟槽201的宽度小于第一沟槽的上部的宽度。采用含氮化合物侧壁残留304作为第二沟槽刻蚀的硬掩膜，可以不需要光刻版，能够节省成本。
在一个实施例中，第二沟槽201的深度为10微米以上。
S180，在第二沟槽的侧壁和底部形成氧化硅层。
在本实施例中，是通过热氧化的工艺形成氧化硅层206，被含氮化合物侧壁残留304覆盖的位置不会形成氧化硅层206，参见图5。
在本实施例中，步骤S180后还包括分别向第二沟槽201内注入N型离子和P型离子，在第二沟槽201的底部周围形成N型环104和P型环106的步骤。在一个实施例中，是先注入N型离子，注入深度较深，形成N型环104；后注入P型离子，注入深度较浅，在N型环104上方形成P型环106。在一个实施例中，注入的N型离子为磷离子、注入的P型离子为硼离子，由于硼 离子的扩散速度较快故P型环106比N型环104宽。N型环104和P型环106能够形成纵向耗尽，同时较浅的P型环106起到降低来自于沟槽隔离结构的两侧P阱区漏电的作用。
S190，向第一沟槽和第二沟槽内淀积多晶硅。
在一个实施例中，是淀积多晶硅至所需的厚度以后就停止淀积。在本实施例中，是淀积过量的多晶硅后，再以含氮化合物残留304作为掩膜进行回刻，将多晶硅404刻蚀至所需的厚度，例如含氮化合物残留304下方，如图6所示。采用回刻多晶硅404的方式，能够尽量避免器件的多晶硅工艺导致的残留，从而降低表面漏电的可能性。在一个实施例中，淀积的多晶硅是本征多晶硅。
S200，去除含氮化合物。
为了将含氮化合物去除干净，可以采用湿法刻蚀，例如以浓磷酸为刻蚀剂进行刻蚀。本实施例中通过浓磷酸将氮化硅层302和含氮化合物侧壁残留304一并去除。
S210，在第一沟槽内形成氧化硅将多晶硅覆盖。
在本实施例中，是采用高密度等离子化学气相淀积(HDPCVD)工艺进行氧化硅的淀积。步骤S210完成后可以通过化学机械研磨对露出第一沟槽的氧化硅进行平坦化处理，参见图7。
上述沟槽隔离结构的制造方法，采用第一沟槽+第二沟槽的结构，沟槽隔离结构的上部具有较大的尺寸(即第一沟槽)，这样最终形成的沟槽隔离结构相对于窄沟槽能够降低沟槽隔离结构上方的高压走线导致的漏电可能性。采用含氮化合物残留作为硬掩膜刻蚀深槽，节省了达到同等隔离效果所需的光刻版(mask)数量。
上述沟槽隔离结构的制造方法适用于各种使用深槽隔离结构进行隔离的半导体器件。
本申请还相应提供一种沟槽隔离结构。参见图7，包括沟槽，填充于沟槽内的氧化硅206，以及位于沟槽内、被氧化硅206包围的多晶硅404。沟槽 包括上宽下窄的瓶口结构和从瓶口结构向下延伸的瓶身结构。
在一个实施例中，沟槽隔离结构还包括位于瓶身结构底部周围的N型环104和P型环106，P型环106位于N型环104上方。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种沟槽隔离结构的制造方法，包括：
    在晶圆表面形成上宽下窄的第一沟槽；
    通过淀积向所述第一沟槽内填充氧化硅；
    通过刻蚀去除掉第一沟槽内的氧化硅表面的一部分；
    通过热氧化在第一沟槽顶部的拐角处形成氧化硅拐角结构，所述氧化硅拐角结构为从拐角处往下、位于第一沟槽内部的氧化硅逐渐变厚的结构；
    在晶圆表面淀积含氮化合物，覆盖所述第一沟槽内的氧化硅表面及所述氧化硅拐角结构表面；
    干法刻蚀所述含氮化合物，将第一沟槽内的氧化硅表面的含氮化合物去除，所述氧化硅拐角结构表面形成向沟槽内延伸的含氮化合物侧壁残留；
    以所述含氮化合物侧壁残留为掩膜，继续向下刻蚀氧化硅和晶圆形成第二沟槽；
    在所述第二沟槽的侧壁和底部形成氧化硅层；
    向所述第一沟槽和第二沟槽内淀积多晶硅；
    去除所述含氮化合物侧壁残留；及
    在第一沟槽内形成氧化硅将多晶硅覆盖。
  2. 根据权利要求1所述的制造方法，其中，所述第一沟槽的深度为1～2微米，所述第二沟槽的深度为10微米以上。
  3. 根据权利要求1所述的制造方法，其中，所述在所述第二沟槽的侧壁和底部形成氧化硅层的步骤是采用热氧化工艺，形成的氧化硅层厚度为1000埃以上。
  4. 根据权利要求1所述的制造方法，其中，所述在所述第二沟槽的侧壁和底部形成氧化硅层的步骤之后、所述向所述第一沟槽和第二沟槽内淀积多晶硅的步骤之前，还包括分别向所述第二沟槽内注入N型离子和P型离子，在所述第二沟槽的底部周围形成N型环和P型环的步骤。
  5. 根据权利要求1所述的制造方法，其中，所述去除所述含氮化合物侧壁残留的步骤之前，还包括刻蚀所述多晶硅至所述含氮化合物侧壁残留下方的步骤。
  6. 根据权利要求1所述的制造方法，其中，所述通过淀积向所述第一沟槽内填充氧化硅的步骤之前还包括对所述第一沟槽进行侧壁氧化的步骤。
  7. 根据权利要求1所述的制造方法，其中，所述在晶圆表面形成上宽下窄的第一沟槽的步骤之前还包括在晶圆表面形成氮化硅层的步骤，所述在晶圆表面形成上宽下窄的第一沟槽的步骤是将所述氮化硅层刻穿形成所述第一沟槽。
  8. 根据权利要求1所述的制造方法，其中，所述通过热氧化在第一沟槽顶部的拐角处形成氧化硅拐角结构的步骤中，氧化温度为800～950摄氏度。
  9. 根据权利要求1所述的制造方法，其中，还包括通过外延工艺在衬底上外延出外延层的步骤，所述外延层的掺杂浓度高于所述衬底，所述在晶圆表面形成上宽下窄的第一沟槽的步骤，是在所述外延层中形成所述第一沟槽。
  10. 根据权利要求1所述的制造方法，其中，所述通过淀积向所述第一沟槽内填充氧化硅的步骤，是采用高密度等离子化学气相淀积工艺进行氧化硅的淀积。
  11. 根据权利要求1所述的制造方法，其中，所述通过淀积向所述第一沟槽内填充氧化硅的步骤之后、所述通过刻蚀去除掉第一沟槽内的氧化硅表面的一部分的步骤之前，还包括通过化学机械研磨将露出于所述第一沟槽外面的氧化硅层去除的步骤。
  12. 根据权利要求7所述的制造方法，其中，所述通过淀积向所述第一沟槽内填充氧化硅的步骤之后、所述通过刻蚀去除掉第一沟槽内的氧化硅表面的一部分的步骤之前，还包括将氧化硅层研磨至该氮化硅层的步骤。
  13. 根据权利要求1所述的制造方法，其中，所述去除所述含氮化合物侧壁残留的步骤，是以浓磷酸为刻蚀剂进行刻蚀。
  14. 根据权利要求1所述的制造方法，其中，所述在第一沟槽内形成氧 化硅将多晶硅覆盖的步骤，是采用高密度等离子化学气相淀积工艺进行氧化硅的淀积。
  15. 根据权利要求1所述的制造方法，其中，所述在第一沟槽内形成氧化硅将多晶硅覆盖的步骤之后，还包括通过化学机械研磨对露出第一沟槽的氧化硅进行平坦化处理的步骤。
  16. 根据权利要求1所述的制造方法，其中，所述在晶圆表面形成上宽下窄的第一沟槽的步骤，是采用CHCl 3和/或CH 2Cl 2作为刻蚀剂进行干法刻蚀。
  17. 根据权利要求1所述的制造方法，其中，所述通过刻蚀去除掉第一沟槽内的氧化硅表面的一部分的步骤，是采用干法刻蚀。
  18. 根据权利要求17所述的制造方法，其中，所述通过刻蚀去除掉第一沟槽内的氧化硅表面的一部分的步骤，是采用高密度等离子刻蚀的工艺进行刻蚀。
  19. 一种沟槽隔离结构，包括：
    沟槽，包括上宽下窄的瓶口结构和从所述瓶口结构向下延伸的瓶身结构；
    氧化硅，填充于所述沟槽内；以及
    多晶硅，位于所述沟槽内，被所述氧化硅包围。
  20. 根据权利要求19所述的沟槽隔离结构，其中，还包括位于所述瓶身结构底部周围的N型环和P型环，所述P型环位于所述N型环上方。
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110854061A (zh) * 2019-11-26 2020-02-28 上海华力微电子有限公司 一种提高超浅隔离槽隔离效应的工艺方法
CN113496939A (zh) * 2020-04-03 2021-10-12 无锡华润上华科技有限公司 一种半导体器件及其制作方法
CN113394270B (zh) * 2021-07-16 2025-06-27 杭州士兰集成电路有限公司 一种半导体器件的隔离结构及其制造方法
CN115064436B (zh) * 2022-06-07 2026-04-14 浙江同芯祺科技有限公司 一种用于晶圆的沟槽晶体管加工方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5358891A (en) * 1993-06-29 1994-10-25 Intel Corporation Trench isolation with planar topography and method of fabrication
US6020230A (en) * 1998-04-22 2000-02-01 Texas Instruments-Acer Incorporated Process to fabricate planarized deep-shallow trench isolation having upper and lower portions with oxidized semiconductor trench fill in the upper portion and semiconductor trench fill in the lower portion
US20020081809A1 (en) * 2000-12-22 2002-06-27 Angelo Pinto Method and system for integrating shallow trench and deep trench isolation structures in a semiconductor device
KR20030050199A (ko) * 2001-12-18 2003-06-25 주식회사 하이닉스반도체 반도체 소자의 소자 분리막 형성 방법
CN102097358A (zh) * 2009-12-15 2011-06-15 上海华虹Nec电子有限公司 浅沟隔离槽

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6012647A (ja) 1983-07-01 1985-01-23 Mitsubishi Electric Corp 陰極線管
JPS60126847A (ja) * 1983-12-14 1985-07-06 Hitachi Micro Comput Eng Ltd 半導体装置の製造方法
JPS61150230A (ja) * 1984-12-24 1986-07-08 Hitachi Ltd 溝及び絶縁分離領域の形成方法
JP2568638B2 (ja) * 1988-07-18 1997-01-08 富士通株式会社 半導体装置の製造方法
JPH03215943A (ja) * 1990-01-19 1991-09-20 Mitsubishi Electric Corp 半導体集積回路装置
JPH10223747A (ja) * 1997-02-06 1998-08-21 Nec Corp 半導体装置の製造方法
JPH11307627A (ja) * 1997-08-01 1999-11-05 Nippon Steel Corp 半導体装置及びその製造方法
US6221785B1 (en) * 1998-09-17 2001-04-24 Winbond Electronics Corporation Method for forming shallow trench isolations
US20020179997A1 (en) * 2001-06-05 2002-12-05 International Business Machines Corporation Self-aligned corner Vt enhancement with isolation channel stop by ion implantation
DE10306318B4 (de) * 2003-02-14 2010-07-22 Infineon Technologies Ag Halbleiter-Schaltungsanordnung mit Grabenisolation und Herstellungsverfahren
US20070132056A1 (en) * 2005-12-09 2007-06-14 Advanced Analogic Technologies, Inc. Isolation structures for semiconductor integrated circuit substrates and methods of forming the same
KR20090116702A (ko) * 2007-01-09 2009-11-11 맥스파워 세미컨덕터 인크. 반도체 디바이스
CN201038163Y (zh) * 2007-03-30 2008-03-19 东南大学 沟槽高压p型金属氧化物半导体管
US8252647B2 (en) * 2009-08-31 2012-08-28 Alpha & Omega Semiconductor Incorporated Fabrication of trench DMOS device having thick bottom shielding oxide
US8105903B2 (en) * 2009-09-21 2012-01-31 Force Mos Technology Co., Ltd. Method for making a trench MOSFET with shallow trench structures
CN102024848A (zh) * 2010-11-04 2011-04-20 天津环鑫科技发展有限公司 用于功率器件的沟槽结构及其制造方法
TWI458097B (zh) * 2012-12-12 2014-10-21 Beyond Innovation Tech Co Ltd 溝渠式閘極金氧半場效電晶體及其製造方法
CN104409410A (zh) * 2014-11-19 2015-03-11 上海华力微电子有限公司 改善浅沟槽隔离边缘SiC应力性能的方法
CN105789133B (zh) * 2014-12-24 2019-09-20 上海格易电子有限公司 一种闪存存储单元及制作方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5358891A (en) * 1993-06-29 1994-10-25 Intel Corporation Trench isolation with planar topography and method of fabrication
US6020230A (en) * 1998-04-22 2000-02-01 Texas Instruments-Acer Incorporated Process to fabricate planarized deep-shallow trench isolation having upper and lower portions with oxidized semiconductor trench fill in the upper portion and semiconductor trench fill in the lower portion
US20020081809A1 (en) * 2000-12-22 2002-06-27 Angelo Pinto Method and system for integrating shallow trench and deep trench isolation structures in a semiconductor device
KR20030050199A (ko) * 2001-12-18 2003-06-25 주식회사 하이닉스반도체 반도체 소자의 소자 분리막 형성 방법
CN102097358A (zh) * 2009-12-15 2011-06-15 上海华虹Nec电子有限公司 浅沟隔离槽

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