WO2018228514A1 - 信息处理的方法和通信装置 - Google Patents

信息处理的方法和通信装置 Download PDF

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WO2018228514A1
WO2018228514A1 PCT/CN2018/091423 CN2018091423W WO2018228514A1 WO 2018228514 A1 WO2018228514 A1 WO 2018228514A1 CN 2018091423 W CN2018091423 W CN 2018091423W WO 2018228514 A1 WO2018228514 A1 WO 2018228514A1
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matrix
column
rows
base
base matrix
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French (fr)
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金杰
童文
王俊
帕特尤斯基亚历山大
列昂尼多维奇 马祖连科伊万
张朝龙
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华为技术有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
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    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H—ELECTRICITY
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    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
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    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
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    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
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    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/1177—Regular LDPC codes with parity-check matrices wherein all rows and columns have the same row weight and column weight, respectively
    • H—ELECTRICITY
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    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
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    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
    • H—ELECTRICITY
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    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/615—Use of computational or mathematical techniques
    • H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
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    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/618—Shortening and extension of codes
    • H—ELECTRICITY
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    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing
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    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H—ELECTRICITY
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    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H03M13/6516—Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0047—Decoding adapted to other signal detection operation
    • H04L1/005—Iterative decoding, including iteration between signal detection and decoding operation
    • H—ELECTRICITY
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    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
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    • H04L1/0067—Rate matching
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Definitions

  • Embodiments of the present invention relate to the field of communications, and in particular, to a method and a communication device for information processing.
  • Low density parity check (LDPC) code is a kind of linear block coding with sparse check matrix, which has the characteristics of flexible structure and low decoding complexity. Because it uses a partially parallel iterative decoding algorithm, it has a higher throughput than the traditional Turbo code.
  • the LDPC code can be used for the error correction code of the communication system, thereby improving the reliability and power utilization of the channel transmission.
  • LDPC codes can also be widely used in space communication, optical fiber communication, personal communication systems, ADSL, and magnetic recording devices. At present, LDPC codes have been considered as one of channel coding methods in the fifth generation mobile communication.
  • an LDPC matrix with special structured features can be used.
  • the LDPC matrix H with special structuring features can be obtained by extending the LDPC basis matrix of a quasi-cycle (QC) structure.
  • the length of information bit sequences to be encoded ranges from tens to hundreds, and the code rate required by the communication system is also flexible. How to support the encoding of information length sequences of various lengths, in line with the code rate requirements of the system, becomes a problem to be solved.
  • Embodiments of the present invention provide a method, a communication device, and a system for information processing, which can support encoding and decoding of information bit sequences of various lengths, and meet the flexible code length code rate requirements of the system.
  • an encoding method and an encoder are provided that encode an input sequence using a low density parity check LDPC matrix.
  • a decoding method and decoder are provided that decode an input sequence using a low density parity check LDPC matrix.
  • the LDPC matrix is obtained based on a base map, where the base map includes sub-matrices A, B, C, D, and E, where
  • the sub-matrix B is a matrix of m A rows and m A columns, and the sub-matrix B includes a column with a weight of 3 and a sub-matrix B′ of a double-diagonal structure;
  • the sub-matrix D includes m D rows in a matrix F, the matrix F is a matrix of m F rows (m A + n A ) columns, m D and m F are positive integers, 0 ⁇ m D ⁇ m F , 35 ⁇ m F ⁇ 38;
  • the sub-matrix C is an all-zero matrix of m A rows and m D columns;
  • the sub-matrix E is an identity matrix of m D rows and m D columns.
  • any two adjacent rows in the last 10 rows of the base map are orthogonal.
  • At least 5 groups are included in the last 10 rows of the base map, and each of the at least 5 groups includes at least 2 rows, and the at least 2 rows are orthogonal. of.
  • the weight of 9 rows in the matrix F is 3, and the weight of 1 row is 2.
  • one column has a weight of 16, a column has a weight of 18, a column has a weight of 11, a column has a weight of 10, a column has a weight of 9, and a column has a weight of 1.
  • the weight of the 8,1 column is 7, the weight of the 1 column is 6, the weight of the 2 column is 4, the weight of the 1 column is 3, and the weight of the 2 column is 2.
  • the number of rows in the matrix F conforming to the orthogonal structure is greater than or equal to 10, and wherein the weight of the column in the matrix F is 16, The weight of 1 column is 18, the weight of 1 column is 11, the weight of 2 column is 10, the weight of 1 column is 9, the weight of 1 column is 8, the weight of 1 column is 7, the weight of 1 column is 6, 2 columns The weight of the 4, 1 column is 3, and the weight of the 2 column is 2.
  • 9 rows have a weight of 3, and 1 row has a weight of 2.
  • the matrix F includes at least 10 rows, and any two adjacent rows of the at least 10 rows are orthogonal.
  • the matrix F comprises at least 5 groups, each of the at least 5 groups comprising at least 2 rows, the at least 2 rows being orthogonal.
  • the at least 2 rows may be consecutive rows.
  • the at least 10 lines may be the last 10 lines of the base map 30a.
  • 10 rows in the matrix F conforming to the orthogonal structure may include rows or columns of matrix blocks composed of 25th to 34th rows and 0th column to 13th column in the base map 30a, or, in the matrix F
  • the 10 rows conforming to the orthogonal structure may include rows or columns of matrix blocks composed of the 25th to 34th rows and the 0th column to the 16th column in the base map 30a.
  • the rows in the matrix F can be exchanged, and the columns can also be exchanged with each other.
  • the base matrix of the base map 30a may be any one of the base matrices 30b-1, 30b-2, 30b-3, 30b-4, 30b-5, 30b-6, 30b-7, and 30b-8.
  • a matrix, or a matrix after row/column transformation of the matrix may be any one of the base matrices 30b-1, 30b-2, 30b-3, 30b-4, 30b-5, 30b-6, 30b-7, and 30b-8.
  • the offset matrix of the matrix F may be a matrix shown in the 7th to 41st rows and the 0th column to the 16th column in any of the matrixes 30b-1 to 30b-8, or a row of the matrix.
  • /column transformed matrix; or matrix F's offset matrix may include the matrix shown in rows 4 to 41 and columns 0 through 14 of any of 30b-1 to 30b-8, or The matrix after the row/column transformation of the matrix.
  • the LDPC code requires different spreading factors Z.
  • the offset matrix of the matrix F may be the 7th to 41st of 30b-1
  • the row and the matrix shown in the 0th column to the 16th column are either the row/column transformed matrix of the matrix; or the offset matrix of the matrix F may be the 4th to 41st rows and the 0th in the 30b-1 Column to the matrix shown in column 14, or the row/column transformed matrix of the matrix.
  • the base matrix of the base map 30a may be a matrix shown by 30b-1 or a matrix after row/column transformation of the matrix.
  • the offset matrix of the matrix F may be the 7th to 41st of the 30b-2
  • the base matrix of the base map 30a may be a matrix shown by 30b-2, or a matrix after row/column transformation of the matrix.
  • the offset matrix of the matrix F may be the 7th to 41st lines of 30b-3 and The matrix shown in the 0th column to the 16th column, or the matrix after the row/column transformation of the matrix; or the offset matrix of the matrix F may be the 4th to 41st rows and the 0th column in the 30b-3
  • the matrix shown in column 14 is either the row/column transformed matrix of the matrix.
  • the base matrix of the base map 30a may be a matrix shown by 30b-3, or a matrix after row/column transformation of the matrix.
  • the matrix F may be the offset matrix 30b-4, line 7 to line 41 and second 0 Columns to the matrix shown in column 16, or the row/column transformed matrix of the matrix; or the offset matrix of matrix F may be the 4th to 41st and the 0th to 14th of 30b-4 The matrix shown in the column, or the matrix after the row/column transformation of the matrix.
  • the base matrix of the base map 30a may be a matrix shown by 30b-4, or a matrix after row/column transformation of the matrix.
  • the offset matrix of the matrix F may be the 7th to 41st lines and the 0th in the 30b-5 Columns to the matrix shown in column 16, or the row/column transformed matrix of the matrix; or the offset matrix of matrix F may be the 4th to 41st and the 0th to 14th of 30b-5
  • the base matrix of the base map 30a may be a matrix shown by 30b-5, or a matrix after row/column transformation of the matrix.
  • the offset matrix of the matrix F may be the 7th to 41st lines and the 0th in the 30b-6 Columns to the matrix shown in column 16, or the matrix after row/column transformation of the matrix; or the offset matrix of matrix F may be the 4th to 41st rows and the 0th to 14th of 30b-6 The matrix shown in the column, or the matrix after the row/column transformation of the matrix.
  • the base matrix of the base map 30a may be a matrix shown by 30b-6, or a matrix after row/column transformation of the matrix.
  • the offset matrix of the matrix F may be the 7th to 41st rows and the 0th column of 30b-7.
  • the matrix shown in the 16th column is either the row/column transformed matrix of the matrix; or the offset matrix of the matrix F may be the 4th to 41st rows and the 0th column to the 14th column of 30b-7
  • the base matrix of the base map 30a may be a matrix as shown in 30b-7, or a matrix after row/column transformation of the matrix.
  • the offset matrix of the matrix F may be the 7th to 41st rows and the 0th column of 30b-8 to
  • the matrix shown in the 16th column is either the row/column transformed matrix of the matrix; or the offset matrix of the matrix F may be the 4th to 41st rows and the 0th column to the 14th column of 30b-8.
  • the base matrix of the base map 30a may be a matrix shown by 30b-8, or a matrix after row/column transformation of the matrix.
  • the base map or the base matrix may further include at least one column of built-in punctured bit columns.
  • the base map and base matrix of the LDPC matrix in each of the above implementations can satisfy the performance requirements of code blocks having a block length of 20 to 2560 bits.
  • the method further includes: determining the expansion factor Z.
  • the value of the spreading factor Z is determined according to the length K of the input sequence. For example, if the input sequence length is K, a minimum value satisfying 10*Z ⁇ K can be determined among a plurality of system-defined spreading factors.
  • the LDPC matrix may be obtained based on the base matrix corresponding to Z, or may be obtained based on the Z-based offset matrix.
  • encoding the input sequence using an LDPC matrix includes:
  • the row/column transformation in this application refers to a row transformation, a column transformation, or a row transformation and a column transformation.
  • decoding the input sequence using the LDPC matrix includes:
  • the input sequence is decoded by using an LDPC matrix corresponding to the spreading factor Z; or the LDPC matrix corresponding to the spreading factor Z is subjected to row/column transformation, and the input sequence is encoded using the matrix after the row/column transformation to the input.
  • the sequence is encoded.
  • the row/column transformation in this application refers to a row transformation, a column transformation, or a row transformation and a column transformation.
  • the LDPC matrix may be saved, the input sequence is encoded using the LDPC matrix, or transformed (row/column transform) or extended based on the LDPC matrix to obtain an LDPC matrix usable for encoding.
  • parameters may be saved, and an LDPC matrix for encoding or decoding may be obtained according to the parameters, so that the input sequence may be encoded or decoded based on the LDPC matrix.
  • the parameter includes at least one of: a base map, a base matrix, a transform matrix based on a base/column transformation of a base map or a base matrix, an extended matrix based on a base map or a base matrix, and an offset value of a non-zero element in the base matrix; Or any parameter related to obtaining an LDPC matrix.
  • the base matrix of the LDPC matrix can be stored in a memory.
  • the base map of the LDPC matrix is stored in a memory, and offset values of non-zero elements in the base matrix of the LDPC matrix may be stored in the memory.
  • At least one of the base map and the base matrix used for LDPC encoding or decoding is at least one of a base map and a base matrix of the foregoing LDPC matrix, or Column exchange, or row exchange and column exchange.
  • a communication device can include corresponding modules for performing the above method design.
  • the module can be software and/or hardware.
  • a communication device provided by the third aspect includes a processor and a transceiver component that can be used to implement the functions of various portions of the encoding or decoding method described above.
  • the transceiver component if the communication device is a terminal, a base station or other network device, the transceiver component thereof may be a transceiver. If the communication device is a baseband chip or a baseband single board, the transceiver component may be a baseband chip or a baseband single board. Input/output circuits for receiving/transmitting input/output signals.
  • the communication device can optionally also include a memory for storing data and/or instructions.
  • the processor may include the encoder and the determining unit as described in the first aspect above.
  • the determining unit is operative to determine a spreading factor Z required to encode the input sequence.
  • the encoder is configured to encode the input sequence using an LDPC matrix corresponding to the spreading factor Z.
  • the processor may include the decoder and the obtaining unit as described in the second aspect above.
  • the obtaining unit is configured to acquire a soft value and an expansion factor Z of the LDPC code.
  • the decoder is configured to decode the soft value of the LDPC code based on the base matrix H B corresponding to the spreading factor Z to obtain an information bit sequence.
  • a communication device in a fourth aspect, includes one or more processors.
  • one or more of the processors may implement the functions of the encoder of the first aspect, and in another possible design, the encoder of the first aspect may be the processor In part, the processor can implement other functions in addition to the functions of the encoder described in the first aspect.
  • one or more of the processors may implement the functions of the decoder of the second aspect, and in another possible design, the decoder of the second aspect may be Part of the processor.
  • the communication device may further include a transceiver and an antenna.
  • the communication device may further include a device for generating a transport block CRC, a device for code block splitting and CRC check, an interleaver for interleaving, a modulator for modulation processing, and the like.
  • the communication device may further include a demodulator for demodulation operation, a deinterleaver for deinterleaving, a device for de-rate matching, and the like.
  • a demodulator for demodulation operation e.g., a demodulator for demodulation operation
  • a deinterleaver for deinterleaving e.g., a device for de-rate matching
  • the functionality of these devices can be implemented by one or more processors.
  • the functionality of these devices can be implemented by one or more processors.
  • 1 is a schematic diagram of a base map, a base matrix, and a cyclic permutation matrix of an LDPC code
  • FIG. 2 is a schematic structural diagram of a base diagram of an LDPC code
  • FIG. 3a is a schematic diagram of a LDPC code base diagram according to an embodiment of the present invention.
  • Figure 3b-1 is a schematic diagram of the base matrix of the base diagram shown in Figure 3a;
  • Figure 3b-2 is a schematic diagram of still another base matrix of the base diagram shown in Figure 3a;
  • Figure 3b-3 is a schematic diagram of still another base matrix of the base diagram shown in Figure 3a;
  • Figure 3b-4 is a schematic diagram of still another base matrix of the base diagram shown in Figure 3a;
  • Figure 3b-5 is a schematic diagram of still another base matrix of the base diagram shown in Figure 3a;
  • Figure 3b-6 is a schematic diagram of still another base matrix of the base diagram shown in Figure 3a;
  • 3b-7 is a schematic diagram of still another base matrix of the base diagram shown in FIG. 3a;
  • 3b-8 is a schematic diagram of still another base matrix of the base diagram shown in FIG. 3a;
  • FIG. 5 is a schematic structural diagram of an information processing apparatus according to another embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a communication system according to another embodiment of the present invention.
  • the “communication device” may be a chip (such as a baseband chip, or a data signal processing chip, or a general purpose chip, etc.), a terminal, a base station, or other network device.
  • a terminal is a device having a communication function and may include a handheld device having a wireless communication function, an in-vehicle device, a wearable device, a computing device, or other processing device connected to a wireless modem.
  • Terminals can be called different names in different networks, such as: user equipment, mobile stations, subscriber units, stations, cellular phones, personal digital assistants, wireless modems, wireless communication devices, handheld devices, laptops, cordless phones, Wireless local loop station, etc.
  • a base station also referred to as a base station device, is a device deployed in a radio access network to provide wireless communication functions.
  • the name of a base station may be different in different wireless access systems, for example, in a Universal Mobile Telecommunications System (UMTS) network, a base station is called a Node B, but in an LTE network.
  • a base station is called an evolved Node B (eNB or eNodeB).
  • eNB evolved Node B
  • a base station in a new radio (NR) network is called a transmission reception point (TRP) or a next generation node B (generation node B, gNB). ), or other base stations in various networks may also use other names.
  • TRP transmission reception point
  • gNB next generation node B
  • the invention is not limited to this.
  • the LDPC code can usually be represented by a parity check matrix H.
  • the parity check matrix H of the LDPC code can be obtained by a base graph and a shift value.
  • the base map can usually include m*n matrix elements, which can be represented by a matrix of m rows and n columns.
  • the value of the matrix element is 0 or 1, and the element with a value of 0 is sometimes called a zero element. , indicating that the element can be replaced by Z*Z's zero matrix.
  • An element with a value of 1, sometimes referred to as a non-zero element indicates that the element can be a cyclic permutation matrix of Z*Z (circulant permutation) Matrix) replacement.
  • each matrix element represents an all-zero matrix or a cyclic permutation matrix.
  • the line number and column number of the base map and the matrix are numbered from 0, just for the convenience of understanding. It can be understood that the line number and column number can also be numbered from 1, and the corresponding line number and column number are incremented by 1 based on the line number and column number shown in this article.
  • the element value of the i-th row and the j-th column in the base map is 1, and the offset value is P i,j , P i,j is an integer greater than or equal to 0, the value of the j-th column of the i-th row is 1
  • the element can be replaced by a cyclic permutation matrix of Z*Z corresponding to P i,j , which can be obtained by cyclically shifting the unit matrix of Z*Z by P i, j times to the right.
  • each element with a value of 0 in the base map is replaced by an all-zero matrix of Z*Z, and each element having a value of 1 is replaced by a cyclic permutation matrix of Z*Z corresponding to its offset value,
  • the parity check matrix of the LDPC code may also be referred to as an LDPC matrix.
  • the base map can be used to indicate the location of the offset value, and the non-zero elements in the base map correspond to the offset values.
  • Z is a positive integer, which can also be called a lifting factor, sometimes called lifting size, or lifting factor, etc., which can be determined according to the code block size supported by the system and the size of the information data.
  • the system usually defines a base matrix of m*n. Each element in the base matrix corresponds to the position of each element in the base map. The zero elements in the base map are in the base matrix. The position is unchanged, and is represented by -1.
  • the non-zero element with the value of the jth column in the i-th row and the j-th column in the base map is unchanged in the base matrix, and can be expressed as V i,j , V i,j can be relative to An offset value defined by a predetermined or specific spreading factor Z, for example, is an offset value relative to a maximum spreading factor Z max in the set of the spreading factor Z, where V i,j may be the largest in the set of Z.
  • the base matrix is sometimes referred to as an offset matrix of the base matrix.
  • a base matrix corresponding to the base map 10a is shown.
  • the base map or the base matrix of the LDPC code may further include a p-column built-in puncture bit string, and p may be an integer of 0-2, and these columns participate in encoding, but the system bits corresponding to the encoding are not
  • R (nm)/(np)
  • the LDPC code used in the wireless communication system has a matrix size of m*n, and may include five sub-matrices A, B, C, D, and E, wherein the weight of the matrix is determined by the number of non-zero elements.
  • the weight of the row refers to the number of non-zero elements included in a row
  • the weight of the column refers to the number of non-zero elements included in a column.
  • Submatrix A is a matrix of m A rows and n A columns, which may be of size M A *n A , where each column corresponds to Z systematic bits in the LDPC code, and system bits are sometimes referred to as information bits.
  • the sub-matrix B is a square matrix of m A rows and m A columns, and its size may be m A *m A , and each column corresponds to Z parity bits in the LDPC code.
  • the sub-matrix B includes a sub-matrix B' with a double-diagonal structure and a matrix column with a weight of 3 (referred to as a 3-column re-column), wherein the matrix column with a column weight of 3 may be located before the sub-matrix B', as shown in FIG. 20a; the sub-matrix B may further include one or more columns of columns having a column weight of 1 (referred to as a single column of re-columns).
  • a single column of re-columns referred to as a single column of re-columns
  • the matrix generated based on the sub-matrices A and B is usually a core matrix and can be used to support high code rate encoding.
  • Submatrix C is an all-zero matrix with a size of m A ⁇ m D .
  • the sub-matrix E is an identity matrix having a size of m D ⁇ m D .
  • the submatrix D has a size of m D ⁇ (n A + m A ) and can generally be used to generate a low bit rate check bit.
  • the structure of the two sub-matrices A, B and D is one of the factors influencing the coding performance of the LDPC code.
  • the matrix of the sub-matrices A and B may be encoded to obtain the parity bit corresponding to the sub-matrix B, and then The entire matrix is encoded to obtain parity bits corresponding to the E portion of the sub-matrix. Since the sub-matrix B can include the sub-matrix B' of the double-diagonal structure and a single-column re-column, the parity bits corresponding to the double-diagonal structure can be obtained first in the encoding, and the parity bits corresponding to the single-column re-column can be obtained.
  • H core-dual ⁇ [S P e ] T 0, where S is an input sequence, a vector composed of information bits, P e is a vector composed of parity bits, and [S P e ] T represents The matrix transpose consisting of the input sequences S and P e .
  • H core-dual H core-dual check bit corresponding to the input sequence S includes all information bits; then according to obtain H core-dual check bit corresponding to an input sequence and calculates S Obtaining the parity bits corresponding to the single column re-column in the sub-matrix B, in this case, all the parity bits corresponding to the sub-matrix B can be obtained; and then according to the input sequence S and the parity bits corresponding to the sub-matrix B, the sub-matrix D is partially encoded.
  • the check bits corresponding to the sub-matrix E thus obtaining all information bits and all check bits, these bits constitute the encoded sequence, that is, an LDPC code sequence.
  • the LDPC code encoding may also include shortening and puncturing operations. Both truncated bits and punctured bits are not transmitted.
  • the truncation is generally truncated from the last bit of the information bit, and can be truncated in different ways.
  • the truncated number of bits s 0 can be set to the last s 0 bits in the input sequence S to obtain the input sequence S', such as set to 0 or null, or some other value, and then through the LDPC matrix pair
  • the input sequence S' is encoded.
  • the last (s 0 mod Z) bits in the input sequence S may be set to the known bits to obtain the input sequence S', if set to 0 or null, or some other value.
  • the input sequence S' is encoded using the LDPC matrix H', or the last in the submatrix A
  • the column does not participate in the encoding of the input sequence S'. After the encoding is completed, the truncated bits are not sent.
  • the punching may be a punching bit built in the input sequence or a punching bit.
  • the last bit of the parity bit is usually punctured.
  • the puncturing may be performed according to the preset puncturing order of the system.
  • a possible implementation manner is that the input sequence is first encoded, and then the last p bits in the parity bit are selected according to the number of bits p to be punctured, or p bits are selected according to the system's preset puncturing order. p bits are not sent.
  • the p columns of the matrix corresponding to the punctured bits and the p rows of the non-zero elements in the columns may also be determined, and the rows and columns do not participate in the coding, and the corresponding school is not generated. Check the bit.
  • the decoding involved in the present application may be a plurality of decoding methods, for example, a min-sum (MS) decoding method or a belief propagation decoding method.
  • MS decoding method is sometimes also referred to as a Flood MS decoding method.
  • the input sequence is initialized and iteratively processed, the hard decision detection is performed after the iteration, and the hard decision result is verified. If the decoding result conforms to the check equation, the decoding is successful, the iteration is terminated, and the decision result is output. .
  • the decoding mode is only an example.
  • the base map and/or the base matrix provided by the present application other decoding methods known to those skilled in the art may be used.
  • the LDPC code can be obtained based on the base map and the base matrix.
  • the density evolution method of the base map or the base matrix can determine the upper performance limit of the LDPC code, and the error leveling layer of the LDPC code is determined according to the offset value in the base matrix. Improving the performance of the compiled code and reducing the error leveling layer is one of the goals of determining the base map and the base matrix.
  • the code length in the wireless communication system is flexible, for example, 40 bits, 1280 bits, etc., and FIGS. 3a, 3b-1 to 3b-8, and 3c are respectively an example of a base map and a base matrix of an LDPC code and its core matrix. It can meet the performance requirements of code blocks with block lengths from 20 to 2560 bits. For convenience of explanation and understanding, column numbers and line numbers are respectively shown on the uppermost side and the leftmost side in 3a, 3b-1 to 3b-8, and 3c in the drawing.
  • FIGS. 3a-3c is a schematic diagram showing the performance of the LDPC code shown in FIGS. 3a-3c.
  • the LDPC 1 indicates that the LDPC code is obtained based on the respective base matrix codes corresponding to the base map 30a, and the LDPC 2 indicates a commonly used LDPC code as a comparison.
  • the abscissa indicates the length of the information bit sequence, the unit is the bit, the ordinate is the symbol signal-to-noise ratio (Es/N0), and the performance curve is the BLER of 0.0001, and the LDPC 1 and LDPC 2 have symbol signals under different information bit sequence lengths. Noise ratio performance. It can be seen that under the same BLER, the symbol signal to noise ratio of LDPC 1 under different information bit sequence lengths is lower than that of LDPC 2, that is, the performance is better than LDPC 2.
  • Figure 3a shows an example of a base map 30a of an LDPC code, in which the top row 0-51 in the figure represents the column number, and the leftmost column 0-41 represents the row number, that is, the matrix size of the base map 30a is 42 rows 52. Column.
  • the sub-matrix B corresponds to a parity bit, and has a size of m A rows and m A columns, from the 0th row to the (m A -1) row and the 10th column to the (10+m A -1) column in the base map 30a.
  • Elemental composition
  • the submatrix A and the submatrix B constitute the core matrix portion of the LDPC code base map, that is, a matrix constituting a m A row (m A + n A ) column, which can be used for high bit rate encoding.
  • m A 7 as an example
  • the core matrix portion of the base map of the LDPC code is 7 rows and 17 columns.
  • the sub-matrix B includes one column and three columns of re-columns, that is, the 0th column of the sub-matrix B (the 10th column of the core matrix) has a column weight of 3, and the first to third columns of the sub-matrix B (the eleventh of the core matrix) To 13 columns), the 0th to 3th behaviors are double-diagonal structures, and the sub-matrix B also includes 3 columns of single-column weights.
  • the core matrix of the base map 30a includes two rows of rows having a weight of 10, two rows of weights of 8, two rows of weights of six, and one row of weights of four. . That is, the weights of the rows in the core matrix composed of the submatrix A and the submatrix B are 8, 10, 8, 10, 4, 6, and 6, respectively. It should be noted that the order of the rows in the core matrix can be exchanged, for example, the 0th row and the 2nd row are exchanged, the 1st row and the 3rd row are exchanged, and the like. One of the rows shown in the 0th to 6th rows and the 0th to 16th columns in the core matrix of the base map 30a, respectively.
  • the row exchange does not change the weight of the columns in the matrix
  • the column exchange does not change the weight of the rows in the matrix, and the number of non-zero elements in the matrix does not occur. changed.
  • the weight of each row of the base map after row exchange and column exchange has not changed. Basemaps that use row swapping, or column swapping, or row swapping and column swapping do not affect performance.
  • the performance does not affect the performance as a whole, the impact is acceptable, within the tolerance range, for example, the performance may be within the allowable range for some scenarios or within certain ranges, but In some scenarios or in certain areas, performance has improved and overall has little impact on performance.
  • a small amount of modification to the matrix elements is acceptable for performance.
  • a small number of modifications may be made based on the core matrix of the base map 30a, for example, where the weight of one row satisfies greater than or equal to 2 and is less than or equal to 5, and the weights of the remaining 6 rows respectively satisfy greater than or Equal to 6, and less than or equal to 12. It can be understood that the weights of some of the lines may be increased or decreased by 1-2 according to the solution provided by the present application, which is not limited in this application.
  • sub-matrices C, sub-matrices D, and sub-matrices E of corresponding sizes may be added based on the core matrix to obtain different code rates.
  • the sub-matrix C is an all-zero matrix
  • the sub-matrix is an identity matrix, and its size is mainly determined according to the code rate, and the structure is relatively fixed.
  • the main factors affecting the performance of the compiled code are the core matrix and the sub-matrix D part. Adding rows and columns on the basis of the core matrix to form corresponding C, D and E parts can obtain different code rates.
  • the core matrix portion of the base map 30a may be used as a core matrix, and corresponding sub-matrices C, D, and E are added to meet the requirements of different code rate encoding or decoding.
  • m A may also be any integer value of 4 to 7, and the number of columns of the matrix F also changes accordingly.
  • the two rows are orthogonal to each other. If the adjacent columns in the base map have only one non-zero element in the columns other than the partial columns, the two rows are quasi-orthogonal.
  • the matrix F may comprise a multi-row quasi-orthogonal structure and at least two rows of orthogonal structures.
  • the matrix F includes at least 15 rows conforming to a quasi-orthogonal structure, and in any of the adjacent two rows of the 15 rows, except for the built-in punched bit column, there is at most one non-zero element in the same column, that is, A matrix block composed of the remaining columns other than the built-in punctured bit columns in at least 15 rows of the matrix F has an orthogonal structure.
  • the matrix F may further comprise 10 to 20 rows of rows conforming to the orthogonal structure, that is, among the rows, any one of the adjacent columns has at most one non-zero element, that is, at most one non-integrated perforated bit string. Zero element.
  • the last 10 rows in the matrix F conform to the orthogonal structure, wherein the weight of the 9 rows is 3, and the weight of the 1 row is 2.
  • the column redistribution of the matrix F may be, wherein the weight of one column is 16, the weight of one column is 18, the weight of one column is 11, the weight of two columns is 10, the weight of one column is 9, and the weight of one column is 8.
  • the weight of the 1 column is 7, the weight of the 1 column is 6, the weight of the 2 columns is 4, the weight of the 1 column is 3, and the weight of the 2 columns is 2. If m A >4, the weights of the remaining columns in the matrix F are zero.
  • the row weights are 5, 3, 4, 4, 4, 3, 4, 4, 4, 3, 4, 4, 3, 3, respectively. 3,3,2,3,3,2,4,2,3,2,4,2,3,3,3,3,2,3,3,3,3.
  • the weight of each row in the base map 30a is 8, 10, 8, 10, 4, 6, 6, 6, 4, 5, 5, 5, 4, 5, 4, respectively. ,5,5,4,4,4,4,3,4,4,4,3,5,3,4,3,5,3,4,4,4,4,4,4,4,4 , 4.
  • the size of the sub-matrix D in the LDPC code base map is 15 rows and 17 columns, which may be the 0-14th row of the matrix F in the base map 30a, that is, the base map.
  • the 0th to the 31st columns constitute a matrix portion, wherein the sub-matrix E is an order matrix of 15 rows and 15 columns, and the sub-matrix C is an all-zero of 7 rows and 15 columns. matrix;
  • the size of the sub-matrix D in the LDPC code base map is 25 rows and 17 columns, which may be from lines 0-24 of the matrix F in the base map 30a, that is, the seventh row to the 31st line of the base map 30a.
  • the line is formed into the matrix portion of the 31st row, the 0th column to the 41st column, wherein the sub-matrix E is an element matrix of 25 rows and 25 columns, and the sub-matrix C is an all-zero matrix of 7 rows and 25 columns.
  • the base map of the LDPC code and the rows in the base matrix can be mutually exchanged, and the columns can also be exchanged with each other.
  • the 34th row and the 36th row of the base map 30a can be exchanged, and the 44th column and the 45th column can be exchanged.
  • the sub-matrix D includes m D rows in the matrix F. The m D rows may not be exchanged in rows, or one or more rows may be exchanged between rows, and the sub-matrix E is still a diagonal structure, and no row is performed.
  • the column swap for example, performs row swapping of the 27th and 29th rows of the matrix F, the submatrix D includes the m D rows in the matrix F, and the submatrix E is still a diagonal structure.
  • the matrix F is a quasi-orthogonal matrix before the row exchange, and is still a quasi-orthogonal matrix after the exchange. It can be understood that if the base map or the base matrix includes the sub-matrix D, when the columns of the core matrix are exchanged, the columns in the corresponding sub-matrix D also need to be exchanged.
  • the base matrices 30b-1 to 30b-8 shown in Figs. 3b-1 to 3b-8 are examples of a plurality of base matrices of the base map 30a.
  • the non-zero elements of the i-th row and the j-th column in the base map 30a are invariant in the matrices of the base matrices 30b-1 to 30b-8, and the values are offset values V i,j , and the zero elements are in the offset matrix. It is represented by -1 or null.
  • the sub-matrix D in the base portion corresponding matrix D may include m rows of the matrix F shift matrix, a different value may be selected according to the bit rate D m.
  • the offset matrix corresponding to the sub-matrix D is the m D row in the offset matrix of the matrix F.
  • the offset matrix of the matrix F may be the matrix shown in the 7th row to the 41st row and the 0th column to the 16th column in any of the 30b-1 to 30b-8 matrices.
  • a matrix after row/column transformation of the matrix; or an offset matrix of the matrix F may include rows 4 to 41 and columns 0 to 14 of any of the matrixes 30b-1 to 30b-8 The matrix shown, or the matrix after the row/column transformation of the matrix.
  • the base matrix corresponding thereto may be adopted based on the set of different spreading factors Z, respectively.
  • the above eight set indexes are only described by taking 1, 2, 3, 4, 5, 6, 7, and 8 as an example.
  • the index of the present application for each set is not limited.
  • 0, 1, 2, 3, 4, 5, 6, 7 can be used to represent 8 sets.
  • Other identifiable indexes can also be used to represent 8 sets.
  • Each set index corresponds to a base matrix. Taking the set of the spreading factor Z in Table 1 as an example, the spreading factor Z in different sets of spreading factors has different values. Z is determined, then the base matrix corresponding to Z is also determined. Therefore Z also corresponds to the base matrix.
  • the offset matrix of the matrix F may be the matrix shown in the 7th to 41st rows and the 0th column to the 16th column of 30b-1, or the row of the matrix /column transformed matrix; or the offset matrix of the matrix F may be the matrix shown in the 4th to 41st rows and the 0th column to the 14th column of 30b-1, or after the row/column transformation of the matrix Matrix.
  • the base matrix of the base map 30a may be a matrix represented by 30b-1, or a matrix after row/column transformation of the matrix;
  • the offset matrix of the matrix F may be the matrix shown in the 7th to 41st rows and the 0th column to the 16th column in 30b-2, or the row of the matrix /column transformed matrix; or the offset matrix of the matrix F may be the matrix shown in the 4th to 41st rows and the 0th column to the 14th column in 30b-2, or after the row/column transformation of the matrix Matrix.
  • the base matrix of the base map 30a may be a matrix represented by 30b-2, or a matrix after row/column transformation of the matrix;
  • the offset matrix of the matrix F may be the matrix shown in the 7th to 41st rows and the 0th column to the 16th column in 30b-3, or the row of the matrix /column transformed matrix; or the offset matrix of the matrix F may be the matrix shown in the 4th to 41st rows and the 0th column to the 14th column in 30b-3, or after the row/column transformation of the matrix Matrix.
  • the base matrix of the base map 30a may be a matrix represented by 30b-3, or a matrix after row/column transformation of the matrix;
  • the offset matrix of the matrix F may be the matrix shown in the 7th to 41st rows and the 0th column to the 16th column in 30b-4, or the row of the matrix /column transformed matrix; or the offset matrix of the matrix F may be the matrix shown in the 4th to 41st rows and the 0th column to the 14th column in 30b-4, or after the row/column transformation of the matrix Matrix.
  • the base matrix of the base map 30a may be a matrix represented by 30b-4, or a matrix after row/column transformation of the matrix;
  • the offset matrix of the matrix F may be the matrix shown in the 7th to 41st rows and the 0th column to the 16th column in 30b-5, or the row of the matrix /column transformed matrix; or the offset matrix of the matrix F may be the matrix shown in the 4th to 41st rows and the 0th column to the 14th column of 30b-5, or after the row/column transformation of the matrix Matrix.
  • the base matrix of the base map 30a may be a matrix represented by 30b-5, or a matrix after row/column transformation of the matrix;
  • the offset matrix of the matrix F may be the matrix shown in the 7th to 41st rows and the 0th column to the 16th column in 30b-6, or the row of the matrix. /column transformed matrix; or the offset matrix of the matrix F may be the matrix shown in the 4th to 41st rows and the 0th column to the 14th column in 30b-6, or after the row/column transformation of the matrix Matrix.
  • the base matrix of the base map 30a may be a matrix shown by 30b-6, or a matrix after row/column transformation of the matrix;
  • the offset matrix of the matrix F may be the matrix shown in the 7th to 41st rows and the 0th column to the 16th column in 30b-7, or the row of the matrix /column transformed matrix; or the offset matrix of the matrix F may be the matrix shown in the 4th to 41st rows and the 0th column to the 14th column in 30b-7, or after the row/column transformation of the matrix Matrix.
  • the base matrix of the base map 30a may be a matrix shown by 30b-7, or a matrix after row/column transformation of the matrix;
  • the offset matrix of the matrix F may be the matrix shown in the 7th to 41st rows and the 0th column to the 16th column in 30b-8, or the row of the matrix /column transformed matrix; or the offset matrix of the matrix F may be the matrix shown in the 4th to 41st rows and the 0th column to the 14th column in 30b-8, or after the row/column transformation of the matrix Matrix.
  • the base matrix of the base map 30a may be a matrix shown by 30b-8, or a matrix after row/column transformation of the matrix.
  • the value of the spreading factor Z is determined according to the length K of the input sequence. For example, if the input sequence length is K, the minimum value satisfying 10*Z ⁇ K can be determined as a matrix expansion among a plurality of system-defined spreading factors. The value of the factor. Further, the corresponding base matrix can be selected according to the determined spreading factor.
  • the rows in the base matrix are also interchangeable, and the columns can be exchanged. If the base map is exchanged by at least one of row switching or column switching, the base matrix of the corresponding portion is also exchanged the same.
  • the quasi-orthogonal structure in the present application is not limited to only two adjacent rows, and the matrix conforming to the quasi-orthogonal structure may also be designed to include multiple groups, and each group includes at least 2 rows, for example, 3 rows. Or 4 lines, etc., the lines included in each group are quasi-orthogonal.
  • LDPC 1 indicates that the LDPC code is obtained based on a base matrix code corresponding to the base map 30a
  • LDPC 2 indicates a commonly used LDPC code as a comparison, in which the abscissa indicates the information bit sequence.
  • the length is in bits
  • the ordinate is the symbol signal-to-noise ratio (Es/N0)
  • the performance curve is the performance of LDPC 1 and LDPC 2 under different information bit sequence lengths when the BLER is 0.01 and 0.0001, respectively. It can be seen that under the same BLER, the symbol signal to noise ratio of LDPC 1 under different information bit sequence lengths is lower than that of LDPC 2, that is, the performance is better than LDPC 2.
  • an encoder uses an LDPC matrix to encode an input sequence; a base map of the LDPC matrix may be any one of the foregoing examples, and a base matrix of the LDPC matrix may be the foregoing example. Any of the base matrices.
  • the input sequence of the encoder may be an information bit sequence, or may be an information bit sequence processed by at least one of the following: CRC bit addition or padding bit addition.
  • the method further includes: determining the expansion factor Z; determining the value of the expansion factor Z according to the length K of the input sequence.
  • Kb may be the number of columns of information bits in the base matrix of the LDPC code, and in the set of supported extension factors, find the smallest Z 0 as the size of the expansion factor Z, and satisfy Kb ⁇ Z 0 ⁇ K.
  • the set of spreading factors supported by the base map 30a is ⁇ 24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60 , 64, 72, 80, 88, 96, 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, 384 ⁇ .
  • the value of Kb may also vary according to the value of K, but does not exceed the number of information bit columns in the base matrix of the LDPC code.
  • different thresholds can be set for Kb.
  • thresholds 640, 560, 192 are merely examples. It can also be designed to other values based on system design requirements.
  • the spreading factor Z may be determined by the encoder according to the length K of the input sequence, or may be obtained by the encoder from other entities such as a processor.
  • the encoder encodes the input sequence using the LDPC matrix H.
  • the input sequence may be encoded using the LDPC matrix H corresponding to the spreading factor Z.
  • the input sequence c ⁇ c 0 , c 1 , c 2 , . . . , c K-1 ⁇
  • the length of the input sequence c is K
  • the input sequence c is encoded by the encoder.
  • the output sequence d ⁇ d 0 , d 1 , d 2 , . . . , d N-1 ⁇
  • the output sequence d includes K 0 bits in the input sequence c and check bits in the check sequence w.
  • K 0 is an integer greater than 0 and less than or equal to K, and the length of the check sequence w is NK 0 .
  • check bit sequence w and the input sequence c satisfy the formula (1):
  • c T [c 0 ,c 1 ,c 2 ,...,c K-1 ] T
  • 0 T is the column vector, where all elements have a value of zero.
  • H is an LDPC matrix obtained based on any of the base maps or base matrices exemplified in the foregoing embodiments, and the base map size of H is m rows and n columns, which may be the base map 30a exemplified in the foregoing embodiment.
  • the base map of H includes the p-column built-in punctured column, p is an integer greater than or equal to 0, and the information bits corresponding to the p-column built-in punctured column are not output, that is, the output sequence does not include p.
  • Bit the length of the check sequence w is N+2 ⁇ ZK
  • H 1 may be an all-zero matrix in which each zero element in H BG is replaced by a Z*Z size, and each non-zero element is replaced by a cyclic permutation matrix h i,j of a Z*Z size, wherein the cyclic permutation matrix h i , j is obtained by cyclically shifting the unit matrix of the Z*Z size to P i,j , and sometimes by I(P i,j ).
  • i is the line number and j is the column number.
  • P i,j mod(V i,j ,Z)
  • V i,j is the base matrix corresponding to the extension factor set index corresponding to Z.
  • H 2 may be obtained by replacing each zero element in H BG, EXT with an all-zero matrix of Z*Z size, and each non-zero element is replaced by an identity matrix of Z*Z size.
  • the encoder can be encoded and output in various ways.
  • the base diagram 30a exemplified in the foregoing embodiment is taken as an example.
  • the maximum number of base lines is 42 lines, and the maximum number of columns is 52 columns, including 2 columns of built-in.
  • a base map having the largest number of rows and the largest number of columns is sometimes referred to as a complete base map.
  • N (42+Kb) ⁇ Z
  • the information bits and check bits that need to be transmitted can be determined from the output sequence generated by the encoder in a subsequent processing step.
  • Partial row and column encoding based on the complete base map.
  • the row and column codes can be selected from the complete base map according to the code rate to be transmitted, or the number of information bits and the number of check bits.
  • the base map size of H is 4 ⁇ m ⁇ 42, 14 ⁇ n ⁇ 52, correspondingly for the LDPC matrix H, 4 ⁇ Z ⁇ M ⁇ 42 ⁇ Z, (4 + Kb) ⁇ Z ⁇ N ⁇ (42 +Kb) ⁇ Z.
  • Z is 13, and in the set 7, the input sequence is encoded by the LDPC matrix based on the base matrix 3b-7 corresponding to the set 7;
  • the base matrix of the factor Z can also be expanded, and the i-th row and the j-th column element P i,j satisfy the following relationship:
  • V i,j may be an offset value of an element of the i-th row and the j-th column in the base matrix of the set of Z, that is, a non-zero of the i-th row and the j-th column of the base matrix of the largest spreading factor in the set of Z The offset value of the element.
  • the element P i,j of the i-th row and the j-th column in the base matrix is satisfied.
  • V i,j is the offset value of the non-zero element of the i-th row and the j-th column in the base matrix 3b-7.
  • the base matrix H B of the LDPC matrix H may be any of the base matrices exemplified in the foregoing embodiments or may be changed in a row order or column order with respect to any of the base matrices exemplified above.
  • the description in the description will not be repeated here.
  • other base patterns may be used to conform to the base matrix of the base map 30a, and the present invention is not limited thereto.
  • the base matrix H B of the LDPC code may be stored in a memory, and the encoder obtains an LDPC matrix corresponding to the spreading factor Z, thereby encoding the input sequence.
  • the storage according to the matrix structure may occupy a large storage space, and the base map of the LDPC code may be stored in the memory, respectively. Or storing the offset values of the non-zero elements in each base matrix column by column, and then obtaining the LDPC matrix according to the offset values of the base matrix corresponding to the base map and the spreading factor Z.
  • the base map may indicate the location of the non-zero elements of each base matrix.
  • the save base map may be a location in which the non-zero elements are stored.
  • the position of a non-zero element can be indicated by the row and column in which the non-zero element is located, such as the position of the column in which the non-zero element is located in each row, or the position of the row in which the non-zero element is located in each column.
  • the save base map may also be a location in which the zero element is saved, and may also be indicated by the row and column in which the zero element is located.
  • the position of the column in which the zero element is located in each row, or the position of the row in which the zero element is located in each row, the position of the corresponding non-zero element can be obtained by excluding the position of the zero element. It should be noted that the present invention is merely an example, and the present invention is not limited thereto.
  • the parameters involved in the base or base matrix can be represented using a table.
  • related parameters or tables can be saved in one or more memories.
  • the base map or the base matrix can be obtained by reading the base number of the base map or the base matrix in the memory and the column where the non-zero element is located, and optionally, the row weight of each row can be saved, and each row can be saved.
  • the offset value of a non-zero element can be saved.
  • the parameters involved in the base map 30a can be represented using Table 2.
  • Table 3 only gives a schematic of 2 columns, and other columns can be deduced by analogy.
  • the 14th column to the 51st column are single column re-columns, and may not be saved, but the position of the row where the non-zero element is located is derived from the column number.
  • the parameters of “row weight” and “column weight” in Table 2 or Table 3 above may also be omitted. You can know how many non-zero elements are in this row or column by the column or row in which a non-zero element is located, so the row weight or column weight is known.
  • the parameter values in the column “Non-zero elements in the above table” in Table 3 may not be as small as large. Arrange in order, as long as the parameter value is indexed to the column in which the non-zero element is located, or to the row where the non-zero element is located.
  • a column of "non-zero element offset value” may also be included in Table 2 or Table 3, and a parameter value in the "non-zero element offset value” column and a column in which the non-zero element is located The parameter values in "one-to-one correspondence.
  • the column of "non-zero element offset value” may also be included, and the parameter value in the "non-zero element offset value” column corresponds to the parameter value in the "non-zero element row”.
  • the position of the non-zero element of the structure in the base map may be calculated according to the position of the row and column, and the position of the non-zero element may not be saved.
  • the sub-matrix E is a diagonal matrix, and only non-zero elements exist on the diagonal line.
  • the position of the column in which the non-zero element is located can be calculated according to the line number, and the row where the non-zero element is located can also be calculated according to the column number.
  • the position of the base map 30a is taken as an example.
  • the column in which the non-zero element in row 4 is located is the 14th column.
  • the double diagonal structure B′ in the sub-matrix B is located in the 0th to 3rd rows and the 11th to 13th columns in the base map 30a, and the position of the column in which the non-zero element is located can be calculated according to the line number, or according to the column. Number calculates the position of the row where the non-zero element is located.
  • the parameters involved in each row in the base map 30a can save the position of the column in which the non-zero elements in the 0th column to the 13th column are located, without saving the non-zero elements in the 14th column to the 52nd column.
  • the position of the column that is, the column in which the non-zero element in the single-column column is not stored, can be used to represent H BG2 with 14 columns:
  • the 0th to 3rd rows and the 5th to 41st rows are the same as in Table 4, and the row weight of the 4th row is the row of the 4th row in Table 4. 1, that is, 4, the column where the non-zero element is located is the column where the non-zero element in the fourth row of Table 4 is located, and then a column with the column number of 14, that is, 0, 1, 11, 14 is added.
  • the 0th to 3rd rows and the 6th to 41st rows are the same as in Table 4, and the row weight of the 4th row is 1 in the row of the 4th row in Table 4.
  • the column where the non-zero element is located is the column where the non-zero element in the 4th row of Table 4 is located, and then the position of the column number is 14, that is, 0, 1, 11, 14; the row weight of the 5th row is The row in the fifth row of Table 4 is incremented by 1, which is 6, the column where the non-zero element is located is the column of the non-zero element in the fifth row of Table 4, and a column with the column number of 15, that is, 0, 1 , 5, 7, 11, 15.
  • the 0th to 3rd rows and 7th to 41st rows are the same as in Table 4, and the row weight of the 4th row is 1 in the row of the 4th row in Table 4. That is, 4, the column where the non-zero element is located is the column where the non-zero element in the 4th row of Table 4 is located, and then the position of the column number is 14, that is, 0, 1, 11, 14; the row weight of the 5th row is The row in the fifth row of Table 4 is incremented by 1, which is 6, the column where the non-zero element is located is the column of the non-zero element in the fifth row of Table 4, and a column with the column number of 15, that is, 0, 1 , 5,7,11,15; the row weight of row 6 is the row of row 6 in table 4 plus 1, which is 6, the column of non-zero elements is the non-zero element in row 6 of table 4. The column is further incremented by a column number of 16, that is, 0, 5, 7, 9, 11,
  • each row can store the position of the first 26 columns or the first 27 columns of non-zero elements in four hexadecimal numbers.
  • the first 14 columns of the 0th row are 11110010 011100, which can be recorded as the first
  • the position of the 0-line non-zero element is 0xF2, 0x70, that is, every 8 columns constitute a hexadecimal number.
  • the corresponding hexadecimal number can be obtained by padding 0 to an integer multiple of 8 bits.
  • It can also be padded with 0 to an integer multiple of 8 bits to get the corresponding hexadecimal number.
  • Other lines and so on are not repeated here.
  • the coded LDPC matrix H can be obtained by expanding the base matrix H B according to Z.
  • a cyclic permutation matrix h i,j of Z*Z size is determined, where h i,j is a cycle obtained by cyclically shifting the unit matrix through P i, j times Substituting a matrix, replacing h i,j with a non-zero element P i,j , replacing the zero-element in the base matrix H B with an all-zero matrix of Z*Z size, thereby obtaining a parity check matrix H;
  • the LDPC code can be obtained by encoding by the above method.
  • the communication device may perform one or more operations of performing rate matching on the LDPC code, interleaving the rate matched LDPC code according to the interleaving scheme, and modulating the interleaved LDPC code according to the modulation scheme.
  • Bit sequence B transmit bit sequence B.
  • a decoder decodes an input sequence by using an LDPC matrix; a base map of the LDPC matrix may be any base diagram in the foregoing example, and a base matrix of the LDPC matrix H B may be any of the base matrices in the foregoing examples.
  • the input sequence of the decoder may be a soft value sequence of the LDPC code.
  • the method further includes: determining an expansion factor Z.
  • the communication device at the receiving end can receive the signal including the LDPC code based, obtain the soft value sequence of the LDPC code therein, and determine the corresponding spreading factor Z.
  • the decoder uses the LDPC matrix to decode the input sequence.
  • the LDPC matrix corresponding to the spreading factor Z may be used to decode the soft value sequence of the LDPC code.
  • the LDPC matrix base matrix H B may be any of the base matrices exemplified in the foregoing embodiments or may be transformed in a row order or a column order, or a row order and a column order, with respect to any of the base matrices exemplified above.
  • the base map includes at least the sub-matrix A and the sub-matrix B, and may also include the sub-matrix C, the sub-matrix D, and the sub-matrix E.
  • the base map includes at least the sub-matrix A and the sub-matrix B, and may also include the sub-matrix C, the sub-matrix D, and the sub-matrix E.
  • the base matrix H B of the LDPC code may be stored in the memory, and the LDPC matrix corresponding to the extension factor Z may be used to decode the soft value of the LDPC code;
  • the storage according to the matrix structure may occupy a large storage space, and the base map of the LDPC code may be stored in the memory, respectively, row by row or by row.
  • the column holds the offset values of the non-zero elements in each base matrix, and then obtains the LDPC matrix according to the offset values of the base matrix corresponding to the base map and the spreading factor Z.
  • the storage manner of the base map can also be stored in various ways as described in the foregoing encoding embodiment. It should be noted that the examples herein are merely examples and are not intended to be limiting.
  • Decoding coded reverse process which uses a base matrix H B has the same features in the base matrix of the encoding method embodiment.
  • An extension of the base matrix H B to obtain the LDPC matrix H can also be referred to the coding method embodiment.
  • the communication device may further perform one or more operations of: receiving a signal including LDPC encoding, demodulating, deinterleaving, and de-rate matching the signal to obtain a soft value of the LDPC code. .
  • the base matrix H B may be obtained based on the parameters; for example, the parameters may include one or more of the following: a base matrix The offset value in , or, the spreading factor, or the base map of the base matrix, or the code rate, etc.
  • the row/column transformation refers to a row transformation, or a column transformation, or a row transformation and a column transformation
  • the input sequence is encoded by using a low-density parity check LDPC matrix, which may be performed in one or more of the following manners during encoding or decoding:
  • . i H B base matrix is obtained based on the above a), based on the obtained base matrix H B coding or decoding; for row / column exchange or base matrix obtained based on H B, based on the row / column of the basis matrix encoded transform or translation code.
  • the base matrix based extended matrix coding or decoding may also be included;
  • the preservation referred to in this application may be stored in one or more memories.
  • the one or more memories may be separate settings, or may be integrated in an encoder or decoder, a processor, a chip, a communication device, or a terminal.
  • the one or more memories may be separately provided in a part, and the part may be integrated in a decoder, a processor, a chip, a communication device, or a terminal.
  • the type of the memory may be any form of storage medium, and the present application does not limited.
  • FIG. 5 is a schematic structural diagram of a communication device 500.
  • the device 500 can be used to implement the method described in the foregoing method embodiments. For details, refer to the description in the foregoing method embodiments.
  • the communication device 500 can be a chip, a base station, a terminal, or other network device.
  • the communication device 500 includes one or more processors 501.
  • the processor 501 can be a general purpose processor or a dedicated processor or the like. For example, it can be a baseband processor, or a central processing unit.
  • the baseband processor can be used to process communication protocols and communication data
  • the central processor can be used to control communication devices (eg, base stations, terminals, or chips, etc.), execute software programs, and process data of the software programs.
  • the communication device 500 includes one or more of the processors 501, the one or more processors 501 can implement the functions of the encoder described above, and in another possible design, The above encoder may be part of the processor 501, and the processor 501 may implement other functions in addition to the functions of the encoder.
  • the communication device 500 encodes an input sequence using an LDPC matrix;
  • the base map of the LDPC matrix may be any of the base diagrams in the foregoing examples or may be sequentially changed in a row order or column order with respect to any of the base diagrams exemplified above.
  • a base map in which a transform occurs, or both a row order and a column order are transformed, and the base matrix H B of the LDPC matrix may be any of the base matrices in the foregoing embodiments or may occur in a row order with respect to any of the base matrices exemplified above.
  • the input sequence of the encoder may be an information bit sequence.
  • one or more of the processors 501 may implement the functions of the decoder described above, and in another possible design, the decoder may be part of the processor 501.
  • the communication device 500 can be configured to decode an input sequence by using an LDPC matrix; the base map of the LDPC matrix can be any one of the foregoing examples or a row sequence change with respect to any of the base diagrams exemplified above, Alternatively, the column order may be transformed, or the base sequence in which the row order and the column order are transformed, and the base matrix H B of the LDPC matrix may be any of the base matrix in the foregoing example or relative to any of the base matrixes exemplified above. A base matrix in which the order is transformed, or the column order is transformed, or both the row order and the column order are transformed.
  • the input sequence of the decoder may be a soft value sequence.
  • the processor 501 can also include instructions 503 that can be executed on the processor such that the communication device 500 performs the methods described in the above method embodiments.
  • the communication device 500 can also include circuitry that can implement the functions of the encoder, or decoder, or encoder and decoder in the foregoing method embodiments.
  • the communication device 500 may include one or more memories 502 on which the instructions 504 are stored, and the instructions may be executed on the processor, so that the communication device 500 performs the above method embodiment.
  • data may also be stored in the memory. Instructions and/or data can also be stored in the optional processor.
  • the processor and the memory may be provided separately or integrated.
  • the one or more memories 502 may store parameters related to the base matrix, such as offset values, base maps, extensions based on the base map to the matrix, rows in the base matrix, spreading factors, and the like.
  • the one or more memories 502 may store a base matrix or expand to a matrix based on a base matrix.
  • the communication device 500 may further include a transceiver 505 and an antenna 506.
  • the processor 501 may be referred to as a processing unit to control a communication device (terminal or base station).
  • the transceiver 505 can be referred to as a transceiver unit, a transceiver, a transceiver circuit, or a transceiver, etc., for implementing the transceiver function of the communication device through the antenna 506.
  • the communication device 500 may further include a device for generating a transport block CRC, a device for code block splitting and CRC check, an interleaver for interleaving, a modulator for modulation processing, and the like.
  • the functionality of these devices may be implemented by one or more processors 501.
  • the communication device 500 may further include a demodulator for demodulation operation, a deinterleaver for deinterleaving, or a device for de-rate matching, and the like.
  • the functionality of these devices may be implemented by one or more processors 501.
  • FIG. 6 shows a schematic diagram of a communication system 600 that includes a communication device 60 and a communication device 61 in which information data is received and transmitted between the communication device 60 and the communication device 61.
  • the communication devices 60 and 61 may be the communication device 500, or the communication device device 60 and the communication device 500, respectively, for receiving and transmitting information data.
  • communication device 60 can be a terminal, and corresponding communication device 61 can be a base station; in another example, communication device 60 is a base station and corresponding communication device 61 can be a terminal.
  • a general purpose processor may be a microprocessor.
  • the general purpose processor may be any conventional processor, controller, microcontroller, or state machine.
  • the processor may also be implemented by a combination of computing devices, such as a digital signal processor and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a digital signal processor core, or any other similar configuration. achieve.
  • the steps of the method or algorithm described in the embodiments of the present invention may be directly embedded in hardware, instructions executed by a processor, or a combination of the two.
  • the memory can be RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium in the art.
  • the memory can be coupled to the processor such that the processor can read information from the memory and can write information to the memory.
  • the memory can also be integrated into the processor.
  • the processor and the memory may be disposed in an ASIC, and the ASIC may be disposed in the UE. Alternatively, the processor and memory may also be located in different components in the UE.
  • the present invention can be implemented in hardware, firmware implementation, or a combination thereof.
  • a software program it may be implemented in whole or in part in the form of a computer program product comprising one or more computer instructions.
  • the processes or functions described in accordance with embodiments of the present invention are generated in whole or in part.
  • the functions described above may also be stored in or transmitted as one or more instructions or code on a computer readable medium.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
  • Computer readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another.
  • a storage medium may be any available media that can be accessed by a computer.
  • computer readable media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage media or other magnetic storage device, or can be used for carrying or storing in the form of an instruction or data structure.
  • Any connection may suitably be a computer readable medium.
  • a disk and a disc include a compact disc (CD), a laser disc, a compact disc, a digital versatile disc (DVD), a floppy disk, and a Blu-ray disc, wherein the disc is usually magnetically copied, and the disc is The laser is used to optically replicate the data. Combinations of the above should also be included within the scope of the computer readable media.

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Abstract

本申请公开了编码方法，装置、通信设备和通信系统。该方法包括：使用低密度奇偶校验LDPC矩阵对输入比特序列进行编码；其中，所述LDPC矩阵是基于基图得到的，所述基图包括子矩阵A、B、C、D和E，其中，所述子矩阵A为m A行n A列的矩阵，m A、n A为正整数，且4≤m A≤7，n A＝10；所述子矩阵B为m A行m A列的矩阵，所述子矩阵B包括权重为3的列和双对角结构的子矩阵B'；所述子矩阵D包括矩阵F中m D行，所述矩阵F为m F行(m A+n A)列的矩阵，m D、m F为正整数，0≤m D≤m F，35≤m F≤38；所述子矩阵C为m A行m D列的全0矩阵；所述子矩阵E为m D行m D列的单位矩阵。本申请的编码方法、装置、通信设备和通信系统，能够支持多种长度的信息比特序列的编码需求。

Description

信息处理的方法和通信装置 技术领域
本发明实施例涉及通信领域，尤其涉及信息处理的方法和通信装置。
背景技术
低密度奇偶校验(low density parity check，LDPC)码是一类具有稀疏校验矩阵的线性分组编码，具有结构灵活，译码复杂度低的特点。由于它采用部分并行的迭代译码算法，从而比传统的Turbo码具有更高的吞吐率。LDPC码可用于通信系统的纠错码，从而提高信道传输的可靠性和功率利用率。LDPC码还可以广泛应用于空间通信、光纤通信、个人通信系统、ADSL和磁记录设备等。目前在第五代移动通信中已考虑采用LDPC码作为信道编码方式之一。
实际使用过程中，可以采用具有特殊结构化特征的LDPC矩阵。该具有特殊结构化特征的LDPC矩阵H可以由准循环(quasi cycle，QC)结构的LDPC基矩阵扩展得到。
通常情况下，待编码的信息比特序列长度从几十到上百不等，通信系统要求的码率也灵活多变。如何支持多种长度的信息比特序列的编码，符合系统的码率要求，成为一个需要解决的问题。
发明内容
本发明实施例提供了一种信息处理的方法、通信装置和系统，可以支持多种长度的信息比特序列的编码和译码，符合系统灵活的码长码率要求。
第一方面，提供了一种编码方法及编码器，所述编码器使用低密度奇偶校验LDPC矩阵对输入序列进行编码。
第二方面，提供了一种译码方法及译码器，所述译码器使用低密度奇偶校验LDPC矩阵对输入序列进行译码。
在上述第一方面或第二方面的第一种实现方式中：所述LDPC矩阵是基于基图得到的，所述基图包括子矩阵A、B、C、D和E，其中，
所述子矩阵A为m A行n A列的矩阵，m A、n A为正整数，且4≤m A≤7，n A＝10；
所述子矩阵B为m A行m A列的矩阵，所述子矩阵B包括权重为3的列和双对角结构的子矩阵B’；
所述子矩阵D包括矩阵F中m D行，所述矩阵F为m F行(m A+n A)列的矩阵，m D、m F为正整数，0≤m D≤m F，35≤m F≤38；
所述子矩阵C为m A行m D列的全0矩阵；
所述子矩阵E为m D行m D列的单位矩阵。
基于上述实现方式，在一种可能的实现方式中，所述基图的最后10行中任意相邻两行是正交。
基于上述实现方式，在一种可能的实现方式中，所述基图的最后10行中包括至少5组，所述至少5组中每一组包括至少2行，所述至少2行是正交的。
基于上述任一实现方式，在一种可能的实现方式中，所述矩阵F中9行的权重为3,1行的权重为2。
一种设计中，所述矩阵F中，其中1列的权重为16，1列的权重为18，1列权重为11,2列的权重为10,1列的权重为9,1列的权重为8,1列的权重为7,1列的权重为6,2列的权重为4,1列的权重为3,2列的权重为2。
基于第一种实现方式，在又一种可能的实现方式中，所述矩阵F中符合正交结构的行数大于或者等于10，且，所述矩阵F中，其中1列的权重为16，1列的权重为18，1列权重为11,2列的权重为10,1列的权重为9,1列的权重为8,1列的权重为7,1列的权重为6,2列的权重为4,1列的权重为3,2列的权重为2。
又一种设计中，所述矩阵F中，9行的权重为3，1行的权重为2。
又一种设计中，所述矩阵F包括至少10行，所述至少10行中任意相邻两行是正交。
又一种设计中，所述矩阵F包括至少5组，所述至少5组中每一组包括至少2行，所述至少2行是正交的。可选地，所述至少2行可以是连续的行。例如，所述至少10行可以是基图30a的最后10行。
在上述任一实现方式中，若m A＞4，所述矩阵F中其余列的权重为0。
例如，矩阵F中符合正交结构的10行中可以包括如基图30a中第25行至第34行以及第0列至第13列组成的矩阵块的各行或者各列，或者，矩阵F中符合正交结构的10行中可以包括如基图30a中第25行至第34行以及第0列至第16列组成的矩阵块的各行或者各列。其中矩阵F中各行之间可以交换，各列之间也能相互交换。
基于上述实现方式，基图30a的基矩阵可以为如基矩阵30b-1、30b-2、30b-3、30b-4、30b-5、30b-6、30b-7和30b-8中任一个矩阵，或是该矩阵的行/列变换后的矩阵。
基于上述实现方式，矩阵F的偏移矩阵可以30b-1至30b-8中任一矩阵中第7行至第41行以及第0列至第16列所示的矩阵，或者是该矩阵的行/列变换后的矩阵；或者矩阵F的偏移矩阵可以包括30b-1至30b-8中任一矩阵中第4行至第41行以及第0列至第14列所示的矩阵，或者是该矩阵的行/列变换后的矩阵。
为了支持不同块长，LDPC码需要不同的扩展因子Z，基于前述实现方式，在一种可能的实现方式中，基于不同的扩展因子Z采用与之对应的基矩阵。例如，Z＝a×2 j，a∈{2,3,5,7,9,11,13,15}，
若扩展因子Z＝2×2 j，j＝0,1,2,3,4,5,6,7中的一个，则矩阵F的偏移矩阵可以是30b-1中第7行至第41行以及第0列至第16列所示的矩阵，或者是该矩阵的行/列变换后的矩阵；或者矩阵F的偏移矩阵可以是30b-1中第4行至第41行以及第0列至第14列所示的矩阵，或者是该矩阵的行/列变换后的矩阵。相应地，基图30a的基矩阵可以是30b-1所示的矩阵，或者是该矩阵的行/列变换后的矩阵。
若扩展因子Z＝3×2 j，j＝0,1,2,3,4,5,6,7中的一个，则矩阵F的偏移矩阵可以是30b-2中第7行至第41行以及第0列至第16列所示的矩阵，或者是该矩阵的行/列变换后的矩阵；或者矩阵F的偏移矩阵可以是30b-2中第4行至第41行以及第0列至第14列所示的矩阵，或者是该矩阵的行/列变换后的矩阵。相应地，基图30a的基矩阵可以是30b-2所示的矩阵，或者是该矩阵的行/列变换后的矩阵。
若扩展因子Z＝5×2 j，j＝0,1,2,3,4,5,6中的一个，则矩阵F的偏移矩阵可以是30b-3中第7行至第41行以及第0列至第16列所示的矩阵，或者是该矩阵的行/列变换后的矩阵；或者矩阵F的偏移矩阵可以是30b-3中第4行至第41行以及第0列至第14列所示的矩阵，或者是该矩阵的行/列变换后的矩阵。相应地，基图30a的基矩阵可以是30b-3所示的矩阵，或者是该矩阵的行/列变换后的矩阵。
若扩展因子Z＝7×2 j，j＝0,1,2,3,4,5中的一个，则矩阵F的偏移矩阵可以是30b-4中第7行至第41行以及第0列至第16列所示的矩阵，或者是该矩阵的行/列变换后的矩阵；或者矩阵F的偏移矩阵可以是30b-4中第4行至第41行以及第0列至第14列所示的矩阵，或者是该矩阵的行/列变换后的矩阵。相应地，基图30a的基矩阵可以是30b-4所示的矩阵，或者是该矩阵的行/列变换后的矩阵。
若扩展因子Z＝9×2 j，j＝0,1,2,3,4,5中的一个，则矩阵F的偏移矩阵可以是30b-5中第7行至第41行以及第0列至第16列所示的矩阵，或者是该矩阵的行/列变换后的矩阵；或者矩阵F的偏移矩阵可以是30b-5中第4行至第41行以及第0列至第14列所示的矩阵，或者是该矩阵的行/列变换后的矩阵。相应地，基图30a的基矩阵可以是30b-5所示的矩阵，或者是该矩阵的行/列变换后的矩阵。
若扩展因子Z＝11×2 j，j＝0,1,2,3,4,5中的一个，则矩阵F的偏移矩阵可以是30b-6中第7行至第41行以及第0列至第16列所示的矩阵，或者是该矩阵的行/列变换后的矩阵；或者矩阵F的偏移矩阵可以是30b-6中第4行至第41行以及第0列至第14列所示的矩阵，或者是该矩阵的行/列变换后的矩阵。相应地，基图30a的基矩阵可以是30b-6所示的矩阵，或者是该矩阵的行/列变换后的矩阵。
若扩展因子Z＝13×2 j，j＝0,1,2,3,4中的一个，则矩阵F的偏移矩阵可以是30b-7中第7行至第41行以及第0列至第16列所示的矩阵，或者是该矩阵的行/列变换后的矩阵；或者矩阵F的偏移矩阵可以是30b-7中第4行至第41行以及第0列至第14列所示的矩阵，或者是该矩阵的行/列变换后的矩阵。相应地，基图30a的基矩阵可以是30b-7所示的矩阵，或者是该矩阵的行/列变换后的矩阵。
若扩展因子Z＝15×2 j，j＝0,1,2,3,4中的一个，则矩阵F的偏移矩阵可以是30b-8中第7行至第41行以及第0列至第16列所示的矩阵，或者是该矩阵的行/列变换后的矩阵；或者矩阵F的偏移矩阵可以是30b-8中第4行至第41行以及第0列至第14列所示的矩阵，或者是该矩阵的行/列变换后的矩阵。相应地，基图30a的基矩阵可以是30b-8所示的矩阵，或者是该矩阵的行/列变换后的矩阵。
进一步地，可选地，基于上述实现方式，对于各扩展因子Z，还可以根据上述各集合的基矩阵得到Z的基矩阵中第i行第j列元素P i,j＝f(V i,j,Z)，其中，V i,j是该扩展因子Z所在集合的基矩阵中第i行第j列元素。
例如，
Figure PCTCN2018091423-appb-000001
在又一种可能的实现方式中，基图或者基矩阵还可以包括至少1列内置打孔比特列。
上述各实现方式中的LDPC矩阵的基图和基矩阵可以满足块长为20至2560比特的码块的 性能需求。
基于上述各方面，或者各方面任一种可能的实现方式，在又一种可能的实现方式中，还包括：确定扩展因子Z。例如，根据输入序列的长度K来确定扩展因子Z的取值，如：若输入序列长度为K，可以在多个系统定义的扩展因子中确定满足10*Z≥K的最小值。
可选地，LDPC矩阵可以基于Z对应的基矩阵得到，或者，基于Z的偏移矩阵得到。
对于发送端的通信设备，使用LDPC矩阵对所述输入序列进行编码包括：
使用扩展因子Z对应的LDPC矩阵对所述输入序列进行编码；或者扩展因子Z对应的LDPC矩阵经过了行/列变换，使用行/列变换后的矩阵对输入序列进行编码后的矩阵对所述输入序列进行编码。本申请中行/列变换是指行变换、列变换、或者行变换和列变换。
对于接收端的通信设备，使用LDPC矩阵对输入序列进行译码包括：
使用扩展因子Z对应的LDPC矩阵对输入序列进行译码；或者扩展因子Z对应的LDPC矩阵经过了行/列变换，使用行/列变换后的矩阵对输入序列进行编码后的矩阵对所述输入序列进行编码。本申请中行/列变换是指行变换、列变换、或者行变换和列变换。
在一种可能的实现方式中，可以保存LDPC矩阵，使用该LDPC矩阵对输入序列进行编码，或者基于该LDPC矩阵进行变换(行/列变换)或扩展获得可用于编码的LDPC矩阵。
在另一种可能的实现方式中，可以保存参数，依据所述参数可以获得用于编码或者译码的LDPC矩阵，从而可以基于LDPC矩阵对输入序列进行编码或者译码。所述参数包括以下至少之一：基图、基矩阵、基于基图或基矩阵行/列变换后的变换矩阵、基于基图或基矩阵的扩展矩阵、基矩阵中非零元素的偏移值、或者与获得LDPC矩阵相关的任何参数。
在又一种可能的实现方式中，LDPC矩阵的基矩阵可以保存在存储器中。
在又一种可能的实现方式中，LDPC矩阵的基图保存在存储器中，LDPC矩阵的基矩阵中非零元素的偏移值可以保存在存储器中。
基于上述各可能的实现方式，在一种可能的设计中，用于LDPC编码或者译码的基图和基矩阵中至少一个是上述LDPC矩阵的基图和基矩阵中至少一个经过行交换、或者列交换、或者行交换和列交换后得到的。
第三方面，提供一种通信装置可以包含用于执行上述方法设计中相对应的模块。所述模块可以是软件和/或是硬件。
在一个可能的设计中，第三方面提供的通信装置，包括处理器和收发组件，该处理器和收发组件可用于实现上述编码或者译码方法中各部分的功能。在该设计中，如果该通信装置是终端、基站或者其他网络设备，其收发组件可以是收发机，如果该通信装置是基带芯片或基带单板，其收发组件可以是基带芯片或基带单板的输入/输出电路，用于实现输入/输出信号的接收/发送。所述通信装置可选的还可以包括存储器，用于存储数据和/或指令。
在一种实现方式中，所述处理器可以包括如上述第一方面所述的编码器以及确定单元。所述确定单元用于确定对输入序列编码所需的扩展因子Z。所述编码器用于使用所述扩展因子Z对应的LDPC矩阵对所述输入序列进行编码。
在另一种实现方式中，所述处理器可以包括如上述第二方面所述的译码器以及获取单元。 所述获取单元用于获取LDPC码的软值和扩展因子Z。所述译码器用于基于扩展因子Z对应的基矩阵H B对LDPC码的软值译码得到信息比特序列。
第四方面，提供了一种通信装置，包括一个或多个处理器。
在一种可能的设计中，一个或多个所述处理器可实现第一方面所述编码器的功能，在另一种可能的设计中，第一方面所述编码器可以是所述处理器的一部分，处理器除了实现第一方面所述编码器的功能，还可以实现其他功能。
在一种可能的设计中，一个或多个所述处理器可实现第二方面所述译码器的功能，在另一种可能的设计中，第二方面所述译码器可以是所述处理器的一部分。
可选地，所述通信装置还可以包括收发器以及天线。
可选的，所述通信装置还可以包括用于产生传输块CRC的器件、用于码块分割和CRC校验的器件、用于交织的交织器、或者用于调制处理的调制器等。
可选的，所述通信装置还可以包括，用于解调操作的解调器、用于解交织的解交织器、或者用于解速率匹配的器件等等。可以通过一个或多个处理器实现这些器件的功能。
在一种可能的设计中，可以通过一个或多个处理器实现这些器件的功能。
附图说明
图1为一LDPC码的基图、基矩阵及其循环置换矩阵的示意图；
图2为一LDPC码的基图的结构示意图；
图3a为本发明一实施例提供的LDPC码基图的示意图；
图3b-1为图3a所示的基图的基矩阵的示意图；
图3b-2为图3a所示的基图的又一基矩阵的示意图；
图3b-3为图3a所示的基图的又一基矩阵的示意图；
图3b-4为图3a所示的基图的又一基矩阵的示意图；
图3b-5为图3a所示的基图的又一基矩阵的示意图；
图3b-6为图3a所示的基图的又一基矩阵的示意图；
图3b-7为图3a所示的基图的又一基矩阵的示意图；
图3b-8为图3a所示的基图的又一基矩阵的示意图；
图4为本发明另一实施例提供的性能示意图；
图5为本发明另一实施例提供的信息处理装置的结构示意图；
图6为本发明另一实施例提供的通信系统的示意图。
具体实施方式
为便于理解下面对本申请中涉及到的一些名词做些说明。
本申请中，名词“网络”和“系统”经常交替使用，“装置”和“设备”也经常交替使用，但本领域的技术人员可以理解其含义。“通信装置”可以是芯片(如基带芯片，或者数据信号处理芯片，或者通用芯片等等)，终端，基站，或者其他网络设备。终端是一种具有通信功能 的设备，可以包括具有无线通信功能的手持设备、车载设备、可穿戴设备、计算设备或连接到无线调制解调器的其它处理设备等。在不同的网络中终端可以叫做不同的名称，例如：用户设备，移动台，用户单元，站台，蜂窝电话，个人数字助理，无线调制解调器，无线通信设备，手持设备，膝上型电脑，无绳电话，无线本地环路台等。为描述方便，本申请中简称为终端。基站(base station，BS)，也可称为基站设备，是一种部署在无线接入网用以提供无线通信功能的设备。在不同的无线接入系统中基站的叫法可能有所不同，例如在而在通用移动通讯系统(Universal Mobile Telecommunications System，UMTS)网络中基站称为节点B(NodeB),而在LTE网络中的基站称为演进的节点B(evolved NodeB，eNB或者eNodeB)，在新空口(new radio,NR)网络中的基站称为收发点(transmission reception point，TRP)或者下一代节点B(generation nodeB，gNB)，或者其他各种网络中的基站也可能采用其他叫法。本发明并不限于此。
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行描述。
LDPC码通常可以用奇偶校验矩阵H来表示。LDPC码的奇偶校验矩阵H可以通过基图(base graph)和偏移(shift)值得到。基图通常可以包括m*n个矩阵元素(entry)，可以用m行n列的矩阵形式表示，矩阵元素的值为0或1，其中值为0的元素，有时候也称之为零元素，表示该元素可以被Z*Z的全零矩阵(zero matrix)替换，值为1的元素，有时候也称之为非零元素，表示该元素可以被Z*Z的循环置换矩阵(circulant permutation matrix)替换。也就是说，每个矩阵元素代表的是一个全零矩阵或者一个循环置换矩阵。如图1中10a所示为一个示例性的m＝4，n＝20具有QC结构的LDPC码的基图中的各元素。需要说明的是，在本文中，基图和矩阵的行号和列号均是从0开始编号的，仅仅是为了方便理解。可以理解的是，行号和列号也可以从1开始编号，则相应的行号和列号在本文所示的行号和列号基础上加1。
若基图中第i行第j列的元素值为1，其偏移值为P i,j，P i,j为大于或者等于0的整数，则表示第i行第j列的值为1的元素可以被P i,j对应的Z*Z的循环置换矩阵替换，该循环置换矩阵可通过将Z*Z的单位矩阵进行P i,j次向右循环移位得到。可见，将基图中每个值为0的元素用Z*Z的全零矩阵替换，每个值为1的元素采用其偏移值对应的Z*Z的循环置换矩阵进行替换，则可以得到LDPC码的奇偶校验矩阵。所述LDPC码的奇偶校验矩阵H也可以称为LDPC矩阵。基图可用于指示偏移值的位置，基图中的非零元素与偏移值对应。Z为正整数，也可以称之为扩展(lifting)因子，有时也可以称之为lifting size，或者lifting factor等，可以根据系统支持的码块大小和信息数据的大小确定的。可见奇偶校验矩阵H的大小为(m*Z)*(n*Z)。例如，扩展因子Z＝4，则每个零元素被一个4*4大小的全0矩阵11a替换，若P 2,3＝2，则第2行第3列的非0元素被4*4的循环置换矩阵11d替换，该矩阵是由4*4的单位矩阵11b经过2次向右循环移位得到的，若P 2,4＝0，则第2行第4列的非0元素被单位矩阵11b替换。需要说明的是，此处仅仅只是举例说明，并不以此为限制。
由于P i,j可以是基于扩展因子Z得到的，对于同一个位置上值为1的元素，采用不同的扩展因子Z可能存在不同的P i,j。为了简化实现，通常系统也会定义一个m*n的基矩阵(base matrix)，在基矩阵中每个元素和基图中每个元素的位置一一对应，基图中的零元素在基矩阵中位置不 变，采用-1表示，基图中第i行第j列值为1的非零元素在基矩阵中位置不变，可表示为V i,j，V i,j可以是相对于一个预定或者特定的扩展因子Z定义的偏移值，例如，是相对于扩展因子Z所在集合中最大扩展因子Z max的偏移值，则，其中V i,j可以是采用Z所在集合中最大扩展因子Z max时第i行第j列的非0元素的偏移值。在本申请实施例中，有时也将基矩阵称为基图矩阵的偏移矩阵。
P i,j可以基于V i,j和Z得到。例如，可以表示成P i,j＝f(V i,j,Z)，其中f(V i,j,Z)表示以V i,j和Z为参数的函数。例如，
Figure PCTCN2018091423-appb-000002
如图1中10b所示为基图10a对应的一个基矩阵。
通常LDPC码的基图或基矩阵中还可以包括p列内置打孔(built-in puncture)比特列，p可以为0-2的整数，这些列参与编码，但是其编码对应的系统比特不被发送，则LDPC码基矩阵的码率满足R＝(n-m)/(n-p)。对于一个4行20列(4*20)的基矩阵来讲，如果有2列内置打孔比特列，则码率为(20-4)/(20-2)＝8/9。
无线通信系统中采用的LDPC码，其基图的矩阵大小为m*n，可以包括5个子矩阵A、B、C、D和E，其中，矩阵的权重是由非零元素的个数决定的，行的权重(行重)是指一行中包括的非零元素的个数，列的权重(列重)是指一列中包括的非零元素的个数。如图2中200所示，其中：
子矩阵A为m A行n A列的矩阵，其大小可以为m A*n A，其中每列对应LDPC码中的Z个系统比特，系统比特有时候也称为信息比特。
子矩阵B为为m A行m A列的方阵，其大小可以为m A*m A，每列对应于LDPC码中的Z个校验比特。子矩阵B包括双对角结构的子矩阵B’和一列权重为3的矩阵列(简称为3列重列)，其中列重为3的矩阵列可以位于子矩阵B’之前，如图2中20a所示；子矩阵B还可以包括一列或多列列重为1的矩阵列(简称为单列重列)，例如，一种可能的实现方式如图2中20b或20c所示。
通常基于子矩阵A和B生成的矩阵为核心矩阵，可以用来支持高码率的编码。
子矩阵C为全零矩阵，其大小为m A×m D。
子矩阵E为单位矩阵，其大小为m D×m D。
子矩阵D大小为m D×(n A+m A)，通常可用来生成低码率的校验位。
可以理解的是，上述从数学定义的角度对基图进行表述，由于C为全零矩阵，E为单位矩阵，在一种可能的实现方式中，也可以由子矩阵A和B构成的矩阵，或者子矩阵A、B和D构成的矩阵来简化地表示编码或译码的矩阵的基图。
由于子矩阵C和E的结构相对确定，子矩阵A、B和D两部分的结构是LDPC码的编译码性能的影响因素之一。
采用raptor-like结构的LDPC矩阵进行编码时，一种可能的实现方式为，可以先对子矩阵A和B部分的矩阵，也就是核心矩阵进行编码，得到子矩阵B对应的校验比特，再对整个矩 阵进行编码，得到子矩阵E部分对应的校验比特。由于子矩阵B可以包括双对角结构的子矩阵B’和一单列重列，在编码中可以先获得双对角结构对应的校验比特，再获得单列重列对应的校验比特。
下面给出一种编码的示例方式。假设子矩阵A和B构成的核心矩阵部分为H core，H core中去掉单列重列以及该列非零元素所在的行，得到的矩阵部分为H core-dual，H core-dual中的校验位部分表示为H e＝[H e1H e2],H e1为3列重列，H e2为双对角结构。根据LDPC码矩阵定义，H core-dual·[S P e] T＝0，其中，S为输入序列，为信息比特构成的向量，P e为校验比特构成的向量，[S P e] T表示由输入序列S和P e构成的矩阵转置。因此可以先根据输入序列S和H core-dual计算出H core-dual对应的校验比特，输入序列S中包括所有信息比特；再根据得到H core-dual对应的校验比特和输入序列S计算得到子矩阵B中单列重列对应的校验比特，此时可以得到子矩阵B对应的所有校验比特；再根据输入序列S以及子矩阵B对应的校验比特，利用子矩阵D部分编码得到子矩阵E对应的校验比特，从而得到所有信息比特和所有校验比特，这些比特构成编码后的序列，也就是一个LDPC码序列。
可选地，LDPC码编码还可能包含截短(shortening)和打孔(puncturing)操作。被截短的比特和被打孔的比特均不发送。
其中，截短一般是从信息比特的最后一位开始向前截短，可以采用不同的方式进行截短。例如，被截短的比特数s 0，可以将输入序列S中最后s 0个比特设置为已知比特得到输入序列S’，如设置为0或者null，或者其他一些值，然后通过LDPC矩阵对输入序列S’进行编码，又例如，也可以可以将输入序列S中最后(s 0mod Z)个比特设置为已知比特得到输入序列S’，如设置为0或者null，或者其他一些值，将子矩阵A中最后
Figure PCTCN2018091423-appb-000003
列删除得到LDPC矩阵H’，使用LDPC矩阵H‘对输入序列S’进行编码，或者子矩阵A中最后
Figure PCTCN2018091423-appb-000004
列不参与对输入序列S’的编码。在完成编码后，被截短的比特不发送。
其中，打孔可以是对输入序列中内置打孔比特，或者校验比特进行打孔。对校验比特打孔时通常也是从校验比特的最后一位进行打孔的，当然，也可以按照系统预设的打孔顺序进行打孔。一种可能的实现方式为，先对输入序列进行编码，然后根据需要被打孔的比特数p，选择校验比特中最后p个比特或者根据系统预设的打孔顺序选择p个比特，这p个比特不发送。又一种可能的实现方式中，也可以确定出被打孔比特对应的矩阵的p列以及这些列中非零元素所在的p行，这些行、列不参与编码，也就不产生相应的校验比特。
需要说明的是，这里对编码方式只是举例，基于本申请提供基图和/或基矩阵还可以采用本领域技术人员所知的其他编码方式，本申请并不限定。本申请中涉及的译码，可以是采用多种译码方式，例如可以采用，min-sum(MS)译码方式，也可以采用belief propagation译码方式。MS译码方法有时也称为Flood MS译码方法。例如，对输入序列初始化，并进行迭代处理，在迭代后进行硬判决检测，并对硬判决结果进行校验，如果译码结果符合校验方程，则译码成功，终止迭代，并输出判决结果。如果不符合校验方程，则在最大迭代次数内再次进行迭代处理，若达到最大迭代次数，仍校验失败，则译码失败。可以理解的是，本领域的技术人员可以理解MS译码的原理，在此不再详述。
需要说明的是，对于译码方式只是举例说明，对于基于本申请提供基图和/或基矩阵还可 以采用本领域技术人员所知的其他译码方式，本申请对译码方式并不限定。
通常LDPC码可基于基图和基矩阵获得，对基图或者基矩阵采用密度进化的方法可以确定出LDPC码的性能上限，并且根据基矩阵中的偏移值确定出LDPC码的错误平层。改善编译码性能和降低错误平层是确定基图和基矩阵的目标之一。无线通信系统中码长灵活多变，例如，可以是40比特，1280比特等，图3a、3b-1至3b-8以及3c分别是一个LDPC码及其核心矩阵的基图和基矩阵示例，可满足块长为20至2560比特的码块的性能需求。为方便说明及理解，附图中3a、3b-1至3b-8以及3c中在最上侧以及最左侧，分别示出了列号和行号。
图4给出了图3a-3c所示的LDPC码的性能示意图，LDPC 1表示该LDPC码是基于基图30a对应的各个基矩阵编码得到的，LDPC 2表示作为对比的一种常用的LDPC码，其中横坐标表示信息比特序列的长度，单位为比特，纵坐标为符号信噪比(Es/N0)，性能曲线为BLER为0.0001时，LDPC 1和LDPC 2在不同信息比特序列长度下符号信噪比的性能。可以看出在同样的BLER下，LDPC 1在不同信息比特序列长度下的符号信噪比低于LDPC 2，也就是性能优于LDPC 2。
图3a所示为一个LDPC码的基图30a示例，其中，图中最上面一行0-51表示列编号，最左面一列0-41表示行编号，也就是基图30a的矩阵大小为42行52列。
子矩阵A对应系统比特，大小为m A行10列，其中，4≤m A≤7，例如，m A＝4，在基图30a中由第0行至第3行以及第0列至第9列的元素构成，又例如，m A＞4，以m A＝7为例，在基图30a中由第0行至第6行以及第0列至第9列的元素构成；
子矩阵B对应校验比特，大小为m A行m A列，在基图30a中由第0行至第(m A-1)行以及第10列至第(10+m A-1)列的元素构成；
子矩阵A和子矩阵B构成了LDPC码基图的核心矩阵部分，也即构成了一个m A行(m A+n A)列的矩阵，可用于高码率编码。为了方便描述，以下以m A＝7为例，LDPC码的基图的核心矩阵部分为7行17列。
其中，子矩阵A中可以包括2列内置打孔比特列，则打孔后，核心矩阵可以支持的码率为10/(17-2)＝2/3。
其中，子矩阵B中包括1列3列重列，即子矩阵B的第0列(核心矩阵的第10列)列重为3，子矩阵B的第1至3列(核心矩阵的第11至13列)，第0至3行为双对角结构，子矩阵B还包括3列单列重的列。
以m A＝7为例，基图30a的核心矩阵中，包括了2行权重为10的行，2行权重为8的行，2行权重为6的行，和1行权重为4的行。也就是，子矩阵A和子矩阵B构成的核心矩阵中各行的权值分别为8，10，8，10,4,6和6。需要说明的是，核心矩阵中各行的顺序是可以交换的，例如第0行和第2行交换，第1行和第3行交换等等。可以分别为基图30a的核心矩阵中第0至第6行，第0至第16列所示的各行,之一。这些行顺序可以交换，各列的顺序也可以交换。例如，可以将核心矩阵的第8列和第14列交换等。需要说明的是，此处仅为举例，实际应用中，列顺序的交换，行顺序的交换，是可以根据系统需求灵活设计。
可以理解的是，由于矩阵行之间可以交换、列之间也可以交换，行交换不改变矩阵中列的权重，列交换不改变矩阵中行的权重，矩阵中非零元素的个数是没有发生改变的。经过行交换和列交换后的基图的各行的权重没有改变。使用经过行交换，或者列交换，或者行交换和列交换后的基图不影响性能。
需要说明的是，本申请中，不影响性能是指的从整体讲，影响可接受，在容忍范围内，例如，可能对某些场景或者在某些范围内，性能在允许范围内下降，但是在某些场景或者某些范围内，性能有所改善，整体上看对性能影响不大。
通常对于一个LDPC码给定的基图或者基矩阵而言，对矩阵元素的少量修改对性能影响是可接受的。例如，在一种实现方式中，可以基于基图30a的核心矩阵，进行少量修改，例如，其中1行的权重满足大于或者等于2，且小于或者等于5，其余6行的权重分别满足大于或者等于6，且小于或者等于12。可以理解，也可以参照本申请提供的方案，使其中某些行的权重增加或减少1-2，本申请并不对此进行限定。
为了获得灵活的码率，可以基于核心矩阵添加相应大小的子矩阵C、子矩阵D和子矩阵E，来获得不同的码率。由于子矩阵C为全零矩阵，子矩阵为单位矩阵，其大小主要是根据码率来确定，结构相对固定。影响到编译码性能的主要在于核心矩阵和子矩阵D部分。在核心矩阵的基础上添加行列，形成相应的C、D和E部分可以得到不同码率。例如，可以以基图30a的核心矩阵部分部分作为核心矩阵，为满足不同码率编码或译码的需求，添加相应的子矩阵C、D和E。
子矩阵D的列数m D为子矩阵A和B的列数之和，其行数主要与码率相关。以基图30a为例，若m A＝4，则相应的子矩阵D的列数为(n A+m A)＝14列，若m A＝7，则相应的子矩阵D的列数为(n A+m A)＝17列。若LDPC码支持的码率为R m，则其基图或者基矩阵的大小为m*n，其中，n＝n A/R m+p，m＝n-n A＝n A/R m+p-n A。若最低码率R m＝1/5，内置打孔列数p＝2，以基图30a为例，则n＝52，m＝42，子矩阵D的行数m D最大可以为m-m A＝42-m A，若m A＝4，则0≤m D≤38，若m A＝7，则0≤m D≤35。
为了方便描述，可以定义一个大小为m F行(m A+n A)列的矩阵F，则子矩阵D可以包括其中的m D行，也就是0≤m D≤m F，且35≤m F≤38。仍以m A＝7为例，基图30a中，m A+m D＝42。若m D＝35，相应地子矩阵D大小为35行17列，也就是子矩阵D即矩阵F，对应LDPC码支持的码率为10/50＝1/5。可见，对于m A＝7，基图30a中第7行至第41行以及第0列至第17列构成的矩阵即为矩阵F。对于m A＝4，基图30a中第4行至第41行以及第0列至第13列构成的矩阵即为矩阵F。需要说明的是，此处仅为举例，并不以此为限，m A也可以为4至7中任一整数值，矩阵F的列数也相应改变。
在本发明中，若基图中相邻两行的同一列最多只有1个非零元素，则这两行彼此正交。若基图中相邻两行除了部分列以外的其他列中，同一列最多只有1个非零元素，则这两行是准正交的。
矩阵F可以包括多行准正交结构和至少两行正交结构。例如，矩阵F至少包括15行符合准正交结构的行，这15行中任意相邻2行中除了内置打孔比特列以外的其余列中，同一列中最多只有一个非零元素，也就是矩阵F中至少15行中除了内置打孔比特列以外的其余列构成的矩阵块具有正交结构。矩阵F还可以包括10至20行符合正交结构的行，也就是这些行中，任意相邻2行中同一列最多只有一个非零元素，也就是内置打孔比特列中也最多只有一个非零元素。
例如，以基图30a为例，矩阵F中最后10行符合正交结构，其中9行的权重为3,1行的权重为2。矩阵F的列重分布可以是，其中1列的权重为16，1列的权重为18，1列权重为11,2列的权重为10,1列的权重为9,1列的权重为8,1列的权重为7,1列的权重为6,2列的权重为4,1列的权重为3,2列的权重为2。若m A＞4，所述矩阵F中其余列的权重为0。
以m A＝7为例，在基图30a所示例的矩阵F中，其行重依次为5，3，4，4，4，3，4，4，3，4，4，3，3，3，3，2，3，3，2，4，2，3，2，4，2，3，3，3，3，3，2，3，3，3，3。
由于子矩阵E为单位矩阵，因此基图30a中每一行的权重分别为8，10，8，10，4，6，6，6，4，5，5，5，4，5，5，4，5，5，4，4，4，4，3，4，4，3，5，3，4，3，5，3，4，4，4，4，4，3，4，4，4，4。
仍以m A＝7为例，若m D＝15，LDPC码基图中子矩阵D大小为15行17列，可以是由基图30a中矩阵F的第0-14行，也就是基图30a的第7行至第21行，第0列至第16列的矩阵构成，对应LDPC码支持的码率为10/30＝1/3，也就是在该码率下，LDPC码的基图对应于基图30a的第0行至第21行，第0列至第31列构成的矩阵部分，其中子矩阵E为15行15列的单位矩阵，子矩阵C为7行15列的全0矩阵；
若m D＝25，LDPC码基图中子矩阵D大小为25行17列，可以是由基图30a中矩阵F的第0-24行，也就是基图30a的第7行至第31行，第0列至第16列的矩阵构成构成，对应LDPC码支持的码率为10/40＝1/4，也就是在该码率下，LDPC码的基图对应于基图30a的第0行至第31行，第0列至第41列构成的矩阵部分，其中子矩阵E为25行25列的单位矩阵，子矩阵C为7行25列的全0矩阵。
以此类推，不一一阐述。
需要说明的是，LDPC码的基图和基矩阵中各行是可以相互交换的，各列也是可以相互交换的。例如，可将基图30a的第34行和第36行进行交换，并且将第44列和第45列进行交换。又例如，子矩阵D包括矩阵F中m D行，这m D行可以不进行行交换，也可以将其中一行或多行之间进行行交换，子矩阵E仍为对角结构，不做行、列交换，例如，将矩阵F的第27行和第29行进行行交换，子矩阵D包括矩阵F中m D行，子矩阵E仍为对角结构。矩阵F在进行行交换前是一个准正交的矩阵，经过交换后仍然为一个准正交的矩阵。可以理解的是，若基图或基矩阵包括子矩阵D，那么对核心矩阵的列进行交换时，相应的子矩阵D中列也需要进行交换。
如图3b-1至3b-8所示基矩阵30b-1至30b-8为基图30a的多个基矩阵示例。其中，基图30a中第i行第j列的非零元素在基矩阵30b-1至30b-8各矩阵中的位置不变，值为偏移值V i,j，零元素在偏移矩阵中以-1或者null表示。其中，子矩阵D在基矩阵中相应的部分可以包括矩阵F的偏移矩阵的m D行，可以根据码率的不同选择m D的值。子矩阵D对应的偏移矩阵为矩阵F的偏移矩阵中的m D行。
其中，一种可能的实现方式中，矩阵F的偏移矩阵可以是30b-1至30b-8中任一矩阵中第7行至第41行以及第0列至第16列所示的矩阵，或者是该矩阵的行/列变换后的矩阵；或者矩阵F的偏移矩阵可以包括30b-1至30b-8中任一矩阵中第4行至第41行以及第0列至第14列所示的矩阵，或者是该矩阵的行/列变换后的矩阵。
为了支持不同块长，LDPC码需要不同的扩展因子Z，例如，对于扩展因子Z＝a×2 j，a∈{2,3,5,7,9,11,13,15}。可以划分成如表一所述的8个集合：
表一
集合1 Z＝2×2 j，j＝0,1,2,3,4,5,6,7
集合2 Z＝3×2 j，j＝0,1,2,3,4,5,6,7
集合3 Z＝5×2 j，j＝0,1,2,3,4,5,6
集合4 Z＝7×2 j，j＝0,1,2,3,4,5
集合5 Z＝9×2 j，j＝0,1,2,3,4,5
集合6 Z＝11×2 j，j＝0,1,2,3,4,5
集合7 Z＝13×2 j，j＝0,1,2,3,4
集合8 Z＝15×2 j，j＝0,1,2,3,4
为了保证不同块长下的LDPC码性能，可以分别基于不同的扩展因子Z的集合采用与之对应的基矩阵。可以理解上述8个集合索引仅以1，2,3,4,5,6,7,8为例进行说明。本领域的技术人员可以理解，本申请对于各个集合的索引并不限定。例如，可以使用0,1,2,3,4,5,6,7来表示8个集合。也可以使用其他的可识别的索引来表示8个集合。每个集合索引对应一个基矩阵。以表一中的扩展因子Z的集合为例，不同扩展因子集合中的扩展因子Z取值不同。Z确定了，那么Z对应的基矩阵也就确定了。因此Z与基矩阵也是对应的。
其中，在一种可能的实现方式中：
若扩展因子Z为集合1中的一个，则矩阵F的偏移矩阵可以是30b-1中第7行至第41行以及第0列至第16列所示的矩阵，或者是该矩阵的行/列变换后的矩阵；或者矩阵F的偏移矩阵可以是30b-1中第4行至第41行以及第0列至第14列所示的矩阵，或者是该矩阵的行/列变换后的矩阵。相应地，基图30a的基矩阵可以是30b-1所示的矩阵，或者是该矩阵的行/列变换后的矩阵；
若扩展因子Z为集合2中的一个，则矩阵F的偏移矩阵可以是30b-2中第7行至第41行以及第0列至第16列所示的矩阵，或者是该矩阵的行/列变换后的矩阵；或者矩阵F的偏移矩阵可以是30b-2中第4行至第41行以及第0列至第14列所示的矩阵，或者是该矩阵的行/列变换后的矩阵。相应地，基图30a的基矩阵可以是30b-2所示的矩阵，或者是该矩阵的行/列变换后的矩阵；
若扩展因子Z为集合3中的一个，则矩阵F的偏移矩阵可以是30b-3中第7行至第41行以及第0列至第16列所示的矩阵，或者是该矩阵的行/列变换后的矩阵；或者矩阵F的偏移矩阵可以是30b-3中第4行至第41行以及第0列至第14列所示的矩阵，或者是该矩阵的行/列变换后的矩阵。相应地，基图30a的基矩阵可以是30b-3所示的矩阵，或者是该矩阵的行/列变换后的矩阵；
若扩展因子Z为集合4中的一个，则矩阵F的偏移矩阵可以是30b-4中第7行至第41行以及第0列至第16列所示的矩阵，或者是该矩阵的行/列变换后的矩阵；或者矩阵F的偏移矩阵可以是30b-4中第4行至第41行以及第0列至第14列所示的矩阵，或者是该矩阵的行/列变换后的矩阵。相应地，基图30a的基矩阵可以是30b-4所示的矩阵，或者是该矩阵的行/列变换后的矩阵；
若扩展因子Z为集合5中的一个，则矩阵F的偏移矩阵可以是30b-5中第7行至第41行以及第0列至第16列所示的矩阵，或者是该矩阵的行/列变换后的矩阵；或者矩阵F的偏移矩 阵可以是30b-5中第4行至第41行以及第0列至第14列所示的矩阵，或者是该矩阵的行/列变换后的矩阵。相应地，基图30a的基矩阵可以是30b-5所示的矩阵，或者是该矩阵的行/列变换后的矩阵；
若扩展因子Z为集合6中的一个，则矩阵F的偏移矩阵可以是30b-6中第7行至第41行以及第0列至第16列所示的矩阵，或者是该矩阵的行/列变换后的矩阵；或者矩阵F的偏移矩阵可以是30b-6中第4行至第41行以及第0列至第14列所示的矩阵，或者是该矩阵的行/列变换后的矩阵。相应地，基图30a的基矩阵可以是30b-6所示的矩阵，或者是该矩阵的行/列变换后的矩阵；
若扩展因子Z为集合7中的一个，则矩阵F的偏移矩阵可以是30b-7中第7行至第41行以及第0列至第16列所示的矩阵，或者是该矩阵的行/列变换后的矩阵；或者矩阵F的偏移矩阵可以是30b-7中第4行至第41行以及第0列至第14列所示的矩阵，或者是该矩阵的行/列变换后的矩阵。相应地，基图30a的基矩阵可以是30b-7所示的矩阵，或者是该矩阵的行/列变换后的矩阵；
若扩展因子Z为集合8中的一个，则矩阵F的偏移矩阵可以是30b-8中第7行至第41行以及第0列至第16列所示的矩阵，或者是该矩阵的行/列变换后的矩阵；或者矩阵F的偏移矩阵可以是30b-8中第4行至第41行以及第0列至第14列所示的矩阵，或者是该矩阵的行/列变换后的矩阵。相应地，基图30a的基矩阵可以是30b-8所示的矩阵，或者是该矩阵的行/列变换后的矩阵。
例如，根据输入序列的长度K来确定扩展因子Z的取值，如：若输入序列长度为K，可以在多个系统定义的扩展因子中确定满足10*Z≥K的最小值作为矩阵的扩展因子的取值。进一步，可以根据确定的扩展因子选择相应的基矩阵。
同样的，基矩阵中各行也是可以交换的，各列也可以交换。若基图经过行交换或列交换中至少一种交换，则相应部分的基矩阵也进行同样的交换。
可以理解的是，本申请中准正交结构并不仅仅局限于相邻两行，符合准正交结构的矩阵也可以设计为包含多个组，每个组包含至少2行，例如3行，或者4行等，每个组内包括的行是准正交的。
图4所示的性能曲线图中，LDPC 1表示该LDPC码是基于基图30a对应的一个基矩阵编码得到的，LDPC 2表示作为对比的一种常用的LDPC码，其中横坐标表示信息比特序列的长度，单位为比特，纵坐标为符号信噪比(Es/N0)，性能曲线为BLER分别为0.01和0.0001时，LDPC 1和LDPC 2在不同信息比特序列长度下符号信噪比的性能。可以看出在同样的BLER下，LDPC 1在不同信息比特序列长度下的符号信噪比低于LDPC 2，也就是性能优于LDPC 2。
在本发明一实施例提供的编码方法中，编码器使用LDPC矩阵对输入序列进行编码；该LDPC矩阵的基图可以为前述示例中的任一基图，该LDPC矩阵的基矩阵可以为前述示例中的任一基矩阵。其中，编码器的输入序列可以是信息比特序列，也可以是至少经过下述一种处理后的信息比特序列：CRC比特添加或者填充比特添加。
进一步地，还包括：确定扩展因子Z；可以根据输入序列的长度K来确定扩展因子Z的取值。信息比特序列有时也称为码块(code block)，可以通过对传输块进行码块划分得到。若 信息比特序列长度为K，可以在多个系统定义的扩展因子中确定满足10*Z≥K的最小值，例如，K＝128，系统定义的扩展因子包括前述表一中各集合中的扩展因子，例如，2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,18,20,22,24,26,28,30,32,36,40,44,48,52,56,60,64,72,80,88,96,104,112,120,128,144,160,176,192,208,224,240,256，则可以确定Z为13，在集合7中。需要说明的是，此处只是举例，并不以此为限制。
在又一种可能的设计中，Kb可以为LDPC码的基矩阵中信息比特的列数，在支持的扩展因子集合中，找到最小的Z 0作为扩展因子Z的大小，且满足Kb·Z 0≥K。对于基图30a，其中信息比特的列数Kb max＝10，假设基图30a支持的扩展因子集合为{24,26,28,30,32,36,40,44,48,52,56,60,64,72,80,88,96,104,112,120,128,144,160,176,192,208,224,240,256,288,320,352,384}。
若输入序列的长度K＝529比特，则Z为26，若输入序列的长度K＝5000比特，则Z为240。需要说明的是，此处仅为举例，并不以此为限制。
又例如，Kb的取值也可以根据K的取值变化，但不超过LDPC码的基矩阵中信息比特列数。例如可以为Kb设置不同的门限。
在一个可能的设计如下：需要说明的是，这里的门限值640,560,192仅仅为举例。也可以根据系统设计需求设计为其他值。
if(K>640),Kb＝10；
elseif(K>560),Kb＝9；
elseif(K>192),Kb＝8；
else Kb＝6；end
其中，扩展因子Z可以由编码器根据输入序列的长度K来确定，也可以是由编码器从其他实体(如处理器)获得。
在一种可能的设计中，可以用Null，或者取值为0，或者其他系统约定的值作为填充比特的值。使得经过编码后，这些填充比特能被识别出来不被发送。本发明并不以此为限制。
编码器使用LDPC矩阵H对输入序列进行编码可以是使用扩展因子Z对应的LDPC矩阵H对输入序列进行编码。
在一种可能的实现方式中，输入序列c＝{c 0,c 1,c 2,...,c K-1}，输入序列c长度为K，输入序列c经过编码器编码后得到的输出序列d＝{d 0,d 1,d 2,...,d N-1}，K为大于0的整数，K可以是扩展因子Z的整数倍，例如K＝10·Z。
其中输出序列d中包括输入序列c中的K 0个比特以及校验序列w中的校验比特，K 0为大于0，且小于或者等于K的整数，校验序列w的长度为N-K 0，
Figure PCTCN2018091423-appb-000005
其中，校验比特序列w和输入序列c满足公式(1)：
Figure PCTCN2018091423-appb-000006
其中，c T＝[c 0,c 1,c 2,...,c K-1] T，为输入序列中各比特组成的向量的转置向量，
Figure PCTCN2018091423-appb-000007
为校验序列中各比特组成的向量的转置向量,0 T为列向量，其中所有元素的值为0。
其中H为基于前述各实施例中例举的任一基图或者基矩阵得到的LDPC矩阵，H的基图大小为m行n列,可以是前述实施例中例举的基图30a。
在一种设计中，H的基图中包括p列内置打孔列，p为大于或者等于0的整数，p列内置打孔列对应的信息比特不被输出，也就是输出序列中不包括p列内置打孔列对应的信息比特，则K 0＝K-p·Z，例如，p＝2，则K 0＝K-2·Z，输出序列d中包括输入序列c中的K-2·Z个比特，校验序列w的长度为N+2·Z-K，w T＝[w 0,w 1,w 2,...,w N+2·Z-K-1] T。若p列内置打孔列参与编码，则K 0＝K，校验序列w的长度为N-K。
相应地，H可以为M行(N+p·Z)列或者M行N列，其基图大小m＝M/Z，
Figure PCTCN2018091423-appb-000008
LDPC矩阵H的基图可以表示成[H BG H BG,EXT]，其中
Figure PCTCN2018091423-appb-000009
表示m c×n c大小的全零矩阵，
Figure PCTCN2018091423-appb-000010
表示n c×n c大小的单位矩阵。由于Kb可以根据K改变，H BG包括H BG2中Kb列信息比特对应的列，以及H BG2中第10至10+m A-1列，H BG2列数为10+m A列，4≤m A≤7，例如，若Kb∈{6,8,9}，可以将H BG2中第Kb列至第9列删除后得到H BG，若Kb＝10，则H BG＝H BG2。
在一种可能的设计中，
Figure PCTCN2018091423-appb-000011
为前述各实施例基图中子矩阵C，
Figure PCTCN2018091423-appb-000012
为前述各实施例中子矩阵E，则
Figure PCTCN2018091423-appb-000013
A，B和D分别为前述各实施例基图中子矩阵A、B和D，则m c＝7，0≤n c≤35，H BG2的行数小于或者等于42，且大于或者等于4，H BG2的列数等于17。
在又一种可能的设计中，由于第14至16列为单列重列，且其中非零元素位于第4至6行，m c＝6，0≤n c≤36，H BG2的列数等于16；或者m c＝5，0≤n c≤37，H BG2的列数等于15；或者，m c＝4，0≤n c≤38，H BG2的列数等于14。
相应地，LDPC矩阵H可以表示成H＝[H 1H 2]。其中，
H 1可以是将H BG中每个零元素替换成Z*Z大小的全零矩阵，每个非零元素替换成Z*Z大小的循环置换矩阵h i,j得到，其中循环置换矩阵h i,j是将Z*Z大小的单位矩阵循环右移P i,j得到的，有时也用I(P i,j)表示。其中，i是行号，j是列号，一种可能的设计中P i,j＝mod(V i,j,Z)，V i,j是Z对应的扩展因子集合索引所对应的基矩阵中第i行第j列的非零元素。
H 2可以是将H BG,EXT中每个零元素替换成Z*Z大小的全零矩阵，每个非零元素替换成Z*Z大小的单位矩阵得到。
编码器可以采用多种方式进行编码并输出，下面以前述实施例中例举的基图30a为例进行说明，其中基图行数最大为42行，列数最大为52列，包括2列内置打孔列，也就是说m＝42，n＝52，相应地M＝m·Z＝42·Z，N＝(n·Z-p·Z)＝50·Z。为了方便描述，在本发明中有时将行数最大且列数也最大的基图称为完整基图。
方式一：
基于完整基图编码，从而获取到尽可能多的校验比特。此时，m＝42，n＝52，也就是上述基图的第0至第41行以及第0至第51列。
相应地，对于LDPC矩阵H，M＝42·Z，如果输出序列包括内置打孔列对应的信息比特，则N＝(42+Kb)·Z，如果输出序列不包括除内置打孔列对应的2·Z个信息比特，则N＝(40+Kb)·Z,例如，N＝50·Z。
可以在后续处理环节中从编码器产生的输出序列中确定需要发送的信息比特和校验比特。
方式二：
基于完整基图的部分行、列编码。可以根据需要发送的码率，或者，信息比特和校验比特数等从完整基图中选择行、列编码。
例如，码率为2/3，m＝7，n＝17，也就是基于上述基图30a中第0至6行以及第0至16列的部分编码。
相应地，对于LDPC矩阵H，M＝7·Z，如果输出序列包括内置打孔列对应的信息比特，则N＝17·Z，如果输出序列不包括内置打孔列对应的信息比特，则N＝15·Z。
又例如，码率为5/6，m＝4，n＝14。
又例如，码率为1/5,m＝42，n＝52。
可见，H的基图大小为，4≤m≤42，14≤n≤52，相应地对于LDPC矩阵H,4·Z≤M≤42·Z，(4+Kb)·Z≤N≤(42+Kb)·Z。
例如，Z为13，在集合7中，则基于集合7对应的基矩阵3b-7得到LDPC矩阵对输入序列进行编码；
又一种设计中，也可以扩展因子Z的基矩阵，第i行第j列元素P i,j满足下述关系：
Figure PCTCN2018091423-appb-000014
其中，V i,j可以是Z所在集合的基矩阵中第i行第j列的元素的偏移值，也就是Z所在集合中最大扩展因子的基矩阵的第i行第j列的非零元素的偏移值。
例如，以Z为13为例，其基矩阵中第i行第j列的元素P i,j满足
Figure PCTCN2018091423-appb-000015
其中，V i,j是基矩阵3b-7中第i行第j列的非0元素的偏移值。
需要说明的是，此处仅为举例，本发明不限于此。
在上述各种实现方式中，LDPC矩阵H的基矩阵H B可以是前述各实施例中例举的任一基矩阵或者相对于前述例举的任一基矩阵而言行顺序发生变换、或者列顺序发生变换，或者行顺序和列顺序均发生变换的基矩阵，其基图至少包括子矩阵A和子矩阵B，还可以包括子矩阵C、子矩阵D和子矩阵E，各部分可以参考前述各实施例中的描述，此处不再赘述。当然也可以是其他基图符合基图30a的基矩阵，本发明并不限于此。
在一种可能的实现方式中，LDPC码的基矩阵H B可以是保存在存储器中，编码器获取扩展因子Z对应的LDPC矩阵，从而对输入序列进行编码。在又一种可能的实现方式中，由于LDPC码的基矩阵H B有多个，按照矩阵结构保存会占用较大的存储空间，也可以将LDPC码的基图保存在存储器中，分别逐行或者逐列保存各基矩阵中非零元素的偏移值，然后根据基图和扩展因子Z对应的基矩阵的偏移值得到LDPC矩阵。
基图可以指示各基矩阵非零元素的位置，在又一种可能的实现方式中，保存基图可以是保存其中非零元素的位置。非零元素的位置可以通过非零元素所在的行和列指示，例如每一行中非零元素所在的列的位置，或者，每一列中非零元素所在的行的位置。在又一种可能的实现方式中，保存基图也可以是保存其中零元素的位置，同样，也可以通过零元素所在的行和列指示。例如每一行中零元素所在的列的位置，或者每一行中零元素所在的行的位置，则相应的非零元素的位置可以通过排除零元素所在的位置得到。需要说明的是，此处仅为举例，本发明并不限于此。
在一种设计中，可以对基图或者基矩阵涉及的参数使用表格来表示。例如可以在一个或多个存储器中保存相关的参数或者表格。通过读取存储器中的基图或者基矩阵的行号和非零元素所在的列等相关参数，即可获得基图或者基矩阵，可选地，还可以保存每行的行重，以及每行非零元素的偏移值。
下面以图3a为例进行说明，本申请提供的其他基图或者基矩阵可以参照类似的涉及。
例如，基图30a涉及的参数可以使用表二表示。
表二
Figure PCTCN2018091423-appb-000016
Figure PCTCN2018091423-appb-000017
需要说明的是，此处均只是举例，并不以此为限制。本申请中提供的其他基图或者基矩阵也可以采用类似的表格来表述相关参数。可以理解，上述基图30a以及表二是为了帮助理解对于基图和基矩阵的设计，其表现形式并不仅仅局限于基图30a以及表二的表现形式。还可以包括其他可能的变形。
在一种实现方式中，可以通过，列号，列重，非零元素所在的行，或者零元素所在的行。例如表三的形式，表三仅给出了其中2列的示意，其他列可以以此类推，不一一赘述。其中第14列至第51列为单列重列，也可以不保存，而是根据列号推算出非零元素所在的行的位置。
表三
列号 列重 非零元素所在的行
0 22 0,1,2,4,5,6,8,10,11,13,15,18,19,21,23,25,27,29,32,34,36,39
1 23 0,2,3,4,5,7,8,9,10,12,13,14,16,17,19,20,22,24,28,35,38,41
... ... ..
在一种实现方式中，上述表二或者表三的“行重”、“列重”这一参数也可以省略。可以 通过一行非零元素所在的列或者行，获知这一行或者这一列有多少个非零元素，因此行重或者列重也就获知了。
在一种实现方式中，对于上述表二“非零元素所在的列”中的参数值，表三中，“非零元素所在的行”中的参数值，也可以不按照由小到大的顺序排列，只要参数值索引到非零元素所在的列，或者索引到非零元素所在的行就可以。
在一种实现方式中，对于表二或者表三中还可以包括“非零元素偏移值”的列，对于“非零元素偏移值”列中的参数值与“非零元素所在的列”中的参数值一一对应。表五中，也可以包括“非零元素偏移值”的列，对于“非零元素偏移值”列中的参数值与“非零元素所在的行”中的参数值一一对应。
在一种设计中，为了节省存储空间，对于基图中结构相对固定的部分，其非零元素的位置可以根据行列位置计算得到，可以不保存其中非零元素的位置。例如，子矩阵E是对角矩阵，仅在对角线上存在非零元素，可以根据行号计算得到其中非零元素所在的列的位置，也可以根据列号计算得到非零元素所在的行的位置，以基图30a为例，对于单列重列，第m e行，m e≥4，其非零元素所在的列的位置为第m e+K b列，此处K b＝10，例如，第4行中非零元素所在的列为第14列。又例如，子矩阵B中双对角结构B’位于基图30a中第0至3行以及第11至13列，可以根据行号计算得到其中非零元素所在的列的位置，也可以根据列号计算得到非零元素所在的行的位置，对于第m B行，若0<m B<3，该行中非零元素的位置包括第m B+K b列，以及第m B+K b+1列,若m B＝0或m B＝3，该行中非零元素的位置包括第m B+K b列。
如表四所示为基图30a中各行所涉及的参数，可以保存第0列至第13列中非零元素所在的列的位置，而不保存第14列至第52列中非零元素所在的列的位置，也就是不保存单列重列中非零元素所在的列，可以用来表示列数为14的H BG2：
表四
行号 行重 非零元素所在的列
0 8 0,1,2,3,6,9,10,11
1 10 0,3,4,5,6,7,8,9,11,12
2 8 0,1,3,4,8,10,12,13
3 10 1,2,4,5,6,7,8,9,10,13
4 3 0,1,11
5 5 0,1,5,7,11
6 5 0,5,7,9,11
7 5 1,5,7,11,13
8 3 0,1,12
9 4 1,8,10,11
10 4 0,1,6,7
11 4 0,7,9,13
12 3 1,3,11
13 4 0,1,8,13
14 4 1,6,11,13
15 3 0,10,11
16 4 1,9,11,12
17 4 1,5,11,12
18 3 0,6,7
19 3 0,1,10
20 3 1,4,11
21 3 0,8,13
22 2 1,2
23 3 0,3,5
24 3 1,2,9
25 2 0,5
26 4 2,7,12,13
27 2 0,6
28 3 1,2,5
29 2 0,4
30 4 2,5,7,9
31 2 1,13
32 3 0,5,12
33 3 2,7,10
34 3 0,12,13
35 3 1,5,11
36 3 0,2,7
37 2 10,13
38 3 1,5,11
39 3 0,7,12
40 3 2,10,13
41 3 1,5,11
当然，对于列数为15列的H BG2其存储的参数，第0至3行和第5至41行与表四中相同，第4行的行重为表四中第4行的行重加1，即为4，非零元素所在的列为表四中第4行中非零元素所在的列再增加一个列号为14的位置，即0,1,11,14。对于列数为16列的H BG2其存储的参数，第0至3行和第6至41行与表四中相同，第4行的行重为表四中第4行的行重加1，即为4，非零元素所在的列为表四中第4行中非零元素所在的列再增加一个列号为14的位置，即0,1,11,14；第5行的行重为表四中第5行的行重加1，即为6，非零元素所在的列为表四中第5行中非零元素所在的列再增加一个列号为15的位置，即0,1,5,7，11,15。
对于列数为17列的H BG2其存储的参数，第0至3行和第7至41行与表四中相同，第4行的行重为表四中第4行的行重加1，即为4，非零元素所在的列为表四中第4行中非零元素所在的列再增加一个列号为14的位置，即0,1,11,14；第5行的行重为表四中第5行的行重加1，即为6，非零元素所在的列为表四中第5行中非零元素所在的列再增加一个列号为15的位置， 即0,1,5,7，11,15；第6行的行重为表四中第6行的行重加1，即为6，非零元素所在的列为表四中第6行中非零元素所在的列再增加一个列号为16的位置，即0,5,7,9,11，16；如表五所示：
表五
行号 行重 非零元素所在的列
0 8 0,1,2,3,6,9,10,11
1 10 0,3,4,5,6,7,8,9,11,12
2 8 0,1,3,4,8,10,12,13
3 10 1,2,4,5,6,7,8,9,10,13
4 4 0,1,11,14
5 6 0,1,5,7,11,15
6 6 0,5,7,9,11,16
7 5 1,5,7,11,13
8 3 0,1,12
9 4 1,8,10,11
10 4 0,1,6,7
11 4 0,7,9,13
12 3 1,3,11
13 4 0,1,8,13
14 4 1,6,11,13
15 3 0,10,11
16 4 1,9,11,12
17 4 1,5,11,12
18 3 0,6,7
19 3 0,1,10
20 3 1,4,11
21 3 0,8,13
22 2 1,2
23 3 0,3,5
24 3 1,2,9
25 2 0,5
26 4 2,7,12,13
27 2 0,6
28 3 1,2,5
29 2 0,4
30 4 2,5,7,9
31 2 1,13
32 3 0,5,12
33 3 2,7,10
34 3 0,12,13
35 3 1,5,11
36 3 0,2,7
37 2 10,13
38 3 1,5,11
39 3 0,7,12
40 3 2,10,13
41 3 1,5,11
在上述设计中，行重一栏均为可选。在有一种可能的设计中，可以对于基图按照每一行或每一列的1和0视为2进制数，采用10进制或者16进制数保存可以节省存储空间。以前述任一基图为例，每行可以用4个16进制数保存前26列或者前27列非零元素的位置，例如，第0行前14列为11110010 011100，则可以记为第0行非零元素的位置为0xF2，0x70，也就是每8列组成一个16进制数，对于其中最后2列，可以通过填充0达到8位的整数倍得到相应的16进制数，当然，也可以在其前面填充0达到8位的整数倍得到相应的16进制数，其他行以此类推，此处不再赘述。
需要说明的是，此处均只是举例，并不以此为限制。
对信息比特序列进行编码时，可以根据Z对基矩阵H B进行扩展得到编码的LDPC矩阵H。对基矩阵H B中每一非零元素P i,j，确定Z*Z大小的循环置换矩阵h i,j，其中h i,j为单位矩阵经过P i,j次循环移位得到的循环置换矩阵，将h i,j替换非零元素P i,j，将Z*Z大小的全零矩阵替换基矩阵H B中的零元素，从而得到奇偶校验矩阵H；
在通信系统中，可采用上述方法编码后得到LDPC码。获得LDPC码后，通信装置，还可以进行以下一个或多个操作：对LDPC码进行速率匹配；根据交织方案对速率匹配后的LDPC码进行交织；根据调制方案对交织后的LDPC码进行调制得到比特序列B；发送比特序列B。
在本发明另一实施例提供的译码方法中，译码器使用LDPC矩阵对输入序列进行译码；该LDPC矩阵的基图可以为前述示例中的任一基图，该LDPC矩阵的基矩阵H B可以为前述示例中的任一基矩阵。其中，译码器的输入序列可以是LDPC码的软值序列。
进一步地，还包括：确定扩展因子Z。接收端的通信设备可以接收包含基于LDPC编码的信号，获取其中LDPC码的软值序列，并确定出相应的扩展因子Z。
译码器使用LDPC矩阵对输入序列进行译码可以是使用扩展因子Z对应的LDPC矩阵对LDPC码的软值序列进行译码。
由于译码是编码的逆过程，对LDPC矩阵H及其基图的描述可参见前述编码实施例。在进行译码时也可以基于完整基图进行译码，或者，基于完整基图的部分行、列译码。其中LDPC矩阵基矩阵H B可以是前述各实施例中例举的任一基矩阵或者相对于前述例举的任一基矩阵而 言行顺序发生变换、或者列顺序发生变换，或者行顺序和列顺序均发生变换的基矩阵，其基图至少包括子矩阵A和子矩阵B，还可以包括子矩阵C、子矩阵D和子矩阵E，各部分可以参考前述各实施例中的描述，此处不再赘述。
在一种可能的设计中，LDPC码的基矩阵H B可以是保存在存储器中，获取到扩展因子Z对应的LDPC矩阵可以对LDPC码的软值进行译码；
在又一种可能的实现方式中，由于LDPC码的基矩阵有多个，按照矩阵结构保存会占用较大的存储空间，也可以将LDPC码的基图保存在存储器中，分别逐行或者逐列保存各基矩阵中非零元素的偏移值，然后根据基图和扩展因子Z对应的基矩阵的偏移值得到LDPC矩阵。
基图的存储方式也可以参照前述编码实施例中所描述的各种方式存储。需要说明的是，此处均只是举例，并不以此为限制。
译码是编码的逆过程，其使用的基矩阵H B具有与编码方法实施例中的基矩阵相同的特征。对基矩阵H B扩展得到LDPC矩阵H也可以参考编码方法实施例。
在通信系统中，所述译码方法之前，通信装置还可以进行以下一个或多个操作：接收包含基于LDPC编码的信号，对信号进行解调，解交织以及解速率匹配得到LDPC码的软值。
在一种可能的实现方式中，可以保存以下一个或多个：
a)用于获得上述各实现方式中列举的任一基矩阵H B中的参数，基于所述参数可以获得所述基矩阵H B；例如，所述参数可以包括以下一个或多个：基矩阵中的偏移值，或者，扩展因子，或者，基矩阵的基图，或者，码率等。
b)上述各实现方式中列举的任一基矩阵H B；
c)基于所述基矩阵H B扩展后的矩阵；
d)基于上述各实现方式中列举的任一基矩阵H B经过行/列变换后的基矩阵。本申请中，行/列变换是指行变换、或者列变换、或者行变换和列变换；
e)基于所述行/列变换后的基矩阵扩展后的矩阵。
在一种可能的实现方式中，使用低密度奇偶校验LDPC矩阵对输入序列进行编码，可以是在编码或者译码过程中，按照以下方式的一种或者多种进行：
i.基于上述a)获得基矩阵H B，基于获得的基矩阵H B编码或者译码；或者基于获得的基矩阵H B进行行/列交换，基于行/列变换后的基矩阵编码或者译码。这里基于基矩阵编码或者译码，可选的，还可以包括基于基矩阵的扩展矩阵编码或者译码；
ii.基于b)或者d)保存的基矩阵(保存基矩阵H B、或者保存的基于基矩阵H B行/列变换后的基矩阵)编码或者译码，或者基于所述保存的基矩阵进行行/列变换，基于行/列变换后的基矩阵编码或者译码。这里，基于基矩阵编码或者译码，可选的，还可以包括基于基矩阵的扩展矩阵编码或者译码；
iii.基于c)或者e)进行编码或者译码。
本申请中涉及的保存，可以是指的保存在一个或者多个存储器中。所述一个或者多个存储器，可以是单独的设置，也可以是集成在编码器或者译码器，处理器、芯片、通信装置、或者终端。所述一个或者多个存储器，也可以是一部分单独设置，一部分集成在译码器、处理器、芯片、通信装置、或者终端中，存储器的类型可以是任意形式的存储介质，本申请并不对此限 定。
图5给出了一种通信装置500的结构示意图，装置500可用于实现上述方法实施例中描述的方法，可以参见上述方法实施例中的说明。所述通信装置500可以是芯片，基站，终端或者其他网络设备。
所述通信装置500包括一个或多个处理器501。所述处理器501可以是通用处理器或者专用处理器等。例如可以是基带处理器、或中央处理器。基带处理器可以用于对通信协议以及通信数据进行处理，中央处理器可以用于对通信装置(如，基站、终端、或芯片等)进行控制，执行软件程序，处理软件程序的数据。
在一种可能的设计中，所述通信装置500包括一个或多个所述处理器501，所述一个或多个处理器501可实现上述编码器的功能，在另一种可能的设计中，上述编码器可以是所述处理器501的一部分，处理器501除了实现编码器的功能，还可以实现其他功能。
所述通信装置500使用LDPC矩阵对输入序列进行编码；该LDPC矩阵的基图可以为前述示例中的任一基图或者相对于前述例举的任一基图而言行顺序发生变换、或者列顺序发生变换，或者行顺序和列顺序均发生变换的基图，该LDPC矩阵的基矩阵H B可以为前述实施例中的任一基矩阵或者相对于前述例举的任一基矩阵而言行顺序发生变换、或者列顺序发生变换，或者行顺序和列顺序均发生变换的基矩阵。其中，编码器的输入序列可以是信息比特序列。
在一种可能的设计中，一个或多个所述处理器501可实现上述译码器的功能，在另一种可能的设计中，上述译码器可以是所述处理器501的一部分。
所述通信装置500可用于使用LDPC矩阵对输入序列进行译码；该LDPC矩阵的基图可以为前述示例中的任一基图或者相对于前述例举的任一基图而言行顺序发生变换、或者列顺序发生变换，或者行顺序和列顺序均发生变换的基图，该LDPC矩阵的基矩阵H B可以为前述示例中的任一基矩阵或者相对于前述例举的任一基矩阵而言行顺序发生变换、或者列顺序发生变换，或者行顺序和列顺序均发生变换的基矩阵。其中，译码器的输入序列可以是软值序列。
可选的一种设计中，处理器501也可以包括指令503，所述指令可以在所述处理器上被运行，使得所述通信装置500执行上述方法实施例中描述的方法。
在又一种可能的设计中，通信装置500也可以包括电路，所述电路可以实现前述方法实施例中编码器、或者译码器、或者编码器和译码器的功能。
可选的，所述通信装置500中可以包括一个或多个存储器502，其上存有指令504，所述指令可在所述处理器上被运行，使得所述通信装置500执行上述方法实施例中描述的方法。可选的，所述存储器中还可以存储有数据。可选的处理器中也可以存储指令和/或数据。所述处理器和存储器可以单独设置，也可以集成在一起。可选的，一个或多个存储器502可以存储与基矩阵相关的参数，例如偏移值，基图，基于基图扩展到矩阵、基矩阵中的各行，扩展因子等等。可选的，所述一个或者多个存储器502可以存储基矩阵或者基于基矩阵扩展到矩阵。
可选的，所述通信装置500还可以包括收发器505以及天线506。所述处理器501可以称为处理单元，对通信装置(终端或者基站)进行控制。所述收发器505可以称为收发单元、收发机、收发电路、或者收发器等，用于通过天线506实现通信装置的收发功能.
可选的，所述通信装置500还可以包括用于产生传输块CRC的器件、用于码块分割和CRC 校验的器件、用于交织的交织器、或者用于调制处理的调制器等。可以通过一个或多个处理器501实现这些器件的功能。
可选的，所述通信装置500还可以包括，用于解调操作的解调器、用于解交织的解交织器、或者用于解速率匹配的器件等等。可以通过一个或多个处理器501实现这些器件的功能。
图6给出了一种通信系统600的示意图，通信系统600中包括通信设备60和通信设备61，其中，信息数据在通信设备60和通信设备61之间接收和发送。通信设备60和61可以是所述通信装500，或者通信设备备60和分别包括通信装置500，对信息数据进行接收和发送。在一个例子中，通信设备60可以为终端，相应的通信设备61可以为基站；在另一个例子中，通信设备60为基站，相应的通信设备61可以为终端。
本领域技术任何还可以了解到本发明实施例列出的各种说明性逻辑块(illustrative logical block)和步骤(step)可以通过电子硬件、电脑软件，或两者的结合进行实现。这样的功能是通过硬件还是软件来实现取决于特定的应用和整个系统的设计要求。本领域技术人员可以对于每种特定的应用，可以使用各种方法实现所述的功能，但这种实现不应被理解为超出本发明实施例保护的范围。
本发明实施例中所描述的各种说明性的逻辑单元和电路可以通过通用处理器，数字信号处理器，专用集成电路(ASIC)，现场可编程门阵列(FPGA)或其它可编程逻辑装置，离散门或晶体管逻辑，离散硬件部件，或上述任何组合的设计来实现或操作所描述的功能。通用处理器可以为微处理器，可选地，该通用处理器也可以为任何传统的处理器、控制器、微控制器或状态机。处理器也可以通过计算装置的组合来实现，例如数字信号处理器和微处理器，多个微处理器，一个或多个微处理器联合一个数字信号处理器核，或任何其它类似的配置来实现。
本发明实施例中所描述的方法或算法的步骤可以直接嵌入硬件、处理器执行的指令、或者这两者的结合。存储器可以是RAM存储器、闪存、ROM存储器、EPROM存储器、EEPROM存储器、寄存器、硬盘、可移动磁盘、CD-ROM或本领域中其它任意形式的存储媒介。例如，存储器可以与处理器连接，以使得处理器可以从存储器中读取信息，并可以向存储器存写信息。可选地，存储器还可以集成到处理器中。处理器和存储器可以设置于ASIC中，ASIC可以设置于UE中。可选地，处理器和存储器也可以设置于UE中的不同的部件中。
通过以上的实施方式的描述，所属领域的技术人员可以清楚地了解到本发明可以用硬件实现，或固件实现，或它们的组合方式来实现。当使用软件程序实现时，可以全部或部分地以计算机程序产品的形式实现，所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机指令时，全部或部分地产生按照本发明实施例所述的流程或功能。当使用软件程序实现时，也可以将上述功能存储在计算机可读介质中或作为计算机可读介质上的一个或多个指令或代码进行传输。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一计算机可读存储介质传输。计算机可读介质包括计算机存储介质和通信介质，其中通信介质包括便于从一个地方向另一个地方传送计算机程序的任何介质。存储介质可以是计算机能够存取的任何可用介质。以此为例但不限于：计算机可读介质可以包括RAM、ROM、EEPROM、CD-ROM或其他光盘存储、磁盘存储介质或者其他磁存储设备、或者能够用于携带或存储具有 指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质。此外。任何连接可以适当的成为计算机可读介质。例如，如果软件是使用同轴电缆、光纤光缆、双绞线、数字用户线(DSL)或者诸如红外线、无线电和微波之类的无线技术从网站、服务器或者其他远程源传输的，那么同轴电缆、光纤光缆、双绞线、DSL或者诸如红外线、无线和微波之类的无线技术包括在所属介质的定义中。如本发明所使用的，盘(Disk)和碟(disc)包括压缩光碟(CD)、激光碟、光碟、数字通用光碟(DVD)、软盘和蓝光光碟，其中盘通常磁性的复制数据，而碟则用激光来光学的复制数据。上面的组合也应当包括在计算机可读介质的保护范围之内。
总之，以上所述仅为本发明技术方案的较佳实施例而已，并非用于限定本发明的保护范围。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (33)

  1. 一种编码方法，其特征在于，所述方法包括：
    确定扩展因子Z及其对应的基矩阵；
    基于扩展因子Z和所述基矩阵对输入序列进行低密度奇偶校验LDPC编码得到编码后的序列；
    其中，所述基矩阵包括42行52列，所述基矩阵中第0至3行的第10列的列重为3，所述基矩阵中第0至3行的第11至13列为双对角结构，所述基矩阵中第0至3行的第14至51列为全0矩阵，第4至41行中的第14至51列为单位矩阵，所述基矩阵中最后10行中的9行权重为4,1行的权重为3。
  2. 一种译码方法，其特征在于，所述方法包括：
    确定扩展因子Z及其对应的基矩阵；
    基于扩展因子Z和所述基矩阵对输入序列进行低密度奇偶校验LDPC译码；
    其中，所述基矩阵包括42行52列，所述基矩阵中第0至3行的第10列的列重为3，所述基矩阵中第0至3行的第11至13列为双对角结构，所述基矩阵中第0至3行的第14至51列为全0矩阵，第4至41行中的第14至51列为单位矩阵，所述基矩阵中最后10行中的9行权重为4,1行的权重为3。
  3. 根据权利要求1或2所述的方法，其特征在于，所述基矩阵每一行的行重分别为8，10，8，10，4，6，6，6，4，5，5，5，4，5，5，4，5，5，4，4，4，4，3，4，4，3，5，3，4，3，5，3，4，4，4，4，4，3，4，4，4，4。
  4. 根据权利要求1至3任一项所述的方法，所述基矩阵中最后10行包括至少5组，所述至少5组中每一组包括至少2行，所述至少2行是正交的。可选地，所述至少2行可以是连续的行。
  5. 根据权利要求1至4任一项所述的方法，其特征在于，所述基矩阵中最后10行中，其中1行的第0至13列的结构满足：，
    Figure PCTCN2018091423-appb-100001
    其余9行的第0至13列的结构满足以下之一，
    Figure PCTCN2018091423-appb-100002
    Figure PCTCN2018091423-appb-100003
    其中，元素entry为空nul l表示零元素，entry为“1”的表示非零元素。
  6. 根据权利要求5所述的方法，其特征在于，所述基矩阵中最后10行的第0至13列满足以下结构，，其中entry为空nul l表示零元素，entry为“1”表示非零元素：
    Figure PCTCN2018091423-appb-100004
  7. 根据权利要求6所述的方法，其特征在于，所述基矩阵中第7至41行的第0至13列满足以下结构，其中entry为空nul l表示零元素，entry为“1”表示非零元素：
    Figure PCTCN2018091423-appb-100005
  8. 根据权利要求7所述的方法，其特征在于，所述基矩阵的第0至6行的第0至16列满足以下结构：
    Figure PCTCN2018091423-appb-100006
    其中entry为空nul l表示零元素，entry为“1”表示非零元素。
  9. 根据权利要求1至8任一项所述的方法，其特征在于，所述基矩阵包括以下行、列上的非零元素，其中i表示行号，j表示列号，i和j均为大于或等于0的整数：
    i＝0,j＝0,1,2,3,6,9,10,11；
    i＝1,j＝0,3,4,5,6,7,8,9,11,12；
    i＝2,j＝0,1,3,4,8,10,12,13；
    i＝3,j＝1,2,4,5,6,7,8,9,10,13；
    i＝4,j＝0,1,11,14；
    i＝5,j＝0,1,5,7,11,15；
    i＝6,j＝0,5,7,9,11,16；
    i＝7,j＝1,5,7,11,13,17；
    i＝8,j＝0,1,12,18；
    i＝9,j＝1,8,10,11,19；
    i＝10,j＝0,1,6,7,20；
    i＝11,j＝0,7,9,13,21；
    i＝12,j＝1,3,11,22；
    i＝13,j＝0,1,8,13,23；
    i＝14,j＝1,6,11,13,24；
    i＝15,j＝0,10,11,25；
    i＝16,j＝1,9,11,12,26；
    i＝17,j＝1,5,11,12,27；
    i＝18,j＝0,6,7,28；
    i＝19,j＝0,1,10,29；
    i＝20,j＝1,4,11,30；
    i＝21,j＝0,8,13,31；
    i＝22,j＝1,2,32；
    i＝23,j＝0,3,5,33；
    i＝24,j＝1,2,9,34；
    i＝25,j＝0,5,35；
    i＝26,j＝2,7,12,13,36；
    i＝27,j＝0,6,37；
    i＝28,j＝1,2,5,38；
    i＝29,j＝0,4,39；
    i＝30,j＝2,5,7,9,40；
    i＝31,j＝1,13,41；
    i＝32,j＝0,5,12,42；
    i＝33,j＝2,7,10,43；
    i＝34,j＝0,12,13,44；
    i＝35,j＝1,5,11,45；
    i＝36,j＝0,2,7,46；
    i＝37,j＝10,13,47；
    i＝38,j＝1,5,11,48；
    i＝39,j＝0,7,12,49；
    i＝40,j＝2,10,13,50；
    i＝41,j＝1,5,11,51。
  10. 根据权利要求1，3至9任一项所述的方法，其特征在于，所述基于扩展因子Z和所述基矩阵对输入序列进行编码得到编码后的序列，包括：
    基于扩展因子Z和所述基矩阵的变换矩阵对所述输入序列进行编码得到编码后的序列，其中所述基矩阵的变换矩阵的基矩阵对应于所述基矩阵经过行交换、或者列交换、或者行交换和列交换后的矩阵。
  11. 根据权利要求1，3至9任一项所述的方法，其特征在于，所述基于扩展因子Z和所述基矩阵对输入序列进行编码得到编码后的序列，包括：
    基于扩展因子Z和所述基矩阵得到低密度奇偶校验LDPC矩阵H；
    根据所述LDPC矩阵H对所述输入序列进行编码得到编码后的序列。
  12. 根据权利要求1，3至12任一项所述的方法，其特征在于，
    所述输入序列表示为c＝{c 0,c 1,c 2,...,c K-1}，所述编码后的序列表示为d＝{d 0,d 1,d 2,...,d N-1}，所述编码后的序列d包括所述输入序列c中K-2·Z个比特和校验序列w中的校验比特，所述校验序列表示为w＝{w 0,w 1,w 2,...,w N+2·Z-K-1}；其中，K为Z的整数倍，N满足N＝(40+Kb)·Z,Kb为{6,8,9,10}中的一个。
  13. 根据权利要求12所述的方法，其特征在于，K＝10·Z，N＝50·Z。
  14. 根据权利要求11至13任一项所述的方法，其特征在于，
    所述校验序列w和所述输入序列c满足：
    Figure PCTCN2018091423-appb-100007
    其中，c T＝[c 0,c 1,c 2,...,c K-1] T，
    Figure PCTCN2018091423-appb-100008
    0 T为列向量，其所有元素的值为0。
  15. 根据权利要求11至14任意一项所述的方法，其特征在于，所述基矩阵中的每一零元素对应于所述LDPC矩阵H中Z*Z大小的全零矩阵，所述基矩阵中每一非零元素(i，j)对应于所述LDPC矩阵H中Z*Z大小的循环置换矩阵I(P i,j)，i为行号，j为列号，P i,j＝mod(V i,j,Z)，V i,j为所述基矩阵中非零元素(i，j)的值。
  16. 一种装置，用于执行如权利要求1至15项任一项所述的方法。
  17. 一种装置，其特征在于，所述通信装置包括处理器以及与所述处理器耦合的存储器，所述处理器用于：
    确定扩展因子Z及其对应的基矩阵；
    基于扩展因子Z和所述基矩阵对输入序列进行低密度奇偶校验LDPC编码得到编码后的序列；
    其中，所述基矩阵包括以下行、列上的非零元素，其中i表示行号，j表示列号，i和j均为大于或等于0的整数：
    i＝0,j＝0,1,2,3,6,9,10,11；
    i＝1,j＝0,3,4,5,6,7,8,9,11,12；
    i＝2,j＝0,1,3,4,8,10,12,13；
    i＝3,j＝1,2,4,5,6,7,8,9,10,13；
    i＝4,j＝0,1,11,14；
    i＝5,j＝0,1,5,7,11,15；
    i＝6,j＝0,5,7,9,11,16；
    i＝7,j＝1,5,7,11,13,17；
    i＝8,j＝0,1,12,18；
    i＝9,j＝1,8,10,11,19；
    i＝10,j＝0,1,6,7,20；
    i＝11,j＝0,7,9,13,21；
    i＝12,j＝1,3,11,22；
    i＝13,j＝0,1,8,13,23；
    i＝14,j＝1,6,11,13,24；
    i＝15,j＝0,10,11,25；
    i＝16,j＝1,9,11,12,26；
    i＝17,j＝1,5,11,12,27；
    i＝18,j＝0,6,7,28；
    i＝19,j＝0,1,10,29；
    i＝20,j＝1,4,11,30；
    i＝21,j＝0,8,13,31；
    i＝22,j＝1,2,32；
    i＝23,j＝0,3,5,33；
    i＝24,j＝1,2,9,34；
    i＝25,j＝0,5,35；
    i＝26,j＝2,7,12,13,36；
    i＝27,j＝0,6,37；
    i＝28,j＝1,2,5,38；
    i＝29,j＝0,4,39；
    i＝30,j＝2,5,7,9,40；
    i＝31,j＝1,13,41；
    i＝32,j＝0,5,12,42；
    i＝33,j＝2,7,10,43；
    i＝34,j＝0,12,13,44；
    i＝35,j＝1,5,11,45；
    i＝36,j＝0,2,7,46；
    i＝37,j＝10,13,47；
    i＝38,j＝1,5,11,48；
    i＝39,j＝0,7,12,49；
    i＝40,j＝2,10,13,50；
    i＝41,j＝1,5,11,51。
  18. 一种装置，其特征在于，所述通信装置包括处理器以及与所述处理器耦合的存储器，所述处理器用于：
    确定扩展因子Z及其对应的基矩阵；
    基于扩展因子Z和所述基矩阵对输入序列进行低密度奇偶校验LDPC译码；
    其中，所述基矩阵包括以下行、列上的非零元素，其中i表示行号，j表示列号，i和j均为大于或等于0的整数：
    i＝0,j＝0,1,2,3,6,9,10,11；
    i＝1,j＝0,3,4,5,6,7,8,9,11,12；
    i＝2,j＝0,1,3,4,8,10,12,13；
    i＝3,j＝1,2,4,5,6,7,8,9,10,13；
    i＝4,j＝0,1,11,14；
    i＝5,j＝0,1,5,7,11,15；
    i＝6,j＝0,5,7,9,11,16；
    i＝7,j＝1,5,7,11,13,17；
    i＝8,j＝0,1,12,18；
    i＝9,j＝1,8,10,11,19；
    i＝10,j＝0,1,6,7,20；
    i＝11,j＝0,7,9,13,21；
    i＝12,j＝1,3,11,22；
    i＝13,j＝0,1,8,13,23；
    i＝14,j＝1,6,11,13,24；
    i＝15,j＝0,10,11,25；
    i＝16,j＝1,9,11,12,26；
    i＝17,j＝1,5,11,12,27；
    i＝18,j＝0,6,7,28；
    i＝19,j＝0,1,10,29；
    i＝20,j＝1,4,11,30；
    i＝21,j＝0,8,13,31；
    i＝22,j＝1,2,32；
    i＝23,j＝0,3,5,33；
    i＝24,j＝1,2,9,34；
    i＝25,j＝0,5,35；
    i＝26,j＝2,7,12,13,36；
    i＝27,j＝0,6,37；
    i＝28,j＝1,2,5,38；
    i＝29,j＝0,4,39；
    i＝30,j＝2,5,7,9,40；
    i＝31,j＝1,13,41；
    i＝32,j＝0,5,12,42；
    i＝33,j＝2,7,10,43；
    i＝34,j＝0,12,13,44；
    i＝35,j＝1,5,11,45；
    i＝36,j＝0,2,7,46；
    i＝37,j＝10,13,47；
    i＝38,j＝1,5,11,48；
    i＝39,j＝0,7,12,49；
    i＝40,j＝2,10,13,50；
    i＝41,j＝1,5,11,51。
  19. 根据权利要求17所述的装置，其特征在于，所述基于扩展因子Z和所述基矩阵对输入序列进行编码得到编码后的序列，包括：
    基于扩展因子Z和所述基矩阵的变换矩阵对所述输入序列进行编码得到编码后的序列，其中所述基矩阵的变换矩阵的基矩阵对应于所述基矩阵经过行交换、或者列交换、或者行交换和列交换后的矩阵。
  20. 根据权利要求17所述的装置，其特征在于，所述基于扩展因子Z和所述基矩阵对输入序列进行编码得到编码后的序列，包括：
    基于扩展因子Z和所述基矩阵得到低密度奇偶校验LDPC矩阵H；
    根据所述LDPC矩阵H对所述输入序列进行编码得到编码后的序列。
  21. 根据权利要求17，19或者20任一项所述的装置，其特征在于，
    所述输入序列表示为c＝{c 0,c 1,c 2,...,c K-1}，所述编码后的序列表示为d＝{d 0,d 1,d 2,...,d N-1}，所述编码后的序列d包括所述输入序列c中K-2·Z个比特和校验序列w中的校验比特，所述校验序列表示为w＝{w 0,w 1, w2,...,w N+2·Z-K-1}；其中，K为Z的整数倍，N满足N＝(40+Kb)·Z,Kb为{6,8,9,10}中的一个。
  22. 根据权利要求21所述的装置，其特征在于，K＝10·Z，N＝50·Z。
  23. 根据权利要求20至22任一项所述的装置，其特征在于，所述校验序列w和所述输入 序列c满足：
    Figure PCTCN2018091423-appb-100009
    其中，c T＝[c 0,c 1,c 2,...,c K-1] T，
    Figure PCTCN2018091423-appb-100010
    0 T为列向量，其所有元素的值为0。
  24. 根据权利要求20至23任一项所述的装置，其特征在于，所述基矩阵中的每一零元素对应于所述LDPC矩阵H中Z*Z大小的全零矩阵，所述基矩阵中每一非零元素(i，j)对应于所述LDPC矩阵H中Z*Z大小的循环置换矩阵I(P i,j)，i为行号，j为列号，P i,j＝mod(V i,j,Z)，V i,j为所述基矩阵中非零元素(i,j)的值。
  25. 根据权利要求17至24任一项所述的装置，其特征在于：所述存储器用于保存以下一项或多项：
    扩展因子、基矩阵的基图、基矩阵的基图相关的参数、基矩阵、基矩阵的变换矩阵、基矩阵的相关参数、LDPC矩阵、LDPC矩阵的生成矩阵、或LDPC矩阵的相关参数。
  26. 根据权利要求25所述的装置，其特征在于，所述基矩阵的相关参数包括以下一个或多个：所述基矩阵中非零元素的位置，或所述基矩阵中非零元素的值，或者所述基矩阵中每一行非零元素的行重，或者所述基矩阵中每一列非零元素的列重，或者，码率。
  27. 一种通信装置，其特征在于，包括如权利要求16，17,19至26任一项所述的装置，以及
    用于对编码后得到的LDPC码进行速率匹配的器件；
    用于对所述速率匹配后的LDPC码进行交织的器件；
    用于对所述交织后的LDPC码进行调制的器件。
  28. 一种通信装置，其特征在于，包括如权利要求16,18至26任一项所述的装置，以及
    解调器，用于对信号进行解调；
    解交织器，用于对所述解调后的信号进行解交织；
    解速率匹配器，用于对所述解交织后的信号进行解速率匹配得到所述LDPC码的软值序列。
  29. 一种终端，其特征在于，包括如权利要求16至26任一项所述的装置，或者权利要求27或者28所述的通信装置。
  30. 一种基站，其特征在于，包括如权利要求16至26任一项所述的装置，或者权利要求27或者28所述的通信装置。
  31. 一种通信系统，其特征在于包括如权利要求29所述的终端以及如权利要求30所述的基站。
  32. 一种计算机可读存储介质，包括指令，当其在计算机上运行时，使得计算机执行如权利要求1至15任一项所述的方法。
  33. 一种计算机程序产品，当其在计算机上运行时，使得计算机执行权利要求1至15任一项所述的方法。
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