WO2018201609A1 - 信息处理的方法和通信装置 - Google Patents

信息处理的方法和通信装置 Download PDF

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Publication number
WO2018201609A1
WO2018201609A1 PCT/CN2017/092877 CN2017092877W WO2018201609A1 WO 2018201609 A1 WO2018201609 A1 WO 2018201609A1 CN 2017092877 W CN2017092877 W CN 2017092877W WO 2018201609 A1 WO2018201609 A1 WO 2018201609A1
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WIPO (PCT)
Prior art keywords
matrix
sub
column
base
columns
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PCT/CN2017/092877
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English (en)
French (fr)
Inventor
郑晨
马亮
刘晓健
魏岳军
曾歆
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华为技术有限公司
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Priority claimed from CN201710381396.2A external-priority patent/CN108809328B/zh
Priority claimed from PCT/CN2017/086227 external-priority patent/WO2018201540A1/zh
Priority claimed from PCT/CN2017/087073 external-priority patent/WO2018201547A1/zh
Priority claimed from PCT/CN2017/087943 external-priority patent/WO2018201554A1/zh
Priority to KR1020197023750A priority Critical patent/KR102205936B1/ko
Priority to JP2019546359A priority patent/JP7171590B2/ja
Priority to MX2019010697A priority patent/MX2019010697A/es
Priority to AU2017413002A priority patent/AU2017413002B2/en
Priority to RU2019128364A priority patent/RU2740151C1/ru
Priority to CA3051761A priority patent/CA3051761C/en
Priority to CN201780090448.9A priority patent/CN110999091B/zh
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP23170415.6A priority patent/EP4250571A3/en
Priority to BR112019018329A priority patent/BR112019018329B8/pt
Priority to MYPI2019004703A priority patent/MY195263A/en
Priority to EP17908540.2A priority patent/EP3540948A4/en
Publication of WO2018201609A1 publication Critical patent/WO2018201609A1/zh
Priority to US16/205,186 priority patent/US10432219B2/en
Priority to ZA2019/05493A priority patent/ZA201905493B/en
Priority to US16/584,911 priority patent/US10924134B2/en
Priority to US17/161,539 priority patent/US11374591B2/en
Priority to US17/742,183 priority patent/US11777521B2/en
Priority to JP2022175642A priority patent/JP2023014085A/ja
Priority to US18/448,782 priority patent/US20240048155A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/033—Theoretical methods to calculate these checking codes
    • H03M13/036—Heuristic code construction methods, i.e. code construction or code search based on using trial-and-error
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/618—Shortening and extension of codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing
    • H03M13/6368—Error control coding in combination with rate matching by puncturing using rate compatible puncturing or complementary puncturing
    • H03M13/6393—Rate compatible low-density parity check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H03M13/6516—Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location

Definitions

  • Embodiments of the present invention relate to the field of communications, and in particular, to a method and a communication device for information processing.
  • Low density parity check (LDPC) code is a kind of linear block coding with sparse check matrix, which has the characteristics of flexible structure and low decoding complexity. Because it uses a partially parallel iterative decoding algorithm, it has a higher throughput than the traditional Turbo code.
  • the LDPC code can be used for the error correction code of the communication system, thereby improving the reliability and power utilization of the channel transmission.
  • LDPC codes can also be widely used in space communication, optical fiber communication, personal communication systems, ADSL, and magnetic recording devices. At present, LDPC codes have been considered as one of channel coding methods in the fifth generation mobile communication.
  • an LDPC matrix with special structured features can be used.
  • the LDPC matrix H with special structuring features can be obtained by extending the LDPC basis matrix of a quasi-cycle (QC) structure.
  • QC-LDPC is suitable for hardware with high parallelism and provides higher throughput.
  • the LDPC matrix can be designed to be applied to channel coding.
  • Embodiments of the present invention provide a method, a communication device, and a system for information processing, which can support encoding and decoding of information bit sequences of various lengths, and meet the flexible code length code rate requirements of the system.
  • an encoding method and an encoder are provided that encode an input sequence using a low density parity check LDPC matrix.
  • a decoding method and decoder are provided that decode an input sequence using a low density parity check LDPC matrix.
  • the base map of the LDPC matrix is represented as a matrix of m rows and n columns, m is an integer greater than or equal to 5, and n is an integer greater than or equal to 27.
  • the base map includes at least a sub-matrix A and a sub-matrix B, wherein the sub-matrix A is a matrix of 5 rows and 22 columns; the sub-matrix B is a matrix of 5 rows and 5 columns, wherein the sub-matrix B includes A column with a weight of 3 and a sub-matrix B' of a double-diagonal structure.
  • one of the columns has a weight of 5
  • the first column has a weight of 4
  • the remaining 20 columns have a weight of 3.
  • one of the columns has a weight of 3, and the three columns have a weight of 2, respectively.
  • the sub-matrix B further includes one column with a weight of one.
  • the base map of the LDPC matrix is represented as a matrix of m rows and n columns, m is an integer greater than or equal to 5, and n is an integer greater than or equal to 27.
  • the base map includes at least a sub-matrix A and a sub-matrix B, wherein the sub-matrix A is a matrix of 5 rows and 22 columns; the sub-matrix B is a matrix of 5 rows and 5 columns; wherein the sub-matrix A and In the matrix formed by the sub-matrix B, the weight of one column is 5, the weight of one column is 4, the weight of 21 columns is 3, the weight of 3 columns is 2, and the weight of 1 column is 1.
  • the weight of one row satisfies greater than or The value is equal to 1, and is less than or equal to 5, and the weights of the remaining 4 rows respectively satisfy greater than or equal to 17, and are less than or equal to 21.
  • the matrix composed of the sub-matrix A and the sub-matrix B may include rows of 5 rows of matrix blocks composed of the 0th row to the 4th row and the 0th column to the 26th column in the base map 30a. Or columns, where rows can be exchanged and columns can be exchanged.
  • the third row and the zeroth row of the matrix block formed by the sub-matrix A and the sub-matrix B in the base map 30a can be exchanged, the second row and the first row are exchanged, and the 23rd column and the 25th column are exchanged to obtain a basis.
  • the core matrix portion in Figure 80a is the core matrix portion in Figure 80a.
  • a portion of the base matrix of the LDPC matrix corresponding to the sub-matrix A and the sub-matrix B may be represented as, for example, base matrices 30b-1, 30b-2, 30b-3, 30b-4, 30b-5, 30b- 6. Any of 30b-7, 30b-8, 30b-9 or 30b-10.
  • a portion of the base matrix of the LDPC matrix corresponding to the sub-matrix A and the sub-matrix B may be represented as based on the base matrix 30b-1, 30b-2, 30b-3, 30b-4, 30b-5, 30b-6, 30b-7 Any one of 30b-8, 30b-9 or 30b-10 undergoing column switching, or row switching, or row switching and column switching.
  • a portion of the base matrix of the LDPC matrix corresponding to the sub-matrix A and the sub-matrix B may include base matrices 30b-1, 30b-2, 30b-3, 30b-4, 30b-5, 30b-6, 30b-7, Each row or column of any of 30b-8, 30b-9 or 30b-10.
  • portions of the base matrix of the LDPC matrix corresponding to the sub-matrix A and the sub-matrix B may be represented as base matrices 80b-1, 80b-2, 80b-3, 80b-4, 80b-5, and 80b- 6, wherein 80b-4 is a matrix of 30b-3 after row and column exchange, 80b-5 is a matrix of 30b-4 after row and column exchange, and 80b-6 is a matrix of 30b-5 after row and column exchange.
  • the LDPC code requires different spreading factors Z. Based on the foregoing implementation manner, in a possible implementation manner, a base matrix corresponding thereto is adopted based on different spreading factors Z.
  • the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be the base matrix 30b in FIG. 3b. -1 is shown;
  • the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be the base matrix 30b in FIG. 3b. -2 is shown;
  • the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be as shown in FIG. 3b.
  • the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be the base matrix 30b in FIG. 3b. -4 is shown;
  • the portion of the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 30b-5 of FIG. 3b.
  • the portion of the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 80b-1 of FIG. 8b;
  • the portion of the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 80b-2 of FIG. 8b;
  • the portion of the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 80b-3 of FIG. 8b;
  • the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in FIG. 8b.
  • the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be the base matrix 80b of FIG. 8b. -5 is shown;
  • the portion of the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 80b-6 in the figure.
  • the sub-matrix A may further include two columns of built-in punctured bit columns.
  • a sub-matrix C, a sub-matrix D, and a sub-matrix E of corresponding sizes may be added based on the core matrix to obtain different code rates.
  • the sub-matrix C is an all-zero matrix of 5 rows and m D columns;
  • the sub-matrix D is a matrix of 27 rows of m D rows;
  • the sub-matrix E is an identity matrix of m D rows and m D columns;
  • n D is an integer and 0 ⁇ m D ⁇ 41.
  • the sub-matrix D includes m D rows in the matrix F, the matrix F is 41 rows and 27 columns, and the row weights of the rows of the matrix F are 7, 7, 9, 8, 7, 7, 8, 6 respectively. ,6,5,6,5,5,6,5,5,5,5,5,4,4,4,5,4,5,4,4,4,4,3,4,4,4,4 , 3, 3, 4, 4, 3, 3, 3, 4.
  • the matrix F is a matrix composed of the 5th row to the 45th row and the 0th column to the 26th column in the base map 30a.
  • the offset matrix of the matrix F can be represented as any of the base matrices 30c-1, 30c-2, 30c-3, 30c-4, and 30c-5.
  • lines 17 and 19 of base map 30a may be swapped, and columns 39 and 41 may be swapped to obtain base map matrix 80a as shown in Figure 8a.
  • the sub-matrix D includes m D rows in the matrix F, and the m D rows may not be exchanged in rows, or one or more rows may be exchanged between rows, and the sub-matrix E is still a diagonal structure, for example, a sub-matrix
  • the matrix D includes m D rows in the matrix F, wherein the 12th row and the 14th row of the matrix F are row-exchanged, and the sub-matrix E is still in a diagonal structure, thereby obtaining the base map 80a.
  • the LDPC code requires different spreading factors Z.
  • a base matrix corresponding thereto is adopted based on different spreading factors Z.
  • the sub-matrix D in the base matrix may include m D rows of the offset matrix as shown in 30c-1;
  • the sub-matrix D in the base matrix may include m D rows of the offset matrix as shown in 30c-2;
  • the sub-matrix D in the base matrix may include m D rows of the offset matrix as shown in 30c-3 ;
  • the sub-matrix D in the base matrix may include m D rows of the offset matrix as shown in 30c-4;
  • the sub-matrix D in the base matrix may include m D rows of the offset matrix as shown in 30c-5.
  • the set of spreading factors may be ⁇ 24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104 , 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, 384 ⁇ :
  • the offset matrix of the matrix F may be as shown in 80c-1;
  • the offset matrix of the matrix F may be as shown in 80c-2;
  • the offset matrix of the matrix F may be as shown in 80c--3;
  • the offset matrix of the matrix F may be as shown in 80c-4;
  • the offset matrix of the matrix F may be as shown in 80c-5;
  • the offset matrix of the matrix F may be as shown in 80c-6.
  • the base map and base matrix of the LDPC matrix in the first implementation can satisfy the performance requirements of code blocks having a block length of 352 to 8448 bits.
  • the method further includes: determining the expansion factor Z.
  • the value of the spreading factor Z is determined according to the length K of the input sequence. For example, if the input sequence length is K, a minimum value satisfying 22*Z ⁇ K can be determined among a plurality of system-defined spreading factors.
  • encoding the input sequence using an LDPC matrix includes:
  • the input sequence is encoded using an LDPC matrix corresponding to the spreading factor Z.
  • decoding the input sequence using the LDPC matrix includes:
  • the input sequence is decoded using an LDPC matrix corresponding to the spreading factor Z.
  • the base matrix of the LDPC matrix may be stored in a memory.
  • the base map of the LDPC matrix is stored in the memory, and the offset value of the non-zero element in the base matrix of the LDPC matrix may be Saved in memory.
  • At least one of the base map and the base matrix used for LDPC encoding or decoding is at least one of a base map and a base matrix of the foregoing LDPC matrix, or Column exchange, or row exchange and column exchange.
  • a communication apparatus can include a module for performing any of the possible implementations of the first aspect of the method design described above.
  • the module can be software and/or hardware.
  • the communication device provided by the third aspect comprises the encoder, the determining unit and the processing unit according to the first aspect described above.
  • the determining unit is operative to determine a spreading factor Z required to encode the input sequence.
  • the processing unit is configured to encode the input sequence by using an LDPC matrix corresponding to the spreading factor Z.
  • the communication device further includes a transceiver, and the transceiver is configured to send a signal corresponding to the encoded information data.
  • a communication apparatus can include a module for performing any of the possible implementations of the second aspect of the method design described above.
  • the module can be software and/or hardware.
  • the communication device provided by the fourth aspect includes the decoder, the obtaining unit and the processing unit according to the second aspect described above.
  • the obtaining unit is configured to acquire a soft value and an expansion factor Z of the LDPC code.
  • the processing unit is configured to decode the soft value of the LDPC code based on the base matrix H B corresponding to the spreading factor Z to obtain an information bit sequence.
  • the communication device also includes a transceiver for receiving a signal comprising an LDPC based code.
  • a communication device in a fifth aspect, includes one or more processors.
  • one or more of the processors may implement the functions of the encoder of the first aspect, and in another possible design, the encoder of the first aspect may be the processor In part, the processor can implement other functions in addition to the functions of the encoder described in the first aspect.
  • one or more of the processors may implement the functions of the decoder of the second aspect, and in another possible design, the decoder of the second aspect may be Part of the processor.
  • the communication device may further include a transceiver and an antenna.
  • the communication device may further include a device for generating a transport block CRC, a device for code block splitting and CRC check, an interleaver for interleaving, a modulator for modulation processing, and the like.
  • the communication device may further include a demodulator for demodulation operation, a deinterleaver for deinterleaving, a device for de-rate matching, and the like.
  • a demodulator for demodulation operation e.g., a demodulator for demodulation operation
  • a deinterleaver for deinterleaving e.g., a device for de-rate matching
  • the functionality of these devices can be implemented by one or more processors.
  • the functionality of these devices can be implemented by one or more processors.
  • an embodiment of the present invention provides a communication system, including the communication device according to the above third aspect, and the communication device according to the fourth aspect.
  • an embodiment of the present invention provides a communication system, where the system includes one or more communication devices according to the fifth aspect.
  • an embodiment of the present invention provides a computer storage medium having stored thereon a program, and when executed, causes a computer to perform the method described in the above aspect.
  • Yet another aspect of the present application provides a computer program product comprising instructions which, when run on a computer, cause the computer to perform the methods described in the various aspects above.
  • the method, device, communication device and communication system of the information processing according to the embodiments of the present invention can adapt to the flexible code length code rate requirement of the system in coding performance and error leveling.
  • 1 is a schematic diagram of a base map, a base matrix, and a cyclic permutation matrix of an LDPC code
  • FIG. 2 is a schematic structural diagram of a base diagram of an LDPC code
  • FIG. 3a is a schematic diagram of a LDPC code base diagram according to an embodiment of the present invention.
  • 3b is a schematic diagram of a base matrix of an LDPC code according to another embodiment of the present invention.
  • 3c is a schematic diagram of a base matrix of an LDPC code according to another embodiment of the present invention.
  • FIG. 5 is a schematic diagram of performance provided by another embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of an information processing apparatus according to another embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a communication system according to another embodiment of the present invention.
  • FIG. 8a is a schematic diagram of a LDPC code base diagram according to another embodiment of the present invention.
  • FIG. 8b is a schematic diagram of a base matrix of an LDPC code according to another embodiment of the present invention.
  • FIG. 8c is a schematic diagram of a base matrix of an LDPC code according to another embodiment of the present invention.
  • FIG. 9 is a schematic diagram of performance of an LDPC code according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of performance of an LDPC code according to an embodiment of the present invention.
  • FIG. 11a is a schematic diagram of a LDPC code base diagram according to another embodiment of the present invention.
  • Figure 11b is a schematic diagram of a base matrix of a base map based on the LDPC code provided in Figure 11a;
  • FIG. 12 is a schematic diagram of a base diagram according to another embodiment of the present invention.
  • the “communication device” may be a chip (such as a baseband chip, or a data signal processing chip, or a general purpose chip, etc.), a terminal, a base station, or other network device.
  • a terminal is a device having a communication function, and may include a handheld device having a wireless communication function, an in-vehicle device, a wearable device, a computing device, or other processing device connected to a wireless modem.
  • Terminals can be called different names in different networks, such as: user equipment, mobile stations, subscriber units, stations, cellular phones, personal digital assistants, wireless modems, wireless communication devices, handheld devices, laptops, cordless phones, Wireless local loop station, etc.
  • a base station also referred to as a base station device, is a device deployed in a radio access network to provide wireless communication functions.
  • the name of a base station may be different in different wireless access systems, for example, in a Universal Mobile Telecommunications System (UMTS) network, a base station is called a Node B, but in an LTE network.
  • a base station is called an evolved Node B (eNB or eNodeB).
  • eNB evolved Node B
  • a base station in a new radio (NR) network is called a transmission reception point (TRP) or a next generation node B (generation node B, gNB). ), or other base stations in various networks may also use other names.
  • TRP transmission reception point
  • gNB next generation node B
  • the invention is not limited to this.
  • the LDPC code can usually be represented by a parity check matrix H.
  • the parity check matrix H of the LDPC code can be obtained by a base graph and a shift value.
  • the base map can usually include m*n matrix elements, which can be represented by a matrix of m rows and n columns.
  • the value of the matrix element is 0 or 1, and the element with a value of 0 is sometimes called a zero element. , indicating that the element can be replaced by Z*Z's zero matrix.
  • An element with a value of 1, sometimes referred to as a non-zero element indicates that the element can be a cyclic permutation matrix of Z*Z (circulant permutation) Matrix) replacement.
  • each matrix element represents an all-zero matrix or a cyclic permutation matrix.
  • the base and column numbers of the base map and the matrix are numbered from 0, for convenience of explanation.
  • the 0th column is represented as the base map and the first column of the matrix, the first column.
  • the second column, the 0th row, represented as the base map and the matrix represents the base map and the first row of the matrix, the first row is represented as the base map and the second row of the matrix, and so on.
  • the line number and column number can also be numbered from 1, and the corresponding line number and column number are incremented by 1 on the basis of the line number and column number shown in this article, for example, if the line number or column number is from 1 Starting with the number, the first column represents the base column and the first column of the matrix, the second column represents the base map and the second column of the matrix, the first row represents the first row representing the base map and the matrix, and the second row represents the base map. And the second line of the matrix, and so on.
  • the element value of the i-th row and the j-th column in the base map is 1, and the offset value is P i,j , P i,j is an integer greater than or equal to 0, the value of the j-th column of the i-th row is 1
  • the element can be replaced by a cyclic permutation matrix of Z*Z corresponding to P i,j , which can be obtained by cyclically shifting the unit matrix of Z*Z by P i, j times to the right.
  • each element with a value of 0 in the base map is replaced by an all-zero matrix of Z*Z, and each element having a value of 1 is replaced by a cyclic permutation matrix of Z*Z corresponding to its offset value,
  • the parity check matrix of the LDPC code can be used to indicate the location of the offset value, and the non-zero elements in the base map correspond to the offset values.
  • Z is a positive integer, which can also be called a lifting factor, sometimes called lifting size, or lifting factor, etc., which can be determined according to the code block size supported by the system and the size of the information data. It can be seen that the size of the parity check matrix H is (m*Z)*(n*Z).
  • each zero element is replaced by a 4*4 size all-zero matrix 11a.
  • the cyclic permutation matrix 11d is replaced by a quadrature cyclic shift of the 4*4 unit matrix 11b.
  • the system usually defines a base matrix of m*n.
  • Each element in the base matrix corresponds to the position of each element in the base map.
  • the zero elements in the base map are in the base matrix.
  • the medium position is unchanged, and is represented by -1.
  • the non-zero element with the value of the jth column in the i-th row and the j-th column in the base map is unchanged in the base matrix, and can be expressed as P i,j , P i,j is greater than or equal to A positive integer of 0.
  • the base matrix is sometimes referred to as an offset matrix of the base matrix.
  • a base matrix corresponding to the base map 10a is shown.
  • the base map or the base matrix of the LDPC code may further include a p-column built-in puncture bit string, and p may be an integer of 0-2, and these columns participate in encoding, but the system bits corresponding to the encoding are not
  • R (nm)/(np)
  • the LDPC code used in the wireless communication system is a QC-LDPC code, and the check bit portion has a double diagonal structure or a raptor-like structure, which can simplify coding and support incremental redundant hybrid retransmission.
  • a QC-LDPC shift network QSN
  • Banyan network a Banyan network
  • Benes network is generally used to implement cyclic shift of information.
  • a matrix of a QC-LDPC code having a raptor-like structure has a matrix size of m rows and n columns, and may generally include five sub-matrices A, B, C, D, and E, wherein the weight of the matrix is determined by a non-zero element
  • row weight refers to the number of non-zero elements included in a row
  • the weight of the column column The number.
  • Submatrix A is a matrix of m A rows and n A columns, which may be of size M A *n A , where each column corresponds to Z systematic bits in the LDPC code, and system bits are sometimes referred to as information bits.
  • the sub-matrix B is a square matrix of m A rows and m A columns, and its size may be m A *m A , and each column corresponds to Z parity bits in the LDPC code.
  • the sub-matrix B includes a sub-matrix B' with a double-diagonal structure and a matrix column with a weight of 3 (referred to as a 3-column re-column), wherein the matrix column with a column weight of 3 is located before the sub-matrix B', as shown in FIG.
  • the sub-matrix B may further include a matrix column having a column weight of 1 (referred to as a single column re-column), and the single-column re-column may be located in the first column or the last column of the sub-matrix B, and the non-zero elements in the sub-matrix B
  • the last line causes the row of the last row of the submatrix B to have a weight of 1, as shown by 20b or 20c in FIG.
  • the matrix generated based on the sub-matrices A and B is usually a core matrix and can be used to support high code rate encoding.
  • the sub-matrix C is an all-zero matrix having a size of m A ⁇ (n - (m A + n A )).
  • the sub-matrix E is an identity matrix having a size of (mm A ) ⁇ (mm A ).
  • the submatrix D has a size of (mm A ) ⁇ (n A + m A ) and is generally used to generate a low bit rate check bit.
  • the structure of the two parts of the sub-matrices A and D is one of the factors influencing the coding performance of the LDPC code.
  • the matrix of the sub-matrices A and B may be encoded to obtain the parity bit corresponding to the sub-matrix B, and then The entire matrix is encoded to obtain parity bits corresponding to the E portion of the sub-matrix. Since the sub-matrix B can include the sub-matrix B' of the double-diagonal structure and a single-column re-column, the parity bits corresponding to the double-diagonal structure can be obtained first in the encoding, and the parity bits corresponding to the single-column re-column can be obtained.
  • H core-dual ⁇ [S P e ] T 0, where S is an input sequence, a vector composed of information bits, P e is a vector composed of parity bits, and [S P e ] T represents The matrix transpose consisting of the input sequences S and P e .
  • H core-dual H core-dual check bit corresponding to the input sequence S includes all information bits; then according to obtain H core-dual check bit corresponding to an input sequence and calculates S Obtaining the parity bits corresponding to the single column re-column in the sub-matrix B, in this case, all the parity bits corresponding to the sub-matrix B can be obtained; and then according to the input sequence S and the parity bits corresponding to the sub-matrix B, the sub-matrix D is partially encoded.
  • the check bits corresponding to the sub-matrix E thus obtaining all information bits and all check bits, these bits constitute the encoded sequence, that is, an LDPC code sequence.
  • the LDPC code encoding may also include shortening and puncturing operations. Both truncated bits and punctured bits are not transmitted.
  • the truncation is generally truncated from the last bit of the information bit, and can be truncated in different ways.
  • the truncated number of bits s 0 can be set to the last s 0 bits in the input sequence S to obtain the input sequence S', such as set to 0 or null, or some other value, and then through the LDPC matrix pair
  • the input sequence S' is encoded.
  • the last (s 0 mod Z) bits in the input sequence S may be set to the known bits to obtain the input sequence S', if set to 0 or null, or some other value.
  • the input sequence S' is encoded using the LDPC matrix H', or the last in the submatrix A
  • the column does not participate in the encoding of the input sequence S'. After the encoding is completed, the truncated bits are not sent.
  • the punching may be a punching bit built in the input sequence or a punching bit.
  • the last bit of the parity bit is usually punctured.
  • the puncturing may be performed according to the preset puncturing order of the system.
  • a possible implementation manner is that the input sequence is first encoded, and then the last p bits in the parity bit are selected according to the number of bits p to be punctured, or p bits are selected according to the system's preset puncturing order. p bits are not sent.
  • the p columns of the matrix corresponding to the punctured bits and the p rows of the non-zero elements in the columns may also be determined, and the rows and columns do not participate in the coding, and the corresponding school is not generated. Check the bit.
  • the decoding involved in the present application may be a plurality of decoding methods, for example, a min-sum (MS) decoding method or a belief propagation decoding method.
  • MS decoding method is sometimes also referred to as a Flood MS decoding method.
  • the input sequence is initialized and iteratively processed, the hard decision detection is performed after the iteration, and the hard decision result is verified. If the decoding result conforms to the check equation, the decoding is successful, the iteration is terminated, and the decision result is output. .
  • the decoding mode is only an example.
  • the base map and/or the base matrix provided by the present application, other decoding methods known to those skilled in the art may be used.
  • the decoding method is not limited in this application.
  • the LDPC code can be obtained based on the base map and the base matrix.
  • the density evolution method of the base map or the base matrix can determine the upper performance limit of the LDPC code, and the error leveling layer of the LDPC code is determined according to the offset value in the base matrix. Improving the performance of the compiled code and reducing the error leveling layer is one of the goals of determining the base map and the base matrix.
  • the code length in the wireless communication system is flexible, and may be a small block length code block such as 40 bits or 1280 bits, or a large block length code block such as 5000 bits 8448 bits.
  • FIGS. 3a, 3b, and 3c are respectively an example of a base map and a base matrix of an LDPC code, which can satisfy the performance requirement of a block of blocks having a block length of up to 8448 bits
  • FIGS. 8a, 8b, and 8c show another LDPC code.
  • Base and base matrix examples Figures 11a and 11b give an example of a base and base matrix for another LDPC code.
  • the column numbers and row numbers are respectively shown on the uppermost side and the leftmost side in the drawings 3a, 3b, and 3c.
  • FIGS. 4 and 5 respectively show the LDPC codes shown in FIGS. 3a-3c. Schematic diagram of performance at two different code rates. Fig.
  • FIG. 3a shows an example of a base map 30a of an LDPC code, in which the uppermost row 0-67 of the figure represents the column number, and the leftmost column 0-45 represents the row number, that is, the size of the base map is 46 rows and 68 columns.
  • the sub-matrix A corresponds to a systematic bit, and has a size of 5 rows and 22 columns, and is composed of elements of the 0th row to the 4th row and the 0th column to the 21st column in the base map 30a;
  • the sub-matrix B corresponds to a parity bit, and has a size of 5 rows and 5 columns, and is composed of elements of the 0th row to the 4th row and the 22nd column to the 26th column in the base map 30a;
  • Submatrix A and submatrix B form the core matrix part of the LDPC code base map, that is, form a matrix of 5 rows and 27 columns, which can be used for high bit rate coding.
  • the weight of one column is 5
  • the weight of one column is 4
  • the weight of 21 columns is 3
  • the weight of 3 columns is 2
  • the weight of 1 column is 1.
  • the row weight of the last row (the fourth row) of the submatrix B and the column weight of the last column (the fourth column of the submatrix B, the 26th column of the core matrix) are both 1, and the matrix B includes 1 column and 3 columns.
  • Re-column that is, column 0 of the sub-matrix B (column 22 of the core matrix) has a column weight of 3, columns 1 to 3 of the sub-matrix B (columns 23 to 25 of the core matrix), and behaviors 0 to 3 Diagonal structure.
  • the core matrix of the base map 30a includes four rows of rows having a weight of 19, and one row of rows having a weight of three. That is, the weights of the rows in the core matrix composed of the submatrix A and the submatrix B are 19, 19, 19, 19, and 3, respectively. It should be noted that the order of the rows in the core matrix can be exchanged, for example, the 0th row and the 2nd row are exchanged, the 1st row and the 3rd row are exchanged, and the like.
  • the row having a weight of 3 may be as shown in the fourth row of the core matrix of the base map 30a, and the columns 0 to 26; the row having the weight 19 may be the 0th to the 3rd rows in the core matrix of the base map 30a, respectively.
  • the order of the 27 columns of the core matrix portion after the column exchange is given, and the column number refers to the column number of the matrix after the exchange. 0 starts numbering, and the column number before the exchange refers to the column number of the matrix listed in the matrix before the exchange.
  • the row exchange does not change the weight of the columns in the matrix
  • the column exchange does not change the weight of the rows in the matrix, and the number of non-zero elements in the matrix does not occur. changed.
  • the weight of each row of the base map 80a after the row exchange and the column exchange does not change.
  • Basemaps that use row swapping, or column swapping, or row swapping and column swapping do not affect performance.
  • the performance does not affect the overall meaning, the impact is acceptable, and the tolerance is For example, performance may be degraded within a certain range for some scenarios or within certain ranges, but performance may be improved in some scenarios or within certain ranges, and overall has little effect on performance.
  • the core matrix of the base map 80a still includes the columns in the core matrix of the base map 30a, and the weight of one row is 3.
  • the remaining 4 lines have a weight of 19, but the order of the lines is different.
  • the core matrix of the base map 30a after the column exchange still includes the columns in the core matrix of the base map 30a, 1
  • the weight of the column is 5, the weight of the 1 column is 4, the weight of the 21 column is 3, the weight of the 3 column is 2, and the weight of the 1 column is 1, except that the order of the columns is different. It should be noted that this is merely an example and is not limited thereto.
  • a small amount of modification to the matrix elements is acceptable for performance.
  • a small number of modifications may be made based on the core matrix of the base map 30a, for example, where the weight of one row satisfies greater than or equal to 1, and is less than or equal to 5, and the weights of the remaining four rows respectively satisfy greater than or Equal to 17, and less than or equal to 21.
  • 1 row has a weight of 2
  • the remaining 4 rows have a weight of 18, or 1 row has a weight of 4
  • the remaining 4 rows have weights of 17, 18, 19, 19, and so on. It can be understood that the weights of some of the lines may be increased or decreased by 1-2 according to the solution provided by the present application, which is not limited in this application.
  • the rows with the row weight of 1 in the submatrix B are usually in the same row.
  • the number of built-in punctured bit columns is 2, that is, the 0th column and the 1st column are built-in punctured bit columns, as shown in the base map 30a or 80a, in the 4th row, the 0th column and the 1st column.
  • the elements are non-zero elements, the elements in columns 2 through 25 are zero elements, the elements in column 26 are non-zero elements, and the weight in row 4 is 3, not only in the core matrix, but also in the weight of the row.
  • the weight of the rows in the graph matrix is also minimal. This setup improves the performance of encoding and decoding.
  • the LDPC code requires different spreading factors Z.
  • the spreading factor Z may comprise one or more of the following designs: 16, 18, 20, 22, 24, 26, 28, 30, 32, 36 ,40,44,48,52,56,60,64,72,80,88,96,104,112,120,128,144,160,176,192,208,224,240,256,288,320 , 352,384.
  • the base matrix corresponding thereto can be adopted based on different spreading factors Z, respectively.
  • An example of a plurality of base matrices of the core matrix in the base map 30a is shown in Figure 3b.
  • Each base matrix is obtained based on the core matrix of the base map 30a and the spreading factor Z, wherein the non-zero elements of the i-th row and the j-th column in the base map 30a are offset values P i in the i-th row and the j-th column of the base matrix , j , the zero element in the base map 30a is represented by -1 or null in the offset matrix.
  • the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be the base matrix 30b in FIG. 3b. -1 is shown;
  • the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be the base matrix 30b in FIG. 3b. -2 is shown;
  • the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be as shown in FIG. 3b.
  • the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be the base matrix 30b in FIG. 3b. -4 is shown;
  • the portion of the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 30b-5 in the figure.
  • the set of spreading factors may be ⁇ 24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, 384 ⁇ :
  • the portion of the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 30b-6 of FIG. 3b;
  • the portion of the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 30b-7 in FIG. 3b;
  • the portion of the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 30b-8 of FIG. 3b;
  • the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be as shown in FIG. 3b.
  • the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be the base matrix 30b in FIG. 3b. -4 is shown;
  • the portion of the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 30b-5 in the figure.
  • the base matrix corresponding to the base map may also be more, and the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may correspond to different Base matrix, for example:
  • the portion of the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 30b-6 of FIG. 3b;
  • the portion of the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 30b-7 in FIG. 3b;
  • the portion of the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 30b-8 of FIG. 3b;
  • the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 30b-9 or 30b-10 in FIG. 3b. ;
  • the portion of the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 30b-3 in FIG. 3b;
  • the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be the base matrix 30b in FIG. 3b. -4 is shown;
  • the portion of the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 30b-5 in the figure.
  • FIG. 8b An example of a plurality of base matrices of the core matrix in the base map 80a is shown in Figure 8b.
  • Each base matrix is obtained based on the core matrix of the base map 80a and the spreading factor Z, wherein the non-zero elements of the i-th row and the j-th column in the base map 80a are offset values P i in the i-th row and the j-th column of the base matrix.
  • j the zero element in the base map 80a is represented by -1 or null in the offset matrix.
  • the set of spreading factors may be ⁇ 24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, 384 ⁇ :
  • the portion of the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 80b-1 of FIG. 8b;
  • the portion of the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 80b-2 of FIG. 8b;
  • the portion of the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 80b-3 of FIG. 8b;
  • the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in FIG. 8b.
  • the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be the base matrix 80b of FIG. 8b. -5 is shown;
  • the portion of the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 80b-6 in the figure.
  • the base matrix corresponding to the base map may also be more, and the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be different.
  • Base matrix for example, where:
  • the portion of the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 80b-1 of FIG. 8b;
  • the portion of the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 80b-2 of FIG. 8b;
  • the portion of the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 80b-3 of FIG. 8b;
  • the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 80b-7 or 80b-8 in FIG. 8b. ;
  • the portion of the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 80b-4 in FIG. 8b;
  • the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be the base matrix 80b of FIG. 8b. -5 is shown;
  • the portion of the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 80b-6 in the figure.
  • the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 80b-9 of FIG. 8b. Since the spreading factor Z can be divided in a number of ways, correspondingly, the base matrix used for a set of spreading factors Z can be combined with performance considerations.
  • the value of the spreading factor Z is determined according to the length K of the input sequence. For example, if the input sequence length is K, the minimum value satisfying 22*Z ⁇ K can be determined as a matrix expansion among a plurality of system-defined spreading factors. The value of the factor. Further, the corresponding base matrix can be selected according to the determined spreading factor. As shown in Table 2, as an example of the correspondence between the base matrix and the spreading factor, a plurality of system-defined spreading factors are divided into 8 groups, that is, 8 sets, and the set indexes are 1 to 8, respectively, correspondingly, The matrix also has 8 PCM1-PCM8:
  • the base matrix 80b-9 can be used as the PCM 8
  • the spreading factor Z is any one of 15, 30, 60, 120, 240, 80b-9 can be used as the base matrix
  • the expansion factor Z is used to expand to obtain the LDPC check matrix.
  • Z is greater than or equal to 24, the base matrix 80b-9 performs relatively well.
  • the rows in the base matrix are also interchangeable, and the columns can be exchanged. If the base map is exchanged by at least one of row switching or column switching, the base matrix of the corresponding portion is also exchanged the same.
  • 80b-1 is a matrix after row and column exchange corresponding to 30b-6
  • 80b-2 is a matrix after row and column corresponding to 30b-7
  • 80b-3 is corresponding to 30b- 8 matrix after row and column exchange
  • 80b-4 is the matrix after row and column corresponding to 30b-3
  • 80b-5 is the matrix after row and column corresponding to 30b-4
  • 80b-6 is corresponding to 30b-5
  • 80b-7 is the matrix after the row and column exchange corresponding to 30b-9
  • 80b-8 is the matrix after the row and column exchange corresponding to 30b-10.
  • the portion of the base matrix of the LDPC matrix corresponding to the sub-matrix A and the sub-matrix B may include the base matrix 30b-1, 30b-2, 30b-3, 30b-4, 30b-5, 30b- Each row or column of any of 6, 30b-7, 30b-8, 30b-9 or 30b-10, that is, based on base matrices 30b-1, 30b-2, 30b-3, 30b-4, 30b-5 Any one of 30b-6, 30b-7, 30b-8, 30b-9 or 30b-10 undergoing column switching, or row switching, or row switching and column switching.
  • sub-matrices C, sub-matrices D, and sub-matrices E of corresponding sizes may be added based on the core matrix to obtain different code rates.
  • the sub-matrix C is an all-zero matrix
  • the sub-matrix is an identity matrix, and its size is mainly determined according to the code rate, and the structure is relatively fixed.
  • the main factors affecting the performance of the compiled code are the core matrix and the sub-matrix D part. Adding rows and columns on the basis of the core matrix to form corresponding C, D and E parts can obtain different code rates.
  • the core matrix portion of the base map 30a or the core matrix portion of the base map 80a may be used as the core matrix, and corresponding sub-matrices C, D, and E are added to meet the requirements of different code rate encoding or decoding.
  • the number of columns of the sub-matrix D is the sum of the number of columns of the sub-matrices A and B, and the number of rows thereof is mainly related to the code rate.
  • the code rate supported by the LDPC code is R m
  • the size of the base map or the base matrix Is m*n, where n n A /R m +p
  • the minimum code rate R m 1/3
  • a matrix F having a size of 41 rows and 27 columns can be defined, and the sub-matrix D can include the m D rows therein, and the sub-matrices A and B and the sub-matrices C and E of the corresponding sizes constitute a code rate of 22/.
  • m D 41
  • the sub-matrix D has a size of 41 rows and 27 columns, that is, the sub-matrix D, that is, the matrix F
  • the row weights are 7, 7, 9, 8, 7, 7, 8, 6, 6, 5, 6, 5, 5, 6, 5, 5, 5, 5 , 4, 4, 4, 5, 4, 5, 4, 4, 4, 4, 3, 4, 4, 4, 4, 3, 3, 4, 4, 3, 3, 3, 4.
  • the weight of each row in the base map 30a is 8, 8, 10, 9, 8, 8, 9, 7, 7, 6, 7, 6, 6, 7, 6, 6, 6,6,5,5,5,6,5,6,5,5,5,5,4,5,5,5,5,4,4,5,5,4,4,4,5.
  • the two rows are orthogonal to each other.
  • the matrix F may be a matrix of quasi-orthogonal structures, and in the matrix block composed of the remaining columns except the built-in punctured bit columns in the matrix F, in the same column of any two adjacent rows There is at most one non-zero element, that is, the matrix block of the matrix F except the built-in punctured bit column has an orthogonal structure.
  • the matrix F is a matrix composed of the 5th row to the 45th row and the 0th column to the 26th column, wherein the 0th column and the 1st column are built-in punched bit columns, and the 5th row is In the matrix block formed by the 45th row and the 2nd column to the 26th column, the 5th row and the 6th row are orthogonal to each other, the 6th row and the 7th row are orthogonal to each other, and the 23rd row and the 24th row are orthogonal to each other.
  • Lines 32 and 33 are orthogonal to each other, and so on.
  • the size of the sub-matrix D in the LDPC code base map is 15 rows and 27 columns, which may be the 0-14th row of the matrix F in the base map 30a, that is, the 5th row to the 19th row of the base map 30a.
  • 19 rows, the 0th column to the 41st column constitutes a matrix part, wherein the sub-matrix E is an element matrix of 15 rows and 15 columns, and the sub-matrix C is an all-zero matrix of 5 rows and 15 columns;
  • the size of the sub-matrix D in the LDPC code base map is 19 rows and 27 columns, which may be from the 0th to 18th rows of the matrix F in the base map 30a, that is, the 5th to 23rd lines of the base map 30a.
  • the line is formed into the matrix portion of the 23rd line, the 0th column to the 41st column, wherein the sub-matrix E is an element matrix of 19 rows and 19 columns, and the sub-matrix C is an all-zero matrix of 5 rows and 19 columns.
  • the base map of the LDPC code and the rows in the base matrix can be mutually exchanged, and the columns can also be exchanged with each other.
  • the 17th line and the 19th line of the base map 30a can be exchanged, and the 39th and 41st columns can be exchanged to obtain the base map matrix 80a as shown in Fig. 8a.
  • the sub-matrix D includes m D rows in the matrix F. The m D rows may not be exchanged in rows, or one or more rows may be exchanged between rows, and the sub-matrix E is still a diagonal structure, and no row is performed.
  • the column exchange for example, performs row swapping of the 12th row and the 14th row of the matrix F, the submatrix D includes the m D rows in the matrix F, and the submatrix E is still a diagonal structure, thereby obtaining the base map 80a.
  • the matrix F is a quasi-orthogonal matrix before the row exchange, and is still a quasi-orthogonal matrix after the exchange.
  • the matrix F is a matrix composed of the 5th row to the 45th row and the 0th column to the 26th column, wherein the 0th column and the 1st column are built-in punched bit columns, and the 5th column is In the matrix block formed by the 45th row and the 2nd column to the 26th column, the 5th row and the 6th row are orthogonal to each other, the 29th row and the 30th row are orthogonal to each other, and so on.
  • the base map or the base matrix includes the sub-matrix D
  • the columns in the corresponding sub-matrix D also need to be exchanged, for example, the 23rd column and the 25th column in the core matrix.
  • the 23rd column and the 25th column of the sub-matrix D also need to be exchanged accordingly. This is for the sake of example only and is not intended to be limiting.
  • the sub-matrix D satisfies the quasi-orthogonal structure, that is, the adjacent two rows of the other columns are orthogonal except for the built-in punched columns.
  • the distance is orthogonal.
  • the built-in punched column may also be other columns, and is not limited herein.
  • the matrix F of the quasi-orthogonal structure may also include at least 2 rows of orthogonal rows, and at least 2 rows of the orthogonal rows are adjacent to the next two rows, and the columns of the 0th column to the 26th column are the most There is only one non-zero element. For example, if m D >30, the code rate supported by the corresponding LDPC code is less than 2/5, and the last 11 lines in the matrix F, that is, the 30th to 40th rows and the 0th column to the 26th column of the matrix F Sub-matrices can be orthogonal.
  • the adjacent two rows in the 0th to the 29th rows of the matrix F have at most one non-zero element except the built-in punched bit column, and the adjacent two rows in the 30th to 40th rows are 0th through 26th.
  • Column columns have at most one non-zero element.
  • the sub-matrices formed by the 26th to 40th rows and the 0th column to the 26th column in the matrix F may be orthogonal. That is, the adjacent two rows in the 0th row to the 25th row of the matrix F have at most one non-zero element except the built-in punch bit column, and the adjacent two rows in the 26th row to the 40th row are the 0th column to the There are at most one non-zero element in each of the 26 columns. As shown in FIG.
  • the base map 170a wherein the matrix F is a matrix composed of the 5th to 45th rows and the 0th column to the 26th column of the base map, the matrix F is a quasi-orthogonal structure, and the 26th line of the matrix F The 40th line is orthogonal, wherein the adjacent rows of the 26th to 40th rows have at most one non-zero element.
  • the core matrix portion of the base map 170a is the same as the core matrix portion of the base map 80a.
  • each row can be modified with 1-2 non-zero elements or 1-2 zero elements without affecting its performance.
  • the last 21 lines in the matrix F that is, the sub-matrices formed by the 25th to 45th rows and the 0th column to the 26th column of the matrix F may be orthogonal. That is, the adjacent two rows in the 0th to the 19th rows of the matrix F have at most one non-zero element except the built-in punched bit column, and the adjacent two rows in the 20th to 40th rows are 0th through 26th. Column columns have at most one non-zero element.
  • 11a is the same as the core matrix portion of the base map 80a, and the fifth row to the 45th row conform to the quasi-orthogonal structure, and it can be said that the fifth row to the 25th row conform to the quasi-orthogonal structure. Lines 25 to 45 conform to the orthogonal structure.
  • the core matrix portion in the base map shown in Fig. 12 is the same as the core matrix portion in the base map 80a, and the fifth row to the 45th row conform to the quasi-orthogonal structure.
  • the base matrix 30c shown in FIG. 3c is an example of a base matrix of the base map 30a, in which the non-zero elements of the i-th row and the j-th column in the base map 30a are not changed in the base matrix 30c, and the value is the offset value P i . j .
  • the offset matrix corresponding to the sub-matrix D is the offset matrix of the matrix F.
  • the offset matrix of the matrix F is to replace the non-zero elements of the i-th row and the j-th column in the matrix F with the offset value P i,j , and the zero elements are represented by -1 or null in the offset matrix.
  • the base map is only an example, and the base map may be 80a or 180a, etc., and details are not described herein.
  • the offset matrix of the matrix F may include each row or column of any one of 30c-1 to 30c-10.
  • the offset matrix of the matrix F may be a matrix as shown in 30c-1, or a row of the matrix /column transformed matrix;
  • the offset matrix of the matrix F may be a matrix as shown in 30c-2, or a row of the matrix /column transformed matrix;
  • the offset matrix of the matrix F may be a matrix as shown in 30c-3, or a matrix after row/column transformation of the matrix;
  • the offset matrix of the matrix F may be a matrix as shown in 30c-4, or a row of the matrix /column transformed matrix;
  • the offset matrix of the matrix F may be a matrix as shown in 30c-5, or the row/column transformation of the matrix matrix.
  • each of the base matrices corresponding to the base map 30a has a code rate of 1/3.
  • the set of spreading factors may be ⁇ 24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104 , 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, 384 ⁇ :
  • the offset matrix of the matrix F may be a matrix as shown in 30c-6, or a matrix after row/column transformation of the matrix;
  • the offset matrix of the matrix F may be a matrix as shown in 30c-7, or a matrix after row/column transformation of the matrix;
  • the offset matrix of the matrix F may be a matrix as shown in 30c-8, or a matrix after row/column transformation of the matrix;
  • the offset matrix of the matrix F may be a matrix as shown in 30c-3, or the matrix The matrix after the row/column transformation;
  • the offset matrix of the matrix F may be a matrix as shown in 30c-4, or a row of the matrix /column transformed matrix;
  • the offset matrix of the matrix F may be a matrix as shown in 30c-5, or a matrix after row/column transformation of the matrix. .
  • the offset matrix of the matrix F has more options.
  • the offset matrix of the matrix F may also be a matrix such as 30c-9, or a matrix after row/column transformation of the matrix, or a matrix such as 30c-10, or a row/column transformation of the matrix.
  • the matrix for example, can be designed as follows for the spreading factor:
  • the offset matrix of the matrix F may be a matrix as shown in 30c-6, or a matrix after row/column transformation of the matrix;
  • the offset matrix of the matrix F may be a matrix as shown in 30c-7, or a matrix after row/column transformation of the matrix;
  • the offset matrix of the matrix F may be a matrix as shown in 30c-8, or a matrix after row/column transformation of the matrix;
  • the offset matrix of the matrix F may be a matrix as shown in 30c-9 or 30c-10, or after the row/column transformation of the matrix Matrix
  • the offset matrix of the matrix F may be a matrix as shown in 30c-3, or a matrix after row/column transformation of the matrix;
  • the offset matrix of the matrix F may be a matrix as shown in 30c-4, or a row of the matrix /column transformed matrix;
  • the offset matrix of the matrix F may be a matrix as shown in 30c-5, or a matrix after row/column transformation of the matrix. .
  • the offset matrix of the matrix F may include each row or column of any one of 80c-1 to 80c-9.
  • the set of spreading factors can be ⁇ 24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104, 112, 120, 128, 144,160,176,192,208,224,240,256,288,320,352,384 ⁇ :
  • the offset matrix of the matrix F may be a matrix as shown in 80c-1, or a matrix after row/column transformation of the matrix;
  • the offset matrix of the matrix F may be a matrix as shown in 80c-2, or a matrix after row/column transformation of the matrix;
  • the offset matrix of the matrix F may be a matrix as shown in 80c-3, or a matrix after row/column transformation of the matrix;
  • the offset matrix of the matrix F may be a matrix as shown in 80c-4, or the matrix The matrix after the row/column transformation;
  • the offset matrix of the matrix F may be a matrix as shown in 80c-5, or a row of the matrix /column transformed matrix;
  • the offset matrix of the matrix F may be a matrix as shown in 80c-6, or a matrix after row/column transformation of the matrix. .
  • the granularity supported by the spreading factor Z may be designed to be finer, so that the offset matrix of the matrix F has more choices.
  • the offset matrix of the matrix F may also be a matrix such as 80c-7, or a matrix after row/column transformation of the matrix, or a matrix such as 80c-8, or a row/column transformation of the matrix.
  • the matrix for example, can be designed as follows for the spreading factor, where:
  • the offset matrix of the matrix F may be a matrix as shown in 80c-1, or a matrix after row/column transformation of the matrix;
  • the offset matrix of the matrix F may be a matrix as shown in 80c-2, or a matrix after row/column transformation of the matrix;
  • the offset matrix of the matrix F may be a matrix as shown in 80c-3, or a matrix after row/column transformation of the matrix;
  • the offset matrix of the matrix F may be a matrix as shown in 80c-7 or 80c-8, or after the row/column transformation of the matrix Matrix
  • the offset matrix of the matrix F may be a matrix as shown in 80c-4, or a matrix after row/column transformation of the matrix;
  • the offset matrix of the matrix F may be a matrix as shown in 80c-5, or a row of the matrix /column transformed matrix;
  • the offset matrix of the matrix F may be a matrix as shown in 80c-6, or a matrix after row/column transformation of the matrix. .
  • the offset matrix of the matrix F may be a matrix as shown in 80c-9, or a row of the matrix. /column transformed matrix, into In one step, when Z is greater than or equal to 24, the offset matrix of matrix F is relatively better with 80c-9 performance.
  • the rows in the base matrix are also interchangeable, and the columns can be exchanged. If the base map has undergone at least one of row switching or column switching, the base matrix of the corresponding portion is also exchanged the same.
  • 80c-1 is a matrix after row switching corresponding to 30c-6
  • 80c-2 is a matrix after row switching corresponding to 30c-7
  • 80c-3 is corresponding to 30c-
  • 80c-4 is the matrix after row row corresponding to 30c-3
  • 80c-5 is the matrix after row row corresponding to 30c-4
  • 80c-6 is corresponding to 30c-5.
  • 80c-7 is the matrix after row row corresponding to 30c-9
  • 80c-8 is the matrix after row row corresponding to 30c-10.
  • each of the base matrices corresponding to the base map 80a has a code rate of 1/3.
  • the core matrix of the base map that is, the portion formed by the sub-matrices A and B can be used in the base map 30a.
  • the core matrix portion of the base map may include the m D rows in the matrix portion formed by the 5th row to the 45th row and the 0th column to the 26th column in the base map 30a.
  • the core matrix portion in the base matrix may be one of 30b-3, 30b-4, 30b-5, 30b-6, 30b-7, 30b-8, 30b-9, and 30b-10, and the sub-matrix D corresponds to
  • the portion may include m D rows of any of the following matrices: 30c-3, 30c-4, 30c-5, 30c-6, 30c-7, 30c-8, 30c-9, and 30c-10.
  • the core matrix and the portion corresponding to the sub-matrix D can be selected according to the spreading factor.
  • the core matrix of the base map that is, the portion formed by the sub-matrices A and B may adopt the core matrix portion in the base map 80a, and the sub-matrix D of the base map may include the fifth in the base map 80a.
  • the line goes to line 45, and the m D line in the matrix portion formed by the 0th column to the 26th column.
  • the core matrix portion in the base matrix may be one of 80b-1, 80b-2, 80b-3, 80b-4, 80b-5, 80b-6, 80b-7, 80b-8 and 80b-9
  • the portion corresponding to the sub-matrix D may include m D rows of any of the following matrices: 80c-1, 80c-2, 80c-3, 80c-4, 80c-5, 80c-6, 80c-7, 80c-8, and 80c -9.
  • the core matrix and the portion corresponding to the sub-matrix D can be selected according to the spreading factor.
  • the core matrix of the base map may adopt the core matrix portion in the base map 80a
  • the sub-matrix D of the base map may include the fifth in the base map 170a.
  • Rows to the 45th row, the 0th row to the 26th column constitute the m D row, such as the base map 170a, and accordingly, the base matrix may be the 5th row including the base matrix 170b-1 as in Fig. 17b.
  • the core matrix of the base map may adopt the core matrix portion in the base map 80a, and the sub-matrix D portion of the base map may include the fifth row to the 45th row in the base map as shown in FIG.
  • the m D row in the matrix portion composed of the 0th column to the 26th column is as shown in FIG.
  • the quasi-orthogonal structure in the present application is not limited to only two adjacent rows, and the matrix conforming to the quasi-orthogonal structure may also be designed to include multiple groups, and each group includes at least 2 rows, for example, 3 rows. Or 4 lines, etc., the lines included in each group are quasi-orthogonal.
  • LDPC 1 indicates that the LDPC code is obtained based on the respective base matrix codes corresponding to the base map 30a
  • LDPC 2 indicates a commonly used LDPC code as a comparison, in which the abscissa represents The length of the information bit sequence, in bits, the ordinate is the symbol signal-to-noise ratio (Es/N0), and the performance curve is the BLER of 0.01 and 0.0001, respectively.
  • an encoder uses an LDPC matrix to encode an input sequence; a base map of the LDPC matrix may be any one of the foregoing examples, and a base matrix H B of the LDPC matrix may be Any of the base matrices in the foregoing examples.
  • the input sequence of the encoder may be an information bit sequence, or may be an information bit sequence processed by at least one of the following: CRC bit addition or padding bit addition.
  • the method further includes: determining the expansion factor Z; determining the value of the expansion factor Z according to the length K of the input sequence.
  • K K b ⁇ Z
  • Z K / K b
  • these padding bits can be identified and not sent.
  • the invention is not limited thereto.
  • the encoder encodes the input sequence using the LDPC matrix H.
  • the input sequence may be encoded using the LDPC matrix H corresponding to the spreading factor Z.
  • the input sequence c ⁇ c 0 , c 1 , c 2 , . . . , c K-1 ⁇
  • the length of the input sequence c is K
  • the input sequence c is encoded by the encoder.
  • the output sequence d ⁇ d 0 , d 1 , d 2 , ..., d N-1 ⁇
  • K is an integer greater than 0, and K may be an integer multiple of the spreading factor Z.
  • the output sequence d includes K 0 bits in the input sequence c and check bits in the check sequence w.
  • K 0 is an integer greater than 0 and less than or equal to K, and the length of the check sequence w is NK 0 .
  • check bit sequence w and the input sequence c satisfy the formula (1):
  • c T [c 0 ,c 1 ,c 2 ,...,c K-1 ] T
  • 0 T is the column vector, where all elements have a value of zero.
  • H is an LDPC matrix obtained based on any of the base diagrams exemplified in the foregoing embodiments, and the base map size of H is m rows and n columns, and may be any base diagram exemplified in the foregoing embodiment, for example, 30a. 80a, 170a, and Fig. 12, and the like.
  • the base map of H includes the p-column built-in punctured column, p is an integer greater than or equal to 0, the information bits corresponding to the p-column built-in punctured column are not output, and the output sequence does not include the p-column.
  • the base map of the LDPC matrix H can be expressed as [H BG H BG, EXT ], where Represents an all zero matrix of m c ⁇ n c size, An identity matrix representing the size of n c ⁇ n c .
  • the 26th column is a single column and the non-zero element is located in the 5th row
  • the first four rows of the twenty-sixth column in the base map of the foregoing embodiments and the first four rows of the sub-matrix C in the foregoing embodiments may also be included.
  • the portion of the sub-matrix A, B, and D in the base map of the embodiment removes the matrix formed by the last column.
  • the number of rows of HBG is less than or equal to 46, and is greater than or equal to 5, and the number of columns of H BG is equal to 26.
  • the number of lines may be 4 H BG rows, i.e. rows of 0-3.
  • H 1 may be an all-zero matrix in which each zero element in H BG is replaced by a Z*Z size, and each non-zero element is replaced by a cyclic permutation matrix h i,j of a Z*Z size, wherein the cyclic permutation matrix h i , j is obtained by cyclically shifting the unit matrix of the Z*Z size to P i,j , and sometimes by I(P i,j ).
  • i is the line number and j is the column number.
  • P i,j mod(V i,j ,Z)
  • V i,j is the base matrix corresponding to the extension factor set index corresponding to Z.
  • H 2 may be obtained by replacing each zero element in H BG, EXT with an all-zero matrix of Z*Z size, and each non-zero element is replaced by an identity matrix of Z*Z size.
  • the encoder can be encoded and output in various ways.
  • the following is an example of the base map 80a, 170a or the base map shown in FIG. 12 as exemplified in the foregoing embodiment, wherein the number of base map lines is up to 46 lines.
  • the maximum number of columns is 68 columns, including two columns of built-in punched columns.
  • the base map having the largest number of rows and the largest number of columns is sometimes referred to as a complete base map.
  • the information bits and check bits that need to be transmitted can be determined from the output sequence generated by the encoder in a subsequent processing step.
  • Partial row and column encoding based on the complete base map Can be sent according to the bit rate, or information bits and school The number of bits is checked, and the row and column codes are selected from the complete base map.
  • the base map size of H is 5 ⁇ m ⁇ 46, 27 ⁇ n ⁇ 68, correspondingly for the LDPC matrix H, 5 ⁇ Z ⁇ M ⁇ 46 ⁇ Z, 27 ⁇ Z ⁇ N ⁇ 68 ⁇ Z.
  • the base map size is 4 ⁇ m ⁇ 46, 26 ⁇ n ⁇ 68, correspondingly for the LDPC matrix H, 4 ⁇ Z ⁇ M ⁇ 46 ⁇ Z, 26 ⁇ Z ⁇ N ⁇ 68 ⁇ Z.
  • the base matrix H B of the LDPC matrix H may be any of the base matrices exemplified in the foregoing embodiments or may be changed in a row order or column order with respect to any of the base matrices exemplified above.
  • the description in the description will not be repeated here.
  • other base patterns may be used to conform to the base matrix of the base map shown in the foregoing embodiments, and the present invention is not limited thereto.
  • the base matrix H B of the LDPC code may be stored in a memory, and the encoder obtains an LDPC matrix corresponding to the spreading factor Z, thereby encoding the input sequence.
  • the storage according to the matrix structure may occupy a large storage space, and the base map of the LDPC code may be stored in the memory, respectively. Or storing the offset values of the non-zero elements in each base matrix column by column, and then obtaining the LDPC matrix according to the offset values of the base matrix corresponding to the base map and the spreading factor Z.
  • the base map may indicate the location of the non-zero elements of each base matrix.
  • the save base map may be a location in which the non-zero elements are stored.
  • the position of a non-zero element can be indicated by the row and column in which the non-zero element is located, such as the position of the column in which the non-zero element is located in each row, or the position of the row in which the non-zero element is located in each column.
  • the save base map may also be a location in which the zero element is saved, and may also be indicated by the row and column in which the zero element is located.
  • the position of the column in which the zero element is located in each row, or the position of the row in which the zero element is located in each row, the position of the corresponding non-zero element can be obtained by excluding the position of the zero element. It should be noted that the present invention is merely an example, and the present invention is not limited thereto.
  • the parameters involved in the base or base matrix can be represented using a table.
  • related parameters or tables can be saved in one or more memories.
  • the base map or the base matrix can be obtained by reading the base number of the base map or the base matrix in the memory and the column where the non-zero element is located, and optionally, the row weight of each row can be saved, and each row can be saved.
  • the offset value of a non-zero element can be saved.
  • FIG. 11a The following is an example of FIG. 11a.
  • Other base maps or base matrices provided by the present application may refer to similar references.
  • the base matrix portion of the base map 80a, the base map 170a, or FIG. 12 can be represented using Table 3.
  • the base map of the LDPC matrix may include the core portion shown in Table 3.
  • the other parts of the base map of the LDPC matrix may be as shown in the base map 80a, the base map 170a or FIG. 12, or other structures described in the present application, or other matrix structures, which are not limited in this application.
  • the parameters involved in the first 24 lines of the base map may be as shown in Table 4, and the other lines are similar, and are not listed in Table 4 due to space limitations.
  • basemaps or base matrices provided in this application may also use similar tables to express relevant parameters. It can be understood that the above-mentioned base map 170a and Tables 3 and 4 are to help understand the design of the base map and the base matrix, and the representation thereof is not limited to the representations of the base map 170a or Table 3 and Table 4. Other possible variations may also be included.
  • the form of Table 5 For example, the form of Table 5.
  • the parameters “row weight” and “column weight” in Table 3 or Table 4 or Table 5 above may also be omitted. You can know how many non-zero elements are in this row or column by the column or row in which a non-zero element is located, so the row weight or column weight is known.
  • the parameter value in the “row of the non-zero element” in Table 5 may also not be small. Arrange in a large order, as long as the parameter value is indexed to the column in which the non-zero element is located, or to the row where the non-zero element is located.
  • a column of "non-zero element offset value” may also be included in Table 3 or Table 4, and a parameter value in the "non-zero element offset value” column and a column in which the non-zero element is located The parameter values in "one-to-one correspondence.
  • the column of "non-zero element offset value” may also be included, and the parameter value in the "non-zero element offset value” column corresponds to the parameter value in the "non-zero element row”.
  • the position of the non-zero element of the structure in the base map may be calculated according to the position of the row and column, and the position of the non-zero element may not be saved.
  • the sub-matrix E is a diagonal matrix, and only non-zero elements exist on the diagonal line.
  • the position of the column in which the non-zero element is located can be calculated according to the line number, and the row where the non-zero element is located can also be calculated according to the column number.
  • the position of the base map 80a, the base map 170a or the base map of FIG. 12 is taken as an example.
  • the position of the column where the non-zero element is located is the m e + K b column.
  • K b 22
  • the column in which the non-zero element in row 7 is located is the 29th column.
  • the double diagonal structure B′ in the sub-matrix B is located in the base map 80a, the base map 170a, or the 0th to 3rd rows and the 23rd to 25th columns in any of the base maps in FIG. 12, and can be calculated according to the line number.
  • the position of the column where the zero element is located can also calculate the position of the row where the non-zero element is located according to the column number.
  • the position of the non-zero element in the row includes the mth B +K b column, and the m b + K b +1 column
  • the position of the non-zero element in the row includes the m b + K b column; for example, the sub-matrix B
  • the parameters involved in each row in Figure 12 can save the position of the column in which the non-zero elements in columns 0 through 25 are located, without saving the non-zero elements in columns 26 through 68.
  • the position of the column that is, the column in which the non-zero elements in the single-column re-column of the sub-matrix E and the sub-matrix B are not stored, can be used to represent the H BG with a column number of 26:
  • the parameters involved in each row in Figure 12 can save the position of the column in which the non-zero elements in columns 0 to 26 are located, without saving the non-zero elements in columns 27 through 68.
  • the position of the column that is, the column in which the non-zero element in the sub-matrix E is not stored, can be used to represent the H BG with a column number of 27:
  • each row can store the position of the first 26 columns or the first 27 columns of non-zero elements in four hexadecimal numbers.
  • the first 26 columns of the 0th row are 11110110 01111101 10111111 00, then it can be recorded.
  • the position of the non-zero element is 0xF6, 0x7D, 0xBF, 0x00, that is, every 8 columns constitute a hexadecimal number.
  • the coded LDPC matrix H can be obtained by expanding the base matrix H B according to Z.
  • a cyclic permutation matrix h i,j of Z*Z size is determined, where h i,j is a cycle obtained by cyclically shifting the unit matrix through P i, j times
  • the permutation matrix replaces h i,j with a non-zero element P i,j , and replaces the zero-element in the base matrix H B with an all-zero matrix of Z*Z size, thereby obtaining a parity check matrix H.
  • the H B i-th row j-th column element P i,j in the base matrix can satisfy the relationship shown in the following (2):
  • V i,j may be an offset value of an element of the i-th row and the j-th column in the base matrix of the set of the expansion factor Z, or an i-th row of the base matrix of the largest spreading factor in the set of the expansion factor Z The offset value of the non-zero element of the column.
  • V i,j is the offset value of the non-zero element of the i-th row and the j-th column in the base matrix indicated by the PCM 7.
  • V i,j is the offset value of the non-zero element of the i-th row and the j-th column in the base matrix indicated by the PCM 7.
  • the 22nd to 3rd rows and the 0th to 25th columns of the input sequence and the base matrix, that is, the H core-dual portion can be obtained first. 25 columns corresponding to the check bits; and according to the input sequence and the check bit corresponding to the H core-dual , the 26th column, that is, the parity bit corresponding to the single column re-column is obtained; and then according to the input sequence and the corresponding columns 22 to 26
  • the check bit and the partial code corresponding to the sub-matrix D obtain the check bits corresponding to the E-part E, thereby completing the encoding.
  • the LDPC code can be obtained by encoding by the above method.
  • the communication device may perform one or more operations of performing rate matching on the LDPC code, interleaving the rate matched LDPC code according to the interleaving scheme, and modulating the interleaved LDPC code according to the modulation scheme.
  • Bit sequence X transmit bit sequence X.
  • a decoder decodes an input sequence by using an LDPC matrix; a base map of the LDPC matrix may be any base diagram in the foregoing example, and a base matrix of the LDPC matrix H B may be any of the base matrices in the foregoing examples.
  • the input sequence of the decoder may be a soft value sequence of the LDPC code.
  • the method further includes: determining an expansion factor Z.
  • the communication device at the receiving end can receive the signal including the LDPC code based, obtain the soft value sequence of the LDPC code therein, and determine the corresponding spreading factor Z.
  • the decoder uses the LDPC matrix H to decode the input sequence.
  • the LDPC matrix H corresponding to the spreading factor Z may be used to decode the soft value sequence of the LDPC code.
  • decoding is the inverse of encoding
  • a description of the LDPC matrix H and its base map can be found in the aforementioned encoding embodiment. It can also be decoded based on the complete base map when decoding, or based on partial row and column decoding of the complete base map.
  • the base matrix H B of the LDPC matrix H may be any of the base matrices exemplified in the foregoing embodiments or may be converted in a row order or a column order, or a row order may be changed with respect to any of the base matrices exemplified above.
  • the base matrix in which the column order is transformed, the base map includes at least the sub-matrix A and the sub-matrix B, and may further include a sub-matrix C, a sub-matrix D, and a sub-matrix E.
  • other base patterns may be used to conform to the base matrix of the base map shown in the foregoing embodiments, and the present invention is not limited thereto.
  • the base matrix H B of the LDPC code may be stored in the memory, and the LDPC matrix corresponding to the extension factor Z may be used to decode the soft value of the LDPC code;
  • the storage according to the matrix structure may occupy a large storage space, and the base map of the LDPC code may be stored in the memory, respectively, row by row or by row.
  • the column holds the offset values of the non-zero elements in each base matrix, and then obtains the LDPC matrix according to the offset values of the base matrix corresponding to the base map and the spreading factor Z.
  • the storage manner of the base map can also be stored in various ways as described in the foregoing encoding embodiment.
  • Decoding coded reverse process which uses a base matrix H B has the same features in the base matrix of the encoding method embodiment.
  • An extension of the base matrix H B to obtain the LDPC matrix H can also be referred to the coding method embodiment.
  • the communication device may further perform one or more operations of: receiving a signal including LDPC encoding, demodulating, deinterleaving, and de-rate matching the signal to obtain a soft value of the LDPC code. .
  • the base matrix H B being obtainable based on the parameters;
  • the parameters may include one or more of the following: And/or base matrix row number, row weight, column number, column weight, position of non-zero elements, offset value in base matrix, non-zero element offset value and corresponding position, compensation value, spreading factor, extension A set of factors, or a base map of the base matrix, or a code rate, etc.
  • the row/column transformation refers to a row transformation, or a column transformation, or a row transformation and a column transformation
  • the input sequence is encoded or decoded using a low-density parity check LDPC matrix, which may be performed in one or more of the following manners during encoding or decoding:
  • . i H B base matrix is obtained based on the above a), based on the obtained base matrix H B coding or decoding; for row / column exchange or base matrix obtained based on H B, based on the row / column of the basis matrix encoded transform or translation code.
  • the base matrix based extended matrix coding or decoding may also be included;
  • the extension involved in the present application may be based on matrix deformation or processing to obtain an expanded matrix, which is not limited in the application.
  • the extension may be to compensate the matrix. For example, the offset values are respectively increased or decreased for each offset value greater than or equal to 0 in the base matrix, thereby obtaining a compensation matrix.
  • the extension may be to extend the rows and columns to the matrix, and to obtain the expanded matrix.
  • the extension may be to transform the non-zero values of the matrix.
  • the preservation referred to in this application may be stored in one or more memories.
  • the one or more memories may be separate settings, or may be integrated in an encoder or decoder, a processor, a chip, a communication device, or a terminal.
  • the one or more memories may be separately provided in a part, and the part may be integrated in a decoder, a processor, a chip, a communication device, or a terminal.
  • the type of the memory may be any form of storage medium, and the present application does not limited.
  • FIG. 6 is a schematic structural diagram of a communication device 600.
  • the device 600 can be used to implement the method described in the foregoing method embodiments. For details, refer to the description in the foregoing method embodiments.
  • the communication device 600 can be a chip, a base station, a terminal, or other network device.
  • the communication device 600 includes one or more processors 601.
  • the processor 601 can be a general purpose processor or a dedicated processor or the like. For example, it can be a baseband processor, or a central processing unit.
  • the baseband processor can be used to process communication protocols and communication data
  • the central processor can be used to control communication devices (eg, base stations, terminals, or chips, etc.), execute software programs, and process data of the software programs.
  • the communication device 600 includes one or more of the processors 601, and the one or more processors 601 can implement the functions of the encoder described above.
  • the above encoder may be part of the processor 601, and the processor 601 may implement other functions in addition to the functions of the encoder.
  • the communication device 600 encodes an input sequence using an LDPC matrix;
  • the base map of the LDPC matrix may be any of the base diagrams in the foregoing examples or may be sequentially changed in a row order or column order with respect to any of the base diagrams exemplified above.
  • a base map in which a transform occurs, or both a row order and a column order are transformed, and the base matrix H B of the LDPC matrix may be any of the base matrices in the foregoing embodiments or may occur in a row order with respect to any of the base matrices exemplified above.
  • the input sequence of the encoder may be an information bit sequence.
  • one or more of the processors 601 may implement the functions of the decoder described above, and in another possible design, the decoder may be part of the processor 601.
  • the communication device 600 may be configured to decode an input sequence by using an LDPC matrix; the base map of the LDPC matrix may be any base map in the foregoing example or may be changed in a row order with respect to any of the base diagrams exemplified above, Alternatively, the column order may be transformed, or the base sequence in which the row order and the column order are transformed, and the base matrix H B of the LDPC matrix may be any of the base matrix in the foregoing example or relative to any of the base matrixes exemplified above. A base matrix in which the order is transformed, or the column order is transformed, or both the row order and the column order are transformed.
  • the input sequence of the decoder may be a soft value sequence.
  • the processor 601 can also include instructions 603 that can be executed on the processor such that the communication device 600 performs the methods described in the above method embodiments.
  • the communication device 600 can also include circuitry that can implement the functions of the encoder, or decoder, or encoder and decoder in the foregoing method embodiments.
  • the communication device 600 may include one or more memories 602 on which the instructions 604 are stored, and the instructions may be executed on the processor, so that the communication device 600 performs the above method embodiment.
  • data may also be stored in the memory. Instructions and/or data can also be stored in the optional processor.
  • the processor and the memory may be provided separately or integrated.
  • the one or more memories 602 may store parameters related to the base matrix, such as offset values, base maps, extensions based on the base map to the matrix, rows in the base matrix, spreading factors, and the like.
  • the one or more memories 602 may store a base matrix or extend to a matrix based on a base matrix.
  • the communication device 600 may further include a transceiver 605 and an antenna 606.
  • the processor 601 may be referred to as a processing unit that controls a communication device (terminal or base station).
  • the transceiver 605 can be referred to as a transceiver unit, a transceiver, a transceiver circuit, or a transceiver, etc., for implementing the transceiver function of the communication device through the antenna 606.
  • the communication device 600 may further include a device for generating a transport block CRC, a device for code block splitting and CRC check, an interleaver for interleaving, a modulator for modulation processing, and the like.
  • a device for generating a transport block CRC a device for generating a transport block CRC
  • a device for code block splitting and CRC check a device for code block splitting and CRC check
  • an interleaver for interleaving
  • a modulator for modulation processing and the like.
  • the functionality of these devices can be implemented by one or more processors 601.
  • the communication device 600 may further include a demodulator for demodulation operation, a deinterleaver for deinterleaving, a device for de-rate matching, and the like.
  • a demodulator for demodulation operation e.g., a demodulator for demodulation operation
  • a deinterleaver for deinterleaving e.g., a device for de-rate matching
  • the functionality of these devices can be implemented by one or more processors 601.
  • FIG. 7 shows a schematic diagram of a communication system 700 that includes a communication device 70 and a communication device 71, wherein the information data is received and transmitted between the communication device 70 and the communication device 71.
  • the communication devices 70 and 71 may be the communication device 600, or the communication devices 70 and 71 respectively include a communication device 600 that receives and transmits information data.
  • communication device 70 can be a terminal, and corresponding communication device 71 can be a base station; in another example, communication device 70 is a base station and corresponding communication device 71 can be a terminal.
  • a general purpose processor may be a microprocessor.
  • the general purpose processor may be any conventional processor, controller, microcontroller, or state machine.
  • the processor may also be implemented by a combination of computing devices, such as a digital signal processor and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a digital signal processor core, or any other similar configuration. achieve.
  • the steps of the method or algorithm described in the embodiments of the present invention may be directly embedded in hardware, instructions executed by a processor, or a combination of the two.
  • the memory can be RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium in the art.
  • the memory can be coupled to the processor such that the processor can read information from the memory and can write information to the memory.
  • the memory can also be integrated into the processor.
  • the processor and the memory may be disposed in an ASIC, and the ASIC may be disposed in a communication device such as a base station or a terminal. Alternatively, the processor and memory may also be provided in different components in the communication device.
  • the present invention can be implemented in hardware, firmware implementation, or a combination thereof.
  • a software program it may be implemented in whole or in part in the form of a computer program product comprising one or more computer instructions.
  • the processes or functions described in accordance with embodiments of the present invention are generated in whole or in part.
  • the functions described above may also be stored in or transmitted as one or more instructions or code on a computer readable medium.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
  • Computer readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another.
  • a storage medium may be any available media that can be accessed by a computer.
  • computer readable media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage media or other magnetic storage device, or can be used for carrying or storing in the form of an instruction or data structure.
  • Any connection may suitably be a computer readable medium.
  • a disk and a disc include a compact disc (CD), a laser disc, a compact disc, a digital versatile disc (DVD), a floppy disk, and a Blu-ray disc, wherein the disc is usually magnetically copied, and the disc is The laser is used to optically replicate the data. Combinations of the above should also be included within the scope of the computer readable media.
  • encoding/decoding means encoding, decoding, or encoding and decoding.

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Abstract

一种编码方法、装置、通信设备和通信系统。该方法包括：使用低密度奇偶校验LDPC矩阵对输入比特序列进行编码；其中，所述LDPC矩阵的基图表示为m行n列的矩阵，m为大于或者等于5的整数，n为大于或者等于27的整数；所述基图至少包括子矩阵A和子矩阵B，其中，所述子矩阵A为5行22列的矩阵；所述子矩阵B为5行5列的矩阵，其中，所述子矩阵B包括一权重为3的列和双对角结构的子矩阵B'。所述的编码方法、装置、通信设备和通信系统，能够支持多种长度的信息比特序列的编码需求。

Description

信息处理的方法和通信装置 技术领域
本发明实施例涉及通信领域，尤其涉及信息处理的方法和通信装置。
背景技术
低密度奇偶校验(low density parity check，LDPC)码是一类具有稀疏校验矩阵的线性分组编码，具有结构灵活，译码复杂度低的特点。由于它采用部分并行的迭代译码算法，从而比传统的Turbo码具有更高的吞吐率。LDPC码可用于通信系统的纠错码，从而提高信道传输的可靠性和功率利用率。LDPC码还可以广泛应用于空间通信、光纤通信、个人通信系统、ADSL和磁记录设备等。目前在第五代移动通信中已考虑采用LDPC码作为信道编码方式之一。
实际使用过程中，可以采用具有特殊结构化特征的LDPC矩阵。该具有特殊结构化特征的LDPC矩阵H可以由准循环(quasi cycle，QC)结构的LDPC基矩阵扩展得到。QC-LDPC适合并行度高的硬件，提供的吞吐率更高。可以通过对LDPC矩阵进行设计使之应用于信道编码。
发明内容
本发明实施例提供了一种信息处理的方法、通信装置和系统，可以支持多种长度的信息比特序列的编码和译码，符合系统灵活的码长码率要求。
第一方面，提供了一种编码方法及编码器，所述编码器使用低密度奇偶校验LDPC矩阵对输入序列进行编码。
第二方面，提供了一种译码方法及译码器，所述译码器使用低密度奇偶校验LDPC矩阵对输入序列进行译码。
在上述第一方面或第二方面的第一种实现方式中：所述LDPC矩阵的基图表示为m行n列的矩阵，m为大于或者等于5的整数，n为大于或者等于27的整数；所述基图至少包括子矩阵A和子矩阵B，其中，所述子矩阵A为5行22列的矩阵；所述子矩阵B为5行5列的矩阵，其中，所述子矩阵B包括权重为3的列和双对角结构的子矩阵B’。
可选的，所述子矩阵A中，其中1列的权重为5，1列的权重为4，其余20列的权重分别为3。
可选的，所述子矩阵B中，其中1列的权重为3，3列的权重分别为2。
基于上述实现方式，所述子矩阵B还包括1列权重为1的列。
在上述第一方面或第二方面的第二种实现方式中：所述LDPC矩阵的基图表示为m行n列的矩阵，m为大于或者等于5的整数，n为大于或者等于27的整数；所述基图至少包括子矩阵A和子矩阵B，其中，所述子矩阵A为5行22列的矩阵；所述子矩阵B为5行5列的矩阵；其中，所述子矩阵A和所述子矩阵B构成的矩阵中，其中1列的权重为5，1列的权重为4，21列的权重为3，3列的权重为2,1列的权重为1。
可选的，所述子矩阵A和所述子矩阵B构成的矩阵中，其中1行的权重满足大于或 者等于1，且小于或者等于5，其余4行的权重分别满足大于或者等于17，且小于或者等于21。
例如，在所述子矩阵A和所述子矩阵B构成的矩阵中，其中1行的权重为3，其余4行的权重为19。在这种情况下，所述子矩阵A和所述子矩阵B构成的矩阵可以包括如基图30a中第0行至第4行以及第0列至第26列组成的5行矩阵块的各行或者各列，其中行之间可以交换，列之间也能相互交换。例如，可以将基图30a中子矩阵A和子矩阵B构成的矩阵块的第3行和第0行交换，第2行和第1行交换，以及将第23列和第25列进行交换得到基图80a中的核心矩阵部分。
基于上述实现方式，LDPC矩阵的基矩阵对应所述子矩阵A和子矩阵B构成的部分可以表示为如基矩阵30b-1、30b-2、30b-3、30b-4、30b-5、30b-6、30b-7、30b-8、30b-9或30b-10中任一个。
LDPC矩阵的基矩阵对应所述子矩阵A和子矩阵B构成的部分可以表示为基于基矩阵30b-1、30b-2、30b-3、30b-4、30b-5、30b-6、30b-7、30b-8、30b-9或30b-10中任一个经过列交换，或者行交换，或者行交换和列交换的矩阵。例如LDPC矩阵的基矩阵对应所述子矩阵A和子矩阵B构成的部分可以包括基矩阵30b-1、30b-2、30b-3、30b-4、30b-5、30b-6、30b-7、30b-8、30b-9或30b-10中任一个的各行或者各列。
基于上述实现方式，LDPC矩阵的基矩阵对应所述子矩阵A和子矩阵B构成的部分可以表示为如基矩阵80b-1、80b-2、80b-3、80b-4、80b-5和80b-6中任一个，其中，80b-4是30b-3经过行列交换后的矩阵，80b-5是30b-4经过行列交换后的矩阵，80b-6是30b-5经过行列交换后的矩阵。
为了支持不同块长，LDPC码需要不同的扩展因子Z，基于前述实现方式，在一种可能的实现方式中，基于不同的扩展因子Z采用与之对应的基矩阵。
例如：
若扩展因子Z为{16，18，20，22，24，26，28，30}中的一个，则基图30a的基矩阵对应子矩阵A和子矩阵B的部分可以如图3b中基矩阵30b-1所示；
若扩展因子Z为{32，36，40，44，48，52，56，60}中的一个，则基图30a的基矩阵对应子矩阵A和子矩阵B的部分可以如图3b中基矩阵30b-2所示；
若扩展因子Z为{60，64，72，80，88，96，104，112，120}中的一个，则基图30a的基矩阵对应子矩阵A和子矩阵B的部分可以如图3b中基矩阵30b-3所示；
若扩展因子Z为{128，144，160，176，192，208，224，240}中的一个，则基图30a的基矩阵对应子矩阵A和子矩阵B的部分可以如图3b中基矩阵30b-4所示；
若扩展因子Z为{256，288，320，352，384}中的一个，则基图30a的基矩阵对应子矩阵A和子矩阵B的部分可以如图3b中基矩阵30b-5所示。
在又一种可能的实现方式中，
若扩展因子Z为{24，26，28，30}中的一个，则基图80a的基矩阵对应子矩阵A和子矩阵B的部分可以如图8b中基矩阵80b-1所示；
若扩展因子Z为{32，36，40，44}中的一个，则基图80a的基矩阵对应子矩阵A和子矩阵B的部分可以如图8b中基矩阵80b-2所示；
若扩展因子Z为{48，52，56，60}中的一个，则基图80a的基矩阵对应子矩阵A和子矩阵B的部分可以如图8b中基矩阵80b-3所示；
若扩展因子Z为{60，64，72，80，88，96，104，112，120}中的一个，则基图80a的基矩阵对应子矩阵A和子矩阵B的部分可以如图8b中基矩阵80b-4所示；
若扩展因子Z为{128，144，160，176，192，208，224，240}中的一个，则基图80a的基矩阵对应子矩阵A和子矩阵B的部分可以如图8b中基矩阵80b-5所示；
若扩展因子Z为{256，288，320，352，384}中的一个，则基图80a的基矩阵对应子矩阵A和子矩阵B的部分可以如图中基矩阵80b-6所示。
在又一种可能的实现方式中，子矩阵A还可以包括2列内置打孔比特列。
进一步，为了获得灵活的码率，可以基于核心矩阵添加相应大小的子矩阵C、子矩阵D和子矩阵E，来获得不同的码率。
其中，
所述子矩阵C为5行mD列的全零矩阵；
所述子矩阵D为mD行27列的矩阵；
所述子矩阵E为mD行mD列的单位矩阵；
mD为整数且0≤mD≤41。
其中，子矩阵D包括矩阵F中的mD行，所述矩阵F为41行27列，所述矩阵F的各行的行重分别为7，7，9，8，7，7，8，6，6，5，6，5，5，6，5，5，5，5，4，4，4，5，4，5，4，4，4，4，3，4，4，4，4，3，3，4，4，3，3，3，4。
在一种可能的实现方式中，矩阵F为基图30a中第5行至第45行以及第0列至第26列构成的矩阵。
在一种可能的实现方式中，矩阵F的偏移矩阵可以表示为如基矩阵30c-1、30c-2、30c-3、30c-4和30c-5中任一个。
在又一种可能的实现方式中，，可将基图30a的第17行和第19行进行交换，并且将第39列和第41列进行交换得到如图8a所示的基图矩阵80a。又例如，子矩阵D包括矩阵F中mD行，这mD行可以不进行行交换，也可以将其中一行或多行之间进行行交换，子矩阵E仍为对角结构，例如，子矩阵D包括矩阵F中mD行，其中，矩阵F的第12行和第14行进行行交换，子矩阵E仍为对角结构，从而得到基图80a。
为了支持不同块长，LDPC码需要不同的扩展因子Z，基于前述实现方式，在一种可能的实现方式中，基于不同的扩展因子Z采用与之对应的基矩阵。例如：
在一种可能的实现方式中，
若扩展因子Z为{16，18，20，22，24，26，28，30}中的一个，基矩阵中子矩阵D可以包括如30c-1所示的偏移矩阵的mD行；
若扩展因子Z为{32，36，40，44，48，52，56，60}中的一个，基矩阵中子矩阵D可以包括如30c-2所示的偏移矩阵的mD行；
若扩展因子Z为{60，64，72，80，88，96，104，112，120}中的一个，基矩阵中子矩阵D可以包括如30c-3所示的偏移矩阵的mD行；
若扩展因子Z为{128，144，160，176，192，208，224，240}中的一个，基矩阵中子矩阵D可以包括如30c-4所示的偏移矩阵的mD行；
若扩展因子Z为{256，288，320，352，384}中的一个，基矩阵中子矩阵D可以包括如30c-5所示的偏移矩阵的mD行。
又一种可能的实现方式中，扩展因子集合可以为{24，26，28，30，32，36，40，44，48，52，56，60，64，72，80，88，96，104，112，120，128，144，160，176，192，208，224，240，256，288，320，352，384}：
若扩展因子Z为{24，26，28，30}中的一个，则矩阵F的偏移矩阵可以如80c-1所示；
若扩展因子Z为{32，36，40，44}中的一个，则矩阵F的偏移矩阵可以如80c-2所示；
若扩展因子Z为{48，52，56，60}中的一个，则矩阵F的偏移矩阵可以如80c--3所示；
若扩展因子Z为{60，64，72，80，88，96，104，112，120}中的一个，则矩阵F的偏移矩阵可以如80c-4所示；
若扩展因子Z为{128，144，160，176，192，208，224，240}中的一个，则矩阵F的偏移矩阵可以如80c-5所示；
若扩展因子Z为{256，288，320，352，384}中的一个，则矩阵F的偏移矩阵可以如80c-6所示。
第一种实现方式中的LDPC矩阵的基图和基矩阵可以满足块长为352至8448比特的码块的性能需求。
基于上述各方面，或者各方面任一种可能的实现方式，在又一种可能的实现方式中，还包括：确定扩展因子Z。例如，根据输入序列的长度K来确定扩展因子Z的取值，如：若输入序列长度为K，可以在多个系统定义的扩展因子中确定满足22*Z≥K的最小值。
对于发送端的通信设备，使用LDPC矩阵对所述输入序列进行编码包括：
使用扩展因子Z对应的LDPC矩阵对所述输入序列进行编码。
对于接收端的通信设备，使用LDPC矩阵对输入序列进行译码包括：
使用扩展因子Z对应的LDPC矩阵对输入序列进行译码。
基于上述各方面，或者各方面任一种可能的实现方式，在又一种可能的实现方式中，LDPC矩阵的基矩阵可以保存在存储器中。
基于上述各方面，或者各方面任一种可能的实现方式，在又一种可能的实现方式中，LDPC矩阵的基图保存在存储器中，LDPC矩阵的基矩阵中非零元素的偏移值可以保存在存储器中。
基于上述各可能的实现方式，在一种可能的设计中，用于LDPC编码或者译码的基图和基矩阵中至少一个是上述LDPC矩阵的基图和基矩阵中至少一个经过行交换、或者列交换、或者行交换和列交换后得到的。
第三方面，提供一种通信装置可以包含用于执行上述方法设计中第一方面任一种可能的实现方式相对应的模块。所述模块可以是软件和/或是硬件。
在一个可能的设计中，第三方面提供的通信装置，包括如上述第一方面所述的编码器、确定单元以及处理单元。所述确定单元用于确定对输入序列编码所需的扩展因子Z。所述处理单元，用于使用所述扩展因子Z对应的LDPC矩阵对所述输入序列进行编码。
可选地，所述通信装置还包括收发器，所述收发器用于发送对应于所编码后的信息数据的信号。
第四方面，提供一种通信装置可以包含用于执行上述方法设计中第二方面任一种可能的实现方式相对应的模块。所述模块可以是软件和/或是硬件。
在一种可能的设计中，第四方面提供的通信装置，包括如上述第二方面所述的译码器，获取单元以及处理单元。所述获取单元用于获取LDPC码的软值和扩展因子Z。所述处理单元，用于基于扩展因子Z对应的基矩阵HB对LDPC码的软值译码得到信息比特序列。
所述通信装置还包括收发器，所述收发器用于接收包含基于LDPC编码的信号。
第五方面，提供了一种通信装置，包括一个或多个处理器。
在一种可能的设计中，一个或多个所述处理器可实现第一方面所述编码器的功能，在另一种可能的设计中，第一方面所述编码器可以是所述处理器的一部分，处理器除了实现第一方面所述编码器的功能，还可以实现其他功能。
在一种可能的设计中，一个或多个所述处理器可实现第二方面所述译码器的功能，在另一种可能的设计中，第二方面所述译码器可以是所述处理器的一部分。
可选地，所述通信装置还可以包括收发器以及天线。
可选的，所述通信装置还可以包括用于产生传输块CRC的器件、用于码块分割和CRC校验的器件、用于交织的交织器、或者用于调制处理的调制器等。
可选的，所述通信装置还可以包括，用于解调操作的解调器、用于解交织的解交织器、或者用于解速率匹配的器件等等。可以通过一个或多个处理器实现这些器件的功能。
在一种可能的设计中，可以通过一个或多个处理器实现这些器件的功能。
第六方面，本发明实施例提供了一种通信系统，该系统包括上述第三方面所述的通信装置和上述第四方面所述的通信装置。
第七方面，本发明实施例提供了一种通信系统，该系统包括一个或多个第五方面所述的通信装置。
再一方面，本发明实施例提供了一种计算机存储介质，其上存储有程序，当其运行时，使得计算机执行上述方面所述的方法。
本申请的又一方面提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述各方面所述的方法。
本发明实施例的信息处理的方法、装置、通信设备和通信系统，在编码性能和错误平层上能够适应系统灵活多变的码长码率需要。
附图说明
图1为一LDPC码的基图、基矩阵及其循环置换矩阵的示意图；
图2为一LDPC码的基图的结构示意图；
图3a为本发明一实施例提供的LDPC码基图的示意图；
图3b为本发明另一实施例提供的LDPC码的基矩阵的示意图；
图3c为本发明另一实施例提供的LDPC码的基矩阵的示意图；
图4为本发明另一实施例提供的性能示意图；
图5为本发明另一实施例提供的性能示意图；
图6为本发明另一实施例提供的信息处理装置的结构示意图；
图7为本发明另一实施例提供的通信系统的示意图；
图8a为本发明另一实施例提供的LDPC码基图的示意图；
图8b为本发明另一实施例提供的LDPC码的基矩阵的示意图；
图8c为本发明另一实施例提供的LDPC码的基矩阵的示意图；
图9为本发明实施例提供的LDPC码的性能示意图；
图10为本发明实施例提供的LDPC码的性能示意图；
图11a为本发明另一实施例提供的LDPC码基图的示意图；
图11b为基于图11a提供的LDPC码的基图的基矩阵的示意图；
图12为本发明另一实施例提供的基图的示意图。
具体实施方式
为便于理解下面对本申请中涉及到的一些名词做些说明。
本申请中，名词“网络”和“系统”经常交替使用，“装置”和“设备”也经常交替使用，但本领域的技术人员可以理解其含义。“通信装置”可以是芯片(如基带芯片，或者数据信号处理芯片，或者通用芯片等等)，终端，基站，或者其他网络设备。终端是一种具有通信功能的设备，可以包括具有无线通信功能的手持设备、车载设备、可穿戴设备、计算设备或连接到无线调制解调器的其它处理设备等。在不同的网络中终端可以叫做不同的名称，例如：用户设备，移动台，用户单元，站台，蜂窝电话，个人数字助理，无线调制解调器，无线通信设备，手持设备，膝上型电脑，无绳电话，无线本地环路台等。为描述方便，本申请中简称为终端。基站(base station，BS)，也可称为基站设备，是一种部署在无线接入网用以提供无线通信功能的设备。在不同的无线接入系统中基站的叫法可能有所不同，例如在而在通用移动通讯系统(Universal Mobile Telecommunications System，UMTS)网络中基站称为节点B(NodeB),而在LTE网络中的基站称为演进的节点B(evolved NodeB，eNB或者eNodeB)，在新空口(new radio,NR)网络中的基站称为收发点(transmission reception point，TRP)或者下一代节点B(generation nodeB，gNB)，或者其他各种网络中的基站也可能采用其他叫法。本发明并不限于此。
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行描述。
LDPC码通常可以用奇偶校验矩阵H来表示。LDPC码的奇偶校验矩阵H可以通过基图(base graph)和偏移(shift)值得到。基图通常可以包括m*n个矩阵元素(entry)，可以用m行n列的矩阵形式表示，矩阵元素的值为0或1，其中值为0的元素，有时候也称之为零元素，表示该元素可以被Z*Z的全零矩阵(zero matrix)替换，值为1的元素，有时候也称之为非零元素，表示该元素可以被Z*Z的循环置换矩阵(circulant permutation matrix)替换。也就是说，每个矩阵元素代表的是一个全零矩阵或者一个循环置换矩阵。如图1中10a所示为一个示例性的m＝4，n＝20具有QC结构的LDPC码的基图中的各元素。需要 说明的是，在本文中，基图和矩阵的行号和列号均是从0开始编号的，仅仅是为了方便说明，例如第0列表示为基图和矩阵的第一列，第1列表示为基图和矩阵的第二列、第0行表示基图和矩阵的第一行，第1行表示为基图和矩阵的第二行，以此类推。
可以理解的是，行号和列号也可以从1开始编号，则相应的行号和列号在本文所示的行号和列号基础上加1，例如，如果行号或者列号从1开始编号，则第1列表示基图和矩阵的第一列，第2列表示基图和矩阵的第二列，第1行表示表示基图和矩阵的第一行，第2行表示基图和矩阵的第二行，以此类推。
若基图中第i行第j列的元素值为1，其偏移值为Pi,j，Pi,j为大于或者等于0的整数，则表示第i行第j列的值为1的元素可以被Pi,j对应的Z*Z的循环置换矩阵替换，该循环置换矩阵可通过将Z*Z的单位矩阵进行Pi,j次向右循环移位得到。可见，将基图中每个值为0的元素用Z*Z的全零矩阵替换，每个值为1的元素采用其偏移值对应的Z*Z的循环置换矩阵进行替换，则可以得到LDPC码的奇偶校验矩阵。基图可用于指示偏移值的位置，基图中的非零元素与偏移值对应。Z为正整数，也可以称之为扩展(lifting)因子，有时也可以称之为lifting size，或者lifting factor等，可以根据系统支持的码块大小和信息数据的大小确定的。可见奇偶校验矩阵H的大小为(m*Z)*(n*Z)。例如，扩展因子Z＝4，则每个零元素被一个4*4大小的全0矩阵11a替换，若P2,3＝2，则第2行第3列的非0元素被4*4的循环置换矩阵11d替换，该矩阵是由4*4的单位矩阵11b经过2次向右循环移位得到的，若P2,4＝0，则第2行第4列的非0元素被单位矩阵11b替换。需要说明的是，此处仅仅只是举例说明，并不以此为限制。
由于Pi,j可以是基于扩展因子Z得到的，对于同一个位置上值为1的元素，采用不同的扩展因子Z可能存在不同的Pi,j。为了简化实现，通常系统也会定义一个m*n的基矩阵(base matrix)，在基矩阵中每个元素和基图中每个元素的位置一一对应，基图中的零元素在基矩阵中位置不变，采用-1表示，基图中第i行第j列值为1的非零元素在基矩阵中位置不变，可表示为Pi,j，Pi,j为大于或者等于0的正整数。在本申请实施例中，有时也将基矩阵称为基图矩阵的偏移矩阵。
如图1中10b所示为基图10a对应的一个基矩阵。
通常LDPC码的基图或基矩阵中还可以包括p列内置打孔(built-in puncture)比特列，p可以为0-2的整数，这些列参与编码，但是其编码对应的系统比特不被发送，则LDPC码基矩阵的码率满足R＝(n-m)/(n-p)。对于一个4行20列(4*20)的基矩阵来讲，如果有2列内置打孔比特列，则码率为(20-4)/(20-2)＝8/9。
无线通信系统中采用的LDPC码为QC-LDPC码，其校验位部分具有双对角结构或者raptor-like结构，可以简化编码，支持增量冗余混合重传。QC-LDPC码的译码器中中通常采用QC-LDPC移位网络(QC-LDPC shift network，QSN)，Banyan网络或者Benes网络实现信息的循环移位。
具有raptor-like结构的QC-LDPC码的基图的矩阵大小为m行n列，通常可以包括5个子矩阵A、B、C、D和E，其中，矩阵的权重是由非零元素的个数决定的，行的权重(行重)是指一行中包括的非零元素的个数，列的权重(列重)是指一列中包括的非零元素 的个数。如图2中200所示，其中：
子矩阵A为mA行nA列的矩阵，其大小可以为mA*nA，其中每列对应LDPC码中的Z个系统比特，系统比特有时候也称为信息比特。
子矩阵B为为mA行mA列的方阵，其大小可以为mA*mA，每列对应于LDPC码中的Z个校验比特。子矩阵B包括双对角结构的子矩阵B’和一列权重为3的矩阵列(简称为3列重列)，其中列重为3的矩阵列位于子矩阵B’之前，如图2中20a所示；子矩阵B还可以包括一列重为1的矩阵列(简称为单列重列)，单列重列可以位于子矩阵B的首列或者最后一列，并且其中的非零元素在子矩阵B的最后一行，使得子矩阵B的最后一行的行重为1，如图2中20b或20c所示。
通常基于子矩阵A和B生成的矩阵为核心矩阵，可以用来支持高码率的编码。
子矩阵C为全零矩阵，其大小为mA×(n-(mA+nA))。
子矩阵E为单位矩阵，其大小为(m-mA)×(m-mA)。
子矩阵D大小为(m-mA)×(nA+mA)，通常可用来生成低码率的校验位。
可以理解的是，上述从数学定义的角度对基图进行表述，由于C为全零矩阵，E为单位矩阵，在一种可能的实现方式中，也可以由子矩阵A和B构成的矩阵，或者子矩阵A、B和D构成的矩阵来简化地表示编码或译码的矩阵的基图。
由于子矩阵B、C和E的结构相对确定，子矩阵A和D两部分的结构是LDPC码的编译码性能的影响因素之一。
采用raptor-like结构的LDPC矩阵进行编码时，一种可能的实现方式为，可以先对子矩阵A和B部分的矩阵，也就是核心矩阵进行编码，得到子矩阵B对应的校验比特，再对整个矩阵进行编码，得到子矩阵E部分对应的校验比特。由于子矩阵B可以包括双对角结构的子矩阵B’和一单列重列，在编码中可以先获得双对角结构对应的校验比特，再获得单列重列对应的校验比特。
下面给出一种编码的示例方式。假设子矩阵A和B构成的核心矩阵部分为Hcore，Hcore中去掉单列重列以及该列非零元素所在的行，得到的矩阵部分为Hcore-dual，Hcore-dual中的校验位部分表示为He＝[He1 He2],He1为3列重列，He2为双对角结构。根据LDPC码矩阵定义，Hcore-dual·[S Pe]T＝0，其中，S为输入序列，为信息比特构成的向量，Pe为校验比特构成的向量，[S Pe]T表示由输入序列S和Pe构成的矩阵转置。因此可以先根据输入序列S和Hcore-dual计算出Hcore-dual对应的校验比特，输入序列S中包括所有信息比特；再根据得到Hcore-dual对应的校验比特和输入序列S计算得到子矩阵B中单列重列对应的校验比特，此时可以得到子矩阵B对应的所有校验比特；再根据输入序列S以及子矩阵B对应的校验比特，利用子矩阵D部分编码得到子矩阵E对应的校验比特，从而得到所有信息比特和所有校验比特，这些比特构成编码后的序列，也就是一个LDPC码序列。
可选地，LDPC码编码还可能包含截短(shortening)和打孔(puncturing)操作。被截短的比特和被打孔的比特均不发送。
其中，截短一般是从信息比特的最后一位开始向前截短，可以采用不同的方式进行截短。例如，被截短的比特数s0，可以将输入序列S中最后s0个比特设置为已知比特得到输入序列S’，如设置为0或者null，或者其他一些值，然后通过LDPC矩阵对输入序列S’进行编码，又例如，也可以可以将输入序列S中最后(s0mod Z)个比特设置为已知比特 得到输入序列S’，如设置为0或者null，或者其他一些值，将子矩阵A中最后
Figure PCTCN2017092877-appb-000001
列删除得到LDPC矩阵H’，使用LDPC矩阵H‘对输入序列S’进行编码，或者子矩阵A中最后
Figure PCTCN2017092877-appb-000002
列不参与对输入序列S’的编码。在完成编码后，被截短的比特不发送。
其中，打孔可以是对输入序列中内置打孔比特，或者校验比特进行打孔。对校验比特打孔时通常也是从校验比特的最后一位进行打孔的，当然，也可以按照系统预设的打孔顺序进行打孔。一种可能的实现方式为，先对输入序列进行编码，然后根据需要被打孔的比特数p，选择校验比特中最后p个比特或者根据系统预设的打孔顺序选择p个比特，这p个比特不发送。又一种可能的实现方式中，也可以确定出被打孔比特对应的矩阵的p列以及这些列中非零元素所在的p行，这些行、列不参与编码，也就不产生相应的校验比特。
需要说明的是，这里对编码方式只是举例，基于本申请提供基图和/或基矩阵还可以采用本领域技术人员所知的其他编码方式，本申请并不限定。本申请中涉及的译码，可以是采用多种译码方式，例如可以采用，min-sum(MS)译码方式，也可以采用belief propagation译码方式。MS译码方法有时也称为Flood MS译码方法。例如，对输入序列初始化，并进行迭代处理，在迭代后进行硬判决检测，并对硬判决结果进行校验，如果译码结果符合校验方程，则译码成功，终止迭代，并输出判决结果。如果不符合校验方程，则在最大迭代次数内再次进行迭代处理，若达到最大迭代次数，仍校验失败，则译码失败。可以理解的是，本领域的技术人员可以理解MS译码的原理，在此不再详述。
需要说明的是，对于译码方式只是举例说明，对于基于本申请提供基图和/或基矩阵还可以采用本领域技术人员所知的其他译码方式，本申请对译码方式并不限定。
通常LDPC码可基于基图和基矩阵获得，对基图或者基矩阵采用密度进化的方法可以确定出LDPC码的性能上限，并且根据基矩阵中的偏移值确定出LDPC码的错误平层。改善编译码性能和降低错误平层是确定基图和基矩阵的目标之一。无线通信系统中码长灵活多变，既可以是如40比特，1280比特这样的小块长码块，也可以是如5000比特8448比特这样的大块长码块。图3a、3b以及3c分别为一个LDPC码的基图和基矩阵示例，可满足块长多达8448比特的码块的性能需求，图8a、图8b以及图8c给出了另一LDPC码的基图和基矩阵示例，图11a和图11b给出另一LDPC码的基图和基矩阵示例。为方便说明及理解，附图中3a、3b以及3c中在最上侧以及最左侧，分别示出了列号和行号图4和图5分别给出了图3a-3c所示的LDPC码在两种不同码率时的性能示意图。图3a所示为一个LDPC码的基图30a示例，其中，图中最上面一行0-67表示列编号，最左面一列0-45表示行编号，也就是基图的大小为46行68列。
子矩阵A对应系统比特，大小为5行22列，在基图30a中由第0行至第4行以及第0列至第21列的元素构成；
子矩阵B对应校验比特，大小为5行5列，在基图30a中由第0行至第4行以及第22列至第26列的元素构成；
子矩阵A和子矩阵B构成了LDPC码基图的核心矩阵部分，也即构成了一个5行27列的矩阵，可用于高码率编码。例如，子矩阵A和子矩阵B构成的核心矩阵部分中，1列的权重为5，1列的权重为4，21列的权重为3，3列的权重为2，1列的权重为1。
其中，子矩阵A中可以包括2列内置打孔比特列，则打孔后，核心矩阵可以支持的码率为22/(27-2)＝0.88。子矩阵A中，包括1列的权重为5，1列的权重为4，其余20列的权重分别为3。例如，可以2列内置打孔比特列的权重分别为5和4。
其中，子矩阵B中最后1行(第4行)的行重和最后一列(子矩阵B的第4列，核心矩阵的第26列)的列重均为1，矩阵B包括1列3列重列，即子矩阵B的第0列(核心矩阵的第22列)列重为3，子矩阵B的第1至3列(核心矩阵的第23至25列)，第0至3行为双对角结构。
基图30a的核心矩阵中，包括了4行权重为19的行，和1行权重为3的行。也就是，子矩阵A和子矩阵B构成的核心矩阵中各行的权值分别为19，19，19，19和3。需要说明的是，核心矩阵中各行的顺序是可以交换的，例如第0行和第2行交换，第1行和第3行交换等等。权重为3的行可以如基图30a的核心矩阵中第4行，第0至第26列所示；权重为19的行可以分别为基图30a的核心矩阵中第0至第3行，第0至第26列所示的各行之一。这些行顺序可以交换，各列的顺序也可以交换。例如，可以将核心矩阵的第8列和第25列交换，第10列和第26列交换等。例如，可以将核心矩阵的第3行和第0行交换，第2行和第1行交换，为了保持子矩阵B中的双对角结构，还可以在此基础上将第23列和第25列进行交换得到如图8a所示的基图80a的核心矩阵部分，也即80a中第0行至第5行，第0列至第26列构成的矩阵部分。需要说明的是，此处仅为举例，实际应用中，列顺序的交换，行顺序的交换，是可以e根据系统需求灵活设计。
如表一所示，为对基图80a的一种列交换示例，为了方便描述，此处给出核心矩阵部分的27列经过列交换后顺序，列号是指交换后矩阵的列号，从0开始编号，交换前列号是指矩阵列在交换前矩阵中的列号，如表一所示，将交换前矩阵中的第8列和第10列交换到第25列和第26列，交换前矩阵中的第9列交换到第8列的位置，将交换前矩阵中的第11列至第21列交换到第9列至第19列，交换前矩阵中的第25列和第26列交换到第20列和第21列。在这种方式下，可以对特定码率和码长的性能有所改善，例如，图9为基于表一所示的基矩阵的性能示意图，在2/3码率，BLER＝1E-2，码长为(672,960)时性能得到改善；图10为基于表一所示的基矩阵的性能示意图，在2/3码率，BLER＝1E-2，在码长为(1952,2624)时性能得到改善。
表一
列号 0 1 2 3 4 5 6 7 8 9 10 11 12 13
交换前列号 0 1 2 3 4 5 6 7 9 11 12 13 14 15
列号 14 15 16 17 18 19 20 21 22 23 24 25 26
交换前列号 16 17 18 19 20 21 25 26 22 23 24 8 10
可以理解的是，由于矩阵行之间可以交换、列之间也可以交换，行交换不改变矩阵中列的权重，列交换不改变矩阵中行的权重，矩阵中非零元素的个数是没有发生改变的。经过行交换和列交换后的基图80a的各行的权重没有改变。使用经过行交换，或者列交换，或者行交换和列交换后的基图不影响性能。
需要说明的是，本申请中，不影响性能是指的从整体讲，影响可接受，在容忍范围 内，例如，可能对某些场景或者在某些范围内，性能在允许范围内下降，但是在某些场景或者某些范围内，性能有所改善，整体上看对性能影响不大。
以上述基图30a和基图80a的核心矩阵为例，基图30a的行顺序交换后，基图80a的核心矩阵中仍然包括基图30a的核心矩阵中的各列，1行的权重为3，其余4行的权重为19，只是行的顺序不同。如果对基图30a中列进行交换，例如第5列和第7列交换，可以发现，经过列交换后的基图30a的核心矩阵中仍然包括了基图30a的核心矩阵中的各列，1列的权重为5，1列的权重为4，21列权重为3，3列权重为2，1列权重为1，只是列的顺序不同。需要说明的是，此处仅为举例，并不限于此。
通常对于一个LDPC码给定的基图或者基矩阵而言，对矩阵元素的少量修改对性能影响是可接受的。例如，在一种实现方式中，可以基于基图30a的核心矩阵，进行少量修改，例如，其中1行的权重满足大于或者等于1，且小于或者等于5，其余4行的权重分别满足大于或者等于17，且小于或者等于21。例如，1行的权重为2，其余4行的权重为18，或者1行的权重为4，其余4行的权重分别为17，18，19，19等等。可以理解，也可以参照本申请提供的方案，使其中某些行的权重增加或减少1-2，本申请并不对此进行限定。
在子矩阵A中也可以包括1行，在该行中除了位于内置打孔列上的元素，其余元素均为零元素。进一步地，为了使得这一行在核心矩阵或者基图矩阵中权重最小，通常和子矩阵B中行重为1的行在同一行。例如，内置打孔比特列数为2，也就是第0列和第1列为内置打孔比特列，如基图30a或者80a所示，第4行中，第0列和第1列上的元素为非零元素，第2列至第25列上的元素为零元素，第26列的元素为非零元素，第4行的权重为3，不仅在核心矩阵中行的权重最小，在整个基图矩阵中行的权重也是最小的。这种设置可以改善编码和译码的性能。
为了支持不同块长，LDPC码需要不同的扩展因子Z，例如，扩展因子Z可以包括以下设计中的一个或多个：16，18，20，22，24，26，28，30，32，36，40，44，48，52，56，60，64，72，80，88，96，104，112，120，128，144，160，176，192，208，224，240，256，288，320，352，384。为了保证不同块长下的LDPC码性能，可以分别基于不同的扩展因子Z采用与之对应的基矩阵。如图3b所示为基图30a中核心矩阵的多个基矩阵示例。各基矩阵是基于基图30a的核心矩阵和扩展因子Z得到的，其中，基图30a中第i行第j列的非零元素在基矩阵第i行第j列为偏移值Pi,j，基图30a中零元素在偏移矩阵中以-1或者null表示。
其中，在一种可能的实现方式中：
若扩展因子Z为{16，18，20，22，24，26，28，30}中的一个，则基图30a的基矩阵对应子矩阵A和子矩阵B的部分可以如图3b中基矩阵30b-1所示；
若扩展因子Z为{32，36，40，44，48，52，56，60}中的一个，则基图30a的基矩阵对应子矩阵A和子矩阵B的部分可以如图3b中基矩阵30b-2所示；
若扩展因子Z为{60，64，72，80，88，96，104，112，120}中的一个，则基图30a的基矩阵对应子矩阵A和子矩阵B的部分可以如图3b中基矩阵30b-3所示；
若扩展因子Z为{128，144，160，176，192，208，224，240}中的一个，则基图30a的基矩阵对应子矩阵A和子矩阵B的部分可以如图3b中基矩阵30b-4所示；
若扩展因子Z为{256，288，320，352，384}中的一个，则基图30a的基矩阵对应子矩阵A和子矩阵B的部分可以如图中基矩阵30b-5所示。
在又一种可能的实现方式中，扩展因子集合可以为{24，26，28，30，32，36，40，44，48，52，56，60，64，72，80，88，96，104，112，120，128，144，160，176，192，208，224，240，256，288，320，352，384}：
若扩展因子Z为{24，26，28，30}中的一个，则基图30a的基矩阵对应子矩阵A和子矩阵B的部分可以如图3b中基矩阵30b-6所示；
若扩展因子Z为{32，36，40，44}中的一个，则基图30a的基矩阵对应子矩阵A和子矩阵B的部分可以如图3b中基矩阵30b-7所示；
若扩展因子Z为{48，52，56，60}中的一个，则基图30a的基矩阵对应子矩阵A和子矩阵B的部分可以如图3b中基矩阵30b-8所示；
若扩展因子Z为{60，64，72，80，88，96，104，112，120}中的一个，则基图30a的基矩阵对应子矩阵A和子矩阵B的部分可以如图3b中基矩阵30b-3所示；
若扩展因子Z为{128，144，160，176，192，208，224，240}中的一个，则基图30a的基矩阵对应子矩阵A和子矩阵B的部分可以如图3b中基矩阵30b-4所示；
若扩展因子Z为{256，288，320，352，384}中的一个，则基图30a的基矩阵对应子矩阵A和子矩阵B的部分可以如图中基矩阵30b-5所示。
基于上述实现方式，在又一种可能的实现方式中，为了进一步改善性能，基图对应的基矩阵也可以更多，基图30a的基矩阵对应子矩阵A和子矩阵B的部分可以对应到不同的基矩阵，例如：
若扩展因子Z为{24，26，28，30}中的一个，则基图30a的基矩阵对应子矩阵A和子矩阵B的部分可以如图3b中基矩阵30b-6所示；
若扩展因子Z为{32，36，40，44}中的一个，则基图30a的基矩阵对应子矩阵A和子矩阵B的部分可以如图3b中基矩阵30b-7所示；
若扩展因子Z为{48，52，56，60}中的一个，则基图30a的基矩阵对应子矩阵A和子矩阵B的部分可以如图3b中基矩阵30b-8所示；
若扩展因子Z为{64，72，80，88}中的一个，则基图30a的基矩阵对应子矩阵A和子矩阵B的部分可以如图3b中基矩阵30b-9或者30b-10所示；
若扩展因子Z为{96，104，112，120}中的一个，则基图30a的基矩阵对应子矩阵A和子矩阵B的部分可以如图3b中基矩阵30b-3所示；
若扩展因子Z为{128，144，160，176，192，208，224，240}中的一个，则基图30a的基矩阵对应子矩阵A和子矩阵B的部分可以如图3b中基矩阵30b-4所示；
若扩展因子Z为{256，288，320，352，384}中的一个，则基图30a的基矩阵对应子矩阵A和子矩阵B的部分可以如图中基矩阵30b-5所示。
如图8b所示为基图80a中核心矩阵的多个基矩阵示例。各基矩阵是基于基图80a的核心矩阵和扩展因子Z得到的，其中，基图80a中第i行第j列的非零元素在基矩阵第i行第j列为偏移值Pi,j，基图80a中零元素在偏移矩阵中以-1或者null表示。
在又一种可能的实现方式中，扩展因子集合可以为{24，26，28，30，32，36，40，44，48，52，56，60，64，72，80，88，96，104，112，120，128，144，160，176，192，208，224，240，256，288，320，352，384}：
若扩展因子Z为{24，26，28，30}中的一个，则基图80a的基矩阵对应子矩阵A和子矩阵B的部分可以如图8b中基矩阵80b-1所示；
若扩展因子Z为{32，36，40，44}中的一个，则基图80a的基矩阵对应子矩阵A和子矩阵B的部分可以如图8b中基矩阵80b-2所示；
若扩展因子Z为{48，52，56，60}中的一个，则基图80a的基矩阵对应子矩阵A和子矩阵B的部分可以如图8b中基矩阵80b-3所示；
若扩展因子Z为{60，64，72，80，88，96，104，112，120}中的一个，则基图80a的基矩阵对应子矩阵A和子矩阵B的部分可以如图8b中基矩阵80b-4所示；
若扩展因子Z为{128，144，160，176，192，208，224，240}中的一个，则基图80a的基矩阵对应子矩阵A和子矩阵B的部分可以如图8b中基矩阵80b-5所示；
若扩展因子Z为{256，288，320，352，384}中的一个，则基图80a的基矩阵对应子矩阵A和子矩阵B的部分可以如图中基矩阵80b-6所示。
基于上述实现方式，在又一种可能的实现方式中，为了进一步改善性能，基图对应的基矩阵也可以更多，基图80a的基矩阵对应子矩阵A和子矩阵B的部分可以对应到不同的基矩阵，例如，其中：
若扩展因子Z为{24，26，28，30}中的一个，则基图80a的基矩阵对应子矩阵A和子矩阵B的部分可以如图8b中基矩阵80b-1所示；
若扩展因子Z为{32，36，40，44}中的一个，则基图80a的基矩阵对应子矩阵A和子矩阵B的部分可以如图8b中基矩阵80b-2所示；
若扩展因子Z为{48，52，56，60}中的一个，则基图80a的基矩阵对应子矩阵A和子矩阵B的部分可以如图8b中基矩阵80b-3所示；
若扩展因子Z为{64，72，80，88}中的一个，则基图80a的基矩阵对应子矩阵A和子矩阵B的部分可以如图8b中基矩阵80b-7或者80b-8所示；
若扩展因子Z为{96，104，112，120}中的一个，则基图80a的基矩阵对应子矩阵A和子矩阵B的部分可以如图8b中基矩阵80b-4所示；
若扩展因子Z为{128，144，160，176，192，208，224，240}中的一个，则基图80a的基矩阵对应子矩阵A和子矩阵B的部分可以如图8b中基矩阵80b-5所示；
若扩展因子Z为{256，288，320，352，384}中的一个，则基图80a的基矩阵对应子矩阵A和子矩阵B的部分可以如图中基矩阵80b-6所示。
在又一种可能的实现方式中，基图80a的基矩阵对应子矩阵A和子矩阵B的部分可以如图8b中基矩阵80b-9所示。由于扩展因子Z可以采用多种方式划分，因此相应的，对一组扩展因子Z使用的基矩阵可以结合性能考虑。
例如，根据输入序列的长度K来确定扩展因子Z的取值，如：若输入序列长度为K，可以在多个系统定义的扩展因子中确定满足22*Z≥K的最小值作为矩阵的扩展因子的取值。进一步，可以根据确定的扩展因子选择相应的基矩阵。如表二所示，为基矩阵和扩展因子对应关系的一种示例，多个系统定义的扩展因子被划分成8组，也就是8个集合，集合索引分别为1至8，相应地，基矩阵也有8个PCM1-PCM8：
表二
Figure PCTCN2017092877-appb-000003
Figure PCTCN2017092877-appb-000004
例如，基矩阵80b-9可以作为PCM8，则扩展因子Z为15,30,60,120,240中的任一个时，可以采用80b-9作为基矩阵，相应地使用扩展因子Z进行扩展得到LDPC校验矩阵。进一步地，Z大于或者等于24时，基矩阵80b-9性能相对较好。
同样的，基矩阵中各行也是可以交换的，各列也可以交换。若基图经过行交换或列交换中至少一种交换，则相应部分的基矩阵也进行同样的交换。
可以看到，在上述实现方式中，80b-1是相应于30b-6的行列交换后的矩阵，80b-2是相应于30b-7的行列交换后的矩阵，80b-3是相应于30b-8的行列交换后的矩阵，80b-4是相应于30b-3的行列交换后的矩阵，80b-5是相应于30b-4的行列交换后的矩阵，80b-6是相应于30b-5的行列交换后的矩阵，80b-7是相应于30b-9的行列交换后的矩阵，80b-8是相应于30b-10的行列交换后的矩阵。
当然，可以理解的是，LDPC矩阵的基矩阵对应所述子矩阵A和子矩阵B构成的部分可以包括基矩阵30b-1、30b-2、30b-3、30b-4、30b-5、30b-6、30b-7、30b-8、30b-9或30b-10中任一个的各行或者各列，也就是基于基矩阵30b-1、30b-2、30b-3、30b-4、30b-5、30b-6、30b-7、30b-8、30b-9或30b-10中任一个经过列交换，或者行交换，或者行交换和列交换的矩阵。
为了获得灵活的码率，可以基于核心矩阵添加相应大小的子矩阵C、子矩阵D和子矩阵E，来获得不同的码率。由于子矩阵C为全零矩阵，子矩阵为单位矩阵，其大小主要是根据码率来确定，结构相对固定。影响到编译码性能的主要在于核心矩阵和子矩阵D部分。在核心矩阵的基础上添加行列，形成相应的C、D和E部分可以得到不同码率。例如，可以以基图30a的核心矩阵部分或者基图80a的核心矩阵部分作为核心矩阵，为满足不同码率编码或译码的需求，添加相应的子矩阵C、D和E。
子矩阵D的列数为子矩阵A和B的列数之和，其行数主要与码率相关。以基图30a为例，则相应的子矩阵D的列数mD为(nA+mA)＝27列，若LDPC码支持的码率为Rm，则其基图或者基矩阵的大小为m*n，其中，n＝nA/Rm+p，m＝n-nA＝nA/Rm+p-nA。若最低码率Rm＝1/3，内置打孔列数p＝2，以基图30a为例，则n＝68，m＝46，子矩阵D的行数mD最大可以为m-mA＝46-5＝41，也就是0≤mD≤41。
为了方便描述，可以定义一个大小为41行27列的矩阵F，则子矩阵D可以包括其中的mD行，和子矩阵A、B以及相应大小的子矩阵C和E一起构成码率为22/(25+mD)的LDPC码的基图。基图30a中，mD＝41，相应地子矩阵D大小为41行27列，也就是子矩阵D即矩阵F，对应LDPC码支持的码率为22/66＝1/3。可见，基图30a中第5行至第45行以及 第0列至第26列构成的矩阵即为矩阵F。
在图30a所示例的矩阵F中，其行重依次为7，7，9，8，7，7，8，6，6，5，6，5，5，6，5，5，5，5，4，4，4，5，4，5，4，4，4，4，3，4，4，4，4，3，3，4，4，3，3，3，4。
由于子矩阵E为单位矩阵，因此基图30a中每一行的权重为8，8，10，9，8，8，9，7，7，6，7，6，6，7，6，6，6，6，5，5，5，6，5，6，5，5，5，5，4，5，5，5，5，4，4，5，5，4，4，4，5。
在本发明中，若基图中相邻两行的同一列最多只有1个非零元素，则这两行彼此正交。
在一种可能的实现方式中，矩阵F可以是一个准正交结构的矩阵，在矩阵F中除了内置打孔比特列以外的其余列构成的矩阵块中，任意相邻两行的同一列中最多只有一个非零元素，也就是矩阵F中除了内置打孔比特列以外的其余列构成的矩阵块具有正交结构。以基图30a为例，矩阵F为第5行至第45行以及第0列至第26列构成的矩阵，其中，第0列和第1列为内置打孔比特列，则由第5行至第45行以及第2列至第26列构成的矩阵块中，第5行和第6行相互正交，第6行和第7行相互正交，第23行和第24行相互正交，第32行和第33行相互正交，以此类推。若mD＝15，LDPC码基图中子矩阵D大小为15行27列，可以是由基图30a中矩阵F的第0-14行，也就是基图30a的第5行至第19行，第0列至第26列的矩阵构成，对应LDPC码支持的码率为22/40＝0.55，也就是在该码率下，LDPC码的基图对应于基图30a的第0行至第19行，第0列至第41列构成的矩阵部分，其中子矩阵E为15行15列的单位矩阵，子矩阵C为5行15列的全0矩阵；
若mD＝19，LDPC码基图中子矩阵D大小为19行27列，可以是由基图30a中矩阵F的第0-18行，也就是基图30a的第5行至第23行，第0列至第26列的矩阵构成构成，对应LDPC码支持的码率为22/44＝1/2，也就是在该码率下，LDPC码的基图对应于基图30a的第0行至第23行，第0列至第41列构成的矩阵部分，其中子矩阵E为19行19列的单位矩阵，子矩阵C为5行19列的全0矩阵。
以此类推，不一一阐述。
需要说明的是，LDPC码的基图和基矩阵中各行是可以相互交换的，各列也是可以相互交换的。例如，可将基图30a的第17行和第19行进行交换，并且将第39列和第41列进行交换得到如图8a所示的基图矩阵80a。又例如，子矩阵D包括矩阵F中mD行，这mD行可以不进行行交换，也可以将其中一行或多行之间进行行交换，子矩阵E仍为对角结构，不做行、列交换，例如，将矩阵F的第12行和第14行进行行交换，子矩阵D包括矩阵F中mD行，子矩阵E仍为对角结构，从而得到基图80a。矩阵F在进行行交换前是一个准正交的矩阵，经过交换后仍然为一个准正交的矩阵。例如，在基图80a中，矩阵F为第5行至第45行以及第0列至第26列构成的矩阵，其中，第0列和第1列为内置打孔比特列，则由第5行至第45行以及第2列至第26列构成的矩阵块中，第5行和第6行相互正交，第29行和第30行相互正交，以此类推。可以理解的是，若基图或基矩阵包括子矩阵D，那么对核心矩阵的列进行交换时，相应的子矩阵D中列也需要进行交换，例如，核心矩阵中第23列和第25列进行交换，子矩阵D中第23列和第25列也需要相应进行交换。此处仅为举例，并不以此为限制。
本发明各实施例中子矩阵D满足准正交结构，也就是除了内置打孔列之外，其他各列相邻两行是正交的。例如：本发明各实施例提供的基图30a、80a以及170a，图12中子矩阵D，例如，第0列和第1列这2列为内置打孔列，其他各列相邻两行之间是正交的。需要说明的是，内置打孔列也可以是其他列，此处并不做限制。
在又一种可能的实现方式中，准正交结构的矩阵F中也可以包括至少2行正交行，至少2行正交行中相邻两行第0列至第26列中每一列最多只有1个非零元素。例如，若mD>30，则对应LDPC码支持的码率小于2/5，矩阵F中最后11行，也就是矩阵F的第30行至第40行以及第0列至第26列构成的子矩阵可以是正交的。也就是矩阵F第0行至第29行中相邻两行除了内置打孔比特列以外其他列最多只有一个非零元素，第30行至第40行中相邻两行第0列至第26列各列最多只有一个非零元素。
又例如，矩阵F中第26行至第40行以及第0列至第26列构成的子矩阵可以是正交的。也就是矩阵F中第0行至第25行中相邻两行除了内置打孔比特列以外其他列最多只有一个非零元素，第26行至第40行中相邻两行第0列至第26列各列最多只有一个非零元素。如图11a所示基图170a，其中矩阵F为基图的第5行至第45行以及第0列至第26列构成的矩阵，矩阵F为准正交结构，并且矩阵F的第26行至第40行是正交的，其中第26行至第40行相邻两行各列最多只有一个非零元素。
基图170a的核心矩阵部分与基图80a中的核心矩阵部分相同。对每一码率中的子矩阵D，每一行可以进行1-2个非零元素或者1-2个零元素的修改，而不影响其性能。
又例如，若mD>20，矩阵F中最后21行，也就是矩阵F的第25行至第45行以及第0列至第26列构成的子矩阵可以是正交的。也就是矩阵F第0行至第19行中相邻两行除了内置打孔比特列以外其他列最多只有一个非零元素，第20行至第40行中相邻两行第0列至第26列各列最多只有一个非零元素。如图11a所示基图170a其核心矩阵与基图80a中的核心矩阵部分相同，第5行至第45行符合准正交结构，也可以说第5行至第25行符合准正交结构，第25行至第45行符合正交结构。
图12所示的基图中核心矩阵部分与基图80a中的核心矩阵部分相同，其第5行至第45行符合准正交结构。
如图3c所示基矩阵30c为基图30a的基矩阵示例，其中，基图30a中第i行第j列的非零元素在基矩阵30c中位置不变，值为偏移值Pi,j。其中，子矩阵D的部分包括矩阵F的偏移矩阵的mD行，对于图3c中所示的基矩阵30c，mD＝41，可以根据码率的不同选择mD值。子矩阵D对应的偏移矩阵为矩阵F的偏移矩阵。这里矩阵F的偏移矩阵也就是将矩阵F中第i行第j列的非零元素替换为偏移值Pi,j，零元素在偏移矩阵中以-1或者null表示。需要说明的是，此处仅为举例，基图也可以是80a或者180a等，此处不一一赘述。
其中，一种可能的实现方式中，矩阵F的偏移矩阵可以包括30c-1至30c-10中任一矩阵的各行或者各列。例如：
若扩展因子Z为{16，18，20，22，24，26，28，30}中的一个，则矩阵F的偏移矩阵可以是如30c-1所示的矩阵，或者是该矩阵的行/列变换后的矩阵；
若扩展因子Z为{32，36，40，44，48，52，56，60}中的一个，则矩阵F的偏移矩阵可以是如30c-2所示的矩阵，或者是该矩阵的行/列变换后的矩阵；
若扩展因子Z为{60，64，72，80，88，96，104，112，120}中的一个，则 矩阵F的偏移矩阵可以是如30c-3所示的矩阵，或者是该矩阵的行/列变换后的矩阵；
若扩展因子Z为{128，144，160，176，192，208，224，240}中的一个，则矩阵F的偏移矩阵可以是如30c-4所示的矩阵，或者是该矩阵的行/列变换后的矩阵；
若扩展因子Z为{256，288，320，352，384}中的一个，则则矩阵F的偏移矩阵可以是如30c-5所示的矩阵，或者是该矩阵的行/列变换后的矩阵。
将基矩阵30c中子矩阵D替换为上述各矩阵F的偏移矩阵中的mD行，可以得到与基图30a对应的不同码率的各个基矩阵。若mD＝41，将基矩阵30c中第5行至第45行，第0列至第26列构成的矩阵部分替换为各矩阵F的偏移矩阵，可以得到与大小为46行68列的基图30a对应的各个基矩阵，此时码率为1/3。
又一种可能的实现方式中，扩展因子集合可以为{24，26，28，30，32，36，40，44，48，52，56，60，64，72，80，88，96，104，112，120，128，144，160，176，192，208，224，240，256，288，320，352，384}：
若扩展因子Z为{24，26，28，30}中的一个，则矩阵F的偏移矩阵可以是如30c-6所示的矩阵，或者是该矩阵的行/列变换后的矩阵；
若扩展因子Z为{32，36，40，44}中的一个，则矩阵F的偏移矩阵可以是如30c-7所示的矩阵，或者是该矩阵的行/列变换后的矩阵；
若扩展因子Z为{48，52，56，60}中的一个，则矩阵F的偏移矩阵可以是如30c-8所示的矩阵，或者是该矩阵的行/列变换后的矩阵；
若扩展因子Z为{60，64，72，80，88，96，104，112，120}中的一个，则矩阵F的偏移矩阵可以是如30c-3所示的矩阵，或者是该矩阵的行/列变换后的矩阵；
若扩展因子Z为{128，144，160，176，192，208，224，240}中的一个，则矩阵F的偏移矩阵可以是如30c-4所示的矩阵，或者是该矩阵的行/列变换后的矩阵；
若扩展因子Z为{256，288，320，352，384}中的一个，则矩阵F的偏移矩阵可以是如30c-5所示的矩阵，或者是该矩阵的行/列变换后的矩阵。
基于上述实现方式，在又一种可能的实现方式中，为了进一步改善性能，矩阵F的偏移矩阵有更多的选择。例如矩阵F的偏移矩阵还可以是如30c-9的矩阵，或者是该矩阵的行/列变换后的矩阵，或者是如30c-10的矩阵，或者是该矩阵的行/列变换后的矩阵，例如，可以对扩展因子做如下设计：
若扩展因子Z为{24，26，28，30}中的一个，则矩阵F的偏移矩阵可以是如30c-6所示的矩阵，或者是该矩阵的行/列变换后的矩阵；
若扩展因子Z为{32，36，40，44}中的一个，则矩阵F的偏移矩阵可以是如30c-7所示的矩阵，或者是该矩阵的行/列变换后的矩阵；
若扩展因子Z为{48，52，56，60}中的一个，则矩阵F的偏移矩阵可以是如30c-8所示的矩阵，或者是该矩阵的行/列变换后的矩阵；
若扩展因子Z为{64，72，80，88}中的一个，则矩阵F的偏移矩阵可以是如30c-9或者30c-10所示的矩阵，或者是该矩阵的行/列变换后的矩阵；
若扩展因子Z为{96，104，112，120}中的一个，则矩阵F的偏移矩阵可以是如30c-3所示的矩阵，或者是该矩阵的行/列变换后的矩阵；
若扩展因子Z为{128，144，160，176，192，208，224，240}中的一个，则矩阵F的偏移矩阵可以是如30c-4所示的矩阵，或者是该矩阵的行/列变换后的矩阵；
若扩展因子Z为{256，288，320，352，384}中的一个，则矩阵F的偏移矩阵可以是如30c-5所示的矩阵，或者是该矩阵的行/列变换后的矩阵。
又一种可能的实现方式中，矩阵F的偏移矩阵可以包括80c-1至80c-9中任一矩阵的各行或者各列。例如：扩展因子集合可以为{24，26，28，30，32，36，40，44，48，52，56，60，64，72，80，88，96，104，112，120，128，144，160，176，192，208，224，240，256，288，320，352，384}：
若扩展因子Z为{24，26，28，30}中的一个，则矩阵F的偏移矩阵可以是如80c-1所示的矩阵，或者是该矩阵的行/列变换后的矩阵；
若扩展因子Z为{32，36，40，44}中的一个，则矩阵F的偏移矩阵可以是如80c-2所示的矩阵，或者是该矩阵的行/列变换后的矩阵；
若扩展因子Z为{48，52，56，60}中的一个，则矩阵F的偏移矩阵可以是如80c-3所示的矩阵，或者是该矩阵的行/列变换后的矩阵；
若扩展因子Z为{60，64，72，80，88，96，104，112，120}中的一个，则矩阵F的偏移矩阵可以是如80c-4所示的矩阵，或者是该矩阵的行/列变换后的矩阵；
若扩展因子Z为{128，144，160，176，192，208，224，240}中的一个，则矩阵F的偏移矩阵可以是如80c-5所示的矩阵，或者是该矩阵的行/列变换后的矩阵；
若扩展因子Z为{256，288，320，352，384}中的一个，则矩阵F的偏移矩阵可以是如80c-6所示的矩阵，或者是该矩阵的行/列变换后的矩阵。
基于上述实现方式，在又一种可能的实现方式中，为了进一步改善性能，可以将扩展因子Z支持的粒度设计得更细，从而使得矩阵F的偏移矩阵有更多的选择。例如矩阵F的偏移矩阵还可以是如80c-7的矩阵，或者是该矩阵的行/列变换后的矩阵，或者是如80c-8的矩阵，或者是该矩阵的行/列变换后的矩阵，例如，可以对扩展因子做如下设计，其中：
若扩展因子Z为{24，26，28，30}中的一个，则矩阵F的偏移矩阵可以是如80c-1所示的矩阵，或者是该矩阵的行/列变换后的矩阵；
若扩展因子Z为{32，36，40，44}中的一个，则矩阵F的偏移矩阵可以是如80c-2所示的矩阵，或者是该矩阵的行/列变换后的矩阵；
若扩展因子Z为{48，52，56，60}中的一个，则矩阵F的偏移矩阵可以是如80c-3所示的矩阵，或者是该矩阵的行/列变换后的矩阵；
若扩展因子Z为{64，72，80，88}中的一个，则矩阵F的偏移矩阵可以是如80c-7或者80c-8所示的矩阵，或者是该矩阵的行/列变换后的矩阵；
若扩展因子Z为{96，104，112，120}中的一个，则矩阵F的偏移矩阵可以是如80c-4所示的矩阵，或者是该矩阵的行/列变换后的矩阵；
若扩展因子Z为{128，144，160，176，192，208，224，240}中的一个，则矩阵F的偏移矩阵可以是如80c-5所示的矩阵，或者是该矩阵的行/列变换后的矩阵；
若扩展因子Z为{256，288，320，352，384}中的一个，则矩阵F的偏移矩阵可以是如80c-6所示的矩阵，或者是该矩阵的行/列变换后的矩阵。
又一种可能的实现方式中，若扩展因子Z为为15,30,60,120,240中的任一个时，则矩阵F的偏移矩阵可以是如80c-9所示的矩阵，或者是该矩阵的行/列变换后的矩阵，进 一步地，Z大于或者等于24时，矩阵F的偏移矩阵采用80c-9性能相对较好。
同样的，基矩阵中各行也是可以交换的，各列也可以交换。若基图经过了行交换或列交换中至少一种，则相应部分的基矩阵也进行同样的交换。
可以看到，在上述实现方式中，80c-1是相应于30c-6的行交换后的矩阵，80c-2是相应于30c-7的行交换后的矩阵，80c-3是相应于30c-8的行交换后的矩阵，80c-4是相应于30c-3的行交换后的矩阵，80c-5是相应于30c-4的行交换后的矩阵，80c-6是相应于30c-5的行交换后的矩阵，80c-7是相应于30c-9的行交换后的矩阵，80c-8是相应于30c-10的行交换后的矩阵。
将基矩阵80c中子矩阵D替换为上述各矩阵F的偏移矩阵中的mD行，可以得到与基图80a对应的不同码率的各个基矩阵。若mD＝41，将基矩阵80c中第5行至第45行，第0列至第26列构成的矩阵部分替换为各矩阵F的偏移矩阵，可以得到与大小为46行68列的基图80a对应的各个基矩阵，此时码率为1/3。
需要说明的是，由于基图和基矩阵中各行、各列都可以交换，一种可能的实现方式中，基图的核心矩阵，也就是子矩阵A和B构成的部分可以采用基图30a中的核心矩阵部分，基图的子矩阵D可以包括基图30a中第5行到第45行，第0列到第26列构成的矩阵部分中的mD行。相应地，基矩阵中核心矩阵部分可以为30b-3，30b-4，30b-5，30b-6，30b-7、30b-8、30b-9以及30b-10中的一个，子矩阵D对应的部分可以包括以下任一矩阵的mD行：30c-3，30c-4，30c-5，30c-6，30c-7、30c-8、30c-9和30c-10。可以根据扩展因子选择核心矩阵和子矩阵D对应的部分。
又一种可能的实现方式中，基图的核心矩阵，也就是子矩阵A和B构成的部分可以采用基图80a中的核心矩阵部分，基图的子矩阵D可以包括基图80a中第5行到第45行，第0列到第26列构成的矩阵部分中的mD行。相应地，基矩阵中核心矩阵部分可以为80b-1，80b-2，80b-3，80b-4，80b-5、80b-6、80b-7、80b-8和80b-9中的一个，子矩阵D对应的部分可以包括以下任一矩阵的mD行：80c-1，80c-2，80c-3，80c-4，80c-5、80c-6、80c-7、80c-8和80c-9。可以根据扩展因子选择核心矩阵和子矩阵D对应的部分。
又一种可能的实现方式中，基图的核心矩阵，也就是子矩阵A和B构成的部分可以采用基图80a中的核心矩阵部分，基图的子矩阵D可以包括基图170a中第5行到第45行，第0列到第26列构成的矩阵部分中的mD行，如基图170a，相应地，基矩阵可以是包括如图17b中基矩阵170b-1的第5行至第45行中的mD行和第0行至第4行。
又一种可能的实现方式中，基图的核心矩阵可以采用基图80a中的核心矩阵部分，基图的子矩阵D部分可以包括如图12所示的基图中第5行到第45行，第0列到第26列构成的矩阵部分中的mD行，如图12所示。
可以理解的是，本申请中准正交结构并不仅仅局限于相邻两行，符合准正交结构的矩阵也可以设计为包含多个组，每个组包含至少2行，例如3行，或者4行等，每个组内包括的行是准正交的。
图5a和图5b所示的性能曲线图中，LDPC 1表示该LDPC码是基于基图30a对应的各个基矩阵编码得到的，LDPC 2表示作为对比的一种常用的LDPC码，其中横坐标表示信息比特序列的长度，单位为比特，纵坐标为符号信噪比(Es/N0)，性能曲线为BLER分别为0.01和0.0001时，LDPC 1和LDPC 2在不同信息比特序列长度下符号信噪比的性能。其中，图5a中码率R＝8/9，图5b中码率R＝1/3。可以看出在同样的BLER下，LDPC 1在 不同信息比特序列长度下的符号信噪比低于LDPC 2，也就是性能优于LDPC 2。
在本发明一实施例提供的编码方法中，编码器使用LDPC矩阵对输入序列进行编码；该LDPC矩阵的基图可以为前述示例中的任一基图，该LDPC矩阵的基矩阵HB可以为前述示例中的任一基矩阵。其中，编码器的输入序列可以是信息比特序列，也可以是至少经过下述一种处理后的信息比特序列：CRC比特添加或者填充比特添加。
进一步地，还包括：确定扩展因子Z；可以根据输入序列的长度K来确定扩展因子Z的取值。信息比特序列有时也称为码块(code block)，可以通过对传输块进行码块划分得到。若信息比特序列长度为Kc，可以在多个系统定义的扩展因子中确定满足22*Z≥Kc的最小值，例如，Kc＝3800，系统定义的扩展因子包括16，18，20，22，24，26，28，30，32，36，40，44，48，52，56，60，64，72，80，88，96，104，112，120，128，144，160，176，192，208，224，240，256，288，320，352，384，则可以确定Z为176。需要说明的是，此处只是举例，并不以此为限制。
在一种可能的设计中，可以对信息比特序列进行填充得到输入序列，使得输入序列的长度K＝Kb·Z，Z＝K/Kb。例如，可以用Null，或者取值为0，或者其他系统约定的值作为填充比特的值。经过编码后，这些填充比特能被识别出来不被发送。本发明并不以此为限制。
编码器使用LDPC矩阵H对输入序列进行编码可以是使用扩展因子Z对应的LDPC矩阵H对输入序列进行编码。
在一种可能的实现方式中，输入序列c＝{c0,c1,c2,...,cK-1}，输入序列c长度为K，输入序列c经过编码器编码后得到的输出序列d＝{d0,d1,d2,...,dN-1}，K为大于0的整数，K可以是扩展因子Z的整数倍。
其中输出序列d中包括输入序列c中的K0个比特以及校验序列w中的校验比特，K0为大于0，且小于或者等于K的整数，校验序列w的长度为N-K0，
Figure PCTCN2017092877-appb-000005
其中，校验比特序列w和输入序列c满足公式(1)：
Figure PCTCN2017092877-appb-000006
其中，cT＝[c0,c1,c2,...,cK-1]T，为输入序列中各比特组成的向量的转置向量，
Figure PCTCN2017092877-appb-000007
为校验序列中各比特组成的向量的转置向量,0T为列向量，其中所有元素的值为0。
其中H为基于前述各实施例中例举的任一基图得到的LDPC矩阵，H的基图大小为m行n列,可以是前述实施例中例举的任一基图，例如，30a，80a、170a以及图12等。
在一种设计中，H的基图中包括p列内置打孔列，p为大于或者等于0的整数，p列内置打孔列对应的信息比特不被输出，也输出序列中不包括p列内置打孔列对应的信息比特，则K0＝K-p·Z，例如，p＝2，则K0＝K-2·Z，校验序列w的长度为N+2·Z-K。若p列内置打孔列参与编码，则K0＝K，校验序列w的长度为N-K
相应地，H可以为M行(N+p·Z)列或者M行N列，其基图大小m＝M/Z，
Figure PCTCN2017092877-appb-000008
LDPC矩阵H的基图可以表示成[HBG HBG,EXT]，其中
Figure PCTCN2017092877-appb-000009
Figure PCTCN2017092877-appb-000010
表示mc×nc大小的全零矩阵，
Figure PCTCN2017092877-appb-000011
表示nc×nc大小的单位矩阵。
在一种可能的设计中，
Figure PCTCN2017092877-appb-000012
为前述各实施例基图中子矩阵C，
Figure PCTCN2017092877-appb-000013
为前述各实施例中子矩阵E，则
Figure PCTCN2017092877-appb-000014
A，B和D分别为前述各实施例基图中子矩阵A、B和D，则mc＝5，0≤nc≤41，HBG的行数小于或者等于46，且大于或者等于5，HBG的列数等于27。
在又一种可能的设计中，由于第26列为一单列重列，且其中非零元素位于第5行，因此
Figure PCTCN2017092877-appb-000015
也可以包括前述各实施例基图中第26列的前4行以及为前述各实施例中子矩阵C中的前4行，
Figure PCTCN2017092877-appb-000016
也可以包括前述各实施例中基图子矩阵E以及第26列的第5至第46行和子矩阵C的最后1行，则mc＝4，0≤nc≤42；HBG为前述各实施例基图中子矩阵A、B和D组成的部分去掉最后一列构成的矩阵，HBG的行数小于或者等于46，且大于或者等于5，HBG的列数等于26。可选地，如果需要进一步提高码率，HBG的行数可以为4行，也就是第0至3行。
相应地，LDPC矩阵H可以表示成H＝[H1 H2]。其中，
H1可以是将HBG中每个零元素替换成Z*Z大小的全零矩阵，每个非零元素替换成Z*Z大小的循环置换矩阵hi,j得到，其中循环置换矩阵hi,j是将Z*Z大小的单位矩阵循环右移Pi,j得到的，有时也用I(Pi,j)表示。其中，i是行号，j是列号，一种可能的设计中Pi,j＝mod(Vi,j,Z)，Vi,j是Z对应的扩展因子集合索引所对应的基矩阵中第i行第j列的非零元素。
H2可以是将HBG,EXT中每个零元素替换成Z*Z大小的全零矩阵，每个非零元素替换成Z*Z大小的单位矩阵得到。
编码器可以采用多种方式进行编码并输出，下面以前述实施例中例举的基图80a、170a或者图12所示基图中任一为例进行说明，其中基图行数最大为46行，列数最大为68列，包括2列内置打孔列，为了方便描述，在本发明中有时将行数最大且列数也最大的基图称为完整基图。
方式一：
基于完整基图编码，从而获取到尽可能多的校验比特。此时，m＝46，n＝68，也就是上述任一基图的第0至第45行以及第0至第67列。
相应地，对于LDPC矩阵H，M＝46·Z，如果输出序列包括内置打孔列对应的信息比特，则N＝68·Z，如果输出序列不包括除内置打孔列对应的2·Z个信息比特，则N＝66·Z。
可以在后续处理环节中从编码器产生的输出序列中确定需要发送的信息比特和校验比特。
方式二：
基于完整基图的部分行、列编码。可以根据需要发送的码率，或者，信息比特和校 验比特数等从完整基图中选择行、列编码。
例如，码率为8/9，m＝5，n＝27，也就是基于上述任一基图中第0至4行以及第0至26列的部分编码。
相应地，对于LDPC矩阵H，M＝5·Z，如果输出序列包括内置打孔列对应的信息比特，则N＝27·Z，如果输出序列不包括内置打孔列对应的信息比特，则N＝25·Z。
又例如，码率为1/3,m＝46，n＝68。
可见，这种方式下，H的基图大小为，5≤m≤46，27≤n≤68，相应地对于LDPC矩阵H,5·Z≤M≤46·Z，27·Z≤N≤68·Z。
一种可能的设计中，上述例举的任一基图中第26列为单列重列，可以对核心矩阵中单列重列进行打孔，使得核心矩阵相应减少1行和1列，从而m为4，n＝26，也就是基于上述例举的任一基图中第0至3行以及第0至25列的部分编码。这种方式可以获取到更高的码率。从而基图大小为，4≤m≤46，26≤n≤68，相应地对于LDPC矩阵H,4·Z≤M≤46·Z，26·Z≤N≤68·Z。
在上述各种实现方式中，LDPC矩阵H的基矩阵HB可以是前述各实施例中例举的任一基矩阵或者相对于前述例举的任一基矩阵而言行顺序发生变换、或者列顺序发生变换，或者行顺序和列顺序均发生变换的基矩阵，其基图至少包括子矩阵A和子矩阵B，还可以包括子矩阵C、子矩阵D和子矩阵E，各部分可以参考前述各实施例中的描述，此处不再赘述。当然也可以是其他基图符合前述各实施例所示基图的基矩阵，本发明并不限于此。
在一种可能的实现方式中，LDPC码的基矩阵HB可以是保存在存储器中，编码器获取扩展因子Z对应的LDPC矩阵，从而对输入序列进行编码。
在又一种可能的实现方式中，由于LDPC码的基矩阵HB有多个，按照矩阵结构保存会占用较大的存储空间，也可以将LDPC码的基图保存在存储器中，分别逐行或者逐列保存各基矩阵中非零元素的偏移值，然后根据基图和扩展因子Z对应的基矩阵的偏移值得到LDPC矩阵。
基图可以指示各基矩阵非零元素的位置，在又一种可能的实现方式中，保存基图可以是保存其中非零元素的位置。非零元素的位置可以通过非零元素所在的行和列指示，例如每一行中非零元素所在的列的位置，或者，每一列中非零元素所在的行的位置。在又一种可能的实现方式中，保存基图也可以是保存其中零元素的位置，同样，也可以通过零元素所在的行和列指示。例如每一行中零元素所在的列的位置，或者每一行中零元素所在的行的位置，则相应的非零元素的位置可以通过排除零元素所在的位置得到。需要说明的是，此处仅为举例，本发明并不限于此。
在一种设计中，可以对基图或者基矩阵涉及的参数使用表格来表示。例如可以在一个或多个存储器中保存相关的参数或者表格。通过读取存储器中的基图或者基矩阵的行号和非零元素所在的列等相关参数，即可获得基图或者基矩阵，可选地，还可以保存每行的行重，以及每行非零元素的偏移值。
下面以图11a为例进行说明，本申请提供的其他基图或者基矩阵可以参照类似的涉及。
例如，基图80a、基图170a或者图12的核心矩阵部分的可以使用表三来表示。
表三
Figure PCTCN2017092877-appb-000017
例如，LDPC矩阵的基图可以包括表三所示的核心部分。LDPC矩阵的基图的其他部分可以如基图80a、基图170a或者图12所示，或者本申请中描述的其他结构，或者是其他的矩阵结构，本申请并不做限定。
又例如，以基图170a为例，基图的前24行所涉及的参数可以如表四所示，其他的行类似，鉴于篇幅限制，并未在表四列出。
表四
行号 行重 非零元素所在的列
0 19 0,1,2,3,5,6,9,10,11,12,13,15,16,18,19,20,21,22,23
1 19 0,2,3,4,5,7,8,9,11,12,14,15,16,17,19,21,22,23,24
2 19 0,1,2,4,5,6,7,8,9,10,13,14,15,17,18,19,20,24,25
3 19 0,1,3,4,6,7,8,10,11,12,13,14,16,17,18,20,21,22,25
4 3 0,1,26
5 8 0,1,3,12,16,21,22,27
6 9 0,6,10,11,13,17,18,20,28
7 7 0,1,4,7,8,14,29
8 10 0,1,3,12,16,19,21,22,24,30
9 9 0,1,10,11,13,17,18,20,31
10 7 1,2,4,7,8,14,32
11 8 0,1,12,16,21,22,23,33
12 7 0,1,10,11,13,18,34
13 6 0,3,7,20,23,35
14 7 0,12,15,16,17,21,36
15 7 0,1,10,13,18,25,37
16 6 1,3,11,20,22,38
17 6 0,14,16,17,21,39
18 6 1,12,13,18,19,40
19 6 0,1,7,8,10,41
20 6 0,3,9,11,22,42
21 6 1,5,16,20,21,43
22 5 0,12,13,17,44
23 5 1,2,10,18,45
… … …
需要说明的是，此处均只是举例，并不以此为限制。本申请中提供的其他基图或者基矩阵也可以采用类似的表格来表述相关参数。可以理解，上述基图170a以及表三、表四是为了帮助理解对于基图和基矩阵的设计，其表现形式并不仅仅局限于基图170a或者表三、表四的表现形式。还可以包括其他可能的变形。
在一种实现方式中，可以通过，列号，列重非零元素所在的行，或者零元素所在的行。例如表五的形式。
表五
列号 列重 非零元素所在的行
0 5 0,1,2,3,4
1 4 0,2,3,4,
2 3 0,1,2
3 3 0,1,3
4 3 1,2,3
5 3 0,1,2
6 3 0,2,3
7 3 1,2,3
8 3 1,2,3
9 3 0,1,2
10 3 0,2,3
11 3 0,1,3
12 3 0,1,3
13 3 0,2,3
14 3 1,2,3
15 3 0,1,2
16 3 0,1,3
17 3 1,2,3
18 3 0,2,3
19 3 0,1,2
20 3 0,2,3
21 3 0,1,3
22 3 0,1,3
23 2 0,1
24 2 1，2
25 2 2,3
26 1 4
在一种实现方式中，上述表三或者表四或者表五的“行重”、“列重”这一参数也可以省略。可以通过一行非零元素所在的列或者行，获知这一行或者这一列有多少个非零元素，因此行重或者列重也就获知了。
在一种实现方式中，对于上述表三或者表四“非零元素所在的列”中的参数值，表五中，“非零元素所在的行”中的参数值，也可以不按照由小到大的顺序排列，只要参数值索引到非零元素所在的列，或者索引到非零元素所在的行就可以。
在一种实现方式中，对于表三或者表四中还可以包括“非零元素偏移值”的列，对于“非零元素偏移值”列中的参数值与“非零元素所在的列”中的参数值一一对应。表五中，也可以包括“非零元素偏移值”的列，对于“非零元素偏移值”列中的参数值与“非零元素所在的行”中的参数值一一对应。
在一种设计中，为了节省存储空间，对于基图中结构相对固定的部分，其非零元素的位置可以根据行列位置计算得到，可以不保存其中非零元素的位置。例如，子矩阵E是对角矩阵，仅在对角线上存在非零元素，可以根据行号计算得到其中非零元素所在的列的位置，也可以根据列号计算得到非零元素所在的行的位置，以基图80a、基图170a或者图12中任一基图为例，对于第me行，me≥4，其非零元素所在的列的位置为第me+Kb列，此处Kb＝22，例如，第7行中非零元素所在的列为第29列。又例如，子矩阵B中双对角结构B’位于基图80a、基图170a或者图12中任一基图中第0至3行以及第23至25列，可以根据行号计算得到其中非零元素所在的列的位置，也可以根据列号计算得到非零元素所在的行的位置，对于第mB行，若0<mB<3，该行中非零元素的位置包括第mB+Kb列，以及第mB+Kb+1列,若mB＝0或者mB＝3，该行中非零元素的位置包括第mB+Kb列；又例如，子矩阵B中单列重列，也就是基图80a、基图170a或者图12中任一基图中第26列，若mB＝4，该行中非零元素的位置包括第mB+Kb列。
如表六所示为图12中各行所涉及的参数，可以保存第0列至第25列中非零元素所在的列的位置，而不保存第26列至第68列中非零元素所在的列的位置，也就是不保存子矩阵E以及子矩阵B的单列重列中非零元素所在的列，可以用来表示列数为26的HBG：
表六
行号 行重 非零元素所在的列
0 19 0,1,2,3,5,6,9,10,11,12,13,15,16,18,19,20,21,22,23
1 19 0,2,3,4,5,7,8,9,11,12,14,15,16,17,19,21,22,23,24
2 19 0,1,2,4,5,6,7,8,9,10,13,14,15,17,18,19,20,24,25
3 19 0,1,3,4,6,7,8,10,11,12,13,14,16,17,18,20,21,22,25
4 2 0,1
5 7 0,1,3,12,16,21,22
6 8 0,6,10,11,13,17,18,20
7 6 0,1,4,7,8,14
8 9 0,1,3,12,16,19,21,22,24
9 8 0,1,10,11,13,17,18,20
10 6 1,2,4,7,8,14
11 7 0,1,12,16,21,22,23
12 6 0,1,10,11,13,18
13 5 0,3,7,20,23
14 6 0,12,15,16,17,21
15 6 0,1,10,13,18,25
16 5 1,3,11,20,22
17 5 0,14,16,17,21
18 5 1,12,13,18,19
19 5 0,1,7,8,10
20 5 0,3,9,11,22
21 5 1,5,16,20,21
22 4 0,12,13,17
23 4 1,2,10,18
24 5 0,3,4,11,22
25 4 1,6,7,14
26 4 0,2,4,15
27 3 1,6,8
28 4 0,4,19,21
29 4 1,14,18,25
30 4 0,10,13,24
31 4 1,7,22,25
32 4 0,12,14,24
33 4 1,2,11,21
34 4 0,7,15,17
35 4 1,6,12,22
36 4 0,14,15,18
37 3 1,13,23
38 4 0,9,10,12
39 4 1,3,7,19
40 3 0,8,17
41 4 1,3,9,18
42 3 0,4,24
43 4 1,16,18,25
44 4 0,7,9,22
45 3 1,6,10
如表七所示为图12中各行所涉及的参数，可以保存第0列至第26列中非零元素所在的列的位置，而不保存第27列至第68列中非零元素所在的列的位置，也就是不保存子矩阵E中非零元素所在的列，可以用来表示列数为27的HBG：
表七
行号 行重 非零元素所在的列
0 19 0,1,2,3,5,6,9,10,11,12,13,15,16,18,19,20,21,22,23
1 19 0,2,3,4,5,7,8,9,11,12,14,15,16,17,19,21,22,23,24
2 19 0,1,2,4,5,6,7,8,9,10,13,14,15,17,18,19,20,24,25
3 19 0,1,3,4,6,7,8,10,11,12,13,14,16,17,18,20,21,22,25
4 3 0,1,26
5 7 0,1,3,12,16,21,22
6 8 0,6,10,11,13,17,18,20
7 6 0,1,4,7,8,14
8 9 0,1,3,12,16,19,21,22,24
9 8 0,1,10,11,13,17,18,20
10 6 1,2,4,7,8,14
11 7 0,1,12,16,21,22,23
12 6 0,1,10,11,13,18
13 5 0,3,7,20,23
14 6 0,12,15,16,17,21
15 6 0,1,10,13,18,25
16 5 1,3,11,20,22
17 5 0,14,16,17,21
18 5 1,12,13,18,19
19 5 0,1,7,8,10
20 5 0,3,9,11,22
21 5 1,5,16,20,21
22 4 0,12,13,17
23 4 1,2,10,18
24 5 0,3,4,11,22
25 4 1,6,7,14
26 4 0,2,4,15
27 3 1,6,8
28 4 0,4,19,21
29 4 1,14,18,25
30 4 0,10,13,24
31 4 1,7,22,25
32 4 0,12,14,24
33 4 1,2,11,21
34 4 0,7,15,17
35 4 1,6,12,22
36 4 0,14,15,18
37 3 1,13,23
38 4 0,9,10,12
39 4 1,3,7,19
40 3 0,8,17
41 4 1,3,9,18
42 3 0,4,24
43 4 1,16,18,25
44 4 0,7,9,22
45 3 1,6,10
在上述设计中，行重一栏均为可选。在有一种可能的设计中，可以对于基图按照每一行或每一列的1和0视为2进制数，采用10进制或者16进制数保存可以节省存储空间。以前述任一基图为例，每行可以用4个16进制数保存前26列或者前27列非零元素的位置，例如，第0行前26列为11110110 01111101 10111111 00，则可以记为第0行非零元素的位置为0xF6，0x7D,0xBF，0x00，也就是每8列组成一个16进制数，对于其中最后2列或3列，可以通过填充0达到8位得到相应的16进制数，其他行以此类推，此处不再赘述。
对信息比特序列进行编码时，可以根据Z对基矩阵HB进行扩展得到编码的LDPC矩阵H。对基矩阵HB中每一非零元素Pi,j，确定Z*Z大小的循环置换矩阵hi,j，其中hi,j为单位矩阵经过Pi,j次循环移位得到的循环置换矩阵，将hi,j替换非零元素Pi,j，将Z*Z大小的全零矩阵替换基矩阵HB中的零元素，从而得到奇偶校验矩阵H。
在一种可能的设计中，对于扩展因子Z，其基矩阵中HB第i行第j列元素Pi,j可以满足下述(2)所示关系：
Figure PCTCN2017092877-appb-000018
其中，Vi,j可以是扩展因子Z所在集合的基矩阵中第i行第j列的元素的偏移值，或者是扩展因子Z所在集合中最大扩展因子的基矩阵的第i行第j列的非零元素的偏移值。
例如，以表二所示扩展因子Z的集合与基矩阵索引对应关系为例，Z＝13，其基矩阵中第i行第j列的元素Pi,j满足(2).
其中，Vi,j是PCM7所指示的基矩阵中第i行第j列的非零元素的偏移值。对于Z＝13而言，需要将PCM7所指示的基矩阵中第i行第j列的非零元素的偏移值Vi,j对Z＝13取模。
需要说明的是，此处仅为举例，本发明不限于此。
以基图80a或者170a为例，确定出基矩阵HB后，可以先通过输入序列和基矩阵的第0至3行以及第0至第25列，也就是Hcore-dual部分得到第22至25列对应的校验比特；再根据输入序列和Hcore-dual对应的校验比特得到第26列，也就是单列重列对应的校验比特；然后根据输入序列以及第22至26列对应的校验比特和子矩阵D对应的部分编码得到子矩阵E部分对应的校验比特，从而完成编码。LDPC码的编码过程可以参考前述实现方式描述，此处不再赘述。
在通信系统中，可采用上述方法编码后得到LDPC码。获得LDPC码后，通信装置，还可以进行以下一个或多个操作：对LDPC码进行速率匹配；根据交织方案对速率匹配后的LDPC码进行交织；根据调制方案对交织后的LDPC码进行调制得到比特序列X；发送比特序列X。
在本发明另一实施例提供的译码方法中，译码器使用LDPC矩阵对输入序列进行译码；该LDPC矩阵的基图可以为前述示例中的任一基图，该LDPC矩阵的基矩阵HB可以为前述示例中的任一基矩阵。其中，译码器的输入序列可以是LDPC码的软值序列。
进一步地，还包括：确定扩展因子Z。接收端的通信设备可以接收包含基于LDPC编码的信号，获取其中LDPC码的软值序列，并确定出相应的扩展因子Z。
译码器使用LDPC矩阵H对输入序列进行译码可以是使用扩展因子Z对应的LDPC矩阵H对LDPC码的软值序列进行译码。
由于译码是编码的逆过程，对LDPC矩阵H及其基图的描述可参见前述编码实施例。在进行译码时也可以基于完整基图进行译码，或者，基于完整基图的部分行、列译码。
其中LDPC矩阵H的基矩阵HB可以是前述各实施例中例举的任一基矩阵或者相对于前述例举的任一基矩阵而言行顺序发生变换、或者列顺序发生变换，或者行顺序和列顺序均发生变换的基矩阵，其基图至少包括子矩阵A和子矩阵B，还可以包括子矩阵C、子矩阵D和子矩阵E，各部分可以参考前述各实施例中的描述，此处不再赘述。当然也可以是其他基图符合前述各实施例所示基图的基矩阵，本发明并不限于此。
在一种可能的设计中，LDPC码的基矩阵HB可以是保存在存储器中，获取到扩展因子Z对应的LDPC矩阵可以对LDPC码的软值进行译码；
在又一种可能的实现方式中，由于LDPC码的基矩阵有多个，按照矩阵结构保存会占用较大的存储空间，也可以将LDPC码的基图保存在存储器中，分别逐行或者逐列保存各基矩阵中非零元素的偏移值，然后根据基图和扩展因子Z对应的基矩阵的偏移值得到LDPC矩阵。
基图的存储方式也可以参照前述编码实施例中所描述的各种方式存储。
需要说明的是，此处均只是举例，并不以此为限制。
译码是编码的逆过程，其使用的基矩阵HB具有与编码方法实施例中的基矩阵相同的特征。对基矩阵HB扩展得到LDPC矩阵H也可以参考编码方法实施例。
在通信系统中，所述译码方法之前，通信装置还可以进行以下一个或多个操作：接收包含基于LDPC编码的信号，对信号进行解调，解交织以及解速率匹配得到LDPC码的软值。
在一种可能的实现方式中，可以保存以下一个或多个：
a)用于获得上述各实现方式中列举的任一基矩阵HB中的参数，基于所述参数可以获得所述基矩阵HB；例如，所述参数可以包括以下一个或多个：基图和/或基矩阵的行号、行重、列号、列重、非零元素的位置，基矩阵中的偏移值、非零元素偏移值及对应的位置、补偿值、扩展因子、扩展因子的集合、或者，基矩阵的基图，或者，码率等。
b)上述各实现方式中列举的任一基矩阵HB；
c)基于所述基矩阵HB扩展后的矩阵；
d)基于上述各实现方式中列举的任一基矩阵HB经过行/列变换后的基矩阵。本申请 中，行/列变换是指行变换、或者列变换、或者行变换和列变换；
e)基于所述行/列变换后的基矩阵扩展后的矩阵。
在一种可能的实现方式中，使用低密度奇偶校验LDPC矩阵对输入序列进行编码或译码，可以是在编码或者译码过程中，按照以下方式的一种或者多种进行：
i.基于上述a)获得基矩阵HB，基于获得的基矩阵HB编码或者译码；或者基于获得的基矩阵HB进行行/列交换，基于行/列变换后的基矩阵编码或者译码。这里基于基矩阵编码或者译码，可选的，还可以包括基于基矩阵的扩展矩阵编码或者译码；
ii.基于b)或者d)保存的基矩阵(保存基矩阵HB、或者保存的基于基矩阵HB行/列变换后的基矩阵)编码或者译码，或者基于所述保存的基矩阵进行行/列变换，基于行/列变换后的基矩阵编码或者译码。这里，基于基矩阵编码或者译码，可选的，还可以包括基于基矩阵的扩展矩阵编码或者译码；
iii.基于c)或者e)进行编码或者译码。
本申请中涉及的扩展可以是基于矩阵进行变形或者加工处理获得扩展后的矩阵，对于扩展方式本申请并不做限定。在一种实现方式中，扩展可以是对矩阵进行补偿处理。例如对基矩阵中大于或等于0的各偏移值分别增加或减少补偿值，从而获得补偿矩阵。在另一种实现方式中，扩展可以是对矩阵扩展行和列，是的获得扩展后的矩阵。在又一种实现方式中，扩展可以是对矩阵的非零值进行变换处理。
本申请中涉及的保存，可以是指的保存在一个或者多个存储器中。所述一个或者多个存储器，可以是单独的设置，也可以是集成在编码器或者译码器，处理器、芯片、通信装置、或者终端。所述一个或者多个存储器，也可以是一部分单独设置，一部分集成在译码器、处理器、芯片、通信装置、或者终端中，存储器的类型可以是任意形式的存储介质，本申请并不对此限定。
图6给出了一种通信装置600的结构示意图，装置600可用于实现上述方法实施例中描述的方法，可以参见上述方法实施例中的说明。所述通信装置600可以是芯片，基站，终端或者其他网络设备。
所述通信装置600包括一个或多个处理器601。所述处理器601可以是通用处理器或者专用处理器等。例如可以是基带处理器、或中央处理器。基带处理器可以用于对通信协议以及通信数据进行处理，中央处理器可以用于对通信装置(如，基站、终端、或芯片等)进行控制，执行软件程序，处理软件程序的数据。
在一种可能的设计中，所述通信装置600包括一个或多个所述处理器601，所述一个或多个处理器601可实现上述编码器的功能，在另一种可能的设计中，上述编码器可以是所述处理器601的一部分，处理器601除了实现编码器的功能，还可以实现其他功能。
所述通信装置600使用LDPC矩阵对输入序列进行编码；该LDPC矩阵的基图可以为前述示例中的任一基图或者相对于前述例举的任一基图而言行顺序发生变换、或者列顺序发生变换，或者行顺序和列顺序均发生变换的基图，该LDPC矩阵的基矩阵HB可以为前述实施例中的任一基矩阵或者相对于前述例举的任一基矩阵而言行顺序发生变换、或者列顺序发生变换，或者行顺序和列顺序均发生变换的基矩阵。其中，编码器的输入序列可以是信息比特序列。
在一种可能的设计中，一个或多个所述处理器601可实现上述译码器的功能，在另一种可能的设计中，上述译码器可以是所述处理器601的一部分。
所述通信装置600可用于使用LDPC矩阵对输入序列进行译码；该LDPC矩阵的基图可以为前述示例中的任一基图或者相对于前述例举的任一基图而言行顺序发生变换、或者列顺序发生变换，或者行顺序和列顺序均发生变换的基图，该LDPC矩阵的基矩阵HB可以为前述示例中的任一基矩阵或者相对于前述例举的任一基矩阵而言行顺序发生变换、或者列顺序发生变换，或者行顺序和列顺序均发生变换的基矩阵。其中，译码器的输入序列可以是软值序列。
可选的一种设计中，处理器601也可以包括指令603，所述指令可以在所述处理器上被运行，使得所述通信装置600执行上述方法实施例中描述的方法。
在又一种可能的设计中，通信装置600也可以包括电路，所述电路可以实现前述方法实施例中编码器、或者译码器、或者编码器和译码器的功能。
可选的，所述通信装置600中可以包括一个或多个存储器602，其上存有指令604，所述指令可在所述处理器上被运行，使得所述通信装置600执行上述方法实施例中描述的方法。可选的，所述存储器中还可以存储有数据。可选的处理器中也可以存储指令和/或数据。所述处理器和存储器可以单独设置，也可以集成在一起。可选的，一个或多个存储器602可以存储与基矩阵相关的参数，例如偏移值，基图，基于基图扩展到矩阵、基矩阵中的各行，扩展因子等等。可选的，所述一个或者多个存储器602可以存储基矩阵或者基于基矩阵扩展到矩阵。
可选的，所述通信装置600还可以包括收发器605以及天线606。所述处理器601可以称为处理单元，对通信装置(终端或者基站)进行控制。所述收发器605可以称为收发单元、收发机、收发电路、或者收发器等，用于通过天线606实现通信装置的收发功能.
可选的，所述通信装置600还可以包括用于产生传输块CRC的器件、用于码块分割和CRC校验的器件、用于交织的交织器、或者用于调制处理的调制器等。可以通过一个或多个处理器601实现这些器件的功能。
可选的，所述通信装置600还可以包括，用于解调操作的解调器、用于解交织的解交织器、或者用于解速率匹配的器件等等。可以通过一个或多个处理器601实现这些器件的功能。
图7给出了一种通信系统700的示意图，通信系统700中包括通信设备70和通信设备71，其中，信息数据在通信设备70和通信设备71之间接收和发送。通信设备70和71可以是所述通信装置600，或者通信设备70和71分别包括通信装置600，对信息数据进行接收和发送。在一个例子中，通信设备70可以为终端，相应的通信设备71可以为基站；在另一个例子中，通信设备70为基站，相应的通信设备71可以为终端。
本领域技术任何还可以了解到本发明实施例列出的各种说明性逻辑块(illustrative logical block)和步骤(step)可以通过电子硬件、电脑软件，或两者的结合进行实现。这样的功能是通过硬件还是软件来实现取决于特定的应用和整个系统的设计要求。本领域技术人员可以对于每种特定的应用，可以使用各种方法实现所述的功能，但这种实现不应被理解为超出本发明实施例保护的范围。
本发明实施例中所描述的各种说明性的逻辑单元和电路可以通过通用处理器，数字信号处理器，专用集成电路(ASIC)，现场可编程门阵列(FPGA)或其它可编程逻辑装置，离散门或晶体管逻辑，离散硬件部件，或上述任何组合的设计来实现或操作所描述的功能。通用处理器可以为微处理器，可选地，该通用处理器也可以为任何传统的处理器、控制器、微控制器或状态机。处理器也可以通过计算装置的组合来实现，例如数字信号处理器和微处理器，多个微处理器，一个或多个微处理器联合一个数字信号处理器核，或任何其它类似的配置来实现。
本发明实施例中所描述的方法或算法的步骤可以直接嵌入硬件、处理器执行的指令、或者这两者的结合。存储器可以是RAM存储器、闪存、ROM存储器、EPROM存储器、EEPROM存储器、寄存器、硬盘、可移动磁盘、CD-ROM或本领域中其它任意形式的存储媒介。例如，存储器可以与处理器连接，以使得处理器可以从存储器中读取信息，并可以向存储器存写信息。可选地，存储器还可以集成到处理器中。处理器和存储器可以设置于ASIC中，ASIC可以设置于通信装置(如基站或终端)中。可选地，处理器和存储器也可以设置于通信装置中的不同的部件中。
通过以上的实施方式的描述，所属领域的技术人员可以清楚地了解到本发明可以用硬件实现，或固件实现，或它们的组合方式来实现。当使用软件程序实现时，可以全部或部分地以计算机程序产品的形式实现，所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机指令时，全部或部分地产生按照本发明实施例所述的流程或功能。当使用软件程序实现时，也可以将上述功能存储在计算机可读介质中或作为计算机可读介质上的一个或多个指令或代码进行传输。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一计算机可读存储介质传输。计算机可读介质包括计算机存储介质和通信介质，其中通信介质包括便于从一个地方向另一个地方传送计算机程序的任何介质。存储介质可以是计算机能够存取的任何可用介质。以此为例但不限于：计算机可读介质可以包括RAM、ROM、EEPROM、CD-ROM或其他光盘存储、磁盘存储介质或者其他磁存储设备、或者能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质。此外。任何连接可以适当的成为计算机可读介质。例如，如果软件是使用同轴电缆、光纤光缆、双绞线、数字用户线(DSL)或者诸如红外线、无线电和微波之类的无线技术从网站、服务器或者其他远程源传输的，那么同轴电缆、光纤光缆、双绞线、DSL或者诸如红外线、无线和微波之类的无线技术包括在所属介质的定义中。如本发明所使用的，盘(Disk)和碟(disc)包括压缩光碟(CD)、激光碟、光碟、数字通用光碟(DVD)、软盘和蓝光光碟，其中盘通常磁性的复制数据，而碟则用激光来光学的复制数据。上面的组合也应当包括在计算机可读介质的保护范围之内。
本申请中，“/”表示和/或的意思。例如编码/译码，表示编码、译码、或者编码和译码。
总之，以上所述仅为本发明技术方案的较佳实施例而已，并非用于限定本发明的保护范围。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (25)

  1. 一种编码方法，其特征在于，所述方法包括：
    基于低密度奇偶校验LDPC矩阵对输入序列进行编码；
    所述LDPC矩阵的基图表示为m行n列的矩阵，m为大于或者等于5的整数，n为大于或者等于27的整数；
    所述基图至少包括子矩阵A和子矩阵B，其中，
    所述子矩阵A为5行22列的矩阵；
    所述子矩阵B为5行5列的矩阵，其中，所述子矩阵B包括权重为3的列和双对角结构的子矩阵B’。
  2. 一种译码方法，其特征在于，所述方法包括：
    基于低密度奇偶校验LDPC矩阵对输入序列进行译码；
    所述LDPC矩阵的基图表示为m行n列的矩阵，m为大于或者等于5的整数，n为大于或者等于27的整数；
    所述基图至少包括子矩阵A和子矩阵B，其中，
    所述子矩阵A为5行22列的矩阵；
    所述子矩阵B为5行5列的矩阵，其中，所述子矩阵B包括一权重为3的列和双对角结构的子矩阵B’。
  3. 根据权利要求1或2所述的方法，其特征在于，所述子矩阵A中，其中1列的权重为5，1列的权重为4，20列的权重为3。
  4. 一种编码方法，其特征在于，所述方法包括：
    基于低密度奇偶校验LDPC矩阵对输入序列进行编码；
    所述LDPC矩阵的基图表示为m行n列的矩阵，m为大于或者等于5的整数，n为大于或者等于27的整数；
    所述基图至少包括子矩阵A和子矩阵B，其中，
    所述子矩阵A为5行22列的矩阵；
    所述子矩阵B为5行5列的矩阵；其中，所述子矩阵A和所述子矩阵B构成的矩阵中，其中1列的权重为5，1列的权重为4，21列的权重为3，3列的权重为2,1列的权重为1。
  5. 一种译码方法，其特征在于，所述方法包括：
    基于低密度奇偶校验LDPC矩阵对输入序列进行译码；
    所述LDPC矩阵的基图表示为m行n列的矩阵，m为大于或者等于5的整数，n为大于或者等于27的整数；
    所述基图至少包括子矩阵A和子矩阵B，其中，
    所述子矩阵A为5行22列的矩阵；
    所述子矩阵B为5行5列的矩阵；其中，所述子矩阵A和所述子矩阵B构成的矩阵中，其中1列的权重为5，1列的权重为4，21列的权重为3，3列的权重为2,1列的权重为1。
  6. 根据权利要求1至5任一项所述的方法，其特征在于，所述子矩阵A和所述子矩阵B构成的矩阵中，其中1行的权重满足大于或者等于1，且小于或者等于5，其余4行的权重分别满足大于或者等于17，且小于或者等于21。
  7. 根据权利要求1至6任一项所述的方法，其特征在于，所述子矩阵A和所述子矩阵B构成的矩阵中，其中1行的权重为3，其余4行的权重为19。
  8. 根据权利要求1至7任一项所述的方法，其特征在于，所述子矩阵A和所述子矩阵B构成的矩阵中，其中1行为：
    Figure PCTCN2017092877-appb-100001
    其余4行分别为以下各行之一：
    Figure PCTCN2017092877-appb-100002
  9. 根据权利要求1至8任一项所述的方法，其特征在于，所述子矩阵A和子矩阵B构成的矩阵包括以下矩阵中各行，或者各列：
    Figure PCTCN2017092877-appb-100003
  10. 根据权利要求1至9任一项所述的方法，其特征在于，所述基图还包括子矩阵C、子矩阵D和子矩阵E，其中，
    所述子矩阵C为5行mD列的全零矩阵；
    所述子矩阵D为mD行27列的矩阵；
    所述子矩阵E为mD行mD列的单位矩阵；
    mD为整数且0≤mD≤41。
  11. 根据权利要求1至7任一项所述的方法，其特征在于，所述子矩阵A和所述子矩阵B构成的矩阵中，其中1行为：
    Figure PCTCN2017092877-appb-100004
    其余4行分别为以下各行之一：
    Figure PCTCN2017092877-appb-100005
  12. 根据权利要求11所述的方法，其特征在于，所述子矩阵A和子矩阵B构成的矩阵包括以下矩阵中各行，或者各列：
    Figure PCTCN2017092877-appb-100006
  13. 根据权利要求1至12任一项所述的方法，其特征在于，用于编码或者译码的基图和基矩阵中至少一个是所述LDPC矩阵的基图和基矩阵中至少一个经过行交换、或者列交换、或者行交换和列交换后得到的。
  14. 一种信息处理方法，包括：
    对输入序列c＝{c0,c1,c2,...,cK-1}进行编码得到输出序列d＝{d0,d1,d2,...,dN-1}，其中K和N为大于0的整数；
    所述输出序列d包括所述输入序列c中K0个比特和校验序列w中的校验比特，K0为整数，且0<K0≤K；
    所述校验序列w和所述输入序列c满足公式
    Figure PCTCN2017092877-appb-100007
    其中，cT＝[c0,c1,c2,...,cK-1]T，为所述输入序列c中各比特组成的向量的转置向量，
    Figure PCTCN2017092877-appb-100008
    为所述校验序列w中各比特组成的向量的转置向量,0T为列向量，其所有元素的值为0；
    H为低密度奇偶校验LDPC矩阵，所述H的基图包括HBG和HBG,EXT，其中
    Figure PCTCN2017092877-appb-100009
    Figure PCTCN2017092877-appb-100010
    表示mc×nc大小的全零矩阵，
    Figure PCTCN2017092877-appb-100011
    表示nc×nc大小的单位矩阵，其中，mc＝5，0≤nc≤41，HBG的行数小于或者等于46，且大于或者等于5，HBG的列数等于27；或者，mc＝4，0≤nc≤42，HBG的行数小于或者等于46，且大于或者等于5，HBG的列数等于26。
  15. 根据权利要求14所述的方法，其特征在于，
    若所述HBG的列数等于27，各行中非零元素所在的列的位置如表七所示。
  16. 根据权利要求14所述的方法，其特征在于，
    若所述HBG的列数等于26，各行中非零元素所在的列的位置如表六所示。
  17. 一种信息处理方法，包括：
    基于LDPC矩阵的基图和扩展因子，对输入序列进行编码/译码；
    所述LDPC矩阵的基图表示为m行n列的矩阵，m为大于或者等于5的整数，n为大于或者等于27的整数；所述基图至少包括5行27列的核心矩阵；所述核心矩阵包括4行行重为19,1行行重为3的列，其中
    所述第一行重为19的行的非零元素所在的列的为0,1,2,3,5,6,9,10,11,12,13,15,16,18,19,20,21,22,以及23；
    所述第二行重为19的行的非零元素所在的列为0,2,3,4,5,7,8,9,11,12,14,15,16,17,19,21,22,23,以及24；
    所述第三行重为19的行的非零元素所在的列为0,1,2,4,5,6,7,8,9,10,13,14,15,17,18,19,20,24,以及25；
    所述第四行重为19的行的非零元素所在的列为0,1,3,4,6,7,8,10,11,12,13,14,16,17,18,20,21,22,以及25；以及
    所述行重为3的列的非零元素所在的列为0,1,26，
    上述数字为列号，其中0表示基图的第一列、1表示基图的第二列、2表示基图的第三列…23表示基图的第24列、24表示基图的第25列、25列表示基图的第26列、26列表示基图的第27列。
  18. 如权利要求17所述方法，其特征在于，包括：
    基于所述基图和偏移值获得LDPC矩阵的基矩阵；
    所述基于LDPC矩阵的基图和扩展因子，对输入序列进行编码/译码包括：
    基于所述基矩阵和扩展因子，对输入序列进行编码/译码。
  19. 一种装置，用于执行如权利要求1至18项任一项所述的方法。
  20. 一种通信装置，其特征在于，所述通信装置包括处理器、存储器以及存储在存储器上并可在处理器上运行的指令，当所述指令被运行时，使得所述通信装置执行如权利要求1至18项任一项所述的方法。
  21. 一种终端，其特征在于，包括如权利要求19所述的装置或权利要求20所述的通信装置。
  22. 一种基站，其特征在于，包括如权利要求1所述的装置或权利要求20所述的通信装置。
  23. 一种通信系统，其特征在于包括如权利要求21所述的终端以及如权利要求22所述的基站。
  24. 一种计算机可读存储介质，包括指令，当其在计算机上运行时，使得计算机执行如权利要求1至18任一项所述的方法。
  25. 一种计算机程序产品，当其在计算机上运行时，使得计算机执行权利要求1至18任一项所述的方法。
PCT/CN2017/092877 2017-05-05 2017-07-13 信息处理的方法和通信装置 WO2018201609A1 (zh)

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