WO2018201609A1 - 信息处理的方法和通信装置 - Google Patents
信息处理的方法和通信装置 Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
- H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/033—Theoretical methods to calculate these checking codes
- H03M13/036—Heuristic code construction methods, i.e. code construction or code search based on using trial-and-error
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
- H03M13/618—Shortening and extension of codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/63—Joint error correction and other techniques
- H03M13/635—Error control coding in combination with rate matching
- H03M13/6362—Error control coding in combination with rate matching by puncturing
- H03M13/6368—Error control coding in combination with rate matching by puncturing using rate compatible puncturing or complementary puncturing
- H03M13/6393—Rate compatible low-density parity check [LDPC] codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6502—Reduction of hardware complexity or efficient processing
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
- H03M13/6516—Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
Definitions
- Embodiments of the present invention relate to the field of communications, and in particular, to a method and a communication device for information processing.
- Low density parity check (LDPC) code is a kind of linear block coding with sparse check matrix, which has the characteristics of flexible structure and low decoding complexity. Because it uses a partially parallel iterative decoding algorithm, it has a higher throughput than the traditional Turbo code.
- the LDPC code can be used for the error correction code of the communication system, thereby improving the reliability and power utilization of the channel transmission.
- LDPC codes can also be widely used in space communication, optical fiber communication, personal communication systems, ADSL, and magnetic recording devices. At present, LDPC codes have been considered as one of channel coding methods in the fifth generation mobile communication.
- an LDPC matrix with special structured features can be used.
- the LDPC matrix H with special structuring features can be obtained by extending the LDPC basis matrix of a quasi-cycle (QC) structure.
- QC-LDPC is suitable for hardware with high parallelism and provides higher throughput.
- the LDPC matrix can be designed to be applied to channel coding.
- Embodiments of the present invention provide a method, a communication device, and a system for information processing, which can support encoding and decoding of information bit sequences of various lengths, and meet the flexible code length code rate requirements of the system.
- an encoding method and an encoder are provided that encode an input sequence using a low density parity check LDPC matrix.
- a decoding method and decoder are provided that decode an input sequence using a low density parity check LDPC matrix.
- the base map of the LDPC matrix is represented as a matrix of m rows and n columns, m is an integer greater than or equal to 5, and n is an integer greater than or equal to 27.
- the base map includes at least a sub-matrix A and a sub-matrix B, wherein the sub-matrix A is a matrix of 5 rows and 22 columns; the sub-matrix B is a matrix of 5 rows and 5 columns, wherein the sub-matrix B includes A column with a weight of 3 and a sub-matrix B' of a double-diagonal structure.
- one of the columns has a weight of 5
- the first column has a weight of 4
- the remaining 20 columns have a weight of 3.
- one of the columns has a weight of 3, and the three columns have a weight of 2, respectively.
- the sub-matrix B further includes one column with a weight of one.
- the base map of the LDPC matrix is represented as a matrix of m rows and n columns, m is an integer greater than or equal to 5, and n is an integer greater than or equal to 27.
- the base map includes at least a sub-matrix A and a sub-matrix B, wherein the sub-matrix A is a matrix of 5 rows and 22 columns; the sub-matrix B is a matrix of 5 rows and 5 columns; wherein the sub-matrix A and In the matrix formed by the sub-matrix B, the weight of one column is 5, the weight of one column is 4, the weight of 21 columns is 3, the weight of 3 columns is 2, and the weight of 1 column is 1.
- the weight of one row satisfies greater than or The value is equal to 1, and is less than or equal to 5, and the weights of the remaining 4 rows respectively satisfy greater than or equal to 17, and are less than or equal to 21.
- the matrix composed of the sub-matrix A and the sub-matrix B may include rows of 5 rows of matrix blocks composed of the 0th row to the 4th row and the 0th column to the 26th column in the base map 30a. Or columns, where rows can be exchanged and columns can be exchanged.
- the third row and the zeroth row of the matrix block formed by the sub-matrix A and the sub-matrix B in the base map 30a can be exchanged, the second row and the first row are exchanged, and the 23rd column and the 25th column are exchanged to obtain a basis.
- the core matrix portion in Figure 80a is the core matrix portion in Figure 80a.
- a portion of the base matrix of the LDPC matrix corresponding to the sub-matrix A and the sub-matrix B may be represented as, for example, base matrices 30b-1, 30b-2, 30b-3, 30b-4, 30b-5, 30b- 6. Any of 30b-7, 30b-8, 30b-9 or 30b-10.
- a portion of the base matrix of the LDPC matrix corresponding to the sub-matrix A and the sub-matrix B may be represented as based on the base matrix 30b-1, 30b-2, 30b-3, 30b-4, 30b-5, 30b-6, 30b-7 Any one of 30b-8, 30b-9 or 30b-10 undergoing column switching, or row switching, or row switching and column switching.
- a portion of the base matrix of the LDPC matrix corresponding to the sub-matrix A and the sub-matrix B may include base matrices 30b-1, 30b-2, 30b-3, 30b-4, 30b-5, 30b-6, 30b-7, Each row or column of any of 30b-8, 30b-9 or 30b-10.
- portions of the base matrix of the LDPC matrix corresponding to the sub-matrix A and the sub-matrix B may be represented as base matrices 80b-1, 80b-2, 80b-3, 80b-4, 80b-5, and 80b- 6, wherein 80b-4 is a matrix of 30b-3 after row and column exchange, 80b-5 is a matrix of 30b-4 after row and column exchange, and 80b-6 is a matrix of 30b-5 after row and column exchange.
- the LDPC code requires different spreading factors Z. Based on the foregoing implementation manner, in a possible implementation manner, a base matrix corresponding thereto is adopted based on different spreading factors Z.
- the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be the base matrix 30b in FIG. 3b. -1 is shown;
- the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be the base matrix 30b in FIG. 3b. -2 is shown;
- the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be as shown in FIG. 3b.
- the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be the base matrix 30b in FIG. 3b. -4 is shown;
- the portion of the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 30b-5 of FIG. 3b.
- the portion of the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 80b-1 of FIG. 8b;
- the portion of the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 80b-2 of FIG. 8b;
- the portion of the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 80b-3 of FIG. 8b;
- the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in FIG. 8b.
- the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be the base matrix 80b of FIG. 8b. -5 is shown;
- the portion of the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 80b-6 in the figure.
- the sub-matrix A may further include two columns of built-in punctured bit columns.
- a sub-matrix C, a sub-matrix D, and a sub-matrix E of corresponding sizes may be added based on the core matrix to obtain different code rates.
- the sub-matrix C is an all-zero matrix of 5 rows and m D columns;
- the sub-matrix D is a matrix of 27 rows of m D rows;
- the sub-matrix E is an identity matrix of m D rows and m D columns;
- n D is an integer and 0 ⁇ m D ⁇ 41.
- the sub-matrix D includes m D rows in the matrix F, the matrix F is 41 rows and 27 columns, and the row weights of the rows of the matrix F are 7, 7, 9, 8, 7, 7, 8, 6 respectively. ,6,5,6,5,5,6,5,5,5,5,5,4,4,4,5,4,5,4,4,4,4,3,4,4,4,4 , 3, 3, 4, 4, 3, 3, 3, 4.
- the matrix F is a matrix composed of the 5th row to the 45th row and the 0th column to the 26th column in the base map 30a.
- the offset matrix of the matrix F can be represented as any of the base matrices 30c-1, 30c-2, 30c-3, 30c-4, and 30c-5.
- lines 17 and 19 of base map 30a may be swapped, and columns 39 and 41 may be swapped to obtain base map matrix 80a as shown in Figure 8a.
- the sub-matrix D includes m D rows in the matrix F, and the m D rows may not be exchanged in rows, or one or more rows may be exchanged between rows, and the sub-matrix E is still a diagonal structure, for example, a sub-matrix
- the matrix D includes m D rows in the matrix F, wherein the 12th row and the 14th row of the matrix F are row-exchanged, and the sub-matrix E is still in a diagonal structure, thereby obtaining the base map 80a.
- the LDPC code requires different spreading factors Z.
- a base matrix corresponding thereto is adopted based on different spreading factors Z.
- the sub-matrix D in the base matrix may include m D rows of the offset matrix as shown in 30c-1;
- the sub-matrix D in the base matrix may include m D rows of the offset matrix as shown in 30c-2;
- the sub-matrix D in the base matrix may include m D rows of the offset matrix as shown in 30c-3 ;
- the sub-matrix D in the base matrix may include m D rows of the offset matrix as shown in 30c-4;
- the sub-matrix D in the base matrix may include m D rows of the offset matrix as shown in 30c-5.
- the set of spreading factors may be ⁇ 24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104 , 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, 384 ⁇ :
- the offset matrix of the matrix F may be as shown in 80c-1;
- the offset matrix of the matrix F may be as shown in 80c-2;
- the offset matrix of the matrix F may be as shown in 80c--3;
- the offset matrix of the matrix F may be as shown in 80c-4;
- the offset matrix of the matrix F may be as shown in 80c-5;
- the offset matrix of the matrix F may be as shown in 80c-6.
- the base map and base matrix of the LDPC matrix in the first implementation can satisfy the performance requirements of code blocks having a block length of 352 to 8448 bits.
- the method further includes: determining the expansion factor Z.
- the value of the spreading factor Z is determined according to the length K of the input sequence. For example, if the input sequence length is K, a minimum value satisfying 22*Z ⁇ K can be determined among a plurality of system-defined spreading factors.
- encoding the input sequence using an LDPC matrix includes:
- the input sequence is encoded using an LDPC matrix corresponding to the spreading factor Z.
- decoding the input sequence using the LDPC matrix includes:
- the input sequence is decoded using an LDPC matrix corresponding to the spreading factor Z.
- the base matrix of the LDPC matrix may be stored in a memory.
- the base map of the LDPC matrix is stored in the memory, and the offset value of the non-zero element in the base matrix of the LDPC matrix may be Saved in memory.
- At least one of the base map and the base matrix used for LDPC encoding or decoding is at least one of a base map and a base matrix of the foregoing LDPC matrix, or Column exchange, or row exchange and column exchange.
- a communication apparatus can include a module for performing any of the possible implementations of the first aspect of the method design described above.
- the module can be software and/or hardware.
- the communication device provided by the third aspect comprises the encoder, the determining unit and the processing unit according to the first aspect described above.
- the determining unit is operative to determine a spreading factor Z required to encode the input sequence.
- the processing unit is configured to encode the input sequence by using an LDPC matrix corresponding to the spreading factor Z.
- the communication device further includes a transceiver, and the transceiver is configured to send a signal corresponding to the encoded information data.
- a communication apparatus can include a module for performing any of the possible implementations of the second aspect of the method design described above.
- the module can be software and/or hardware.
- the communication device provided by the fourth aspect includes the decoder, the obtaining unit and the processing unit according to the second aspect described above.
- the obtaining unit is configured to acquire a soft value and an expansion factor Z of the LDPC code.
- the processing unit is configured to decode the soft value of the LDPC code based on the base matrix H B corresponding to the spreading factor Z to obtain an information bit sequence.
- the communication device also includes a transceiver for receiving a signal comprising an LDPC based code.
- a communication device in a fifth aspect, includes one or more processors.
- one or more of the processors may implement the functions of the encoder of the first aspect, and in another possible design, the encoder of the first aspect may be the processor In part, the processor can implement other functions in addition to the functions of the encoder described in the first aspect.
- one or more of the processors may implement the functions of the decoder of the second aspect, and in another possible design, the decoder of the second aspect may be Part of the processor.
- the communication device may further include a transceiver and an antenna.
- the communication device may further include a device for generating a transport block CRC, a device for code block splitting and CRC check, an interleaver for interleaving, a modulator for modulation processing, and the like.
- the communication device may further include a demodulator for demodulation operation, a deinterleaver for deinterleaving, a device for de-rate matching, and the like.
- a demodulator for demodulation operation e.g., a demodulator for demodulation operation
- a deinterleaver for deinterleaving e.g., a device for de-rate matching
- the functionality of these devices can be implemented by one or more processors.
- the functionality of these devices can be implemented by one or more processors.
- an embodiment of the present invention provides a communication system, including the communication device according to the above third aspect, and the communication device according to the fourth aspect.
- an embodiment of the present invention provides a communication system, where the system includes one or more communication devices according to the fifth aspect.
- an embodiment of the present invention provides a computer storage medium having stored thereon a program, and when executed, causes a computer to perform the method described in the above aspect.
- Yet another aspect of the present application provides a computer program product comprising instructions which, when run on a computer, cause the computer to perform the methods described in the various aspects above.
- the method, device, communication device and communication system of the information processing according to the embodiments of the present invention can adapt to the flexible code length code rate requirement of the system in coding performance and error leveling.
- 1 is a schematic diagram of a base map, a base matrix, and a cyclic permutation matrix of an LDPC code
- FIG. 2 is a schematic structural diagram of a base diagram of an LDPC code
- FIG. 3a is a schematic diagram of a LDPC code base diagram according to an embodiment of the present invention.
- 3b is a schematic diagram of a base matrix of an LDPC code according to another embodiment of the present invention.
- 3c is a schematic diagram of a base matrix of an LDPC code according to another embodiment of the present invention.
- FIG. 5 is a schematic diagram of performance provided by another embodiment of the present invention.
- FIG. 6 is a schematic structural diagram of an information processing apparatus according to another embodiment of the present invention.
- FIG. 7 is a schematic diagram of a communication system according to another embodiment of the present invention.
- FIG. 8a is a schematic diagram of a LDPC code base diagram according to another embodiment of the present invention.
- FIG. 8b is a schematic diagram of a base matrix of an LDPC code according to another embodiment of the present invention.
- FIG. 8c is a schematic diagram of a base matrix of an LDPC code according to another embodiment of the present invention.
- FIG. 9 is a schematic diagram of performance of an LDPC code according to an embodiment of the present invention.
- FIG. 10 is a schematic diagram of performance of an LDPC code according to an embodiment of the present invention.
- FIG. 11a is a schematic diagram of a LDPC code base diagram according to another embodiment of the present invention.
- Figure 11b is a schematic diagram of a base matrix of a base map based on the LDPC code provided in Figure 11a;
- FIG. 12 is a schematic diagram of a base diagram according to another embodiment of the present invention.
- the “communication device” may be a chip (such as a baseband chip, or a data signal processing chip, or a general purpose chip, etc.), a terminal, a base station, or other network device.
- a terminal is a device having a communication function, and may include a handheld device having a wireless communication function, an in-vehicle device, a wearable device, a computing device, or other processing device connected to a wireless modem.
- Terminals can be called different names in different networks, such as: user equipment, mobile stations, subscriber units, stations, cellular phones, personal digital assistants, wireless modems, wireless communication devices, handheld devices, laptops, cordless phones, Wireless local loop station, etc.
- a base station also referred to as a base station device, is a device deployed in a radio access network to provide wireless communication functions.
- the name of a base station may be different in different wireless access systems, for example, in a Universal Mobile Telecommunications System (UMTS) network, a base station is called a Node B, but in an LTE network.
- a base station is called an evolved Node B (eNB or eNodeB).
- eNB evolved Node B
- a base station in a new radio (NR) network is called a transmission reception point (TRP) or a next generation node B (generation node B, gNB). ), or other base stations in various networks may also use other names.
- TRP transmission reception point
- gNB next generation node B
- the invention is not limited to this.
- the LDPC code can usually be represented by a parity check matrix H.
- the parity check matrix H of the LDPC code can be obtained by a base graph and a shift value.
- the base map can usually include m*n matrix elements, which can be represented by a matrix of m rows and n columns.
- the value of the matrix element is 0 or 1, and the element with a value of 0 is sometimes called a zero element. , indicating that the element can be replaced by Z*Z's zero matrix.
- An element with a value of 1, sometimes referred to as a non-zero element indicates that the element can be a cyclic permutation matrix of Z*Z (circulant permutation) Matrix) replacement.
- each matrix element represents an all-zero matrix or a cyclic permutation matrix.
- the base and column numbers of the base map and the matrix are numbered from 0, for convenience of explanation.
- the 0th column is represented as the base map and the first column of the matrix, the first column.
- the second column, the 0th row, represented as the base map and the matrix represents the base map and the first row of the matrix, the first row is represented as the base map and the second row of the matrix, and so on.
- the line number and column number can also be numbered from 1, and the corresponding line number and column number are incremented by 1 on the basis of the line number and column number shown in this article, for example, if the line number or column number is from 1 Starting with the number, the first column represents the base column and the first column of the matrix, the second column represents the base map and the second column of the matrix, the first row represents the first row representing the base map and the matrix, and the second row represents the base map. And the second line of the matrix, and so on.
- the element value of the i-th row and the j-th column in the base map is 1, and the offset value is P i,j , P i,j is an integer greater than or equal to 0, the value of the j-th column of the i-th row is 1
- the element can be replaced by a cyclic permutation matrix of Z*Z corresponding to P i,j , which can be obtained by cyclically shifting the unit matrix of Z*Z by P i, j times to the right.
- each element with a value of 0 in the base map is replaced by an all-zero matrix of Z*Z, and each element having a value of 1 is replaced by a cyclic permutation matrix of Z*Z corresponding to its offset value,
- the parity check matrix of the LDPC code can be used to indicate the location of the offset value, and the non-zero elements in the base map correspond to the offset values.
- Z is a positive integer, which can also be called a lifting factor, sometimes called lifting size, or lifting factor, etc., which can be determined according to the code block size supported by the system and the size of the information data. It can be seen that the size of the parity check matrix H is (m*Z)*(n*Z).
- each zero element is replaced by a 4*4 size all-zero matrix 11a.
- the cyclic permutation matrix 11d is replaced by a quadrature cyclic shift of the 4*4 unit matrix 11b.
- the system usually defines a base matrix of m*n.
- Each element in the base matrix corresponds to the position of each element in the base map.
- the zero elements in the base map are in the base matrix.
- the medium position is unchanged, and is represented by -1.
- the non-zero element with the value of the jth column in the i-th row and the j-th column in the base map is unchanged in the base matrix, and can be expressed as P i,j , P i,j is greater than or equal to A positive integer of 0.
- the base matrix is sometimes referred to as an offset matrix of the base matrix.
- a base matrix corresponding to the base map 10a is shown.
- the base map or the base matrix of the LDPC code may further include a p-column built-in puncture bit string, and p may be an integer of 0-2, and these columns participate in encoding, but the system bits corresponding to the encoding are not
- R (nm)/(np)
- the LDPC code used in the wireless communication system is a QC-LDPC code, and the check bit portion has a double diagonal structure or a raptor-like structure, which can simplify coding and support incremental redundant hybrid retransmission.
- a QC-LDPC shift network QSN
- Banyan network a Banyan network
- Benes network is generally used to implement cyclic shift of information.
- a matrix of a QC-LDPC code having a raptor-like structure has a matrix size of m rows and n columns, and may generally include five sub-matrices A, B, C, D, and E, wherein the weight of the matrix is determined by a non-zero element
- row weight refers to the number of non-zero elements included in a row
- the weight of the column column The number.
- Submatrix A is a matrix of m A rows and n A columns, which may be of size M A *n A , where each column corresponds to Z systematic bits in the LDPC code, and system bits are sometimes referred to as information bits.
- the sub-matrix B is a square matrix of m A rows and m A columns, and its size may be m A *m A , and each column corresponds to Z parity bits in the LDPC code.
- the sub-matrix B includes a sub-matrix B' with a double-diagonal structure and a matrix column with a weight of 3 (referred to as a 3-column re-column), wherein the matrix column with a column weight of 3 is located before the sub-matrix B', as shown in FIG.
- the sub-matrix B may further include a matrix column having a column weight of 1 (referred to as a single column re-column), and the single-column re-column may be located in the first column or the last column of the sub-matrix B, and the non-zero elements in the sub-matrix B
- the last line causes the row of the last row of the submatrix B to have a weight of 1, as shown by 20b or 20c in FIG.
- the matrix generated based on the sub-matrices A and B is usually a core matrix and can be used to support high code rate encoding.
- the sub-matrix C is an all-zero matrix having a size of m A ⁇ (n - (m A + n A )).
- the sub-matrix E is an identity matrix having a size of (mm A ) ⁇ (mm A ).
- the submatrix D has a size of (mm A ) ⁇ (n A + m A ) and is generally used to generate a low bit rate check bit.
- the structure of the two parts of the sub-matrices A and D is one of the factors influencing the coding performance of the LDPC code.
- the matrix of the sub-matrices A and B may be encoded to obtain the parity bit corresponding to the sub-matrix B, and then The entire matrix is encoded to obtain parity bits corresponding to the E portion of the sub-matrix. Since the sub-matrix B can include the sub-matrix B' of the double-diagonal structure and a single-column re-column, the parity bits corresponding to the double-diagonal structure can be obtained first in the encoding, and the parity bits corresponding to the single-column re-column can be obtained.
- H core-dual ⁇ [S P e ] T 0, where S is an input sequence, a vector composed of information bits, P e is a vector composed of parity bits, and [S P e ] T represents The matrix transpose consisting of the input sequences S and P e .
- H core-dual H core-dual check bit corresponding to the input sequence S includes all information bits; then according to obtain H core-dual check bit corresponding to an input sequence and calculates S Obtaining the parity bits corresponding to the single column re-column in the sub-matrix B, in this case, all the parity bits corresponding to the sub-matrix B can be obtained; and then according to the input sequence S and the parity bits corresponding to the sub-matrix B, the sub-matrix D is partially encoded.
- the check bits corresponding to the sub-matrix E thus obtaining all information bits and all check bits, these bits constitute the encoded sequence, that is, an LDPC code sequence.
- the LDPC code encoding may also include shortening and puncturing operations. Both truncated bits and punctured bits are not transmitted.
- the truncation is generally truncated from the last bit of the information bit, and can be truncated in different ways.
- the truncated number of bits s 0 can be set to the last s 0 bits in the input sequence S to obtain the input sequence S', such as set to 0 or null, or some other value, and then through the LDPC matrix pair
- the input sequence S' is encoded.
- the last (s 0 mod Z) bits in the input sequence S may be set to the known bits to obtain the input sequence S', if set to 0 or null, or some other value.
- the input sequence S' is encoded using the LDPC matrix H', or the last in the submatrix A
- the column does not participate in the encoding of the input sequence S'. After the encoding is completed, the truncated bits are not sent.
- the punching may be a punching bit built in the input sequence or a punching bit.
- the last bit of the parity bit is usually punctured.
- the puncturing may be performed according to the preset puncturing order of the system.
- a possible implementation manner is that the input sequence is first encoded, and then the last p bits in the parity bit are selected according to the number of bits p to be punctured, or p bits are selected according to the system's preset puncturing order. p bits are not sent.
- the p columns of the matrix corresponding to the punctured bits and the p rows of the non-zero elements in the columns may also be determined, and the rows and columns do not participate in the coding, and the corresponding school is not generated. Check the bit.
- the decoding involved in the present application may be a plurality of decoding methods, for example, a min-sum (MS) decoding method or a belief propagation decoding method.
- MS decoding method is sometimes also referred to as a Flood MS decoding method.
- the input sequence is initialized and iteratively processed, the hard decision detection is performed after the iteration, and the hard decision result is verified. If the decoding result conforms to the check equation, the decoding is successful, the iteration is terminated, and the decision result is output. .
- the decoding mode is only an example.
- the base map and/or the base matrix provided by the present application, other decoding methods known to those skilled in the art may be used.
- the decoding method is not limited in this application.
- the LDPC code can be obtained based on the base map and the base matrix.
- the density evolution method of the base map or the base matrix can determine the upper performance limit of the LDPC code, and the error leveling layer of the LDPC code is determined according to the offset value in the base matrix. Improving the performance of the compiled code and reducing the error leveling layer is one of the goals of determining the base map and the base matrix.
- the code length in the wireless communication system is flexible, and may be a small block length code block such as 40 bits or 1280 bits, or a large block length code block such as 5000 bits 8448 bits.
- FIGS. 3a, 3b, and 3c are respectively an example of a base map and a base matrix of an LDPC code, which can satisfy the performance requirement of a block of blocks having a block length of up to 8448 bits
- FIGS. 8a, 8b, and 8c show another LDPC code.
- Base and base matrix examples Figures 11a and 11b give an example of a base and base matrix for another LDPC code.
- the column numbers and row numbers are respectively shown on the uppermost side and the leftmost side in the drawings 3a, 3b, and 3c.
- FIGS. 4 and 5 respectively show the LDPC codes shown in FIGS. 3a-3c. Schematic diagram of performance at two different code rates. Fig.
- FIG. 3a shows an example of a base map 30a of an LDPC code, in which the uppermost row 0-67 of the figure represents the column number, and the leftmost column 0-45 represents the row number, that is, the size of the base map is 46 rows and 68 columns.
- the sub-matrix A corresponds to a systematic bit, and has a size of 5 rows and 22 columns, and is composed of elements of the 0th row to the 4th row and the 0th column to the 21st column in the base map 30a;
- the sub-matrix B corresponds to a parity bit, and has a size of 5 rows and 5 columns, and is composed of elements of the 0th row to the 4th row and the 22nd column to the 26th column in the base map 30a;
- Submatrix A and submatrix B form the core matrix part of the LDPC code base map, that is, form a matrix of 5 rows and 27 columns, which can be used for high bit rate coding.
- the weight of one column is 5
- the weight of one column is 4
- the weight of 21 columns is 3
- the weight of 3 columns is 2
- the weight of 1 column is 1.
- the row weight of the last row (the fourth row) of the submatrix B and the column weight of the last column (the fourth column of the submatrix B, the 26th column of the core matrix) are both 1, and the matrix B includes 1 column and 3 columns.
- Re-column that is, column 0 of the sub-matrix B (column 22 of the core matrix) has a column weight of 3, columns 1 to 3 of the sub-matrix B (columns 23 to 25 of the core matrix), and behaviors 0 to 3 Diagonal structure.
- the core matrix of the base map 30a includes four rows of rows having a weight of 19, and one row of rows having a weight of three. That is, the weights of the rows in the core matrix composed of the submatrix A and the submatrix B are 19, 19, 19, 19, and 3, respectively. It should be noted that the order of the rows in the core matrix can be exchanged, for example, the 0th row and the 2nd row are exchanged, the 1st row and the 3rd row are exchanged, and the like.
- the row having a weight of 3 may be as shown in the fourth row of the core matrix of the base map 30a, and the columns 0 to 26; the row having the weight 19 may be the 0th to the 3rd rows in the core matrix of the base map 30a, respectively.
- the order of the 27 columns of the core matrix portion after the column exchange is given, and the column number refers to the column number of the matrix after the exchange. 0 starts numbering, and the column number before the exchange refers to the column number of the matrix listed in the matrix before the exchange.
- the row exchange does not change the weight of the columns in the matrix
- the column exchange does not change the weight of the rows in the matrix, and the number of non-zero elements in the matrix does not occur. changed.
- the weight of each row of the base map 80a after the row exchange and the column exchange does not change.
- Basemaps that use row swapping, or column swapping, or row swapping and column swapping do not affect performance.
- the performance does not affect the overall meaning, the impact is acceptable, and the tolerance is For example, performance may be degraded within a certain range for some scenarios or within certain ranges, but performance may be improved in some scenarios or within certain ranges, and overall has little effect on performance.
- the core matrix of the base map 80a still includes the columns in the core matrix of the base map 30a, and the weight of one row is 3.
- the remaining 4 lines have a weight of 19, but the order of the lines is different.
- the core matrix of the base map 30a after the column exchange still includes the columns in the core matrix of the base map 30a, 1
- the weight of the column is 5, the weight of the 1 column is 4, the weight of the 21 column is 3, the weight of the 3 column is 2, and the weight of the 1 column is 1, except that the order of the columns is different. It should be noted that this is merely an example and is not limited thereto.
- a small amount of modification to the matrix elements is acceptable for performance.
- a small number of modifications may be made based on the core matrix of the base map 30a, for example, where the weight of one row satisfies greater than or equal to 1, and is less than or equal to 5, and the weights of the remaining four rows respectively satisfy greater than or Equal to 17, and less than or equal to 21.
- 1 row has a weight of 2
- the remaining 4 rows have a weight of 18, or 1 row has a weight of 4
- the remaining 4 rows have weights of 17, 18, 19, 19, and so on. It can be understood that the weights of some of the lines may be increased or decreased by 1-2 according to the solution provided by the present application, which is not limited in this application.
- the rows with the row weight of 1 in the submatrix B are usually in the same row.
- the number of built-in punctured bit columns is 2, that is, the 0th column and the 1st column are built-in punctured bit columns, as shown in the base map 30a or 80a, in the 4th row, the 0th column and the 1st column.
- the elements are non-zero elements, the elements in columns 2 through 25 are zero elements, the elements in column 26 are non-zero elements, and the weight in row 4 is 3, not only in the core matrix, but also in the weight of the row.
- the weight of the rows in the graph matrix is also minimal. This setup improves the performance of encoding and decoding.
- the LDPC code requires different spreading factors Z.
- the spreading factor Z may comprise one or more of the following designs: 16, 18, 20, 22, 24, 26, 28, 30, 32, 36 ,40,44,48,52,56,60,64,72,80,88,96,104,112,120,128,144,160,176,192,208,224,240,256,288,320 , 352,384.
- the base matrix corresponding thereto can be adopted based on different spreading factors Z, respectively.
- An example of a plurality of base matrices of the core matrix in the base map 30a is shown in Figure 3b.
- Each base matrix is obtained based on the core matrix of the base map 30a and the spreading factor Z, wherein the non-zero elements of the i-th row and the j-th column in the base map 30a are offset values P i in the i-th row and the j-th column of the base matrix , j , the zero element in the base map 30a is represented by -1 or null in the offset matrix.
- the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be the base matrix 30b in FIG. 3b. -1 is shown;
- the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be the base matrix 30b in FIG. 3b. -2 is shown;
- the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be as shown in FIG. 3b.
- the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be the base matrix 30b in FIG. 3b. -4 is shown;
- the portion of the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 30b-5 in the figure.
- the set of spreading factors may be ⁇ 24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, 384 ⁇ :
- the portion of the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 30b-6 of FIG. 3b;
- the portion of the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 30b-7 in FIG. 3b;
- the portion of the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 30b-8 of FIG. 3b;
- the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be as shown in FIG. 3b.
- the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be the base matrix 30b in FIG. 3b. -4 is shown;
- the portion of the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 30b-5 in the figure.
- the base matrix corresponding to the base map may also be more, and the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may correspond to different Base matrix, for example:
- the portion of the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 30b-6 of FIG. 3b;
- the portion of the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 30b-7 in FIG. 3b;
- the portion of the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 30b-8 of FIG. 3b;
- the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 30b-9 or 30b-10 in FIG. 3b. ;
- the portion of the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 30b-3 in FIG. 3b;
- the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be the base matrix 30b in FIG. 3b. -4 is shown;
- the portion of the base matrix of the base map 30a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 30b-5 in the figure.
- FIG. 8b An example of a plurality of base matrices of the core matrix in the base map 80a is shown in Figure 8b.
- Each base matrix is obtained based on the core matrix of the base map 80a and the spreading factor Z, wherein the non-zero elements of the i-th row and the j-th column in the base map 80a are offset values P i in the i-th row and the j-th column of the base matrix.
- j the zero element in the base map 80a is represented by -1 or null in the offset matrix.
- the set of spreading factors may be ⁇ 24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, 384 ⁇ :
- the portion of the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 80b-1 of FIG. 8b;
- the portion of the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 80b-2 of FIG. 8b;
- the portion of the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 80b-3 of FIG. 8b;
- the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in FIG. 8b.
- the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be the base matrix 80b of FIG. 8b. -5 is shown;
- the portion of the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 80b-6 in the figure.
- the base matrix corresponding to the base map may also be more, and the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be different.
- Base matrix for example, where:
- the portion of the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 80b-1 of FIG. 8b;
- the portion of the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 80b-2 of FIG. 8b;
- the portion of the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 80b-3 of FIG. 8b;
- the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 80b-7 or 80b-8 in FIG. 8b. ;
- the portion of the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 80b-4 in FIG. 8b;
- the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be the base matrix 80b of FIG. 8b. -5 is shown;
- the portion of the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 80b-6 in the figure.
- the base matrix of the base map 80a corresponding to the sub-matrix A and the sub-matrix B may be as shown in the base matrix 80b-9 of FIG. 8b. Since the spreading factor Z can be divided in a number of ways, correspondingly, the base matrix used for a set of spreading factors Z can be combined with performance considerations.
- the value of the spreading factor Z is determined according to the length K of the input sequence. For example, if the input sequence length is K, the minimum value satisfying 22*Z ⁇ K can be determined as a matrix expansion among a plurality of system-defined spreading factors. The value of the factor. Further, the corresponding base matrix can be selected according to the determined spreading factor. As shown in Table 2, as an example of the correspondence between the base matrix and the spreading factor, a plurality of system-defined spreading factors are divided into 8 groups, that is, 8 sets, and the set indexes are 1 to 8, respectively, correspondingly, The matrix also has 8 PCM1-PCM8:
- the base matrix 80b-9 can be used as the PCM 8
- the spreading factor Z is any one of 15, 30, 60, 120, 240, 80b-9 can be used as the base matrix
- the expansion factor Z is used to expand to obtain the LDPC check matrix.
- Z is greater than or equal to 24, the base matrix 80b-9 performs relatively well.
- the rows in the base matrix are also interchangeable, and the columns can be exchanged. If the base map is exchanged by at least one of row switching or column switching, the base matrix of the corresponding portion is also exchanged the same.
- 80b-1 is a matrix after row and column exchange corresponding to 30b-6
- 80b-2 is a matrix after row and column corresponding to 30b-7
- 80b-3 is corresponding to 30b- 8 matrix after row and column exchange
- 80b-4 is the matrix after row and column corresponding to 30b-3
- 80b-5 is the matrix after row and column corresponding to 30b-4
- 80b-6 is corresponding to 30b-5
- 80b-7 is the matrix after the row and column exchange corresponding to 30b-9
- 80b-8 is the matrix after the row and column exchange corresponding to 30b-10.
- the portion of the base matrix of the LDPC matrix corresponding to the sub-matrix A and the sub-matrix B may include the base matrix 30b-1, 30b-2, 30b-3, 30b-4, 30b-5, 30b- Each row or column of any of 6, 30b-7, 30b-8, 30b-9 or 30b-10, that is, based on base matrices 30b-1, 30b-2, 30b-3, 30b-4, 30b-5 Any one of 30b-6, 30b-7, 30b-8, 30b-9 or 30b-10 undergoing column switching, or row switching, or row switching and column switching.
- sub-matrices C, sub-matrices D, and sub-matrices E of corresponding sizes may be added based on the core matrix to obtain different code rates.
- the sub-matrix C is an all-zero matrix
- the sub-matrix is an identity matrix, and its size is mainly determined according to the code rate, and the structure is relatively fixed.
- the main factors affecting the performance of the compiled code are the core matrix and the sub-matrix D part. Adding rows and columns on the basis of the core matrix to form corresponding C, D and E parts can obtain different code rates.
- the core matrix portion of the base map 30a or the core matrix portion of the base map 80a may be used as the core matrix, and corresponding sub-matrices C, D, and E are added to meet the requirements of different code rate encoding or decoding.
- the number of columns of the sub-matrix D is the sum of the number of columns of the sub-matrices A and B, and the number of rows thereof is mainly related to the code rate.
- the code rate supported by the LDPC code is R m
- the size of the base map or the base matrix Is m*n, where n n A /R m +p
- the minimum code rate R m 1/3
- a matrix F having a size of 41 rows and 27 columns can be defined, and the sub-matrix D can include the m D rows therein, and the sub-matrices A and B and the sub-matrices C and E of the corresponding sizes constitute a code rate of 22/.
- m D 41
- the sub-matrix D has a size of 41 rows and 27 columns, that is, the sub-matrix D, that is, the matrix F
- the row weights are 7, 7, 9, 8, 7, 7, 8, 6, 6, 5, 6, 5, 5, 6, 5, 5, 5, 5 , 4, 4, 4, 5, 4, 5, 4, 4, 4, 4, 3, 4, 4, 4, 4, 3, 3, 4, 4, 3, 3, 3, 4.
- the weight of each row in the base map 30a is 8, 8, 10, 9, 8, 8, 9, 7, 7, 6, 7, 6, 6, 7, 6, 6, 6,6,5,5,5,6,5,6,5,5,5,5,4,5,5,5,5,4,4,5,5,4,4,4,5.
- the two rows are orthogonal to each other.
- the matrix F may be a matrix of quasi-orthogonal structures, and in the matrix block composed of the remaining columns except the built-in punctured bit columns in the matrix F, in the same column of any two adjacent rows There is at most one non-zero element, that is, the matrix block of the matrix F except the built-in punctured bit column has an orthogonal structure.
- the matrix F is a matrix composed of the 5th row to the 45th row and the 0th column to the 26th column, wherein the 0th column and the 1st column are built-in punched bit columns, and the 5th row is In the matrix block formed by the 45th row and the 2nd column to the 26th column, the 5th row and the 6th row are orthogonal to each other, the 6th row and the 7th row are orthogonal to each other, and the 23rd row and the 24th row are orthogonal to each other.
- Lines 32 and 33 are orthogonal to each other, and so on.
- the size of the sub-matrix D in the LDPC code base map is 15 rows and 27 columns, which may be the 0-14th row of the matrix F in the base map 30a, that is, the 5th row to the 19th row of the base map 30a.
- 19 rows, the 0th column to the 41st column constitutes a matrix part, wherein the sub-matrix E is an element matrix of 15 rows and 15 columns, and the sub-matrix C is an all-zero matrix of 5 rows and 15 columns;
- the size of the sub-matrix D in the LDPC code base map is 19 rows and 27 columns, which may be from the 0th to 18th rows of the matrix F in the base map 30a, that is, the 5th to 23rd lines of the base map 30a.
- the line is formed into the matrix portion of the 23rd line, the 0th column to the 41st column, wherein the sub-matrix E is an element matrix of 19 rows and 19 columns, and the sub-matrix C is an all-zero matrix of 5 rows and 19 columns.
- the base map of the LDPC code and the rows in the base matrix can be mutually exchanged, and the columns can also be exchanged with each other.
- the 17th line and the 19th line of the base map 30a can be exchanged, and the 39th and 41st columns can be exchanged to obtain the base map matrix 80a as shown in Fig. 8a.
- the sub-matrix D includes m D rows in the matrix F. The m D rows may not be exchanged in rows, or one or more rows may be exchanged between rows, and the sub-matrix E is still a diagonal structure, and no row is performed.
- the column exchange for example, performs row swapping of the 12th row and the 14th row of the matrix F, the submatrix D includes the m D rows in the matrix F, and the submatrix E is still a diagonal structure, thereby obtaining the base map 80a.
- the matrix F is a quasi-orthogonal matrix before the row exchange, and is still a quasi-orthogonal matrix after the exchange.
- the matrix F is a matrix composed of the 5th row to the 45th row and the 0th column to the 26th column, wherein the 0th column and the 1st column are built-in punched bit columns, and the 5th column is In the matrix block formed by the 45th row and the 2nd column to the 26th column, the 5th row and the 6th row are orthogonal to each other, the 29th row and the 30th row are orthogonal to each other, and so on.
- the base map or the base matrix includes the sub-matrix D
- the columns in the corresponding sub-matrix D also need to be exchanged, for example, the 23rd column and the 25th column in the core matrix.
- the 23rd column and the 25th column of the sub-matrix D also need to be exchanged accordingly. This is for the sake of example only and is not intended to be limiting.
- the sub-matrix D satisfies the quasi-orthogonal structure, that is, the adjacent two rows of the other columns are orthogonal except for the built-in punched columns.
- the distance is orthogonal.
- the built-in punched column may also be other columns, and is not limited herein.
- the matrix F of the quasi-orthogonal structure may also include at least 2 rows of orthogonal rows, and at least 2 rows of the orthogonal rows are adjacent to the next two rows, and the columns of the 0th column to the 26th column are the most There is only one non-zero element. For example, if m D >30, the code rate supported by the corresponding LDPC code is less than 2/5, and the last 11 lines in the matrix F, that is, the 30th to 40th rows and the 0th column to the 26th column of the matrix F Sub-matrices can be orthogonal.
- the adjacent two rows in the 0th to the 29th rows of the matrix F have at most one non-zero element except the built-in punched bit column, and the adjacent two rows in the 30th to 40th rows are 0th through 26th.
- Column columns have at most one non-zero element.
- the sub-matrices formed by the 26th to 40th rows and the 0th column to the 26th column in the matrix F may be orthogonal. That is, the adjacent two rows in the 0th row to the 25th row of the matrix F have at most one non-zero element except the built-in punch bit column, and the adjacent two rows in the 26th row to the 40th row are the 0th column to the There are at most one non-zero element in each of the 26 columns. As shown in FIG.
- the base map 170a wherein the matrix F is a matrix composed of the 5th to 45th rows and the 0th column to the 26th column of the base map, the matrix F is a quasi-orthogonal structure, and the 26th line of the matrix F The 40th line is orthogonal, wherein the adjacent rows of the 26th to 40th rows have at most one non-zero element.
- the core matrix portion of the base map 170a is the same as the core matrix portion of the base map 80a.
- each row can be modified with 1-2 non-zero elements or 1-2 zero elements without affecting its performance.
- the last 21 lines in the matrix F that is, the sub-matrices formed by the 25th to 45th rows and the 0th column to the 26th column of the matrix F may be orthogonal. That is, the adjacent two rows in the 0th to the 19th rows of the matrix F have at most one non-zero element except the built-in punched bit column, and the adjacent two rows in the 20th to 40th rows are 0th through 26th. Column columns have at most one non-zero element.
- 11a is the same as the core matrix portion of the base map 80a, and the fifth row to the 45th row conform to the quasi-orthogonal structure, and it can be said that the fifth row to the 25th row conform to the quasi-orthogonal structure. Lines 25 to 45 conform to the orthogonal structure.
- the core matrix portion in the base map shown in Fig. 12 is the same as the core matrix portion in the base map 80a, and the fifth row to the 45th row conform to the quasi-orthogonal structure.
- the base matrix 30c shown in FIG. 3c is an example of a base matrix of the base map 30a, in which the non-zero elements of the i-th row and the j-th column in the base map 30a are not changed in the base matrix 30c, and the value is the offset value P i . j .
- the offset matrix corresponding to the sub-matrix D is the offset matrix of the matrix F.
- the offset matrix of the matrix F is to replace the non-zero elements of the i-th row and the j-th column in the matrix F with the offset value P i,j , and the zero elements are represented by -1 or null in the offset matrix.
- the base map is only an example, and the base map may be 80a or 180a, etc., and details are not described herein.
- the offset matrix of the matrix F may include each row or column of any one of 30c-1 to 30c-10.
- the offset matrix of the matrix F may be a matrix as shown in 30c-1, or a row of the matrix /column transformed matrix;
- the offset matrix of the matrix F may be a matrix as shown in 30c-2, or a row of the matrix /column transformed matrix;
- the offset matrix of the matrix F may be a matrix as shown in 30c-3, or a matrix after row/column transformation of the matrix;
- the offset matrix of the matrix F may be a matrix as shown in 30c-4, or a row of the matrix /column transformed matrix;
- the offset matrix of the matrix F may be a matrix as shown in 30c-5, or the row/column transformation of the matrix matrix.
- each of the base matrices corresponding to the base map 30a has a code rate of 1/3.
- the set of spreading factors may be ⁇ 24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104 , 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, 384 ⁇ :
- the offset matrix of the matrix F may be a matrix as shown in 30c-6, or a matrix after row/column transformation of the matrix;
- the offset matrix of the matrix F may be a matrix as shown in 30c-7, or a matrix after row/column transformation of the matrix;
- the offset matrix of the matrix F may be a matrix as shown in 30c-8, or a matrix after row/column transformation of the matrix;
- the offset matrix of the matrix F may be a matrix as shown in 30c-3, or the matrix The matrix after the row/column transformation;
- the offset matrix of the matrix F may be a matrix as shown in 30c-4, or a row of the matrix /column transformed matrix;
- the offset matrix of the matrix F may be a matrix as shown in 30c-5, or a matrix after row/column transformation of the matrix. .
- the offset matrix of the matrix F has more options.
- the offset matrix of the matrix F may also be a matrix such as 30c-9, or a matrix after row/column transformation of the matrix, or a matrix such as 30c-10, or a row/column transformation of the matrix.
- the matrix for example, can be designed as follows for the spreading factor:
- the offset matrix of the matrix F may be a matrix as shown in 30c-6, or a matrix after row/column transformation of the matrix;
- the offset matrix of the matrix F may be a matrix as shown in 30c-7, or a matrix after row/column transformation of the matrix;
- the offset matrix of the matrix F may be a matrix as shown in 30c-8, or a matrix after row/column transformation of the matrix;
- the offset matrix of the matrix F may be a matrix as shown in 30c-9 or 30c-10, or after the row/column transformation of the matrix Matrix
- the offset matrix of the matrix F may be a matrix as shown in 30c-3, or a matrix after row/column transformation of the matrix;
- the offset matrix of the matrix F may be a matrix as shown in 30c-4, or a row of the matrix /column transformed matrix;
- the offset matrix of the matrix F may be a matrix as shown in 30c-5, or a matrix after row/column transformation of the matrix. .
- the offset matrix of the matrix F may include each row or column of any one of 80c-1 to 80c-9.
- the set of spreading factors can be ⁇ 24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104, 112, 120, 128, 144,160,176,192,208,224,240,256,288,320,352,384 ⁇ :
- the offset matrix of the matrix F may be a matrix as shown in 80c-1, or a matrix after row/column transformation of the matrix;
- the offset matrix of the matrix F may be a matrix as shown in 80c-2, or a matrix after row/column transformation of the matrix;
- the offset matrix of the matrix F may be a matrix as shown in 80c-3, or a matrix after row/column transformation of the matrix;
- the offset matrix of the matrix F may be a matrix as shown in 80c-4, or the matrix The matrix after the row/column transformation;
- the offset matrix of the matrix F may be a matrix as shown in 80c-5, or a row of the matrix /column transformed matrix;
- the offset matrix of the matrix F may be a matrix as shown in 80c-6, or a matrix after row/column transformation of the matrix. .
- the granularity supported by the spreading factor Z may be designed to be finer, so that the offset matrix of the matrix F has more choices.
- the offset matrix of the matrix F may also be a matrix such as 80c-7, or a matrix after row/column transformation of the matrix, or a matrix such as 80c-8, or a row/column transformation of the matrix.
- the matrix for example, can be designed as follows for the spreading factor, where:
- the offset matrix of the matrix F may be a matrix as shown in 80c-1, or a matrix after row/column transformation of the matrix;
- the offset matrix of the matrix F may be a matrix as shown in 80c-2, or a matrix after row/column transformation of the matrix;
- the offset matrix of the matrix F may be a matrix as shown in 80c-3, or a matrix after row/column transformation of the matrix;
- the offset matrix of the matrix F may be a matrix as shown in 80c-7 or 80c-8, or after the row/column transformation of the matrix Matrix
- the offset matrix of the matrix F may be a matrix as shown in 80c-4, or a matrix after row/column transformation of the matrix;
- the offset matrix of the matrix F may be a matrix as shown in 80c-5, or a row of the matrix /column transformed matrix;
- the offset matrix of the matrix F may be a matrix as shown in 80c-6, or a matrix after row/column transformation of the matrix. .
- the offset matrix of the matrix F may be a matrix as shown in 80c-9, or a row of the matrix. /column transformed matrix, into In one step, when Z is greater than or equal to 24, the offset matrix of matrix F is relatively better with 80c-9 performance.
- the rows in the base matrix are also interchangeable, and the columns can be exchanged. If the base map has undergone at least one of row switching or column switching, the base matrix of the corresponding portion is also exchanged the same.
- 80c-1 is a matrix after row switching corresponding to 30c-6
- 80c-2 is a matrix after row switching corresponding to 30c-7
- 80c-3 is corresponding to 30c-
- 80c-4 is the matrix after row row corresponding to 30c-3
- 80c-5 is the matrix after row row corresponding to 30c-4
- 80c-6 is corresponding to 30c-5.
- 80c-7 is the matrix after row row corresponding to 30c-9
- 80c-8 is the matrix after row row corresponding to 30c-10.
- each of the base matrices corresponding to the base map 80a has a code rate of 1/3.
- the core matrix of the base map that is, the portion formed by the sub-matrices A and B can be used in the base map 30a.
- the core matrix portion of the base map may include the m D rows in the matrix portion formed by the 5th row to the 45th row and the 0th column to the 26th column in the base map 30a.
- the core matrix portion in the base matrix may be one of 30b-3, 30b-4, 30b-5, 30b-6, 30b-7, 30b-8, 30b-9, and 30b-10, and the sub-matrix D corresponds to
- the portion may include m D rows of any of the following matrices: 30c-3, 30c-4, 30c-5, 30c-6, 30c-7, 30c-8, 30c-9, and 30c-10.
- the core matrix and the portion corresponding to the sub-matrix D can be selected according to the spreading factor.
- the core matrix of the base map that is, the portion formed by the sub-matrices A and B may adopt the core matrix portion in the base map 80a, and the sub-matrix D of the base map may include the fifth in the base map 80a.
- the line goes to line 45, and the m D line in the matrix portion formed by the 0th column to the 26th column.
- the core matrix portion in the base matrix may be one of 80b-1, 80b-2, 80b-3, 80b-4, 80b-5, 80b-6, 80b-7, 80b-8 and 80b-9
- the portion corresponding to the sub-matrix D may include m D rows of any of the following matrices: 80c-1, 80c-2, 80c-3, 80c-4, 80c-5, 80c-6, 80c-7, 80c-8, and 80c -9.
- the core matrix and the portion corresponding to the sub-matrix D can be selected according to the spreading factor.
- the core matrix of the base map may adopt the core matrix portion in the base map 80a
- the sub-matrix D of the base map may include the fifth in the base map 170a.
- Rows to the 45th row, the 0th row to the 26th column constitute the m D row, such as the base map 170a, and accordingly, the base matrix may be the 5th row including the base matrix 170b-1 as in Fig. 17b.
- the core matrix of the base map may adopt the core matrix portion in the base map 80a, and the sub-matrix D portion of the base map may include the fifth row to the 45th row in the base map as shown in FIG.
- the m D row in the matrix portion composed of the 0th column to the 26th column is as shown in FIG.
- the quasi-orthogonal structure in the present application is not limited to only two adjacent rows, and the matrix conforming to the quasi-orthogonal structure may also be designed to include multiple groups, and each group includes at least 2 rows, for example, 3 rows. Or 4 lines, etc., the lines included in each group are quasi-orthogonal.
- LDPC 1 indicates that the LDPC code is obtained based on the respective base matrix codes corresponding to the base map 30a
- LDPC 2 indicates a commonly used LDPC code as a comparison, in which the abscissa represents The length of the information bit sequence, in bits, the ordinate is the symbol signal-to-noise ratio (Es/N0), and the performance curve is the BLER of 0.01 and 0.0001, respectively.
- an encoder uses an LDPC matrix to encode an input sequence; a base map of the LDPC matrix may be any one of the foregoing examples, and a base matrix H B of the LDPC matrix may be Any of the base matrices in the foregoing examples.
- the input sequence of the encoder may be an information bit sequence, or may be an information bit sequence processed by at least one of the following: CRC bit addition or padding bit addition.
- the method further includes: determining the expansion factor Z; determining the value of the expansion factor Z according to the length K of the input sequence.
- K K b ⁇ Z
- Z K / K b
- these padding bits can be identified and not sent.
- the invention is not limited thereto.
- the encoder encodes the input sequence using the LDPC matrix H.
- the input sequence may be encoded using the LDPC matrix H corresponding to the spreading factor Z.
- the input sequence c ⁇ c 0 , c 1 , c 2 , . . . , c K-1 ⁇
- the length of the input sequence c is K
- the input sequence c is encoded by the encoder.
- the output sequence d ⁇ d 0 , d 1 , d 2 , ..., d N-1 ⁇
- K is an integer greater than 0, and K may be an integer multiple of the spreading factor Z.
- the output sequence d includes K 0 bits in the input sequence c and check bits in the check sequence w.
- K 0 is an integer greater than 0 and less than or equal to K, and the length of the check sequence w is NK 0 .
- check bit sequence w and the input sequence c satisfy the formula (1):
- c T [c 0 ,c 1 ,c 2 ,...,c K-1 ] T
- 0 T is the column vector, where all elements have a value of zero.
- H is an LDPC matrix obtained based on any of the base diagrams exemplified in the foregoing embodiments, and the base map size of H is m rows and n columns, and may be any base diagram exemplified in the foregoing embodiment, for example, 30a. 80a, 170a, and Fig. 12, and the like.
- the base map of H includes the p-column built-in punctured column, p is an integer greater than or equal to 0, the information bits corresponding to the p-column built-in punctured column are not output, and the output sequence does not include the p-column.
- the base map of the LDPC matrix H can be expressed as [H BG H BG, EXT ], where Represents an all zero matrix of m c ⁇ n c size, An identity matrix representing the size of n c ⁇ n c .
- the 26th column is a single column and the non-zero element is located in the 5th row
- the first four rows of the twenty-sixth column in the base map of the foregoing embodiments and the first four rows of the sub-matrix C in the foregoing embodiments may also be included.
- the portion of the sub-matrix A, B, and D in the base map of the embodiment removes the matrix formed by the last column.
- the number of rows of HBG is less than or equal to 46, and is greater than or equal to 5, and the number of columns of H BG is equal to 26.
- the number of lines may be 4 H BG rows, i.e. rows of 0-3.
- H 1 may be an all-zero matrix in which each zero element in H BG is replaced by a Z*Z size, and each non-zero element is replaced by a cyclic permutation matrix h i,j of a Z*Z size, wherein the cyclic permutation matrix h i , j is obtained by cyclically shifting the unit matrix of the Z*Z size to P i,j , and sometimes by I(P i,j ).
- i is the line number and j is the column number.
- P i,j mod(V i,j ,Z)
- V i,j is the base matrix corresponding to the extension factor set index corresponding to Z.
- H 2 may be obtained by replacing each zero element in H BG, EXT with an all-zero matrix of Z*Z size, and each non-zero element is replaced by an identity matrix of Z*Z size.
- the encoder can be encoded and output in various ways.
- the following is an example of the base map 80a, 170a or the base map shown in FIG. 12 as exemplified in the foregoing embodiment, wherein the number of base map lines is up to 46 lines.
- the maximum number of columns is 68 columns, including two columns of built-in punched columns.
- the base map having the largest number of rows and the largest number of columns is sometimes referred to as a complete base map.
- the information bits and check bits that need to be transmitted can be determined from the output sequence generated by the encoder in a subsequent processing step.
- Partial row and column encoding based on the complete base map Can be sent according to the bit rate, or information bits and school The number of bits is checked, and the row and column codes are selected from the complete base map.
- the base map size of H is 5 ⁇ m ⁇ 46, 27 ⁇ n ⁇ 68, correspondingly for the LDPC matrix H, 5 ⁇ Z ⁇ M ⁇ 46 ⁇ Z, 27 ⁇ Z ⁇ N ⁇ 68 ⁇ Z.
- the base map size is 4 ⁇ m ⁇ 46, 26 ⁇ n ⁇ 68, correspondingly for the LDPC matrix H, 4 ⁇ Z ⁇ M ⁇ 46 ⁇ Z, 26 ⁇ Z ⁇ N ⁇ 68 ⁇ Z.
- the base matrix H B of the LDPC matrix H may be any of the base matrices exemplified in the foregoing embodiments or may be changed in a row order or column order with respect to any of the base matrices exemplified above.
- the description in the description will not be repeated here.
- other base patterns may be used to conform to the base matrix of the base map shown in the foregoing embodiments, and the present invention is not limited thereto.
- the base matrix H B of the LDPC code may be stored in a memory, and the encoder obtains an LDPC matrix corresponding to the spreading factor Z, thereby encoding the input sequence.
- the storage according to the matrix structure may occupy a large storage space, and the base map of the LDPC code may be stored in the memory, respectively. Or storing the offset values of the non-zero elements in each base matrix column by column, and then obtaining the LDPC matrix according to the offset values of the base matrix corresponding to the base map and the spreading factor Z.
- the base map may indicate the location of the non-zero elements of each base matrix.
- the save base map may be a location in which the non-zero elements are stored.
- the position of a non-zero element can be indicated by the row and column in which the non-zero element is located, such as the position of the column in which the non-zero element is located in each row, or the position of the row in which the non-zero element is located in each column.
- the save base map may also be a location in which the zero element is saved, and may also be indicated by the row and column in which the zero element is located.
- the position of the column in which the zero element is located in each row, or the position of the row in which the zero element is located in each row, the position of the corresponding non-zero element can be obtained by excluding the position of the zero element. It should be noted that the present invention is merely an example, and the present invention is not limited thereto.
- the parameters involved in the base or base matrix can be represented using a table.
- related parameters or tables can be saved in one or more memories.
- the base map or the base matrix can be obtained by reading the base number of the base map or the base matrix in the memory and the column where the non-zero element is located, and optionally, the row weight of each row can be saved, and each row can be saved.
- the offset value of a non-zero element can be saved.
- FIG. 11a The following is an example of FIG. 11a.
- Other base maps or base matrices provided by the present application may refer to similar references.
- the base matrix portion of the base map 80a, the base map 170a, or FIG. 12 can be represented using Table 3.
- the base map of the LDPC matrix may include the core portion shown in Table 3.
- the other parts of the base map of the LDPC matrix may be as shown in the base map 80a, the base map 170a or FIG. 12, or other structures described in the present application, or other matrix structures, which are not limited in this application.
- the parameters involved in the first 24 lines of the base map may be as shown in Table 4, and the other lines are similar, and are not listed in Table 4 due to space limitations.
- basemaps or base matrices provided in this application may also use similar tables to express relevant parameters. It can be understood that the above-mentioned base map 170a and Tables 3 and 4 are to help understand the design of the base map and the base matrix, and the representation thereof is not limited to the representations of the base map 170a or Table 3 and Table 4. Other possible variations may also be included.
- the form of Table 5 For example, the form of Table 5.
- the parameters “row weight” and “column weight” in Table 3 or Table 4 or Table 5 above may also be omitted. You can know how many non-zero elements are in this row or column by the column or row in which a non-zero element is located, so the row weight or column weight is known.
- the parameter value in the “row of the non-zero element” in Table 5 may also not be small. Arrange in a large order, as long as the parameter value is indexed to the column in which the non-zero element is located, or to the row where the non-zero element is located.
- a column of "non-zero element offset value” may also be included in Table 3 or Table 4, and a parameter value in the "non-zero element offset value” column and a column in which the non-zero element is located The parameter values in "one-to-one correspondence.
- the column of "non-zero element offset value” may also be included, and the parameter value in the "non-zero element offset value” column corresponds to the parameter value in the "non-zero element row”.
- the position of the non-zero element of the structure in the base map may be calculated according to the position of the row and column, and the position of the non-zero element may not be saved.
- the sub-matrix E is a diagonal matrix, and only non-zero elements exist on the diagonal line.
- the position of the column in which the non-zero element is located can be calculated according to the line number, and the row where the non-zero element is located can also be calculated according to the column number.
- the position of the base map 80a, the base map 170a or the base map of FIG. 12 is taken as an example.
- the position of the column where the non-zero element is located is the m e + K b column.
- K b 22
- the column in which the non-zero element in row 7 is located is the 29th column.
- the double diagonal structure B′ in the sub-matrix B is located in the base map 80a, the base map 170a, or the 0th to 3rd rows and the 23rd to 25th columns in any of the base maps in FIG. 12, and can be calculated according to the line number.
- the position of the column where the zero element is located can also calculate the position of the row where the non-zero element is located according to the column number.
- the position of the non-zero element in the row includes the mth B +K b column, and the m b + K b +1 column
- the position of the non-zero element in the row includes the m b + K b column; for example, the sub-matrix B
- the parameters involved in each row in Figure 12 can save the position of the column in which the non-zero elements in columns 0 through 25 are located, without saving the non-zero elements in columns 26 through 68.
- the position of the column that is, the column in which the non-zero elements in the single-column re-column of the sub-matrix E and the sub-matrix B are not stored, can be used to represent the H BG with a column number of 26:
- the parameters involved in each row in Figure 12 can save the position of the column in which the non-zero elements in columns 0 to 26 are located, without saving the non-zero elements in columns 27 through 68.
- the position of the column that is, the column in which the non-zero element in the sub-matrix E is not stored, can be used to represent the H BG with a column number of 27:
- each row can store the position of the first 26 columns or the first 27 columns of non-zero elements in four hexadecimal numbers.
- the first 26 columns of the 0th row are 11110110 01111101 10111111 00, then it can be recorded.
- the position of the non-zero element is 0xF6, 0x7D, 0xBF, 0x00, that is, every 8 columns constitute a hexadecimal number.
- the coded LDPC matrix H can be obtained by expanding the base matrix H B according to Z.
- a cyclic permutation matrix h i,j of Z*Z size is determined, where h i,j is a cycle obtained by cyclically shifting the unit matrix through P i, j times
- the permutation matrix replaces h i,j with a non-zero element P i,j , and replaces the zero-element in the base matrix H B with an all-zero matrix of Z*Z size, thereby obtaining a parity check matrix H.
- the H B i-th row j-th column element P i,j in the base matrix can satisfy the relationship shown in the following (2):
- V i,j may be an offset value of an element of the i-th row and the j-th column in the base matrix of the set of the expansion factor Z, or an i-th row of the base matrix of the largest spreading factor in the set of the expansion factor Z The offset value of the non-zero element of the column.
- V i,j is the offset value of the non-zero element of the i-th row and the j-th column in the base matrix indicated by the PCM 7.
- V i,j is the offset value of the non-zero element of the i-th row and the j-th column in the base matrix indicated by the PCM 7.
- the 22nd to 3rd rows and the 0th to 25th columns of the input sequence and the base matrix, that is, the H core-dual portion can be obtained first. 25 columns corresponding to the check bits; and according to the input sequence and the check bit corresponding to the H core-dual , the 26th column, that is, the parity bit corresponding to the single column re-column is obtained; and then according to the input sequence and the corresponding columns 22 to 26
- the check bit and the partial code corresponding to the sub-matrix D obtain the check bits corresponding to the E-part E, thereby completing the encoding.
- the LDPC code can be obtained by encoding by the above method.
- the communication device may perform one or more operations of performing rate matching on the LDPC code, interleaving the rate matched LDPC code according to the interleaving scheme, and modulating the interleaved LDPC code according to the modulation scheme.
- Bit sequence X transmit bit sequence X.
- a decoder decodes an input sequence by using an LDPC matrix; a base map of the LDPC matrix may be any base diagram in the foregoing example, and a base matrix of the LDPC matrix H B may be any of the base matrices in the foregoing examples.
- the input sequence of the decoder may be a soft value sequence of the LDPC code.
- the method further includes: determining an expansion factor Z.
- the communication device at the receiving end can receive the signal including the LDPC code based, obtain the soft value sequence of the LDPC code therein, and determine the corresponding spreading factor Z.
- the decoder uses the LDPC matrix H to decode the input sequence.
- the LDPC matrix H corresponding to the spreading factor Z may be used to decode the soft value sequence of the LDPC code.
- decoding is the inverse of encoding
- a description of the LDPC matrix H and its base map can be found in the aforementioned encoding embodiment. It can also be decoded based on the complete base map when decoding, or based on partial row and column decoding of the complete base map.
- the base matrix H B of the LDPC matrix H may be any of the base matrices exemplified in the foregoing embodiments or may be converted in a row order or a column order, or a row order may be changed with respect to any of the base matrices exemplified above.
- the base matrix in which the column order is transformed, the base map includes at least the sub-matrix A and the sub-matrix B, and may further include a sub-matrix C, a sub-matrix D, and a sub-matrix E.
- other base patterns may be used to conform to the base matrix of the base map shown in the foregoing embodiments, and the present invention is not limited thereto.
- the base matrix H B of the LDPC code may be stored in the memory, and the LDPC matrix corresponding to the extension factor Z may be used to decode the soft value of the LDPC code;
- the storage according to the matrix structure may occupy a large storage space, and the base map of the LDPC code may be stored in the memory, respectively, row by row or by row.
- the column holds the offset values of the non-zero elements in each base matrix, and then obtains the LDPC matrix according to the offset values of the base matrix corresponding to the base map and the spreading factor Z.
- the storage manner of the base map can also be stored in various ways as described in the foregoing encoding embodiment.
- Decoding coded reverse process which uses a base matrix H B has the same features in the base matrix of the encoding method embodiment.
- An extension of the base matrix H B to obtain the LDPC matrix H can also be referred to the coding method embodiment.
- the communication device may further perform one or more operations of: receiving a signal including LDPC encoding, demodulating, deinterleaving, and de-rate matching the signal to obtain a soft value of the LDPC code. .
- the base matrix H B being obtainable based on the parameters;
- the parameters may include one or more of the following: And/or base matrix row number, row weight, column number, column weight, position of non-zero elements, offset value in base matrix, non-zero element offset value and corresponding position, compensation value, spreading factor, extension A set of factors, or a base map of the base matrix, or a code rate, etc.
- the row/column transformation refers to a row transformation, or a column transformation, or a row transformation and a column transformation
- the input sequence is encoded or decoded using a low-density parity check LDPC matrix, which may be performed in one or more of the following manners during encoding or decoding:
- . i H B base matrix is obtained based on the above a), based on the obtained base matrix H B coding or decoding; for row / column exchange or base matrix obtained based on H B, based on the row / column of the basis matrix encoded transform or translation code.
- the base matrix based extended matrix coding or decoding may also be included;
- the extension involved in the present application may be based on matrix deformation or processing to obtain an expanded matrix, which is not limited in the application.
- the extension may be to compensate the matrix. For example, the offset values are respectively increased or decreased for each offset value greater than or equal to 0 in the base matrix, thereby obtaining a compensation matrix.
- the extension may be to extend the rows and columns to the matrix, and to obtain the expanded matrix.
- the extension may be to transform the non-zero values of the matrix.
- the preservation referred to in this application may be stored in one or more memories.
- the one or more memories may be separate settings, or may be integrated in an encoder or decoder, a processor, a chip, a communication device, or a terminal.
- the one or more memories may be separately provided in a part, and the part may be integrated in a decoder, a processor, a chip, a communication device, or a terminal.
- the type of the memory may be any form of storage medium, and the present application does not limited.
- FIG. 6 is a schematic structural diagram of a communication device 600.
- the device 600 can be used to implement the method described in the foregoing method embodiments. For details, refer to the description in the foregoing method embodiments.
- the communication device 600 can be a chip, a base station, a terminal, or other network device.
- the communication device 600 includes one or more processors 601.
- the processor 601 can be a general purpose processor or a dedicated processor or the like. For example, it can be a baseband processor, or a central processing unit.
- the baseband processor can be used to process communication protocols and communication data
- the central processor can be used to control communication devices (eg, base stations, terminals, or chips, etc.), execute software programs, and process data of the software programs.
- the communication device 600 includes one or more of the processors 601, and the one or more processors 601 can implement the functions of the encoder described above.
- the above encoder may be part of the processor 601, and the processor 601 may implement other functions in addition to the functions of the encoder.
- the communication device 600 encodes an input sequence using an LDPC matrix;
- the base map of the LDPC matrix may be any of the base diagrams in the foregoing examples or may be sequentially changed in a row order or column order with respect to any of the base diagrams exemplified above.
- a base map in which a transform occurs, or both a row order and a column order are transformed, and the base matrix H B of the LDPC matrix may be any of the base matrices in the foregoing embodiments or may occur in a row order with respect to any of the base matrices exemplified above.
- the input sequence of the encoder may be an information bit sequence.
- one or more of the processors 601 may implement the functions of the decoder described above, and in another possible design, the decoder may be part of the processor 601.
- the communication device 600 may be configured to decode an input sequence by using an LDPC matrix; the base map of the LDPC matrix may be any base map in the foregoing example or may be changed in a row order with respect to any of the base diagrams exemplified above, Alternatively, the column order may be transformed, or the base sequence in which the row order and the column order are transformed, and the base matrix H B of the LDPC matrix may be any of the base matrix in the foregoing example or relative to any of the base matrixes exemplified above. A base matrix in which the order is transformed, or the column order is transformed, or both the row order and the column order are transformed.
- the input sequence of the decoder may be a soft value sequence.
- the processor 601 can also include instructions 603 that can be executed on the processor such that the communication device 600 performs the methods described in the above method embodiments.
- the communication device 600 can also include circuitry that can implement the functions of the encoder, or decoder, or encoder and decoder in the foregoing method embodiments.
- the communication device 600 may include one or more memories 602 on which the instructions 604 are stored, and the instructions may be executed on the processor, so that the communication device 600 performs the above method embodiment.
- data may also be stored in the memory. Instructions and/or data can also be stored in the optional processor.
- the processor and the memory may be provided separately or integrated.
- the one or more memories 602 may store parameters related to the base matrix, such as offset values, base maps, extensions based on the base map to the matrix, rows in the base matrix, spreading factors, and the like.
- the one or more memories 602 may store a base matrix or extend to a matrix based on a base matrix.
- the communication device 600 may further include a transceiver 605 and an antenna 606.
- the processor 601 may be referred to as a processing unit that controls a communication device (terminal or base station).
- the transceiver 605 can be referred to as a transceiver unit, a transceiver, a transceiver circuit, or a transceiver, etc., for implementing the transceiver function of the communication device through the antenna 606.
- the communication device 600 may further include a device for generating a transport block CRC, a device for code block splitting and CRC check, an interleaver for interleaving, a modulator for modulation processing, and the like.
- a device for generating a transport block CRC a device for generating a transport block CRC
- a device for code block splitting and CRC check a device for code block splitting and CRC check
- an interleaver for interleaving
- a modulator for modulation processing and the like.
- the functionality of these devices can be implemented by one or more processors 601.
- the communication device 600 may further include a demodulator for demodulation operation, a deinterleaver for deinterleaving, a device for de-rate matching, and the like.
- a demodulator for demodulation operation e.g., a demodulator for demodulation operation
- a deinterleaver for deinterleaving e.g., a device for de-rate matching
- the functionality of these devices can be implemented by one or more processors 601.
- FIG. 7 shows a schematic diagram of a communication system 700 that includes a communication device 70 and a communication device 71, wherein the information data is received and transmitted between the communication device 70 and the communication device 71.
- the communication devices 70 and 71 may be the communication device 600, or the communication devices 70 and 71 respectively include a communication device 600 that receives and transmits information data.
- communication device 70 can be a terminal, and corresponding communication device 71 can be a base station; in another example, communication device 70 is a base station and corresponding communication device 71 can be a terminal.
- a general purpose processor may be a microprocessor.
- the general purpose processor may be any conventional processor, controller, microcontroller, or state machine.
- the processor may also be implemented by a combination of computing devices, such as a digital signal processor and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a digital signal processor core, or any other similar configuration. achieve.
- the steps of the method or algorithm described in the embodiments of the present invention may be directly embedded in hardware, instructions executed by a processor, or a combination of the two.
- the memory can be RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium in the art.
- the memory can be coupled to the processor such that the processor can read information from the memory and can write information to the memory.
- the memory can also be integrated into the processor.
- the processor and the memory may be disposed in an ASIC, and the ASIC may be disposed in a communication device such as a base station or a terminal. Alternatively, the processor and memory may also be provided in different components in the communication device.
- the present invention can be implemented in hardware, firmware implementation, or a combination thereof.
- a software program it may be implemented in whole or in part in the form of a computer program product comprising one or more computer instructions.
- the processes or functions described in accordance with embodiments of the present invention are generated in whole or in part.
- the functions described above may also be stored in or transmitted as one or more instructions or code on a computer readable medium.
- the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
- Computer readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another.
- a storage medium may be any available media that can be accessed by a computer.
- computer readable media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage media or other magnetic storage device, or can be used for carrying or storing in the form of an instruction or data structure.
- Any connection may suitably be a computer readable medium.
- a disk and a disc include a compact disc (CD), a laser disc, a compact disc, a digital versatile disc (DVD), a floppy disk, and a Blu-ray disc, wherein the disc is usually magnetically copied, and the disc is The laser is used to optically replicate the data. Combinations of the above should also be included within the scope of the computer readable media.
- encoding/decoding means encoding, decoding, or encoding and decoding.
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Abstract
Description
列号 | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 |
交换前列号 | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 9 | 11 | 12 | 13 | 14 | 15 |
列号 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 |
交换前列号 | 16 | 17 | 18 | 19 | 20 | 21 | 25 | 26 | 22 | 23 | 24 | 8 | 10 |
行号 | 行重 | 非零元素所在的列 |
0 | 19 | 0,1,2,3,5,6,9,10,11,12,13,15,16,18,19,20,21,22,23 |
1 | 19 | 0,2,3,4,5,7,8,9,11,12,14,15,16,17,19,21,22,23,24 |
2 | 19 | 0,1,2,4,5,6,7,8,9,10,13,14,15,17,18,19,20,24,25 |
3 | 19 | 0,1,3,4,6,7,8,10,11,12,13,14,16,17,18,20,21,22,25 |
4 | 3 | 0,1,26 |
5 | 8 | 0,1,3,12,16,21,22,27 |
6 | 9 | 0,6,10,11,13,17,18,20,28 |
7 | 7 | 0,1,4,7,8,14,29 |
8 | 10 | 0,1,3,12,16,19,21,22,24,30 |
9 | 9 | 0,1,10,11,13,17,18,20,31 |
10 | 7 | 1,2,4,7,8,14,32 |
11 | 8 | 0,1,12,16,21,22,23,33 |
12 | 7 | 0,1,10,11,13,18,34 |
13 | 6 | 0,3,7,20,23,35 |
14 | 7 | 0,12,15,16,17,21,36 |
15 | 7 | 0,1,10,13,18,25,37 |
16 | 6 | 1,3,11,20,22,38 |
17 | 6 | 0,14,16,17,21,39 |
18 | 6 | 1,12,13,18,19,40 |
19 | 6 | 0,1,7,8,10,41 |
20 | 6 | 0,3,9,11,22,42 |
21 | 6 | 1,5,16,20,21,43 |
22 | 5 | 0,12,13,17,44 |
23 | 5 | 1,2,10,18,45 |
… | … | … |
列号 | 列重 | 非零元素所在的行 |
0 | 5 | 0,1,2,3,4 |
1 | 4 | 0,2,3,4, |
2 | 3 | 0,1,2 |
3 | 3 | 0,1,3 |
4 | 3 | 1,2,3 |
5 | 3 | 0,1,2 |
6 | 3 | 0,2,3 |
7 | 3 | 1,2,3 |
8 | 3 | 1,2,3 |
9 | 3 | 0,1,2 |
10 | 3 | 0,2,3 |
11 | 3 | 0,1,3 |
12 | 3 | 0,1,3 |
13 | 3 | 0,2,3 |
14 | 3 | 1,2,3 |
15 | 3 | 0,1,2 |
16 | 3 | 0,1,3 |
17 | 3 | 1,2,3 |
18 | 3 | 0,2,3 |
19 | 3 | 0,1,2 |
20 | 3 | 0,2,3 |
21 | 3 | 0,1,3 |
22 | 3 | 0,1,3 |
23 | 2 | 0,1 |
24 | 2 | 1,2 |
25 | 2 | 2,3 |
26 | 1 | 4 |
行号 | 行重 | 非零元素所在的列 |
0 | 19 | 0,1,2,3,5,6,9,10,11,12,13,15,16,18,19,20,21,22,23 |
1 | 19 | 0,2,3,4,5,7,8,9,11,12,14,15,16,17,19,21,22,23,24 |
2 | 19 | 0,1,2,4,5,6,7,8,9,10,13,14,15,17,18,19,20,24,25 |
3 | 19 | 0,1,3,4,6,7,8,10,11,12,13,14,16,17,18,20,21,22,25 |
4 | 2 | 0,1 |
5 | 7 | 0,1,3,12,16,21,22 |
6 | 8 | 0,6,10,11,13,17,18,20 |
7 | 6 | 0,1,4,7,8,14 |
8 | 9 | 0,1,3,12,16,19,21,22,24 |
9 | 8 | 0,1,10,11,13,17,18,20 |
10 | 6 | 1,2,4,7,8,14 |
11 | 7 | 0,1,12,16,21,22,23 |
12 | 6 | 0,1,10,11,13,18 |
13 | 5 | 0,3,7,20,23 |
14 | 6 | 0,12,15,16,17,21 |
15 | 6 | 0,1,10,13,18,25 |
16 | 5 | 1,3,11,20,22 |
17 | 5 | 0,14,16,17,21 |
18 | 5 | 1,12,13,18,19 |
19 | 5 | 0,1,7,8,10 |
20 | 5 | 0,3,9,11,22 |
21 | 5 | 1,5,16,20,21 |
22 | 4 | 0,12,13,17 |
23 | 4 | 1,2,10,18 |
24 | 5 | 0,3,4,11,22 |
25 | 4 | 1,6,7,14 |
26 | 4 | 0,2,4,15 |
27 | 3 | 1,6,8 |
28 | 4 | 0,4,19,21 |
29 | 4 | 1,14,18,25 |
30 | 4 | 0,10,13,24 |
31 | 4 | 1,7,22,25 |
32 | 4 | 0,12,14,24 |
33 | 4 | 1,2,11,21 |
34 | 4 | 0,7,15,17 |
35 | 4 | 1,6,12,22 |
36 | 4 | 0,14,15,18 |
37 | 3 | 1,13,23 |
38 | 4 | 0,9,10,12 |
39 | 4 | 1,3,7,19 |
40 | 3 | 0,8,17 |
41 | 4 | 1,3,9,18 |
42 | 3 | 0,4,24 |
43 | 4 | 1,16,18,25 |
44 | 4 | 0,7,9,22 |
45 | 3 | 1,6,10 |
行号 | 行重 | 非零元素所在的列 |
0 | 19 | 0,1,2,3,5,6,9,10,11,12,13,15,16,18,19,20,21,22,23 |
1 | 19 | 0,2,3,4,5,7,8,9,11,12,14,15,16,17,19,21,22,23,24 |
2 | 19 | 0,1,2,4,5,6,7,8,9,10,13,14,15,17,18,19,20,24,25 |
3 | 19 | 0,1,3,4,6,7,8,10,11,12,13,14,16,17,18,20,21,22,25 |
4 | 3 | 0,1,26 |
5 | 7 | 0,1,3,12,16,21,22 |
6 | 8 | 0,6,10,11,13,17,18,20 |
7 | 6 | 0,1,4,7,8,14 |
8 | 9 | 0,1,3,12,16,19,21,22,24 |
9 | 8 | 0,1,10,11,13,17,18,20 |
10 | 6 | 1,2,4,7,8,14 |
11 | 7 | 0,1,12,16,21,22,23 |
12 | 6 | 0,1,10,11,13,18 |
13 | 5 | 0,3,7,20,23 |
14 | 6 | 0,12,15,16,17,21 |
15 | 6 | 0,1,10,13,18,25 |
16 | 5 | 1,3,11,20,22 |
17 | 5 | 0,14,16,17,21 |
18 | 5 | 1,12,13,18,19 |
19 | 5 | 0,1,7,8,10 |
20 | 5 | 0,3,9,11,22 |
21 | 5 | 1,5,16,20,21 |
22 | 4 | 0,12,13,17 |
23 | 4 | 1,2,10,18 |
24 | 5 | 0,3,4,11,22 |
25 | 4 | 1,6,7,14 |
26 | 4 | 0,2,4,15 |
27 | 3 | 1,6,8 |
28 | 4 | 0,4,19,21 |
29 | 4 | 1,14,18,25 |
30 | 4 | 0,10,13,24 |
31 | 4 | 1,7,22,25 |
32 | 4 | 0,12,14,24 |
33 | 4 | 1,2,11,21 |
34 | 4 | 0,7,15,17 |
35 | 4 | 1,6,12,22 |
36 | 4 | 0,14,15,18 |
37 | 3 | 1,13,23 |
38 | 4 | 0,9,10,12 |
39 | 4 | 1,3,7,19 |
40 | 3 | 0,8,17 |
41 | 4 | 1,3,9,18 |
42 | 3 | 0,4,24 |
43 | 4 | 1,16,18,25 |
44 | 4 | 0,7,9,22 |
45 | 3 | 1,6,10 |
Claims (25)
- 一种编码方法,其特征在于,所述方法包括:基于低密度奇偶校验LDPC矩阵对输入序列进行编码;所述LDPC矩阵的基图表示为m行n列的矩阵,m为大于或者等于5的整数,n为大于或者等于27的整数;所述基图至少包括子矩阵A和子矩阵B,其中,所述子矩阵A为5行22列的矩阵;所述子矩阵B为5行5列的矩阵,其中,所述子矩阵B包括权重为3的列和双对角结构的子矩阵B’。
- 一种译码方法,其特征在于,所述方法包括:基于低密度奇偶校验LDPC矩阵对输入序列进行译码;所述LDPC矩阵的基图表示为m行n列的矩阵,m为大于或者等于5的整数,n为大于或者等于27的整数;所述基图至少包括子矩阵A和子矩阵B,其中,所述子矩阵A为5行22列的矩阵;所述子矩阵B为5行5列的矩阵,其中,所述子矩阵B包括一权重为3的列和双对角结构的子矩阵B’。
- 根据权利要求1或2所述的方法,其特征在于,所述子矩阵A中,其中1列的权重为5,1列的权重为4,20列的权重为3。
- 一种编码方法,其特征在于,所述方法包括:基于低密度奇偶校验LDPC矩阵对输入序列进行编码;所述LDPC矩阵的基图表示为m行n列的矩阵,m为大于或者等于5的整数,n为大于或者等于27的整数;所述基图至少包括子矩阵A和子矩阵B,其中,所述子矩阵A为5行22列的矩阵;所述子矩阵B为5行5列的矩阵;其中,所述子矩阵A和所述子矩阵B构成的矩阵中,其中1列的权重为5,1列的权重为4,21列的权重为3,3列的权重为2,1列的权重为1。
- 一种译码方法,其特征在于,所述方法包括:基于低密度奇偶校验LDPC矩阵对输入序列进行译码;所述LDPC矩阵的基图表示为m行n列的矩阵,m为大于或者等于5的整数,n为大于或者等于27的整数;所述基图至少包括子矩阵A和子矩阵B,其中,所述子矩阵A为5行22列的矩阵;所述子矩阵B为5行5列的矩阵;其中,所述子矩阵A和所述子矩阵B构成的矩阵中,其中1列的权重为5,1列的权重为4,21列的权重为3,3列的权重为2,1列的权重为1。
- 根据权利要求1至5任一项所述的方法,其特征在于,所述子矩阵A和所述子矩阵B构成的矩阵中,其中1行的权重满足大于或者等于1,且小于或者等于5,其余4行的权重分别满足大于或者等于17,且小于或者等于21。
- 根据权利要求1至6任一项所述的方法,其特征在于,所述子矩阵A和所述子矩阵B构成的矩阵中,其中1行的权重为3,其余4行的权重为19。
- 根据权利要求1至9任一项所述的方法,其特征在于,所述基图还包括子矩阵C、子矩阵D和子矩阵E,其中,所述子矩阵C为5行mD列的全零矩阵;所述子矩阵D为mD行27列的矩阵;所述子矩阵E为mD行mD列的单位矩阵;mD为整数且0≤mD≤41。
- 根据权利要求1至12任一项所述的方法,其特征在于,用于编码或者译码的基图和基矩阵中至少一个是所述LDPC矩阵的基图和基矩阵中至少一个经过行交换、或者列交换、或者行交换和列交换后得到的。
- 一种信息处理方法,包括:对输入序列c={c0,c1,c2,...,cK-1}进行编码得到输出序列d={d0,d1,d2,...,dN-1},其中K和N为大于0的整数;所述输出序列d包括所述输入序列c中K0个比特和校验序列w中的校验比特,K0为整数,且0<K0≤K;
- 根据权利要求14所述的方法,其特征在于,若所述HBG的列数等于27,各行中非零元素所在的列的位置如表七所示。
- 根据权利要求14所述的方法,其特征在于,若所述HBG的列数等于26,各行中非零元素所在的列的位置如表六所示。
- 一种信息处理方法,包括:基于LDPC矩阵的基图和扩展因子,对输入序列进行编码/译码;所述LDPC矩阵的基图表示为m行n列的矩阵,m为大于或者等于5的整数,n为大于或者等于27的整数;所述基图至少包括5行27列的核心矩阵;所述核心矩阵包括4行行重为19,1行行重为3的列,其中所述第一行重为19的行的非零元素所在的列的为0,1,2,3,5,6,9,10,11,12,13,15,16,18,19,20,21,22,以及23;所述第二行重为19的行的非零元素所在的列为0,2,3,4,5,7,8,9,11,12,14,15,16,17,19,21,22,23,以及24;所述第三行重为19的行的非零元素所在的列为0,1,2,4,5,6,7,8,9,10,13,14,15,17,18,19,20,24,以及25;所述第四行重为19的行的非零元素所在的列为0,1,3,4,6,7,8,10,11,12,13,14,16,17,18,20,21,22,以及25;以及所述行重为3的列的非零元素所在的列为0,1,26,上述数字为列号,其中0表示基图的第一列、1表示基图的第二列、2表示基图的第三列…23表示基图的第24列、24表示基图的第25列、25列表示基图的第26列、26列表示基图的第27列。
- 如权利要求17所述方法,其特征在于,包括:基于所述基图和偏移值获得LDPC矩阵的基矩阵;所述基于LDPC矩阵的基图和扩展因子,对输入序列进行编码/译码包括:基于所述基矩阵和扩展因子,对输入序列进行编码/译码。
- 一种装置,用于执行如权利要求1至18项任一项所述的方法。
- 一种通信装置,其特征在于,所述通信装置包括处理器、存储器以及存储在存储器上并可在处理器上运行的指令,当所述指令被运行时,使得所述通信装置执行如权利要求1至18项任一项所述的方法。
- 一种终端,其特征在于,包括如权利要求19所述的装置或权利要求20所述的通信装置。
- 一种基站,其特征在于,包括如权利要求1所述的装置或权利要求20所述的通信装置。
- 一种通信系统,其特征在于包括如权利要求21所述的终端以及如权利要求22所述的基站。
- 一种计算机可读存储介质,包括指令,当其在计算机上运行时,使得计算机执行如权利要求1至18任一项所述的方法。
- 一种计算机程序产品,当其在计算机上运行时,使得计算机执行权利要求1至18任一项所述的方法。
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BR112019018329A BR112019018329B8 (pt) | 2017-05-05 | 2017-07-13 | Método para processamento de informação e aparelho em um dispositivo de comunicações |
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JP2019546359A JP7171590B2 (ja) | 2017-05-05 | 2017-07-13 | 情報処理方法および通信装置 |
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US16/584,911 US10924134B2 (en) | 2017-05-05 | 2019-09-26 | Apparatus and method for channel coding in communication system |
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US20060206781A1 (en) * | 2005-03-04 | 2006-09-14 | Samsung Electronics Co., Ltd. | Method for puncturing low density parity check code |
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