WO2018219025A1 - 阵列基板、电致发光显示面板及显示装置 - Google Patents

阵列基板、电致发光显示面板及显示装置 Download PDF

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Publication number
WO2018219025A1
WO2018219025A1 PCT/CN2018/079992 CN2018079992W WO2018219025A1 WO 2018219025 A1 WO2018219025 A1 WO 2018219025A1 CN 2018079992 W CN2018079992 W CN 2018079992W WO 2018219025 A1 WO2018219025 A1 WO 2018219025A1
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Prior art keywords
signal line
extension
array substrate
substrate
thickness
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PCT/CN2018/079992
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English (en)
French (fr)
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张保侠
盖翠丽
林奕呈
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京东方科技集团股份有限公司
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Priority to US16/327,042 priority Critical patent/US11538884B2/en
Publication of WO2018219025A1 publication Critical patent/WO2018219025A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/17—Passive-matrix OLED displays
    • H10K59/179—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/341—Short-circuit prevention
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/841—Self-supporting sealing arrangements

Definitions

  • the present disclosure relates to the field of display technologies, and more particularly to an array substrate, an electroluminescence display panel, and a display device.
  • OLED display panels can be divided into two types: passive matrix OLED (PMOLED) display panel and active matrix OLED (AMOLED) display panel.
  • the AMOLED display panel has pixels arranged in an array, and belongs to an active display type, and has the advantages of high luminous efficiency, high contrast, wide viewing angle, and the like, and is generally used for a high-definition large-sized display device.
  • the thickness of each film layer on the array substrate in the AMOLED display tends to be extreme, and inevitably, the resulting The quality of the insulating film layer may decrease; and the signal lines on the upper and lower surfaces of the insulating film layer respectively pass a signal having a large differential voltage, especially the voltage between the high-level voltage signal VDD and the low-level voltage signal VSS.
  • the difference is the largest, it is easy to break through the insulating film layer in the intersection area, causing a short circuit between the upper and lower signal lines, affecting the display effect.
  • An embodiment of the present disclosure provides an array substrate, including: a substrate substrate, and first signal lines, an insulating layer, and a second signal line sequentially disposed on the substrate in a direction perpendicular to the substrate; Wherein: the first signal line has a first portion and a second portion, the resistance of the first portion is higher than the resistance of the second portion, at least a portion of the first portion overlaps the second signal line and the second portion And the second signal line is non-overlapping.
  • the first portion of the first signal line includes a portion of the first signal line that completely overlaps the second signal line.
  • the first portion of the first signal line completely overlaps the second signal line.
  • the thickness of the first portion of the first signal line is less than the thickness of the second portion.
  • the thickness of the portion of the insulating layer on the first portion of the first signal line is the same as the thickness of the portion of the insulating layer on the second portion of the first signal line.
  • the first portion of the first signal line has a first extension at a portion overlapping the second signal line, and the second signal line overlaps the first signal line
  • the portion has a second extension portion extending along a width direction of the first portion, the second extension portion extending along a width direction of the second signal line; wherein the first extension portion is An orthographic projection of the second extension on the substrate substrate has an overlap region.
  • the thickness of the first extension is the same as the thickness of the portion of the first signal line that completely overlaps the second signal line.
  • the first extension and the second extension partially overlap the orthographic projection on the substrate.
  • the array substrate further includes: a metal electrode, the orthographic projection of the metal electrode on the substrate substrate at most one of a first signal line and a second signal line on the substrate The orthographic projections on the substrate overlap, and the metal electrodes are connected to the first extension or to the second extension.
  • the metal electrode is located between the layer where the first signal line is located and the insulating layer; the metal electrode is electrically connected to the first extension.
  • the metal electrode is located between the insulating layer and the layer where the second signal line is located; the metal electrode is electrically connected to the second extension.
  • the first signal line is a low level voltage signal line
  • the second signal line is a high level voltage signal line
  • An embodiment of the invention further provides an electroluminescent display panel comprising: the array substrate according to any of the preceding embodiments.
  • An embodiment of the invention further provides a display device comprising: the electroluminescent display panel according to any of the preceding embodiments.
  • FIG. 1a and 1b are respectively side views of an array substrate provided in an embodiment of the present disclosure
  • FIGS. 2a to 2d are top plan views of a first signal line and a second signal line respectively provided in an embodiment of the present disclosure
  • 3a and 3b are schematic diagrams showing positions of metal electrodes provided in an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of an electroluminescent display panel provided in an embodiment of the present disclosure.
  • An embodiment of the present disclosure provides an array substrate, as shown in FIG. 1a and FIG. 1b, which may include: a substrate substrate 01 (white filled region), and a substrate substrate 01 perpendicular to the substrate substrate a first signal line 02 (hatched fill area), an insulating layer 03 (black dot fill area), and a second signal line 04 (vertical line fill area) sequentially disposed in the direction; the first signal line 02 and the second signal line 04 Cross.
  • the first signal line 02 has a first portion 11 having a higher electrical resistance than the second portion 12, and a second portion 12 overlapping at least a portion of the first portion 11 with the second signal line 04
  • the second portion 11 and the second signal line 04 are non-overlapping.
  • the first portion 11 may include only a portion of the first signal line 02 that completely overlaps the second signal line 04 in a direction perpendicular to the substrate.
  • the first portion 11 may also include other portions such as a portion of the second signal line 02 adjacent to the portion completely overlapping the second signal line 04.
  • the orthographic projection of the portion of the first signal line 02 completely overlapping the second signal line 04 on the base substrate 01 completely falls into the orthographic projection of the second signal line 04 on the base substrate 01.
  • the resistance of the first portion 11 in the first signal line 02 may be greater than the resistance of other portions in the first signal line 02.
  • the first signal line covers the
  • the resistance of the first portion 11 of the mutually overlapping regions is set to be larger than the resistance of the non-overlapping portion (for example, the second portion 12), that is, to increase the resistance of the first signal line at the first portion, at a portion overlapping the second signal line Forming a high-resistance region, slowing the flow velocity of the current in the second signal line in the mutually overlapping regions, effectively avoiding the first signal caused by the breakdown of the insulating layer due to the moment of large current flowing in the mutually overlapping regions
  • the short circuit between the line and the second signal line effectively reduces the probability of the first signal line and the second signal line being short-circuited in the intersection area, thereby improving the quality of the display picture.
  • the range of the high resistance area is set to be larger than the area where the first signal line and the second signal line completely overlap, as shown in FIG. 1b.
  • the dashed box is shown; of course, it can also be a dashed box as shown in FIG. 1a, and the range of the high-resistance region is equal to the range in which the first signal line and the second signal line are completely overlapped, which is not limited herein.
  • a signal line for transmitting signals on an array substrate is usually made of a transparent conductive oxide such as indium tin oxide (ITO); however, it is known that ITO is used.
  • ITO indium tin oxide
  • the signal line can usually be made thicker, that is, the thickness is increased. Larger, the smaller the resistance, the better the electrical conductivity; and the thinner the thickness, the greater the electrical resistance and the poorer the electrical conductivity.
  • a plurality of signal lines for transmitting a low-level voltage are often distributed on the array substrate, and a plurality of signals are used.
  • the signal line for transmitting a high-level voltage (such as VDD) respectively provides holes and electrons for the light-emitting layer for emitting light in the array substrate, so that holes and electrons are combined after the light-emitting layer is combined to realize display; therefore, in the present
  • the first signal line 02 may be a low-level voltage signal line, that is, VSS
  • the second signal line 04 may be a high-level voltage signal line, that is, VDD.
  • the first signal line 02 and the second signal line 04 are generally adopted.
  • a transparent conductive oxide such as ITO
  • ITO transparent conductive oxide
  • the thickness of the first portion 11 of the first signal line is smaller than the thickness of the second portion 12 of the first signal line; by thinning the thickness of the first portion 11 of the first signal line 02, the first signal line 02 is increased.
  • the thickness of the insulating layer is generally uniformly disposed, that is, the thickness is consistent; therefore, provided in the embodiment of the present disclosure
  • the thickness of the portion of the insulating layer on the first portion of the first signal line is the same as the thickness of the portion of the insulating layer on the second portion of the first signal line.
  • the thickness of the insulating layer 03 is kept uniform.
  • a snubber capacitor may be formed in the mutually overlapping regions to slow down the flow of the current.
  • the first portion of the first signal line has a first extension at a portion overlapping the second signal line
  • the second signal line has a portion overlapping the first signal line.
  • Second extension extends in a width direction of the first portion
  • the second extension portion extends in a width direction of the second signal line.
  • the thickness of the first extension portion is the same as the thickness of a portion of the first signal line that completely overlaps the second signal line.
  • the position of the insulating layer is not shown in the figure, and the first extension portion of the first portion 11 of the first signal line 02 may have one (eg The first extension portion 02a) shown in FIG. 2a may also be two (the first extension portion 02a and the first extension portion 02b as shown in FIGS. 2b to 2d); and the first extension portion (including the first portion)
  • the shape of the extending portion 02a and the first extending portion 02b) may be square (as shown in FIGS. 2a to 2d), and may be semi-circular or triangular. Of course, other shapes may be used, which are not limited herein.
  • the second extension of the second signal line 04 at the portion overlapping the first signal line may also be one (the second extension 04a as shown in FIG. 2a). ), which may also be two (such as the second extension portion 04a and the second extension portion 04b shown in FIGS. 2b to 2d); and, for example, the second extension portion (including the second extension portion 04a and the second extension portion)
  • the shape of 04b) may be the same as the shape of the first extension (as shown in FIGS. 2a to 2d), and may also be different from the shape of the first extension as long as the first extension and the second extension are on the substrate.
  • a snubber capacitor may be formed, which is not limited herein.
  • the relationship of the first extension portion and the second extension portion may be as shown in FIGS. 2a to 2d, wherein the first extension portion (including the first extension portion 02a and the first extension portion 02b) is on the base substrate
  • the orthographic projection may have a partial overlap with the orthographic projection of the second extension (including the second extension 04a and the second extension 04b) on the substrate, as shown in Figures 2a and 2b; of course, the first extension
  • the orthographic projection on the base substrate (including the first extension portion 02a and the first extension portion 02b) may also be completely on the base substrate by the second extension portion (including the second extension portion 04a and the second extension portion 04b) Orthographic projection, as shown in Figure 2c; of course, the orthographic projection of the first extension (including the first extension 02a and the first extension 02b) on the base substrate may also completely surround the second extension (including the second The orthographic projection of the extension portion 04a and the second extension portion 04b) on the substrate substrate is as shown in FIG. 2d; specifically, it may be designed accordingly according
  • a snubber capacitor can be formed between the first extension portion and the second extension portion, so that the current in the second signal line can be slowed down in the intersection region.
  • Speed reducing the probability that the first signal line and the second signal line are short-circuited in the intersection region; however, the formation of the snubber capacitor invisibly increases the area of the overlapping area of the first signal line and the second signal line, thereby increasing the current flow
  • the area which actually has a certain conflict with the role of the high-resistance zone; in order to avoid such conflicts, and to fully utilize the role of the high-resistance zone and the snubber capacitor, it is necessary to thin the first signal line in the intersection area.
  • the degree, and the area of the snubber capacitor are simulated to obtain an optimal solution to finally reduce the probability of the first signal line and the second signal line being short-circuited in the intersection area; therefore, the first signal line is required in the intersection area.
  • the degree of thinning and the area of the snubber capacitor are not specifically limited herein.
  • the resistance is large, and the current is likely to cause a large voltage drop, which affects the light-emitting effect.
  • a metal electrode can be fabricated on the surface of the first signal line or the second signal line to reduce the voltage drop as an auxiliary electrode; and at the same time, in order not to affect the high resistance region and the snubber capacitor is slowed down.
  • the array substrate may further include: a metal disposed outside the overlapping regions and the overlapping regions An electrode (ie, an orthographic projection of the metal electrode on the substrate substrate at most overlaps with an orthographic projection of one of the first signal line 02 and the second signal line 04 on the substrate substrate, Alternatively, the orthographic projection of the metal electrode on the substrate may overlap with the orthographic projection of the first signal line 02 on the substrate, or may be on the substrate with the second signal line 04.
  • the positive projection overlaps, or may not overlap with the orthographic projection of the first signal line 02 and the second signal line 04 on the substrate, and the metal electrode is connected to the first extension or to the second extension;
  • the metal electrode can be generally located in a non-intersection region, a non-overlapping region, and a non-overlapping region of the second extension portion 04a and the first signal line 02, that is, the metal electrode can be located at a position shown in a broken line frame.
  • the action of the metal electrodes can be realized so that mutual interference does not occur between them.
  • the metal electrode may be disposed between the layer where the first signal line is located and the layer where the second signal line is located (for example, where the first signal line is located and the second signal line is located) a film layer between the layers) and electrical connection with the first signal line or the second signal line according to a specific position; wherein the metal electrode 05 is located between the layer where the first signal line 02 is located and the insulating layer 03 ( For example, when the film layer between the layer where the first signal line 02 is located and the insulating layer 03); as shown in FIG. 3a, the metal electrode 05 (black filled region) is electrically connected to the first extension portion 02a.
  • the metal electrode 05 is located between the layer where the insulating layer 03 and the second signal line 04 are located (for example, a film between the layer where the insulating layer 03 and the second signal line 04 are located).
  • the metal electrode 05 black filled region is electrically connected to the second extension portion 04a.
  • the metal electrode is not limited to the film layer disposed between the layer where the first signal line is located and the layer where the second signal line is located, and may be disposed at other positions according to actual needs, which is not limited herein.
  • an embodiment of the present disclosure further provides an electroluminescent display panel, as shown in FIG. 4, which may include: the array substrate 401 provided in the embodiment of the present disclosure, and may further include an array substrate
  • the substrate 402 is packaged.
  • the array substrate 401 can be fixed to the package substrate 402 by, for example, glue bonding or mechanical connectors.
  • an embodiment of the present disclosure further provides a display device, which may include the above electroluminescent display panel as provided by an embodiment of the present disclosure.
  • the display device may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • Embodiments of the present disclosure provide an array substrate, an electroluminescence display panel, and a display device, the array substrate including: a substrate substrate, and first signal lines, an insulating layer, and a second signal line sequentially disposed on the substrate substrate And the first signal line has a first portion and a second portion, the resistance of the first portion being higher than the resistance of the second portion, at least a portion of the first portion overlapping the second signal line and second The portion is non-overlapping with the second signal line; in order to prevent the first signal line and the second signal line located on the upper and lower surfaces of the insulating layer from being short-circuited in mutually overlapping regions, the first signal line may be covered in the mutual The resistance of the first portion of the stacked region is set to be greater than the resistance of the overlapping portion, that is, the resistance of the first signal line in the mutually overlapping regions is increased, and a high resistance region is formed in the mutually overlapping regions to slow down the second signal The velocity of the current in the line in the mutually overlapping regions

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板、电致发光显示面板及显示装置，该阵列基板包括：衬底基板（01）、以及在所述衬底基板（01）上在垂直于衬底基板（01）的方向上依次设置的第一信号线（02）、绝缘层（03）和第二信号线（04）；其中，所述第一信号线（02）具有第一部分（11）和第二部分（12），所述第一部分（11）的电阻高于第二部分（12）的电阻，所述第一部分（11）的至少一部分与所述第二信号线（04）交叠而第二部分（12）与所述第二信号线（04）是非交叠的。

Description

阵列基板、电致发光显示面板及显示装置
相关申请的交叉引用
本申请要求于2017年6月2日递交中国专利局的、申请号为201720633454.1的中国专利申请的权益，该申请的全部内容以引用方式并入本文。
技术领域
本公开涉及显示技术领域，尤指一种阵列基板、电致发光显示面板及显示装置。
背景技术
有机发光二极管(Organic Light Emitting Display,OLED)显示面板按照驱动方式可以分为无源矩阵型OLED(Passive Matrix OLED,PMOLED)显示面板和有源矩阵型OLED(Active Matrix OLED,AMOLED)显示面板两大类，其中，AMOLED显示面板具有呈阵列式排布的像素，属于主动显示类型，具有发光效能高、对比度高、视角宽等优点，通常被用于高清晰的大尺寸显示装置。
然而，随着显示器的集成化和超薄化的发展，使得位于AMOLED显示器中阵列基板上的各膜层的厚度，尤其是绝缘膜层的厚度，也趋向于极限，不可避免地，制作得到的绝缘膜层的质量会有所下降；而位于绝缘膜层上下表面信号线在分别通入压差较大的信号时，尤其是高电平电压信号VDD和低电平电压信号VSS之间的压差最大，很容易击穿位于交叉区域的绝缘膜层，导致上下信号线之间发生短路，影响显示效果。
公开内容
本公开实施例提供了一种阵列基板，包括：衬底基板、以及在所述衬底基板上在垂直于衬底基板的方向上依次设置的第一信号线、绝缘层和第二信号线；其中：所述第一信号线具有第一部分和第二部分，所述第一部分的电阻高于第二部分的电阻，所述第一部分的至少一部分与所述第二信号线交叠而第二部分与所述第二信号线是非交叠的。
在一实施例中，所述第一信号线的第一部分包括第一信号线的与所述第二信号线完全交叠的部分。
在一实施例中，所述第一信号线的第一部分与所述第二信号线完全交叠。
在一实施例中，所述第一信号线的第一部分的厚度小于第二部分的厚度。
在一实施例中，所述绝缘层在位于所述第一信号线的第一部分上的部位的厚度与所述绝缘层在位于所述第一信号线的第二部分上的部位的厚度相同。
在一实施例中，所述第一信号线的第一部分在与所述第二信号线交叠的部位具有第一延伸部，所述第二信号线在与所述第一信号线交叠的部位具有第二延伸部，所述第一延伸部沿所述第一部分的宽度方向延伸，所述第二延伸部沿所述第二信号线的宽度方向延伸；其中，所述第一延伸部与所述第二延伸部在所述衬底基板上的正投影存在重叠区域。
在一实施例中，第一延伸部的厚度与第一信号线中的与第二信号线完全交叠的部分的厚度相同。
在一实施例中，所述第一延伸部与所述第二延伸部在所述衬底基板上的正投影部分地重叠。
在一实施例中，所述阵列基板还包括：金属电极，所述金属电极在所述衬底基板上的正投影至多与第一信号线和第二信号线中的一者在所述衬底基板上的正投影重叠，所述金属电极与所述第一延伸部或与所述第二延伸部连接。
在一实施例中，所述金属电极位于所述第一信号线所在层与所述绝缘层之间；所述金属电极与所述第一延伸部电连接。
在一实施例中，所述金属电极位于所述绝缘层与所述第二信号线所在层之间；所述金属电极与所述第二延伸部电连接。
在一实施例中，所述第一信号线为低电平电压信号线，所述第二信号线为高电平电压信号线。
本发明的实施例还提供了一种电致发光显示面板，包括：如前述任一实施例所述的阵列基板。
本发明的实施例还提供了一种显示装置，包括：如前述任一实施例所述的电致发光显示面板。
附图说明
图1a和图1b分别为本公开实施例中提供的阵列基板的侧视图；
图2a至图2d分别为本公开实施例中提供的第一信号线和第二信号线的俯视图；
图3a和图3b分别为本公开实施例中提供的金属电极的位置示意图；
图4为本公开实施例中提供的电致发光显示面板的结构示意图。
具体实施方式
下面将结合附图，对本公开实施例提供的一种阵列基板、电致发光显示面板及显示装置的具体实施方式进行详细地说明。需要说明的是，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开实施例提供了一种阵列基板，如图1a和图1b所示的侧视图，可以包括：衬底基板01(白色填充区域)、以及在衬底基板01上在垂直于衬底基板的方向上依次设置的第一信号线02(斜线填充区域)、绝缘层03(黑点填充区域)和第二信号线04(竖线填充区域)；第一信号线02与第二信号线04相交叉。第一信号线02具有第一部分11和第二部分12，所述第一部分11的电阻高于第二部分12的电阻，所述第一部分11的至少一部分与所述第二信号线04交叠而第二部分11与所述第二信号线04是非交叠的。也就是说，第一信号线02的与第二信号线04完全交叠的部分设置在该第一部分11中。而第一部分11可以仅包括第一信号线02的在垂直于所述衬底基板的方向上与第二信号线04完全交叠的部分。或者替代地，第一部分11也可以还包括其他部分，例如第二信号线02中与所述与第二信号线04完全交叠的部分相邻的部分。在此，例如，第一信号线02的与第二信号线04完全交叠的部分在衬底基板01上的正投影完全落入第二信号线04在衬底基板01上的正投影中。
作为示例，第一信号线02中的第一部分11的电阻可以大于第一信号线02中的其他部分的电阻。
本公开实施例提供的上述阵列基板，为了避免位于绝缘层上下表面的第一信号线和第二信号线在相互交叠的区域(或称交叉区域)发生短路，将第一信号线在涵盖该相互交叠的区域的第一部分11的电阻设置为大于非交叠部分(例如第二部分12)的电阻，即提高第一信号线在第一部分的电阻，在与第二信号线相交叠的部分中形成高阻区，减缓第二信号线中的电流在该相互交叠的区域的流通速度，有效避免因在该相互交叠的区域大电流的瞬间通过导致绝缘层的击穿造成第一信号线与第二信号线之间短路，从而有效减少第一信号线与第二信号线在交叉区域发生短路的几率，提高显示画面的质量。
具体地，为了有效避免第一信号线和第二信号线之间发生的短路，一般可以将高 阻区的范围设置为大于第一信号线和第二信号线完全交叠的区域，如图1b所示的虚线框；当然还可以是如图1a所示的虚线框，高阻区范围等于第一信号线和第二信号线完全交叠的的范围，在此不作限定。
需要说明的是，一般在电致发光显示面板中，位于阵列基板用于传输信号的信号线，通常是由透明导电氧化物制作而成，如氧化铟锡(ITO)；然而，众所周知，以ITO材料作为传输信号的信号线时，其自身的电阻与金属的电阻相比要高出很多，所以，一般情况下，为了提高ITO信号线的导电性能，通常可以将信号线做厚，即厚度越大，电阻越小，使得导电性能越好；而厚度越薄，则电阻越大，导电性能变差。
在具体实施时，在电致发光显示面板中，尤其是在OLED显示面板中，其中的阵列基板上往往分布着多条用于传输低电平电压(如VSS)的信号线，和多条用于传输高电平电压(如VDD)的信号线，分别为阵列基板中用于发光的发光层提供空穴和电子，使得空穴和电子在发光层复合后发光，实现显示；因此，在本公开实施例提供的上述阵列基板中，第一信号线02可以为低电平电压信号线，即VSS，第二信号线04可以为高电平电压信号线，即VDD。
具体地，在OLED显示面板中，在第一信号线02为低电平电压信号线和第二信号线04为高电平电压信号线时，第一信号线02和第二信号线04通常采用透明导电氧化物(如ITO)来制作完成，因此，为了实现第一信号线02在与第二信号线相交叠的部分中的电阻大于非交叠部分的电阻，在本公开实施例提供的上述阵列基板中，第一信号线的第一部分11的厚度小于第一信号线的第二部分12的厚度；通过将第一信号线02的第一部分11的厚度减薄，增加第一信号线02在相互交叠的区域的电阻，从而形成高阻区，如图1a和图1b所示。
具体地，由于绝缘层只是用于将第一信号线02和第二信号线04进行绝缘，所以绝缘层的厚度一般是均一设置的，即厚度保持一致的；因此，在本公开实施例提供的上述阵列基板中，绝缘层在位于所述第一信号线的第一部分上的部位的厚度与所述绝缘层在位于所述第一信号线的第二部分上的部位的厚度相同。作为示例，如图1a和图1b所示，绝缘层03的厚度是保持一致的。
在具体实施时，为了减缓第二信号线中的电流在该相互交叠的区域的流通速度，还可以采用在该相互交叠的区域中制作缓冲电容的方式来减缓电流的流动，具体地，在本公开实施例提供的上述阵列基板中，第一信号线的第一部分在与第二信号线交叠的部位具有第一延伸部，第二信号线在与第一信号线交叠的部位具有第二延伸部。第 一延伸部沿所述第一部分的宽度方向延伸，第二延伸部沿所述第二信号线的宽度方向延伸。
第一延伸部与第二延伸部在衬底基板上的正投影存在重叠区域。
作为示例，第一延伸部的厚度与第一信号线中的与第二信号线完全交叠的部分的厚度相同。
作为示例，如图2a至图2d所示，为了显示方便，图中并未示出绝缘层的所在位置，第一信号线02的第一部分11中所具有的第一延伸部可以为一个(如图2a所示的第一延伸部02a)，也可以为两个(如图2b至图2d所示的第一延伸部02a和第一延伸部02b)；并且，第一延伸部(包括第一延伸部02a和第一延伸部02b)的形状可以是方形(如图2a至2d所示)，还可以是半圆形或是三角形，当然，还可以是其他形状，在此不作限定。
具体地，如图2a至图2d所示，第二信号线04在与第一信号线交叠的部位所具有的第二延伸部同样可以为一个(如图2a所示的第二延伸部04a)，也可以为两个(如图2b至图2d所示的第二延伸部04a和第二延伸部04b)；并且，例如，第二延伸部(包括第二延伸部04a和第二延伸部04b)的形状可以与第一延伸部的形状相同(如图图2a至图2d所示)，还可以与第一延伸部的形状不同，只要保证第一延伸部与第二延伸部在衬底基板上的正投影存在重叠区域，形成缓冲电容即可，在此不作限定。
作为示例，第一延伸部与第二延伸部的关系可以如图2a至图2d所示，其中，第一延伸部(包括第一延伸部02a和第一延伸部02b)在衬底基板上的正投影可以与第二延伸部(包括第二延伸部04a和第二延伸部04b)在衬底基板上的正投影具有部分重叠区域，如图2a和图2b所示；当然，第一延伸部(包括第一延伸部02a和第一延伸部02b)在衬底基板上的正投影还可以完全被第二延伸部(包括第二延伸部04a和第二延伸部04b)在衬底基板上的正投影包围，如图2c所示；当然，第一延伸部(包括第一延伸部02a和第一延伸部02b)在衬底基板上的正投影还可以完全包围第二延伸部(包括第二延伸部04a和第二延伸部04b)在衬底基板上的正投影，如图2d所示；具体地，还可以根据实际需要进行相应地设计，在此不作具体限定。
进一步地，因第一信号线和第二信号线分别具有延伸部，使得第一延伸部和第二延伸部之间可以形成缓冲电容，从而可以减缓第二信号线中的电流在交叉区域的流通速度，减少第一信号线与第二信号线在交叉区域发生短路的几率；然而，缓冲电容的形成无形中增加了第一信号线与第二信号线重叠区域的面积，进而增加了电流流过的 面积，这实际上与高阻区的作用存在着一定的冲突；为了避免这种冲突，并能够充分利用高阻区和缓冲电容的作用，需要对第一信号线在交叉区域所要减薄的程度，以及缓冲电容的面积进行仿真模拟，以得到一个最优的方案，来最终实现减少第一信号线与第二信号线在交叉区域发生短路的几率；因此，第一信号线在交叉区域所要减薄的程度，以及缓冲电容的面积在此不作具体限定。
在具体实施时，当第一信号线和第二信号线为透明导电氧化物(如ITO)制作而成时，因其电阻较大，容易导致电流流过产生较大的压降，影响发光效果，进而影响显示效果；为了避免此种情况，例如可以在第一信号线或第二信号线表面制作金属电极，作为辅助电极来减少压降；同时，为了不影响高阻区和缓冲电容在减缓第二信号线中的电流在相互交叠的区域中的流通速度，减少第一信号线和第二信号线在该相互交叠的区域发生短路的几率，在本公开实施例提供的上述阵列基板中，作为示例，在第一延伸部与第二延伸部在衬底基板上的正投影仅部分重叠时，该阵列基板还可以包括：设置于该相互交叠的区域和重叠区域之外的金属电极(即，该金属电极在所述衬底基板上的正投影至多与第一信号线02和第二信号线04中的一者在所述衬底基板上的正投影重叠，或者说，该金属电极在所述衬底基板上的正投影可以与第一信号线02在所述衬底基板上的正投影重叠，或可以与第二信号线04在所述衬底基板上的正投影重叠，或可以与第一信号线02和第二信号线04在所述衬底基板上的正投影均不重叠)，金属电极与第一延伸部或与第二延伸部连接；如图2a所示，金属电极一般可以位于非交叉区域、非交叠区域，以及第二延伸部04a与第一信号线02的非交叠区域，即金属电极可以位于虚线框内所示的位置，以在保证高阻区与缓冲电容的作用时，还能实现金属电极的作用，使它们之间不会产生相互干扰。
具体地，在本公开实施例提供的上述阵列基板中，金属电极可以设置于第一信号线所在层与第二信号线所在层之间(例如位于第一信号线所在层与第二信号线所在层之间的膜层)，并根据具体的位置实现与第一信号线或与第二信号线的电连接；其中，在金属电极05位于第一信号线02所在层与绝缘层03之间(例如位于第一信号线02所在层与绝缘层03之间的膜层)时；如图3a所示，金属电极05(黑色填充区域)与第一延伸部02a电连接。
或者，在本公开实施例提供的上述阵列基板中，在金属电极05位于绝缘层03与第二信号线04所在层之间(例如位于绝缘层03与第二信号线04所在层之间的膜层)时，如图3b所示，金属电极05(黑色填充区域)与第二延伸部04a电连接。
当然，金属电极并不限于设置于第一信号线所在层与第二信号线所在层之间的膜层，还可以根据实际需要设置在其他的位置，在此不作限定。
基于同一公开构思，本公开实施例还提供了一种电致发光显示面板，如图4所示，可以包括：如本公开实施例提供的上述阵列基板401，还可以包括与阵列基板相对设置的封装基板402。作为示例，阵列基板401例如可以用胶粘合或机械连接件等方式与封装基板402固定。
基于同一公开构思，本公开实施例还提供了一种显示装置，可以包括：如本公开实施例提供的上述电致发光显示面板。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件；其具体实施可参见本公开实施例提供的上述电致发光显示面板的描述，相同之处不再赘述。
本公开实施例提供了一种阵列基板、电致发光显示面板及显示装置，该阵列基板包括：衬底基板、以及在衬底基板上依次设置的第一信号线、绝缘层和第二信号线；并且，所述第一信号线具有第一部分和第二部分，所述第一部分的电阻高于第二部分的电阻，所述第一部分的至少一部分与所述第二信号线交叠而第二部分与所述第二信号线是非交叠的；为了避免位于绝缘层上下表面的第一信号线和第二信号线在相互交叠的区域发生短路，可以将第一信号线在涵盖该相互交叠的区域的第一部分的电阻设置为大于给交叠部分的电阻，即提高第一信号线在该相互交叠的区域的电阻，在该相互交叠的区域形成高阻区，减缓第二信号线中的电流在该相互交叠的区域的流通速度，有效避免因在该相互交叠的区域大电流的瞬间通过导致绝缘层的击穿造成第一信号线与第二信号线之间短路，从而有效减少第一信号线与第二信号线在交叉区域发生短路的几率，提高显示画面的质量。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (14)

  1. 一种阵列基板，包括：衬底基板、以及在所述衬底基板上在垂直于衬底基板的方向上依次设置的第一信号线、绝缘层和第二信号线；其中：
    所述第一信号线具有第一部分和第二部分，所述第一部分的电阻高于第二部分的电阻，所述第一部分的至少一部分与所述第二信号线交叠而第二部分与所述第二信号线是非交叠的。
  2. 如权利要求1所述的阵列基板，其中，所述第一信号线的第一部分包括第一信号线的与所述第二信号线完全交叠的部分。
  3. 如权利要求1所述的阵列基板，其中，所述第一信号线的第一部分与所述第二信号线完全交叠。
  4. 如权利要求1所述的阵列基板，其中，所述第一信号线的第一部分的厚度小于第二部分的厚度。
  5. 如权利要求4所述的阵列基板，其中，所述绝缘层在位于所述第一信号线的第一部分上的部位的厚度与所述绝缘层在位于所述第一信号线的第二部分上的部位的厚度相同。
  6. 如权利要求4所述的阵列基板，其中，所述第一信号线的第一部分在与所述第二信号线交叠的部位具有第一延伸部，所述第二信号线在与所述第一信号线交叠的部位具有第二延伸部，所述第一延伸部沿所述第一部分的宽度方向延伸，所述第二延伸部沿所述第二信号线的宽度方向延伸；其中，
    所述第一延伸部与所述第二延伸部在所述衬底基板上的正投影存在重叠区域。
  7. 如权利要求6所述的阵列基板，其中，第一延伸部的厚度与第一信号线中的与第二信号线完全交叠的部分的厚度相同。
  8. 如权利要求6所述的阵列基板，其中，所述第一延伸部与所述第二延伸部在所述衬底基板上的正投影部分地重叠。
  9. 如权利要求8所述的阵列基板，还包括：金属电极，所述金属电极在所述衬底基板上的正投影至多与第一信号线和第二信号线中的一者在所述衬底基板上的正投影重叠，所述金属电极与所述第一延伸部或与所述第二延伸部连接。
  10. 如权利要求8所述的阵列基板，其中，所述金属电极位于所述第一信号线所在层与所述绝缘层之间；所述金属电极与所述第一延伸部电连接。
  11. 如权利要求8所述的阵列基板，其中，所述金属电极位于所述绝缘层与所述第二信号线所在层之间；所述金属电极与所述第二延伸部电连接。
  12. 如权利要求1-11中任一项所述的阵列基板，其中，所述第一信号线为低电平电压信号线，所述第二信号线为高电平电压信号线。
  13. 一种电致发光显示面板，包括：如权利要求1-12中任一项所述的阵列基板。
  14. 一种显示装置，包括：如权利要求13所述的电致发光显示面板。
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CN206711895U (zh) * 2017-06-02 2017-12-05 京东方科技集团股份有限公司 一种阵列基板、电致发光显示面板及显示装置
CN108336098B (zh) * 2018-03-08 2021-01-26 云谷（固安）科技有限公司 防静电电极结构及显示面板
CN112310035A (zh) * 2020-07-31 2021-02-02 比特大陆科技有限公司 封装基板和芯板
CN112768478B (zh) * 2021-01-19 2023-04-07 Tcl华星光电技术有限公司 一种显示面板以及显示面板的制作方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101577280A (zh) * 2008-02-15 2009-11-11 株式会社半导体能源研究所 显示装置
CN101887904A (zh) * 2009-05-15 2010-11-17 上海天马微电子有限公司 集成触摸屏的有机发光二极管显示器
CN104460150A (zh) * 2014-12-09 2015-03-25 深圳市华星光电技术有限公司 阵列基板、液晶显示面板及该阵列基板的制造方法
CN106033765A (zh) * 2015-03-17 2016-10-19 上海和辉光电有限公司 有机发光二极管触控显示面板
CN106816457A (zh) * 2016-12-28 2017-06-09 上海天马微电子有限公司 一种触控显示面板及其制作方法、触控显示装置
CN206711895U (zh) * 2017-06-02 2017-12-05 京东方科技集团股份有限公司 一种阵列基板、电致发光显示面板及显示装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5841490A (en) * 1994-10-31 1998-11-24 Kyocera Corporation Liquid crystal display device and its fabricating method
JP2002323706A (ja) * 2001-02-23 2002-11-08 Nec Corp 横電界方式のアクティブマトリクス型液晶表示装置及びその製造方法
KR100635042B1 (ko) * 2001-12-14 2006-10-17 삼성에스디아이 주식회사 전면전극을 구비한 평판표시장치 및 그의 제조방법
US7250720B2 (en) * 2003-04-25 2007-07-31 Semiconductor Energy Laboratory Co., Ltd. Display device
KR100659532B1 (ko) * 2003-11-28 2006-12-19 삼성에스디아이 주식회사 평판표시장치 및 그의 제조방법
US7652291B2 (en) * 2005-05-28 2010-01-26 Samsung Mobile Display Co., Ltd. Flat panel display
CN102176299B (zh) * 2005-12-02 2013-07-17 株式会社半导体能源研究所 发光器件的驱动方法
JP5250960B2 (ja) * 2006-01-24 2013-07-31 セイコーエプソン株式会社 発光装置および電子機器
JP2010185928A (ja) * 2009-02-10 2010-08-26 Sony Corp 表示装置の製造方法および表示装置
KR101970783B1 (ko) * 2012-05-07 2019-04-23 삼성디스플레이 주식회사 반도체 장치
TWI711165B (zh) * 2014-11-21 2020-11-21 日商半導體能源研究所股份有限公司 半導體裝置及電子裝置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101577280A (zh) * 2008-02-15 2009-11-11 株式会社半导体能源研究所 显示装置
CN101887904A (zh) * 2009-05-15 2010-11-17 上海天马微电子有限公司 集成触摸屏的有机发光二极管显示器
CN104460150A (zh) * 2014-12-09 2015-03-25 深圳市华星光电技术有限公司 阵列基板、液晶显示面板及该阵列基板的制造方法
CN106033765A (zh) * 2015-03-17 2016-10-19 上海和辉光电有限公司 有机发光二极管触控显示面板
CN106816457A (zh) * 2016-12-28 2017-06-09 上海天马微电子有限公司 一种触控显示面板及其制作方法、触控显示装置
CN206711895U (zh) * 2017-06-02 2017-12-05 京东方科技集团股份有限公司 一种阵列基板、电致发光显示面板及显示装置

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