WO2018205238A1 - 一种显示面板 - Google Patents

一种显示面板 Download PDF

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Publication number
WO2018205238A1
WO2018205238A1 PCT/CN2017/084056 CN2017084056W WO2018205238A1 WO 2018205238 A1 WO2018205238 A1 WO 2018205238A1 CN 2017084056 W CN2017084056 W CN 2017084056W WO 2018205238 A1 WO2018205238 A1 WO 2018205238A1
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WO
WIPO (PCT)
Prior art keywords
thin film
film transistor
type thin
terminal
capacitor
Prior art date
Application number
PCT/CN2017/084056
Other languages
English (en)
French (fr)
Inventor
陈猷仁
Original Assignee
惠科股份有限公司
重庆惠科金渝光电科技有限公司
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Application filed by 惠科股份有限公司, 重庆惠科金渝光电科技有限公司 filed Critical 惠科股份有限公司
Priority to US16/325,749 priority Critical patent/US10989970B2/en
Publication of WO2018205238A1 publication Critical patent/WO2018205238A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/22—Antistatic materials or arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix

Definitions

  • the present application relates to the field of display technologies, and in particular, to a display panel.
  • the liquid crystal display has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • Most of the liquid crystal displays on the market are backlight type liquid crystal displays, which include a liquid crystal panel and a backlight module.
  • the working principle of the liquid crystal panel is to place liquid crystal molecules in two parallel glass substrates, and apply a driving voltage on the two glass substrates to control the rotation direction of the liquid crystal molecules to refract the light of the backlight module to generate a picture.
  • a thin film transistor liquid crystal display includes a liquid crystal panel including a color filter substrate (CF Substrate, also referred to as a color filter substrate), a thin film transistor array substrate (Thin Film Transistor Substrate, TFT Substrate), and a backlight module.
  • CF Substrate also referred to as a color filter substrate
  • Thin Film Transistor Substrate TFT Substrate
  • a backlight module In the mask, a transparent electrode is present on the opposite side of the substrate. A layer of liquid crystal molecules (Liquid Crystal, LC) is sandwiched between the two substrates.
  • electrostatic discharge Electrostatic Discharge, ESD for short
  • electrostatic discharge exceeds a certain voltage
  • the integrated circuit chip dielectric breakdown, core wire fuse, leakage current increase accelerated aging, electrical performance parameters change, etc., so ESD protection is very important.
  • the technical problem to be solved by the present application is to provide a display panel that is reliable and effective for protecting a circuit.
  • a display panel comprising:
  • a substrate having a plurality of pixel regions
  • An electrostatic discharge circuit the electrostatic discharge circuit being disposed on the substrate;
  • the electrostatic discharge circuit includes a high level terminal, a low level terminal, an electrostatic input end, and a common end coupled to components of the display panel;
  • a first discharge unit an output end of the first discharge unit is respectively connected to a high level terminal and a low level terminal, and a control end and an input end of the first discharge unit are connected to the static input end;
  • a second discharge unit an input end of the second discharge unit is connected to the static input end, and an output end of the second discharge unit is connected to the common end.
  • the second discharge unit includes a first conductive line connected to the common end at one end, and the common end is connected to the ground.
  • the line width between the high-level terminal (VGH) and the low-level terminal (VGL) requires a smaller line width, which is equivalent to having a larger resistance, and the relative leakage current is also Smaller, the ability of the first discharge unit to exert a separate discharge may not be sufficient.
  • the second conductive line is used for the ground (GND) connection, and its line width is much larger than the line width of VGH and VGL, so the current that can be drained will be larger than originally, to achieve better protection.
  • the second discharge unit includes a first conductive line connected to the common end at one end, and the common end is connected to a common voltage end of the display panel.
  • the line width between the high-level terminal (VGH) and the low-level terminal (VGL) requires a smaller line width, which is equivalent to having a larger resistance, and the relative leakage current is also Smaller, the ability of the first discharge unit to exert a separate discharge may not be sufficient.
  • the second conductive line is used for the common voltage terminal (VCOM) connection, and its line width is much larger than the line width of VGH and VGL, so the current that can be drained is larger than originally, to achieve better protection effect. .
  • the second discharge circuit includes a third thin film transistor, and an input end and a control end of the third thin film transistor are connected to the electrostatic input end, and an output end of the third thin film transistor is connected to the common end .
  • the second discharge unit is discharged through the third thin film transistor, and the setting is simple, effective and reliable.
  • the second discharge circuit includes a capacitor, a first end of the capacitor is connected to the electrostatic input end, and a second end of the capacitor is connected to a control end of the third thin film transistor.
  • the capacitor has the characteristics of blocking DC, AC, high frequency, and low frequency, and the voltage is around VGL to VGH.
  • the two discharge cells do not participate in the action.
  • the second discharge unit can work normally, and does not generate a current leaving the VGL through the second thin film transistor.
  • the second discharge circuit includes a fourth thin film transistor, an input end of the fourth thin film transistor is connected to a second end of the capacitor, and a control end of the fourth thin film transistor is connected to the high level End connection, an output end of the fourth thin film transistor is connected to the low level terminal, or a control end of the fourth thin film transistor is connected to the low level terminal, the fourth thin film transistor The output is connected to the high level terminal.
  • the conduction of the fourth thin film transistor further completes the discharge function of the second discharge unit, and simultaneously pulls the potential of the second end of the capacitor to be consistent with the common end, so that when the voltage is between VGL and VGH, the third thin film transistor is not guided. The discharge works to affect the normal operation of the protection circuit.
  • the first discharge circuit includes a first N-type thin film transistor and a second N-type thin film transistor, and a source of the first N-type thin film transistor is connected to the high-level terminal, and the first N-type a gate and a drain of the thin film transistor are connected and connected to a source of the second N-type thin film transistor, and a source of the second N-type thin film transistor is further connected to the electrostatic input terminal, the second N a gate and a drain of the thin film transistor are connected and connected to the low level terminal;
  • the first discharge circuit includes a first P-type thin film transistor and a second P-type thin film transistor, and a gate and a drain of the first P-type thin film transistor are connected to the high level a terminal is connected, a source of the first P-type thin film transistor is connected to the electrostatic input terminal, and a gate and a drain of the second P-type thin film transistor are connected to and connected to the first P-type thin film transistor a source connection, a source of the second P-type thin film transistor being connected to the low-level terminal;
  • the second discharge circuit includes a third N-type thin film transistor, a capacitor, and a fourth N-type thin film transistor, and a source of the third N-type thin film transistor is connected to a gate of the first N-type thin film transistor.
  • a drain of the third N-type thin film transistor is connected to the common terminal, the common terminal is grounded, a first end of the capacitor is connected to the electrostatic input end, and a second end of the capacitor is connected to the first a gate of the triple N-type thin film transistor, a source of the fourth N-type thin film transistor being connected to a second end of the capacitor, a gate of the fourth N-type thin film transistor and the high-level terminal Connected, the drain of the fourth N-type thin film transistor is connected to the low level terminal.
  • the protection circuit which clarifies the specific electrical components and connection relationships.
  • the second discharge circuit includes a third P-type thin film transistor, a capacitor, and a fourth P-type thin film transistor, and a source of the third P-type thin film transistor is connected to a gate of the second P-type thin film transistor
  • the drain of the third P-type thin film transistor is connected to the common terminal, the common terminal is grounded, the first end of the capacitor is connected to the electrostatic input end, and the second end of the capacitor is a gate connection of a third P-type thin film transistor, a source of the fourth P-type thin film transistor being connected to a second end of the capacitor, a gate of the fourth P-type thin film transistor and the low level
  • the terminal is connected, and a drain of the fourth P-type thin film transistor is connected to the high-level terminal.
  • the protection circuit which clarifies the specific electrical components and connection relationships.
  • the display panel includes a gate integrated circuit, and the high-level terminal and the low-level terminal are respectively turned off at a thin film transistor turn-on voltage end of the gate integrated circuit and a thin film transistor is turned off. Pressure connection. Specific VGH, VGL connection.
  • the display panel since the two first discharge cells and the second discharge cells are connected together, the other end of the second discharge cell is connected to the common terminal, and the ESD discharge current path is increased, and the speed and quantity of the discharge are increased.
  • the display panel has better protection and longer life.
  • FIG. 1 is a schematic diagram of a protection circuit of a display panel according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a protection circuit of a display panel according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a protection circuit of a display panel according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a protection circuit of a display panel according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a protection circuit of a display panel according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a protection circuit of a display panel according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a display panel according to an embodiment of the present application.
  • first and second may include one or more of the features either explicitly or implicitly.
  • a plurality means two or more unless otherwise stated.
  • the term “comprises” and its variations are intended to cover a non-exclusive inclusion.
  • connection In the description of the present application, it should be noted that the terms “installation”, “connected”, and “connected” are to be understood broadly, and may be fixed or detachable, for example, unless otherwise specifically defined and defined. Connected, or integrally connected; can be mechanical or electrical; can be directly connected, or indirectly connected through an intermediate medium, can be the internal communication of the two components.
  • Connected, or integrally connected can be mechanical or electrical; can be directly connected, or indirectly connected through an intermediate medium, can be the internal communication of the two components.
  • the specific meanings of the above terms in the present application can be understood in the specific circumstances for those skilled in the art.
  • the display panel includes: a substrate provided with a plurality of pixel regions; an electrostatic discharge circuit, the electrostatic discharge circuit is disposed on the substrate;
  • the discharge circuit includes a high level terminal, a low level terminal, an electrostatic input end, and a common end coupled to the components of the display panel; and a first discharge unit: the output ends of the first discharge unit are respectively high
  • the level terminal is connected to the low level terminal, the control end and the input end of the first discharge unit are connected to the static input end
  • the second discharge unit is: the input end of the second discharge unit and the static electricity
  • the input terminal is connected, and the output end of the second discharge unit is connected to the common terminal.
  • the discharge unit includes a first thin film transistor and a second thin film transistor, and an output end of the first thin film transistor is connected to the high level terminal, an input end of the first thin film transistor, and an output of the second thin film transistor The terminal is connected to the electrostatic input terminal, and an input end of the second thin film transistor is connected to the low-level terminal.
  • the display panel has better protection and longer life. As shown in FIG.
  • an electrostatic discharge circuit, a gate drive circuit, and a source drive circuit are disposed on the substrate, and the horizontally disposed scan lines and the vertically disposed data lines are coupled to the corresponding circuits, and the plurality of The data line and the plurality of the scan lines are sequentially arranged to form a plurality of pixel regions.
  • the second conductive line is used for the common voltage terminal (VCOM) connection, and its line width is much larger than the line width of VGH and VGL, so the current that can be drained is larger than originally, to achieve better protection effect.
  • the display panel includes a gate integrated circuit, and the high-level terminal and the low-level terminal are respectively connected to a thin film transistor turn-on voltage end of the gate integrated circuit and a thin film transistor off voltage terminal.
  • the display panel includes: a substrate provided with a plurality of pixel regions; an electrostatic discharge circuit, the electrostatic discharge circuit is disposed on the substrate; and the electrostatic discharge circuit includes the display a high-level terminal, a low-level terminal, an electrostatic input terminal, and a common terminal coupled to the components of the panel; and a first discharge unit: the output terminals of the first discharge unit are respectively connected to the high-level terminal and low-power a flat terminal connection, a control end and an input end of the first discharge unit and the static input The second discharge unit is connected to the electrostatic input end, and the output end of the second discharge unit is connected to the common end.
  • the second discharge circuit includes a third thin film transistor, a capacitor, and an input end and a control end of the third thin film transistor are connected to the electrostatic input end, and an output end of the third thin film transistor and the common end connection.
  • the second discharge unit is discharged through the third thin film transistor, and the setting is simple, effective and reliable.
  • the first end of the capacitor is connected to the electrostatic input end, and the second end of the capacitor is connected to the control end of the third thin film transistor.
  • the capacitor has the characteristics of blocking DC, AC, high frequency, and low frequency. When the voltage is around VGL to VGH, the second discharge unit does not participate.
  • the second discharge unit can work normally, and does not generate a current leaving the VGL through the second thin film transistor. Therefore, if the input voltage of the PIN is between VGL and VGH, since the capacitor can be regarded as an open circuit in the direct current, the capacitor and the thin film transistor will not operate.
  • the first thin film transistor and the second thin film transistor are N-type thin film transistors: a first N-type thin film transistor, a second N-type thin film transistor, and a source of the first N-type thin film transistor.
  • a source and a third of the third N-type thin film transistor a gate of an N-type thin film transistor is connected, a drain of the third N-type thin film transistor is connected to the common terminal, the common terminal is connected to a ground, and a first end of the capacitor is connected to the static input terminal.
  • the second end of the capacitor is connected to the gate of the third N-type thin film transistor.
  • the first N-type thin film transistor When a positive large voltage comes in at the moment of the PIN, the first N-type thin film transistor is turned on, and a first discharge current is generated. Since the PIN potential is instantaneously high, the potential of the point between the second end of the capacitor and the gate connection of the third N-type thin film transistor is also increased at the same time as the capacitive coupling effect, and the third N-type thin film transistor is also turned on. At this time, the positive large voltage of the PIN can be discharged to the GND. Since the trace of GND is usually thicker than VGL, the corresponding resistance value is much smaller than VGL, so the second discharge current is greater than the first discharge current.
  • the first discharge unit can use a P-type thin film transistor, or an N-type thin film transistor and a P-type thin film transistor.
  • the first thin film transistor and the second thin film transistor are P-type thin film transistors: a first P-type thin film transistor and a second P-type thin film transistor, and a gate and a drain of the first P-type thin film transistor are connected and Connecting with the high-level terminal, a source of the first P-type thin film transistor is connected to the electrostatic input terminal, and a gate and a drain of the second P-type thin film transistor are connected to the first A source of a P-type thin film transistor is connected, and a source of the second P-type thin film transistor is connected to the low-level terminal.
  • the display panel includes: a substrate provided with a plurality of pixel regions; an electrostatic discharge circuit, the electrostatic discharge circuit is disposed on the substrate; and the electrostatic discharge circuit includes the display a high-level terminal, a low-level terminal, an electrostatic input terminal, and a common terminal coupled to the components of the panel; and a first discharge unit: the output terminals of the first discharge unit are respectively connected to the high-level terminal and low-power a flat terminal is connected, a control end and an input end of the first discharge unit are connected to the electrostatic input end; a second discharge unit: an input end of the second discharge unit is connected to the electrostatic input end, The output of the two discharge cells is connected to the common terminal.
  • the first discharge unit includes a first thin film transistor and a second thin film transistor, and an output end of the first thin film transistor is connected to the high level terminal, an input end of the first thin film transistor, and the An output end of the second thin film transistor is connected to the electrostatic input end, and an input end of the second thin film transistor is connected to the low level terminal.
  • Two connected first discharge cells and a second discharge unit work together, and the other end of the second discharge unit is connected with the common end to increase the ESD discharge current path, and the speed and quantity of the discharge are increased, thereby realizing the display panel Good protection effect and long service life.
  • the second discharge circuit includes a a third thin film transistor, a capacitor, and a fourth thin film transistor, wherein an input end and a control end of the third thin film transistor are connected to the electrostatic input end, and an output end of the third thin film transistor is connected to the common end.
  • the second discharge unit is discharged through the third thin film transistor, and the setting is simple, effective and reliable.
  • the first end of the capacitor is connected to the electrostatic input end, and the second end of the capacitor is connected to the control end of the third thin film transistor.
  • the capacitor has the characteristics of blocking DC, AC, high frequency, and low frequency. When the voltage is around VGL to VGH, the second discharge unit does not participate.
  • the second discharge unit can work normally, and does not generate a current leaving the VGL through the second thin film transistor. Therefore, if the input voltage of the PIN is between VGL and VGH, since the capacitor can be regarded as an open circuit in the direct current, the capacitor and the thin film transistor will not operate.
  • An input end of the fourth thin film transistor is connected to a second end of the capacitor, a control end of the fourth thin film transistor is connected to the high level terminal, an output end of the fourth thin film transistor is The low level terminal is connected, or the control end of the fourth thin film transistor is connected to the low level terminal, and the output end of the fourth thin film transistor is connected to the high level terminal.
  • the conduction of the fourth thin film transistor further completes the discharge function of the second discharge unit, and simultaneously pulls the potential of the second end of the capacitor to be consistent with the common end, so that when the voltage is between VGL and VGH, the third thin film transistor is not guided. The discharge works to affect the normal operation of the protection circuit.
  • FIG. 5 can be regarded as the actual equivalent circuit of FIG. 4.
  • the first thin film transistor and the second thin film transistor are N-type thin film transistors: a first N-type thin film transistor, and a second An N-type thin film transistor, a source of the first N-type thin film transistor is connected to the high-level terminal, and a gate and a drain of the first N-type thin film transistor are connected to the second N-type thin film transistor a source connection, a source of the second N-type thin film transistor is further connected to the electrostatic input terminal, and a gate and a drain of the second N-type thin film transistor are connected to the low-level terminal Connecting, the second discharge circuit includes a third N-type thin film transistor, a capacitor, and a fourth N-type thin film transistor, and a source of the third N-type thin film transistor is connected to a gate of the first N-type thin film transistor a drain of the third N-type thin film transistor is connected to the common terminal, the common terminal is grounded
  • the protection circuit which clarifies the specific electrical components and connection relationships. Since the PIN potential is instantaneously high, the potential of the point between the second end of the capacitor and the gate connection of the third N-type thin film transistor is also increased at the same time as the capacitive coupling effect, and the third N-type thin film transistor is also turned on. At this time, the positive large voltage of the PIN can be discharged to the GND. Since the trace of GND is usually thicker than VGL, the corresponding resistance value is much smaller than VGL, so the second discharge current is greater than the first discharge current. The fourth N-type thin film transistor also pulls the potential of the point between the second end of the capacitor and the gate connection of the third N-type thin film transistor to GND.
  • the discharged current is the first discharge current
  • the sum of the second discharge circuit and the third discharge current is larger, and the total discharge is compared to the single discharge unit.
  • the current is large and has a better protection effect.
  • the first discharge unit can use a P-type thin film transistor, or an N-type thin film transistor and a P-type thin film transistor.
  • the first thin film transistor and the second thin film transistor are P-type thin film transistors: a first P-type thin film transistor and a second P-type thin film transistor, and a gate and a drain of the first P-type thin film transistor are connected and Connecting with the high-level terminal, a source of the first P-type thin film transistor is connected to the electrostatic input terminal, and a gate and a drain of the second P-type thin film transistor are connected to the first A source of a P-type thin film transistor is connected, and a source of the second P-type thin film transistor is connected to the low-level terminal.
  • the display panel includes: a substrate provided with a plurality of pixel regions; an electrostatic discharge circuit, the electrostatic discharge circuit is disposed on the substrate; and the electrostatic discharge The circuit includes a high level terminal, a low level terminal, an electrostatic input end, and a common end coupled to components of the display panel; and a first discharge unit: the first discharge unit includes a first P type film a transistor and a second P-type thin film transistor, a gate and a drain of the first P-type thin film transistor are connected and connected to the high-level terminal, and a source and a source of the first P-type thin film transistor Connected to the electrostatic input terminal, the gate and the drain of the second P-type thin film transistor are connected and connected to the source of the first P-type thin film transistor, and the source and the source of the second P-type thin film transistor Low level
  • the terminal is connected to the second discharge unit: the input end of the second discharge unit is connected to the static input end, and the output end of
  • the display panel since the two first discharge cells and the second discharge cells are connected together, the other end of the second discharge cell is connected to the common terminal, and the ESD discharge current path is increased, and the speed and quantity of the discharge are increased.
  • the display panel has better protection and longer life.
  • the second discharge unit includes a first conductive line connected to the common end at one end, and the common end is grounded.
  • the line width between the high-level terminal (VGH) and the low-level terminal (VGL) requires a smaller line width, which is equivalent to having a larger resistance, and the relative leakage current is also Smaller, the ability of the first discharge unit to exert a separate discharge may not be sufficient.
  • the second conductive line is used for the ground (GND) connection, and its line width is much larger than the line width of VGH and VGL, so the current that can be drained will be larger than originally, to achieve better protection.
  • the second discharge unit includes a first conductive line connected to the common end at one end, and the common end is connected to a common voltage end of the display panel.
  • the second conductive line is used for the common voltage terminal (VCOM) connection, and its line width is much larger than the line width of VGH and VGL, so the current that can be drained is larger than originally, to achieve better protection effect.
  • the display panel includes a gate integrated circuit, and the high-level terminal and the low-level terminal are respectively connected to a thin film transistor turn-on voltage end of the gate integrated circuit and a thin film transistor off voltage terminal.
  • the display panel includes: a substrate provided with a plurality of pixel regions; an electrostatic discharge circuit, the electrostatic discharge circuit is disposed on the substrate; and the electrostatic discharge circuit includes the display a high-level terminal, a low-level terminal, an electrostatic input terminal, and a common terminal coupled to the components of the panel; and a first discharge unit: the first discharge unit includes a first P-type thin film transistor and a second P a thin film transistor, a gate and a drain of the first P-type thin film transistor are connected and connected to the high-level terminal, and a source of the first P-type thin film transistor is connected to the static input terminal, a gate and a drain of the second P-type thin film transistor are connected and connected to a source of the first P-type thin film transistor, a source of the second P-type thin film transistor and the low-level terminal Connecting; a second discharge unit: an input end of the second discharge unit is connected to the electrostatic input end, the second An output of the discharge unit is
  • the second discharge circuit includes a third thin film transistor, a capacitor, and an input end and a control end of the third thin film transistor are connected to the electrostatic input end, and an output end of the third thin film transistor and the common end connection.
  • the second discharge unit is discharged through the third thin film transistor, and the setting is simple, effective and reliable.
  • the second discharge circuit includes a first end of the capacitor connected to the electrostatic input end, and a second end of the capacitor connected to a control end of the third thin film transistor.
  • the capacitor has the characteristics of blocking DC, AC, high frequency, and low frequency.
  • the second discharge unit does not participate.
  • the voltage range is not VGL to VGH, for example, when there is a positive large voltage instantaneously, the second discharge unit can work normally, and does not generate a current leaving the VGL through the second thin film transistor. Therefore, if the input voltage of the PIN is between VGL and VGH, since the capacitor can be regarded as an open circuit in the direct current, the capacitor and the thin film transistor will not operate.
  • the third thin film transistor is a P-type thin film transistor: a third P-type thin film transistor, a source of the third P-type thin film transistor and a gate of the second P-type thin film transistor a drain connection, a drain of the third P-type thin film transistor is connected to the common end, the common end is grounded, a first end of the capacitor is connected to the electrostatic input end, and a second end of the capacitor is Connected to the gate of the third P-type thin film transistor.
  • the potential of the point between the second end of the capacitor and the gate connection of the third N-type thin film transistor is also increased at the same time as the capacitive coupling effect, and the third N-type thin film transistor is also turned on.
  • the positive large voltage of the PIN can be discharged to the GND. Since the trace of GND is usually thicker than VGL, the corresponding resistance value is much smaller than VGL, so the second discharge current is greater than the first discharge current.
  • the display panel includes: a substrate provided with a plurality of pixel regions; an electrostatic discharge circuit, the electrostatic discharge circuit is disposed on the substrate; and the electrostatic discharge circuit includes the display a high-level terminal, a low-level terminal, an electrostatic input terminal, and a common terminal coupled to the components of the panel; and a first discharge unit: the first discharge unit includes a first P-type thin film crystal And a second P-type thin film transistor, a gate and a drain of the first P-type thin film transistor are connected and connected to the high-level terminal, and a source and a source of the first P-type thin film transistor Connected to the electrostatic input terminal, the gate and the drain of the second P-type thin film transistor are connected and connected to the source of the first P-type thin film transistor, and the source and the source of the second P-type thin film transistor
  • the low-level terminal is connected; the second discharge unit: the input end of the second discharge unit is connected to the electrostatic input end, and the output end of
  • the second discharge circuit includes a third thin film transistor, a capacitor, and a fourth thin film transistor, and an input end and a control end of the third thin film transistor are connected to the electrostatic input end, and an output of the third thin film transistor The end is connected to the public end.
  • the second discharge unit is discharged through the third thin film transistor, and the setting is simple, effective and reliable.
  • the second discharge circuit includes a first end of the capacitor connected to the electrostatic input end, and a second end of the capacitor connected to a control end of the third thin film transistor.
  • the capacitor has the characteristics of blocking DC, AC, high frequency, and low frequency.
  • the second discharge unit does not participate.
  • the voltage range is not VGL to VGH, for example, when there is a positive large voltage instantaneously, the second discharge unit can work normally, and does not generate a current leaving the VGL through the second thin film transistor. Therefore, if the input voltage of the PIN is between VGL and VGH, since the capacitor can be regarded as an open circuit in the direct current, the capacitor and the thin film transistor will not operate.
  • the control end of the fourth thin film transistor is connected to the low level terminal, and the output end of the fourth thin film transistor is connected to the high level terminal.
  • the conduction of the fourth thin film transistor further completes the discharge function of the second discharge unit, and simultaneously pulls the potential of the second end of the capacitor to be consistent with the common end, so that when the voltage is between VGL and VGH, the third thin film transistor is not guided.
  • the discharge works to affect the normal operation of the protection circuit.
  • FIG. 8 can be regarded as the actual equivalent circuit of FIG. 7.
  • the third thin film transistor and the fourth thin film transistor are P-type thin film transistors: a third P-type thin film transistor, and a fourth a P-type thin film transistor, a source of the third P-type thin film transistor is connected to a gate of the second P-type thin film transistor, and a drain of the third P-type thin film transistor is connected to the common end, Public termination Ground connection, a first end of the capacitor is connected to the electrostatic input end, a second end of the capacitor is connected to a gate of the third P-type thin film transistor, and a source of the fourth P-type thin film transistor Connected to the second end of the capacitor, a gate of the fourth P-type thin film transistor is connected to the low-level terminal, a drain of the fourth P-type thin film transistor and the high-level terminal connection.
  • the potential of the point between the second end of the capacitor and the gate connection of the third N-type thin film transistor is also increased at the same time as the capacitive coupling effect, and the third N-type thin film transistor is also turned on. At this time, the positive large voltage of the PIN can be discharged to the GND. Since the trace of GND is usually thicker than VGL, the corresponding resistance value is much smaller than VGL, so the second discharge current is greater than the first discharge current.
  • the fourth N-type thin film transistor also pulls the potential of the point between the second end of the capacitor and the gate connection of the third N-type thin film transistor to GND.
  • the discharged current is the first discharge current
  • the sum of the second discharge circuit and the third discharge current is larger, and the total discharge is compared to the single discharge unit.
  • the current is large and has a better protection effect.
  • the present application also discloses a display device including a backlight module and a display panel as described above.
  • the material of the substrate may be glass, plastic or the like.
  • the display panel includes a liquid crystal panel, an OLED (Organic Light-Emitting Diode) panel, a curved panel, a plasma panel, etc.
  • the liquid crystal panel includes an array substrate (Thin Film Transistor Substrate, TFT Substrate) and a color filter substrate (CF Substrate), the array substrate is disposed opposite to the color filter substrate, and a liquid crystal and a spacer (PS) are disposed between the array substrate and the color filter substrate, and the array substrate A thin film transistor (TFT) is disposed on the color film substrate, and a color filter layer is disposed on the color filter substrate.
  • TFT Thin Film Transistor Substrate
  • CF Substrate color filter substrate
  • PS liquid crystal and a spacer
  • the color filter substrate may include a TFT array
  • the color film and the TFT array may be formed on the same substrate
  • the array substrate may include a color filter layer
  • the display panel of the present application may be a curved type panel.

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Abstract

一种显示面板，包括：基板；静电放电电路，静电放电电路设置在基板上；静电放电电路包括与显示面板的元器件耦合的高电平接线端（1）、低电平接线端（2）、静电输入端（4）以及公共端（3）；以及第一放电单元：第一放电单元的输出端分别与高电平接线端（1）和低电平接线端（2）连接，第一放电单元的控制端和输入端与静电输入端（4）连接；第二放电单元（6）：第二放电单元（6）的输入端与静电输入端（4）连接，第二放电单元的输出端与公共端（3）连接。

Description

一种显示面板 【技术领域】
本申请涉及显示技术领域，尤其涉及一种显示面板。
【背景技术】
液晶显示器具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶面板及背光模组(backlightmodule)。液晶面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，并在两片玻璃基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
其中，薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)由于具有低的功耗、优异的画面品质以及较高的生产良率等性能，目前已经逐渐占据了显示领域的主导地位。同样，薄膜晶体管液晶显示器包含液晶面板和背光模组，液晶面板包括彩膜基板(Color Filter Substrate，CF Substrate，也称彩色滤光片基板)、薄膜晶体管阵列基板(Thin Film Transistor Substrate，TFTSubstrate)和光罩(Mask)，上述基板的相对内侧存在透明电极。两片基板之间夹一层液晶分子(LiquidCrystal，LC)。
然而，静电放电即Electrostatic Discharge，简称ESD，静电放电超过一定的电压可使集成电路芯片介质击穿，芯线熔断，漏电流增大加速老化，电性能参数改变等，因而ESD的防护相当重要。
【发明内容】
本申请所要解决的技术问题是提供一种保护电路可靠有效的的显示面板。
本申请的目的是通过以下技术方案来实现的：
一种显示面板，包括：
基板，设有多个像素区；
静电放电电路，所述静电放电电路设置在所述基板上；
所述静电放电电路包括与所述显示面板的元器件耦合的高电平接线端、低电平接线端、静电输入端以及公共端；以及
第一放电单元：所述第一放电单元的输出端分别与高电平接线端和低电平接线端连接，所述第一放电单元的控制端和输入端与所述静电输入端连接；
第二放电单元：所述第二放电单元的输入端与所述静电输入端连接，所述第二放电单元的输出端与所述公共端连接。
其中，所述第二放电单元包括一端与所述公共端连接的第一导电线，所述公共端接地连接。高电平接线端(VGH)与低电平接线端(VGL)之间的所用的导电线所需的线宽较小，这样相当于会有一个比较大的电阻所，相对的泄流电流也比较小，第一放电单元单独发挥泄流的能力可能不够。而第二导电线用于接地端(GND)连接，它的线宽都远远大于VGH、VGL的线宽，所以可以排泄掉的电流会比原本来的大，以达到更好的防护效果。
其中，所述第二放电单元包括一端与所述公共端连接的第一导电线，所述公共端与所述显示面板的公共电压端连接。高电平接线端(VGH)与低电平接线端(VGL)之间的所用的导电线所需的线宽较小，这样相当于会有一个比较大的电阻所，相对的泄流电流也比较小，第一放电单元单独发挥泄流的能力可能不够。而第二导电线用于公共电压端(VCOM)连接，它的线宽都远远大于VGH、VGL的线宽，所以可以排泄掉的电流会比原本来的大，以达到更好的防护效果。
其中，所述第二放电电路包括一个第三薄膜晶体管，所述第三薄膜晶体管的输入端和控制端与所述静电输入端连接，所述第三薄膜晶体管的输出端与所述公共端连接。第二放电单元通过第三薄膜晶体管泄流，设置简单，有效可靠。
其中，所述第二放电电路包括一个电容，所述电容的第一端与所述静电输入端连接，所述电容的第二端与所述第三薄膜晶体管的控制端连接。利用电容具有隔直流、通交流，通高频、阻低频的特性，电压笵围在VGL～VGH时，第 二放电单元不参与作用。同时电压笵围不在VGL～VGH时，例如瞬间有个正的大电压时，第二放电单元能够正常工作，不产生经第二薄膜晶体管留下VGL的电流。
其中，所述第二放电电路包括一个第四薄膜晶体管，所述第四薄膜晶体管的输入端与所述电容的第二端连接，所述第四薄膜晶体管的控制端与所述高电平接线端连接，所述第四薄膜晶体管的输出端与所述低电平接线端连接，或者，所述第四薄膜晶体管的控制端与所述低电平接线端连接，所述第四薄膜晶体管的输出端与所述高电平接线端连接。第四薄膜晶体管的导通进一步完成第二放电单元的放电功用，同时将电容的第二端的电位拉到与公共端一致，这样当电压笵围在VGL～VGH时，第三薄膜晶体管不至于导通放电而影响保护电路的正常工作。
其中，所述第一放电电路包括一个第一N型薄膜晶体管和一个第二N型薄膜晶体管，所述第一N型薄膜晶体管的源极与所述高电平接线端连接，第一N型薄膜晶体管的栅极和漏极相连接并与所述第二N型薄膜晶体管的源极连接，所述第二N型薄膜晶体管的源极还与所述静电输入端连接，所述第二N型薄膜晶体管的栅极和漏极相连接并与所述低电平接线端连接；
所述第二放电电路包括一个第三N型薄膜晶体管、一个电容、一个第四N型薄膜晶体管，所述第三N型薄膜晶体管的源极与第一N型薄膜晶体管的栅极连接，所述第三N型薄膜晶体管的漏极与所述公共端连接，所述公共端接地连接，所述电容的第一端与所述静电输入端连接，所述电容的第二端与所述第三N型薄膜晶体管的栅极连接，所述第四N型薄膜晶体管的源极与所述电容的第二端连接，所述第四N型薄膜晶体管的栅极与所述高电平接线端连接，所述第四N型薄膜晶体管的漏极与所述低电平接线端连接。这里是保护电路的一个实施方式，明确具体采用的电元件以及连接关系。
其中，所述第一放电电路包括一个第一P型薄膜晶体管和一个第二P型薄膜晶体管，所述第一P型薄膜晶体管的栅极和漏极相连接并与所述高电平 接线端连接，所述第一P型薄膜晶体管的源极与所述静电输入端连接，所述第二P型薄膜晶体管的栅极和漏极相连接并与所述第一P型薄膜晶体管的源极连接，所述第二P型薄膜晶体管的源极与所述低电平接线端连接；
所述第二放电电路包括一个第三N型薄膜晶体管、一个电容、一个第四N型薄膜晶体管，所述第三N型薄膜晶体管的源极与第一N型薄膜晶体管的栅极连接，所述第三N型薄膜晶体管的漏极与所述公共端连接，所述公共端接地连接，所述电容的第一端与所述静电输入端连接，所述电容的第二端与所述第三N型薄膜晶体管的栅极连接，所述第四N型薄膜晶体管的源极与所述电容的第二端连接，所述第四N型薄膜晶体管的栅极与所述高电平接线端连接，所述第四N型薄膜晶体管的漏极与所述低电平接线端连接。这里是保护电路的一个实施方式，明确具体采用的电元件以及连接关系。
其中，所述第一放电电路包括一个第一P型薄膜晶体管和一个第二P型薄膜晶体管，所述第一P型薄膜晶体管的栅极和漏极相连接并与所述高电平接线端连接，所述第一P型薄膜晶体管的源极与所述静电输入端连接，所述第二P型薄膜晶体管的栅极和漏极相连接并与所述第一P型薄膜晶体管的源极连接，所述第二P型薄膜晶体管的源极与所述低电平接线端连接；
所述第二放电电路包括一个第三P型薄膜晶体管、一个电容、一个第四P型薄膜晶体管，所述第三P型薄膜晶体管的源极与所述第二P型薄膜晶体管的栅极连接，所述第三P型薄膜晶体管的漏极与所述公共端连接，所述公共端接地连接，所述电容的第一端与所述静电输入端连接，所述电容的第二端与所述第三P型薄膜晶体管的栅极连接，所述第四P型薄膜晶体管的源极与所述电容的第二端连接，所述第四P型薄膜晶体管的栅极与所述低电平接线端连接，所述第四P型薄膜晶体管的漏极与所述高电平接线端连接。这里是保护电路的一个实施方式，明确具体采用的电元件以及连接关系。
其中，所述显示面板包括栅极集成电路，所述高电平接线端、所述低电平接线端分别于所述栅极集成电路的薄膜晶体管开启电压端和薄膜晶体管关闭电 压端连接。具体VGH、VGL的连接。
本申请由于两个相连接的第一放电单元和第二放电单元共同作用，第二放电单元的另一端与公共端连接，增加ESD放电电流路径，泄流的速度和数量得以加大，实现对显示面板更好的保护效果，延长使用寿命。
【附图说明】
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请实施例一种显示面板的保护电路的示意图；
图2是本申请实施例一种显示面板的保护电路的示意图；
图3是本申请实施例一种显示面板的保护电路的示意图；
图4是本申请实施例一种显示面板的保护电路的示意图；
图5是本申请实施例一种显示面板的保护电路的示意图；
图6是本申请实施例一种显示面板的保护电路的示意图；
图7是本申请实施例一种显示面板的保护电路的示意图；
图8是本申请实施例一种显示面板的保护电路的示意图；
图9是本申请实施例一种显示面板的结构示意图。
【具体实施方式】
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、 “右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
下面结合附图和较佳的实施例对本申请作进一步详细说明。
作为本申请的一个实施例，如图1-2所示，所述显示面板包括：基板，设有多个像素区；静电放电电路，所述静电放电电路设置在所述基板上；所述静电放电电路包括与所述显示面板的元器件耦合的高电平接线端、低电平接线端、静电输入端以及公共端；以及第一放电单元：所述第一放电单元的输出端分别与高电平接线端和低电平接线端连接，所述第一放电单元的控制端和输入端与所述静电输入端连接；第二放电单元：所述第二放电单元的输入端与所述静电输入端连接，所述第二放电单元的输出端与所述公共端连接。其中，所述第一 放电单元包括一个第一薄膜晶体管和一个第二薄膜晶体管，所述第一薄膜晶体管的输出端与所述高电平接线端连接，第一薄膜晶体管的输入端、所述第二薄膜晶体管的输出端与所述静电输入端连接，所述第二薄膜晶体管的输入端与所述低电平接线端连接。本申请由于两个相连接的第一放电单元和第二放电单元共同作用，第二放电单元的另一端与公共端连接，增加ESD放电电流路径，泄流的速度和数量得以加大，实现对显示面板更好的保护效果，延长使用寿命。如图9所示，所示基板上设置有静电放电电路、栅极驱动电路和源极驱动电路，水平设置的扫描线和竖直设置的数据线与其相对应的电路耦合连接，多条所述数据线与多条所述扫描线依次相交设置形成多个像素区。
具体的，所述第二放电单元包括一端与所述公共端连接的第一导电线，所述公共端接地连接。高电平接线端(VGH)与低电平接线端(VGL)之间的所用的导电线所需的线宽较小，这样相当于会有一个比较大的电阻所，相对的泄流电流也比较小，第一放电单元单独发挥泄流的能力可能不够。而第二导电线用于接地端(GND)连接，它的线宽都远远大于VGH、VGL的线宽，所以可以排泄掉的电流会比原本来的大，以达到更好的防护效果。所述第二放电单元包括一端与所述公共端连接的第一导电线，所述公共端与所述显示面板的公共电压端连接。而第二导电线用于公共电压端(VCOM)连接，它的线宽都远远大于VGH、VGL的线宽，所以可以排泄掉的电流会比原本来的大，以达到更好的防护效果。其中，所述显示面板包括栅极集成电路，所述高电平接线端、所述低电平接线端分别于所述栅极集成电路的薄膜晶体管开启电压端和薄膜晶体管关闭电压端连接。
作为本申请的又一个实施例，所述显示面板包括：基板，设有多个像素区；静电放电电路，所述静电放电电路设置在所述基板上；所述静电放电电路包括与所述显示面板的元器件耦合的高电平接线端、低电平接线端、静电输入端以及公共端；以及第一放电单元：所述第一放电单元的输出端分别与高电平接线端和低电平接线端连接，所述第一放电单元的控制端和输入端与所述静电输入 端连接；第二放电单元：所述第二放电单元的输入端与所述静电输入端连接，所述第二放电单元的输出端与所述公共端连接。其中，所述第一放电单元包括一个第一薄膜晶体管和一个第二薄膜晶体管，所述第一薄膜晶体管的输出端与所述高电平接线端连接，第一薄膜晶体管的输入端、所述第二薄膜晶体管的输出端与所述静电输入端连接，所述第二薄膜晶体管的输入端与所述低电平接线端连接。两个相连接的第一放电单元和第二放电单元共同作用，第二放电单元的另一端与公共端连接，增加ESD放电电流路径，泄流的速度和数量得以加大，实现对显示面板更好的保护效果，延长使用寿命。所述第二放电电路包括一个第三薄膜晶体管、一个电容，所述第三薄膜晶体管的输入端和控制端与所述静电输入端连接，所述第三薄膜晶体管的输出端与所述公共端连接。第二放电单元通过第三薄膜晶体管泄流，设置简单，有效可靠。所述电容的第一端与所述静电输入端连接，所述电容的第二端与所述第三薄膜晶体管的控制端连接。利用电容具有隔直流、通交流，通高频、阻低频的特性，电压笵围在VGL～VGH时，第二放电单元不参与作用。同时电压笵围不在VGL～VGH时，例如瞬间有个正的大电压时，第二放电单元能够正常工作，不产生经第二薄膜晶体管留下VGL的电流。所以如果PIN的输入电压笵围在VGL～VGH间因为电容在直流电流中可视为开路，这个电容和薄膜晶体管是不会动作的。
具体的，如图3所示，所述第一薄膜晶体管、第二薄膜晶体管为N型薄膜晶体管：第一N型薄膜晶体管、第二N型薄膜晶体管，所述第一N型薄膜晶体管的源极与所述高电平接线端连接，第一N型薄膜晶体管的栅极和漏极相连接并与所述第二N型薄膜晶体管的源极连接，所述第二N型薄膜晶体管的源极还与所述静电输入端连接，所述第二N型薄膜晶体管的栅极和漏极相连接并与所述低电平接线端连接；所述第三N型薄膜晶体管的源极与第一N型薄膜晶体管的栅极连接，所述第三N型薄膜晶体管的漏极与所述公共端连接，所述公共端接地连接，所述电容的第一端与所述静电输入端连接，所述电容的第二端与所述第三N型薄膜晶体管的栅极连接。
当PIN瞬间有个正的大电压进来时，则第一N型薄膜晶体管导通，有第一放电电流产生。由于PIN电位瞬间变高，电容耦合特效下，电容的第二端与第三N型薄膜晶体管的栅极连接之间的点的电位也同时变大，则第三N型薄膜晶体管也导通，此时PIN的正的大电压可以往GND泄流。因为GND的走线通常比VGL粗，所以相对应的电阻值远小于VGL的，故第二放电电流大于第一放电电流。
当然，第一放电单元可以使用P型薄膜晶体管，或者N型薄膜晶体管和P型薄膜晶体管搭配使用。比如，所述第一薄膜晶体管、第二薄膜晶体管为P型薄膜晶体管：第一P型薄膜晶体管、第二P型薄膜晶体管，所述第一P型薄膜晶体管的栅极和漏极相连接并与所述高电平接线端连接，所述第一P型薄膜晶体管的源极与所述静电输入端连接，所述第二P型薄膜晶体管的栅极和漏极相连接并与所述第一P型薄膜晶体管的源极连接，所述第二P型薄膜晶体管的源极与所述低电平接线端连接。
作为本申请的又一个实施例，所述显示面板包括：基板，设有多个像素区；静电放电电路，所述静电放电电路设置在所述基板上；所述静电放电电路包括与所述显示面板的元器件耦合的高电平接线端、低电平接线端、静电输入端以及公共端；以及第一放电单元：所述第一放电单元的输出端分别与高电平接线端和低电平接线端连接，所述第一放电单元的控制端和输入端与所述静电输入端连接；第二放电单元：所述第二放电单元的输入端与所述静电输入端连接，所述第二放电单元的输出端与所述公共端连接。其中，所述第一放电单元包括一个第一薄膜晶体管和一个第二薄膜晶体管，所述第一薄膜晶体管的输出端与所述高电平接线端连接，第一薄膜晶体管的输入端、所述第二薄膜晶体管的输出端与所述静电输入端连接，所述第二薄膜晶体管的输入端与所述低电平接线端连接。两个相连接的第一放电单元和第二放电单元共同作用，第二放电单元的另一端与公共端连接，增加ESD放电电流路径，泄流的速度和数量得以加大，实现对显示面板更好的保护效果，延长使用寿命。所述第二放电电路包括一个 第三薄膜晶体管、一个电容、一个第四薄膜晶体管，所述第三薄膜晶体管的输入端和控制端与所述静电输入端连接，所述第三薄膜晶体管的输出端与所述公共端连接。第二放电单元通过第三薄膜晶体管泄流，设置简单，有效可靠。所述电容的第一端与所述静电输入端连接，所述电容的第二端与所述第三薄膜晶体管的控制端连接。利用电容具有隔直流、通交流，通高频、阻低频的特性，电压笵围在VGL～VGH时，第二放电单元不参与作用。同时电压笵围不在VGL～VGH时，例如瞬间有个正的大电压时，第二放电单元能够正常工作，不产生经第二薄膜晶体管留下VGL的电流。所以如果PIN的输入电压笵围在VGL～VGH间因为电容在直流电流中可视为开路，这个电容和薄膜晶体管是不会动作的。所述第四薄膜晶体管的输入端与所述电容的第二端连接，所述第四薄膜晶体管的控制端与所述高电平接线端连接，所述第四薄膜晶体管的输出端与所述低电平接线端连接，或者，所述第四薄膜晶体管的控制端与所述低电平接线端连接，所述第四薄膜晶体管的输出端与所述高电平接线端连接。第四薄膜晶体管的导通进一步完成第二放电单元的放电功用，同时将电容的第二端的电位拉到与公共端一致，这样当电压笵围在VGL～VGH时，第三薄膜晶体管不至于导通放电而影响保护电路的正常工作。
具体的，如图4-5所示，图5可以看作图4的实际等效电路，所述第一薄膜晶体管、第二薄膜晶体管为N型薄膜晶体管：第一N型薄膜晶体管、第二N型薄膜晶体管，所述第一N型薄膜晶体管的源极与所述高电平接线端连接，第一N型薄膜晶体管的栅极和漏极相连接并与所述第二N型薄膜晶体管的源极连接，所述第二N型薄膜晶体管的源极还与所述静电输入端连接，所述第二N型薄膜晶体管的栅极和漏极相连接并与所述低电平接线端连接；所述第二放电电路包括一个第三N型薄膜晶体管、一个电容、一个第四N型薄膜晶体管，所述第三N型薄膜晶体管的源极与第一N型薄膜晶体管的栅极连接，所述第三N型薄膜晶体管的漏极与所述公共端连接，所述公共端接地连接，所述电容的第一端与所述静电输入端连接，所述电容的第二端与所述第三N型薄膜晶体管的栅极连 接，所述第四N型薄膜晶体管的源极与所述电容的第二端连接，所述第四N型薄膜晶体管的栅极与所述高电平接线端连接，所述第四N型薄膜晶体管的漏极与所述低电平接线端连接。这里是保护电路的一个实施方式，明确具体采用的电元件以及连接关系。由于PIN电位瞬间变高，电容耦合特效下，电容的第二端与第三N型薄膜晶体管的栅极连接之间的点的电位也同时变大，则第三N型薄膜晶体管也导通，此时PIN的正的大电压可以往GND泄流。因为GND的走线通常比VGL粗，所以相对应的电阻值远小于VGL的，故第二放电电流大于第一放电电流。而第四N型薄膜晶体管也会同时把电容的第二端与第三N型薄膜晶体管的栅极连接之间的点的电位拉到GND。所以当PIN瞬间有个大的正电压进来时，泄掉的电流为第一放电电流、第二放电电路与第三放电电流的和值更大，相比第一放电单元的单独作用总的泄流电流较大，有更好的保护效果。
当然，第一放电单元可以使用P型薄膜晶体管，或者N型薄膜晶体管和P型薄膜晶体管搭配使用。比如，所述第一薄膜晶体管、第二薄膜晶体管为P型薄膜晶体管：第一P型薄膜晶体管、第二P型薄膜晶体管，所述第一P型薄膜晶体管的栅极和漏极相连接并与所述高电平接线端连接，所述第一P型薄膜晶体管的源极与所述静电输入端连接，所述第二P型薄膜晶体管的栅极和漏极相连接并与所述第一P型薄膜晶体管的源极连接，所述第二P型薄膜晶体管的源极与所述低电平接线端连接。
作为本申请的又一个实施例，如图2所示，所述显示面板包括：基板，设有多个像素区；静电放电电路，所述静电放电电路设置在所述基板上；所述静电放电电路包括与所述显示面板的元器件耦合的高电平接线端、低电平接线端、静电输入端以及公共端；以及第一放电单元：所述第一放电单元包括一个第一P型薄膜晶体管和一个第二P型薄膜晶体管，所述第一P型薄膜晶体管的栅极和漏极相连接并与所述高电平接线端连接，所述第一P型薄膜晶体管的源极与所述静电输入端连接，所述第二P型薄膜晶体管的栅极和漏极相连接并与所述第一P型薄膜晶体管的源极连接，所述第二P型薄膜晶体管的源极与所述低电平 接线端连接；第二放电单元：所述第二放电单元的输入端与所述静电输入端连接，所述第二放电单元的输出端与所述公共端连接。本申请由于两个相连接的第一放电单元和第二放电单元共同作用，第二放电单元的另一端与公共端连接，增加ESD放电电流路径，泄流的速度和数量得以加大，实现对显示面板更好的保护效果，延长使用寿命。
具体的，所述第二放电单元包括一端与所述公共端连接的第一导电线，所述公共端接地连接。高电平接线端(VGH)与低电平接线端(VGL)之间的所用的导电线所需的线宽较小，这样相当于会有一个比较大的电阻所，相对的泄流电流也比较小，第一放电单元单独发挥泄流的能力可能不够。而第二导电线用于接地端(GND)连接，它的线宽都远远大于VGH、VGL的线宽，所以可以排泄掉的电流会比原本来的大，以达到更好的防护效果。所述第二放电单元包括一端与所述公共端连接的第一导电线，所述公共端与所述显示面板的公共电压端连接。而第二导电线用于公共电压端(VCOM)连接，它的线宽都远远大于VGH、VGL的线宽，所以可以排泄掉的电流会比原本来的大，以达到更好的防护效果。其中，所述显示面板包括栅极集成电路，所述高电平接线端、所述低电平接线端分别于所述栅极集成电路的薄膜晶体管开启电压端和薄膜晶体管关闭电压端连接。
作为本申请的又一个实施例，所述显示面板包括：基板，设有多个像素区；静电放电电路，所述静电放电电路设置在所述基板上；所述静电放电电路包括与所述显示面板的元器件耦合的高电平接线端、低电平接线端、静电输入端以及公共端；以及第一放电单元：所述第一放电单元包括一个第一P型薄膜晶体管和一个第二P型薄膜晶体管，所述第一P型薄膜晶体管的栅极和漏极相连接并与所述高电平接线端连接，所述第一P型薄膜晶体管的源极与所述静电输入端连接，所述第二P型薄膜晶体管的栅极和漏极相连接并与所述第一P型薄膜晶体管的源极连接，所述第二P型薄膜晶体管的源极与所述低电平接线端连接；第二放电单元：所述第二放电单元的输入端与所述静电输入端连接，所述第二 放电单元的输出端与所述公共端连接。两个相连接的第一放电单元和第二放电单元共同作用，第二放电单元的另一端与公共端连接，增加ESD放电电流路径，泄流的速度和数量得以加大，实现对显示面板更好的保护效果，延长使用寿命。所述第二放电电路包括一个第三薄膜晶体管、一个电容，所述第三薄膜晶体管的输入端和控制端与所述静电输入端连接，所述第三薄膜晶体管的输出端与所述公共端连接。第二放电单元通过第三薄膜晶体管泄流，设置简单，有效可靠。所述第二放电电路包括，所述电容的第一端与所述静电输入端连接，所述电容的第二端与所述第三薄膜晶体管的控制端连接。利用电容具有隔直流、通交流，通高频、阻低频的特性，电压笵围在VGL～VGH时，第二放电单元不参与作用。同时电压笵围不在VGL～VGH时，例如瞬间有个正的大电压时，第二放电单元能够正常工作，不产生经第二薄膜晶体管留下VGL的电流。所以如果PIN的输入电压笵围在VGL～VGH间因为电容在直流电流中可视为开路，这个电容和薄膜晶体管是不会动作的。
具体的，如图6所示，所述第三薄膜晶体管为P型薄膜晶体管：第三P型薄膜晶体管，所述第三P型薄膜晶体管的源极与所述第二P型薄膜晶体管的栅极连接，所述第三P型薄膜晶体管的漏极与所述公共端连接，所述公共端接地连接，所述电容的第一端与所述静电输入端连接，所述电容的第二端与所述第三P型薄膜晶体管的栅极连接。由于PIN电位瞬间变高，电容耦合特效下，电容的第二端与第三N型薄膜晶体管的栅极连接之间的点的电位也同时变大，则第三N型薄膜晶体管也导通，此时PIN的正的大电压可以往GND泄流。因为GND的走线通常比VGL粗，所以相对应的电阻值远小于VGL的，故第二放电电流大于第一放电电流。
作为本申请的又一个实施例，所述显示面板包括：基板，设有多个像素区；静电放电电路，所述静电放电电路设置在所述基板上；所述静电放电电路包括与所述显示面板的元器件耦合的高电平接线端、低电平接线端、静电输入端以及公共端；以及第一放电单元：所述第一放电单元包括一个第一P型薄膜晶体 管和一个第二P型薄膜晶体管，所述第一P型薄膜晶体管的栅极和漏极相连接并与所述高电平接线端连接，所述第一P型薄膜晶体管的源极与所述静电输入端连接，所述第二P型薄膜晶体管的栅极和漏极相连接并与所述第一P型薄膜晶体管的源极连接，所述第二P型薄膜晶体管的源极与所述低电平接线端连接；第二放电单元：所述第二放电单元的输入端与所述静电输入端连接，所述第二放电单元的输出端与所述公共端连接。两个相连接的第一放电单元和第二放电单元共同作用，第二放电单元的另一端与公共端连接，增加ESD放电电流路径，泄流的速度和数量得以加大，实现对显示面板更好的保护效果，延长使用寿命。所述第二放电电路包括一个第三薄膜晶体管、一个电容、一个第四薄膜晶体管，所述第三薄膜晶体管的输入端和控制端与所述静电输入端连接，所述第三薄膜晶体管的输出端与所述公共端连接。第二放电单元通过第三薄膜晶体管泄流，设置简单，有效可靠。所述第二放电电路包括，所述电容的第一端与所述静电输入端连接，所述电容的第二端与所述第三薄膜晶体管的控制端连接。利用电容具有隔直流、通交流，通高频、阻低频的特性，电压笵围在VGL～VGH时，第二放电单元不参与作用。同时电压笵围不在VGL～VGH时，例如瞬间有个正的大电压时，第二放电单元能够正常工作，不产生经第二薄膜晶体管留下VGL的电流。所以如果PIN的输入电压笵围在VGL～VGH间因为电容在直流电流中可视为开路，这个电容和薄膜晶体管是不会动作的。所述第四薄膜晶体管的控制端与所述低电平接线端连接，所述第四薄膜晶体管的输出端与所述高电平接线端连接。第四薄膜晶体管的导通进一步完成第二放电单元的放电功用，同时将电容的第二端的电位拉到与公共端一致，这样当电压笵围在VGL～VGH时，第三薄膜晶体管不至于导通放电而影响保护电路的正常工作。
具体的，如图7-8所示，图8可以看作图7的实际等效电路，所述第三薄膜晶体管、第四薄膜晶体管为P型薄膜晶体管：第三P型薄膜晶体管、第四P型薄膜晶体管，所述第三P型薄膜晶体管的源极与所述第二P型薄膜晶体管的栅极连接，所述第三P型薄膜晶体管的漏极与所述公共端连接，所述公共端接 地连接，所述电容的第一端与所述静电输入端连接，所述电容的第二端与所述第三P型薄膜晶体管的栅极连接，所述第四P型薄膜晶体管的源极与所述电容的第二端连接，所述第四P型薄膜晶体管的栅极与所述低电平接线端连接，所述第四P型薄膜晶体管的漏极与所述高电平接线端连接。由于PIN电位瞬间变高，电容耦合特效下，电容的第二端与第三N型薄膜晶体管的栅极连接之间的点的电位也同时变大，则第三N型薄膜晶体管也导通，此时PIN的正的大电压可以往GND泄流。因为GND的走线通常比VGL粗，所以相对应的电阻值远小于VGL的，故第二放电电流大于第一放电电流。而第四N型薄膜晶体管也会同时把电容的第二端与第三N型薄膜晶体管的栅极连接之间的点的电位拉到GND。所以当PIN瞬间有个大的正电压进来时，泄掉的电流为第一放电电流、第二放电电路与第三放电电流的和值更大，相比第一放电单元的单独作用总的泄流电流较大，有更好的保护效果。
作为本申请的又一个实施例，本申请还公开了一种显示装置，所述显示装置包括背光模组和如上所述的显示面板。
需要说明的是，在上述实施例中，所述基板的材料可以选用玻璃、塑料等。
在上述实施例中，显示面板包括液晶面板、OLED(Organic Light-Emitting Diode)面板、曲面面板、等离子面板等，以液晶面板为例，液晶面板包括阵列基板(Thin Film Transistor Substrate，TFT Substrate)和彩膜基板(Color Filter Substrate，CF Substrate)，所述阵列基板与彩膜基板相对设置，所述阵列基板与彩膜基板之间设有液晶和间隔单元(PS，photo spacer)，所述阵列基板上设有薄膜晶体管(TFT，Thin Film Transistor)，彩膜基板上设有彩色滤光层。
在上述实施例中，彩膜基板可包括TFT阵列，彩膜及TFT阵列可形成于同一基板上，阵列基板可包括彩色滤光层。
在上述实施例中，本申请的显示面板可为曲面型面板。
以上内容是结合具体的优选实施方式对本申请所作的进一步详细说明，不 能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (20)

  1. 一种显示面板，包括：
    基板，设有多个像素区；
    静电放电电路，所述静电放电电路设置在所述基板上；
    所述静电放电电路包括与所述显示面板的元器件耦合的高电平接线端、低电平接线端、静电输入端以及公共端；以及
    第一放电单元：所述第一放电单元的输出端分别与高电平接线端和低电平接线端连接，所述第一放电单元的控制端和输入端与所述静电输入端连接；
    第二放电单元：所述第二放电单元的输入端与所述静电输入端连接，所述第二放电单元的输出端与所述公共端连接；
    所述第一放电电路包括一个第一N型薄膜晶体管和一个第二N型薄膜晶体管，所述第一N型薄膜晶体管的源极与所述高电平接线端连接，第一N型薄膜晶体管的栅极和漏极相连接并与所述第二N型薄膜晶体管的源极连接，所述第二N型薄膜晶体管的源极还与所述静电输入端连接，所述第二N型薄膜晶体管的栅极和漏极相连接并与所述低电平接线端连接；
    所述第二放电电路包括一个第三N型薄膜晶体管、一个电容、一个第四N型薄膜晶体管，所述第三N型薄膜晶体管的源极与第一N型薄膜晶体管的栅极连接，所述第三N型薄膜晶体管的漏极与所述公共端连接，所述公共端接地连接，所述电容的第一端与所述静电输入端连接，所述电容的第二端与所述第三N型薄膜晶体管的栅极连接，所述第四N型薄膜晶体管的源极与所述电容的第二端连接，所述第四N型薄膜晶体管的栅极与所述高电平接线端连接，所述第四N型薄膜晶体管的漏极与所述低电平接线端连接；所述显示面板包括栅极集成电路，所述高电平接线端、所述低电平接线端分别于所述栅极集成电路的薄膜晶体管开启电压端和薄膜晶体管关闭电压端连接。
  2. 一种显示面板，包括：
    基板，设有多个像素区；
    静电放电电路，所述静电放电电路设置在所述基板上；
    所述静电放电电路包括与所述显示面板的元器件耦合的高电平接线端、低电平接线端、静电输入端以及公共端；以及
    第一放电单元：所述第一放电单元的输出端分别与高电平接线端和低电平接线端连接，所述第一放电单元的控制端和输入端与所述静电输入端连接；
    第二放电单元：所述第二放电单元的输入端与所述静电输入端连接，所述第二放电单元的输出端与所述公共端连接。
  3. 如权利要求2所述的显示面板，其中，所述第二放电单元包括一端与所述公共端连接的第一导电线，所述公共端接地连接。
  4. 如权利要求2所述的显示面板，其中，所述第二放电单元包括一端与所述公共端连接的第一导电线，所述公共端与所述显示面板的公共电压端连接。
  5. 如权利要求2所述的显示面板，其中，所述第二放电电路包括一个第三薄膜晶体管，所述第三薄膜晶体管的输入端和控制端与所述静电输入端连接，所述第三薄膜晶体管的输出端与所述公共端连接。
  6. 如权利要求5所述的显示面板，其中，所述第二放电电路包括一个电容，所述电容的第一端与所述静电输入端连接，所述电容的第二端与所述第三薄膜晶体管的控制端连接。
  7. 如权利要求2所述的显示面板，其中，所述第二放电电路包括一个第三薄膜晶体管，所述第三薄膜晶体管的输入端和控制端与所述静电输入端连接，所述第三薄膜晶体管的输出端与所述公共端连接；所述第二放电电路包括一个电容，所述电容的第一端与所述静电输入端连接，所述电容的第二端与所述第三薄膜晶体管的控制端连接。
  8. 如权利要求6所述的显示面板，其中，所述第二放电电路包括一个第四薄膜晶体管，所述第四薄膜晶体管的输入端与所述电容的第二端连接，所述第四薄膜晶体管的控制端与所述高电平接线端连接，所述第四薄膜晶体管的输出 端与所述低电平接线端连接，或者，所述第四薄膜晶体管的控制端与所述低电平接线端连接，所述第四薄膜晶体管的输出端与所述高电平接线端连接。
  9. 如权利要求2所述的显示面板，其中，所述第二放电电路包括一个第三薄膜晶体管，所述第三薄膜晶体管的输入端和控制端与所述静电输入端连接，所述第三薄膜晶体管的输出端与所述公共端连接；所述第二放电电路包括一个电容，所述电容的第一端与所述静电输入端连接，所述电容的第二端与所述第三薄膜晶体管的控制端连接；所述第二放电电路包括一个第四薄膜晶体管，所述第四薄膜晶体管的输入端与所述电容的第二端连接，所述第四薄膜晶体管的控制端与所述高电平接线端连接，所述第四薄膜晶体管的输出端与所述低电平接线端连接，或者，所述第四薄膜晶体管的控制端与所述低电平接线端连接，所述第四薄膜晶体管的输出端与所述高电平接线端连接。
  10. 如权利要求2所述的显示面板，其中，所述第二放电单元包括一端与所述公共端连接的第一导电线，所述公共端接地连接；所述第二放电电路包括一个第三薄膜晶体管，所述第三薄膜晶体管的输入端和控制端与所述静电输入端连接，所述第三薄膜晶体管的输出端与所述公共端连接；所述第二放电电路包括一个电容，所述电容的第一端与所述静电输入端连接，所述电容的第二端与所述第三薄膜晶体管的控制端连接；所述第二放电电路包括一个第四薄膜晶体管，所述第四薄膜晶体管的输入端与所述电容的第二端连接，所述第四薄膜晶体管的控制端与所述高电平接线端连接，所述第四薄膜晶体管的输出端与所述低电平接线端连接，或者，所述第四薄膜晶体管的控制端与所述低电平接线端连接，所述第四薄膜晶体管的输出端与所述高电平接线端连接。
  11. 如权利要求2所述的显示面板，其中，所述第二放电单元包括一端与所述公共端连接的第一导电线，所述公共端与所述显示面板的公共电压端连接；所述第二放电电路包括一个第三薄膜晶体管，所述第三薄膜晶体管的输入端和控制端与所述静电输入端连接，所述第三薄膜晶体管的输出端与所述公共端连接；所述第二放电电路包括一个电容，所述电容的第一端与所述静电输入端连 接，所述电容的第二端与所述第三薄膜晶体管的控制端连接；所述第二放电电路包括一个第四薄膜晶体管，所述第四薄膜晶体管的输入端与所述电容的第二端连接，所述第四薄膜晶体管的控制端与所述高电平接线端连接，所述第四薄膜晶体管的输出端与所述低电平接线端连接，或者，所述第四薄膜晶体管的控制端与所述低电平接线端连接，所述第四薄膜晶体管的输出端与所述高电平接线端连接。
  12. 如权利要求2所述的显示面板，其中，所述第一放电电路包括一个第一N型薄膜晶体管和一个第二N型薄膜晶体管，所述第一N型薄膜晶体管的源极与所述高电平接线端连接，第一N型薄膜晶体管的栅极和漏极相连接并与所述第二N型薄膜晶体管的源极连接，所述第二N型薄膜晶体管的源极还与所述静电输入端连接，所述第二N型薄膜晶体管的栅极和漏极相连接并与所述低电平接线端连接；
    所述第二放电电路包括一个第三N型薄膜晶体管、一个电容、一个第四N型薄膜晶体管，所述第三N型薄膜晶体管的源极与第一N型薄膜晶体管的栅极连接，所述第三N型薄膜晶体管的漏极与所述公共端连接，所述公共端接地连接，所述电容的第一端与所述静电输入端连接，所述电容的第二端与所述第三N型薄膜晶体管的栅极连接，所述第四N型薄膜晶体管的源极与所述电容的第二端连接，所述第四N型薄膜晶体管的栅极与所述高电平接线端连接，所述第四N型薄膜晶体管的漏极与所述低电平接线端连接。
  13. 如权利要求2所述的显示面板，其中，所述第一放电电路包括一个第一P型薄膜晶体管和一个第二P型薄膜晶体管，所述第一P型薄膜晶体管的栅极和漏极相连接并与所述高电平接线端连接，所述第一P型薄膜晶体管的源极与所述静电输入端连接，所述第二P型薄膜晶体管的栅极和漏极相连接并与所述第一P型薄膜晶体管的源极连接，所述第二P型薄膜晶体管的源极与所述低电平接线端连接；
    所述第二放电电路包括一个第三N型薄膜晶体管、一个电容、一个第四N 型薄膜晶体管，所述第三N型薄膜晶体管的源极与第一N型薄膜晶体管的栅极连接，所述第三N型薄膜晶体管的漏极与所述公共端连接，所述公共端接地连接，所述电容的第一端与所述静电输入端连接，所述电容的第二端与所述第三N型薄膜晶体管的栅极连接，所述第四N型薄膜晶体管的源极与所述电容的第二端连接，所述第四N型薄膜晶体管的栅极与所述高电平接线端连接，所述第四N型薄膜晶体管的漏极与所述低电平接线端连接。
  14. 如权利要求2所述的显示面板，其中，所述第一放电电路包括一个第一P型薄膜晶体管和一个第二P型薄膜晶体管，所述第一P型薄膜晶体管的栅极和漏极相连接并与所述高电平接线端连接，所述第一P型薄膜晶体管的源极与所述静电输入端连接，所述第二P型薄膜晶体管的栅极和漏极相连接并与所述第一P型薄膜晶体管的源极连接，所述第二P型薄膜晶体管的源极与所述低电平接线端连接；
    所述第二放电电路包括一个第三P型薄膜晶体管、一个电容、一个第四P型薄膜晶体管，所述第三P型薄膜晶体管的源极与所述第二P型薄膜晶体管的栅极连接，所述第三P型薄膜晶体管的漏极与所述公共端连接，所述公共端接地连接，所述电容的第一端与所述静电输入端连接，所述电容的第二端与所述第三P型薄膜晶体管的栅极连接，所述第四P型薄膜晶体管的源极与所述电容的第二端连接，所述第四P型薄膜晶体管的栅极与所述低电平接线端连接，所述第四P型薄膜晶体管的漏极与所述高电平接线端连接。
  15. 如权利要求2所述的显示面板，其中，所述显示面板包括栅极集成电路，所述高电平接线端、所述低电平接线端分别于所述栅极集成电路的薄膜晶体管开启电压端和薄膜晶体管关闭电压端连接。
  16. 如权利要求2所述的显示面板，其中，所述第二放电单元包括一端与所述公共端连接的第一导电线，所述公共端接地连接；所述第二放电电路包括一个第三薄膜晶体管，所述第三薄膜晶体管的输入端和控制端与所述静电输入端连接，所述第三薄膜晶体管的输出端与所述公共端连接；所述第二放电电路 包括一个电容，所述电容的第一端与所述静电输入端连接，所述电容的第二端与所述第三薄膜晶体管的控制端连接；所述第二放电电路包括一个第四薄膜晶体管，所述第四薄膜晶体管的输入端与所述电容的第二端连接，所述第四薄膜晶体管的控制端与所述高电平接线端连接，所述第四薄膜晶体管的输出端与所述低电平接线端连接，或者，所述第四薄膜晶体管的控制端与所述低电平接线端连接，所述第四薄膜晶体管的输出端与所述高电平接线端连接，所述显示面板包括栅极集成电路，所述高电平接线端、所述低电平接线端分别于所述栅极集成电路的薄膜晶体管开启电压端和薄膜晶体管关闭电压端连接。
  17. 如权利要求2所述的显示面板，其中，所述第二放电单元包括一端与所述公共端连接的第一导电线，所述公共端与所述显示面板的公共电压端连接；所述第二放电电路包括一个第三薄膜晶体管，所述第三薄膜晶体管的输入端和控制端与所述静电输入端连接，所述第三薄膜晶体管的输出端与所述公共端连接；所述第二放电电路包括一个电容，所述电容的第一端与所述静电输入端连接，所述电容的第二端与所述第三薄膜晶体管的控制端连接；所述第二放电电路包括一个第四薄膜晶体管，所述第四薄膜晶体管的输入端与所述电容的第二端连接，所述第四薄膜晶体管的控制端与所述高电平接线端连接，所述第四薄膜晶体管的输出端与所述低电平接线端连接，或者，所述第四薄膜晶体管的控制端与所述低电平接线端连接，所述第四薄膜晶体管的输出端与所述高电平接线端连接，所述显示面板包括栅极集成电路，所述高电平接线端、所述低电平接线端分别于所述栅极集成电路的薄膜晶体管开启电压端和薄膜晶体管关闭电压端连接。
  18. 如权利要求2所述的显示面板，其中，所述第一放电电路包括一个第一N型薄膜晶体管和一个第二N型薄膜晶体管，所述第一N型薄膜晶体管的源极与所述高电平接线端连接，第一N型薄膜晶体管的栅极和漏极相连接并与所述第二N型薄膜晶体管的源极连接，所述第二N型薄膜晶体管的源极还与所述静电输入端连接，所述第二N型薄膜晶体管的栅极和漏极相连接并与所述低电 平接线端连接；
    所述第二放电电路包括一个第三N型薄膜晶体管、一个电容、一个第四N型薄膜晶体管，所述第三N型薄膜晶体管的源极与第一N型薄膜晶体管的栅极连接，所述第三N型薄膜晶体管的漏极与所述公共端连接，所述公共端接地连接，所述电容的第一端与所述静电输入端连接，所述电容的第二端与所述第三N型薄膜晶体管的栅极连接，所述第四N型薄膜晶体管的源极与所述电容的第二端连接，所述第四N型薄膜晶体管的栅极与所述高电平接线端连接，所述第四N型薄膜晶体管的漏极与所述低电平接线端连接，所述显示面板包括栅极集成电路，所述高电平接线端、所述低电平接线端分别于所述栅极集成电路的薄膜晶体管开启电压端和薄膜晶体管关闭电压端连接。
  19. 如权利要求2所述的显示面板，其中，所述第一放电电路包括一个第一P型薄膜晶体管和一个第二P型薄膜晶体管，所述第一P型薄膜晶体管的栅极和漏极相连接并与所述高电平接线端连接，所述第一P型薄膜晶体管的源极与所述静电输入端连接，所述第二P型薄膜晶体管的栅极和漏极相连接并与所述第一P型薄膜晶体管的源极连接，所述第二P型薄膜晶体管的源极与所述低电平接线端连接；
    所述第二放电电路包括一个第三N型薄膜晶体管、一个电容、一个第四N型薄膜晶体管，所述第三N型薄膜晶体管的源极与第一N型薄膜晶体管的栅极连接，所述第三N型薄膜晶体管的漏极与所述公共端连接，所述公共端接地连接，所述电容的第一端与所述静电输入端连接，所述电容的第二端与所述第三N型薄膜晶体管的栅极连接，所述第四N型薄膜晶体管的源极与所述电容的第二端连接，所述第四N型薄膜晶体管的栅极与所述高电平接线端连接，所述第四N型薄膜晶体管的漏极与所述低电平接线端连接，所述显示面板包括栅极集成电路，所述高电平接线端、所述低电平接线端分别于所述栅极集成电路的薄膜晶体管开启电压端和薄膜晶体管关闭电压端连接。
  20. 如权利要求2所述的显示面板，其中，所述第一放电电路包括一个第 一P型薄膜晶体管和一个第二P型薄膜晶体管，所述第一P型薄膜晶体管的栅极和漏极相连接并与所述高电平接线端连接，所述第一P型薄膜晶体管的源极与所述静电输入端连接，所述第二P型薄膜晶体管的栅极和漏极相连接并与所述第一P型薄膜晶体管的源极连接，所述第二P型薄膜晶体管的源极与所述低电平接线端连接；
    所述第二放电电路包括一个第三P型薄膜晶体管、一个电容、一个第四P型薄膜晶体管，所述第三P型薄膜晶体管的源极与所述第二P型薄膜晶体管的栅极连接，所述第三P型薄膜晶体管的漏极与所述公共端连接，所述公共端接地连接，所述电容的第一端与所述静电输入端连接，所述电容的第二端与所述第三P型薄膜晶体管的栅极连接，所述第四P型薄膜晶体管的源极与所述电容的第二端连接，所述第四P型薄膜晶体管的栅极与所述低电平接线端连接，所述第四P型薄膜晶体管的漏极与所述高电平接线端连接，所述显示面板包括栅极集成电路，所述高电平接线端、所述低电平接线端分别于所述栅极集成电路的薄膜晶体管开启电压端和薄膜晶体管关闭电压端连接。
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