WO2019015235A1 - 静电放电电路和显示面板 - Google Patents

静电放电电路和显示面板 Download PDF

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Publication number
WO2019015235A1
WO2019015235A1 PCT/CN2017/115797 CN2017115797W WO2019015235A1 WO 2019015235 A1 WO2019015235 A1 WO 2019015235A1 CN 2017115797 W CN2017115797 W CN 2017115797W WO 2019015235 A1 WO2019015235 A1 WO 2019015235A1
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Prior art keywords
transistor
discharge unit
type transistor
common
terminal
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Application number
PCT/CN2017/115797
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English (en)
French (fr)
Inventor
陈猷仁
Original Assignee
惠科股份有限公司
重庆惠科金渝光电科技有限公司
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Priority to US16/632,055 priority Critical patent/US10937384B2/en
Publication of WO2019015235A1 publication Critical patent/WO2019015235A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation

Definitions

  • the present application relates to the field of display technologies, and in particular, to an electrostatic discharge circuit and a display panel.
  • the liquid crystal display has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • Most of the liquid crystal displays on the market are backlight type liquid crystal displays, which include a liquid crystal panel and a backlight module.
  • the working principle of the liquid crystal panel is to place liquid crystal molecules in two parallel glass substrates, and apply a driving voltage on the two glass substrates to control the rotation direction of the liquid crystal molecules to refract the light of the backlight module to generate a picture.
  • a thin film transistor liquid crystal display includes a liquid crystal panel including a color filter substrate (CF Substrate, also referred to as a color filter substrate) and a thin film transistor array substrate (Thin Film Transistor Substrate, TFT Substrate).
  • CF Substrate also referred to as a color filter substrate
  • TFT Substrate Thin Film Transistor Substrate
  • a transparent electrode is present on the opposite inner side of the substrate.
  • a layer of liquid crystal molecules (LC) is sandwiched between the two substrates.
  • ESD Electrostatic Discharge
  • the technical problem to be solved by the present application is to provide a reliable and effective electrostatic discharge circuit for the protection circuit.
  • the present application also provides a display panel including the above electrostatic discharge circuit.
  • An electrostatic discharge circuit includes a first discharge unit, a second discharge unit, and a third discharge unit.
  • the first discharge unit includes a first transistor and a second transistor, a source of the first transistor is connected to a high level terminal, and a gate and a drain of the first transistor are connected to form a first a second transistor having a gate and a drain connected to form a second a first pole connected to the second pole and connected to an electrostatic input terminal, a source of the second transistor being connected to a low level terminal; and an input end of the second discharge unit
  • the electrostatic input end is connected, the output end of the second discharge unit is connected to a common end; the input end of the third discharge unit is connected to the electrostatic input end, and the output end of the third discharge unit is Said public connection.
  • the second discharge unit includes a first conductive line connected to the common end at one end, and the common end is grounded; or the second discharge unit includes a first conductive line connected to the common end at one end.
  • the electrostatic discharge circuit is disposed on the display panel, and the common end is connected to a common voltage end of the display panel.
  • the line width required between the high-level terminal (VGH) and the low-level terminal (VGL) is smaller, which is equivalent to having a larger resistance, and the relative leakage current is also compared. Small, the ability of the first discharge unit to exert a separate discharge may not be sufficient.
  • the first conductive line is used for the ground (GND) connection; or the first conductive line is used for the common voltage terminal (VCOM) connection, and its line width is much larger than the line width of VGH and VGL, so it can be drained.
  • the current will be larger than originally designed to achieve better protection.
  • the third discharge unit includes a second conductive line connected to the common end at one end, and the common end is connected to the ground; or the third discharge unit includes a second conductive line connected to the common end at one end.
  • the common end is connected to a common voltage end of the display panel.
  • the line width required between the high-level terminal (VGH) and the low-level terminal (VGL) is smaller, which is equivalent to having a larger resistance, and the relative leakage current is also compared. Small, the ability of the first discharge unit to exert a separate discharge may not be sufficient.
  • the second conductive line is used for the ground (GND) connection; or the second conductive line is used for the common voltage terminal (VCOM) connection, and its line width is much larger than the line width of VGH and VGL, so it can be drained.
  • the current will be larger than originally designed to achieve better protection.
  • the second discharge unit includes a third transistor, an input end and a control end of the third transistor are connected to the electrostatic input end, and an output end of the third transistor is connected to the common end;
  • the third discharge unit includes a fourth transistor, an input end and a control end of the fourth transistor are connected to the electrostatic input end, and an output end of the fourth transistor is connected to the common end.
  • the second discharge unit is drained by the third transistor, and the setting is simple, effective and reliable; and the third discharge unit is discharged through the fourth transistor, and the setting is simple, effective and reliable.
  • the second discharge unit includes a first capacitor, a first end of the first capacitor is connected to the electrostatic input end, and a second end of the first capacitor is connected to a control end of the third transistor
  • the third discharge unit includes a second capacitor, the first end of the second capacitor is connected to the electrostatic input end, and the second end of the second capacitor is connected to the control end of the fourth transistor .
  • the capacitor has the characteristics of blocking DC, AC, high frequency, and low frequency. When the voltage is around VGL to VGH, the second discharge unit and the third discharge unit do not participate.
  • the second discharge unit can work normally, and does not generate a current that leaves VGL through the second transistor; for example, when there is a negative large voltage instantaneously,
  • the third discharge unit can operate normally.
  • the second discharge unit includes a fifth transistor, and an input end of the fifth transistor is connected to a second end of the first capacitor, and a control terminal of the fifth transistor and the high-level terminal Connecting, the output end of the fifth transistor is connected to the low-level terminal;
  • the third discharge unit includes a sixth transistor, an input end of the sixth transistor and a second end of the second capacitor Connected, the control terminal of the sixth transistor is connected to the low-level terminal, and the output terminal of the sixth transistor is connected to the high-level terminal.
  • the conduction of the fifth transistor further completes the discharge function of the second discharge unit, and simultaneously pulls the potential of the second end of the first capacitor to be consistent with the common end, so that when the voltage is around VGL to VGH, the third The transistor does not conduct conduction and discharge and affects the normal operation of the protection circuit.
  • the conduction of the sixth transistor further completes the discharge function of the third discharge unit, and simultaneously pulls the potential of the second end of the second capacitor to be consistent with the common end, so that when the voltage is around VGL to VGH, the fourth The transistor does not conduct conduction and discharge and affects the normal operation of the protection circuit.
  • the first transistor is a first N-type transistor
  • the second transistor is a second P-type transistor
  • the third transistor is a third N-type transistor
  • the fourth transistor is a fourth P-type transistor
  • the fifth transistor is a fifth N-type transistor
  • the sixth transistor is a sixth P-type transistor.
  • the electrostatic discharge circuit clarifies the specific electrical components and connection relationships.
  • the first transistor is a first N-type transistor
  • the second transistor is a second P-type transistor
  • the third transistor is a third P-type transistor
  • the fourth transistor is a fourth N-type transistor
  • the fifth transistor is a fifth N-type transistor
  • the sixth transistor is a sixth P-type transistor.
  • the electrostatic discharge circuit clarifies the specific electrical components and connection relationships.
  • the present application also discloses an electrostatic discharge circuit including a first discharge unit, a second discharge unit, and a third discharge unit.
  • the first The discharge unit includes a first N-type transistor and a second P-type transistor, the source of the first N-type transistor is connected to a high-level terminal, and the gate and drain phases of the first N-type transistor Connecting to form a first pole, a gate and a drain of the second P-type transistor are connected to form a second pole, and the first pole is connected to the second pole and connected to an electrostatic input end, a source of the second P-type transistor is connected to a low-level terminal;
  • the second discharge unit includes a third N-type transistor, a first capacitor, a fifth N-type transistor, and the third N-type transistor a source is connected to a gate of the first N-type transistor, a drain of the third N-type transistor is connected to a common terminal, the common terminal is grounded, a first end of the first capacitor is An electrostatic input is connected,
  • the third discharge unit includes a fourth P-type transistor, a second capacitor, and a a sixth P-type transistor, a source of the fourth P-type transistor is connected to a gate of the second P-type transistor, and a drain of the fourth P-type transistor is connected to the common end, the common end a ground connection, a first end of the second capacitor is connected to the electrostatic input end, a second end of the second capacitor is connected to a gate of the fourth P-type transistor, and the sixth P-type transistor is a source is connected to the second end of the second capacitor, a gate of the sixth P-type transistor is connected to the low-level terminal, and a drain of the sixth P-type transistor is opposite to the high level
  • the third discharge unit is used for discharging when a negative
  • the present application also discloses a display panel including a substrate, a signal line, and an electrostatic discharge circuit.
  • An active switch is disposed on the substrate; the signal line is disposed on the substrate and coupled to the active switch, the signal line includes a plurality of scan lines and a plurality of data lines, and the plurality of the data lines are A plurality of the scan lines are sequentially disposed to form a plurality of pixel regions; the electrostatic discharge circuit is disposed on the substrate.
  • the display panel further includes: a gate driving circuit and a source driving circuit, wherein the gate driving circuit and the source driving circuit are disposed on the substrate.
  • the second discharge unit and the third discharge unit are connected to the first discharge unit, the second discharge can be respectively performed outside the first discharge unit regardless of whether a positive or negative large voltage comes in at the electrostatic input end.
  • the unit and the third discharge unit increase the ESD discharge current path, and the speed and quantity of the discharge are increased, thereby achieving better protection effect on the display panel and prolonging the service life.
  • FIG. 1 is a schematic diagram of an electrostatic discharge circuit of a display panel according to an embodiment of the present application
  • FIG. 2 is a schematic diagram of an electrostatic discharge circuit of a display panel according to an embodiment of the present application
  • FIG. 3 is a schematic diagram of an electrostatic discharge circuit of a display panel according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of an electrostatic discharge circuit of a display panel according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a display panel according to an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a display device according to an embodiment of the present application.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, features defining “first” and “second” may include one or more of the features either explicitly or implicitly.
  • a plurality means two or more unless otherwise stated.
  • the term “comprises” and its variations are intended to cover a non-exclusive inclusion.
  • connection In the description of the present application, it should be noted that the terms “installation”, “connected”, and “connected” are to be understood broadly, and may be fixed or detachable, for example, unless otherwise explicitly defined and defined. Connected, or integrally connected; can be mechanical or electrical; can be directly connected, or indirectly connected through an intermediate medium, can be the internal communication of the two components.
  • Connected, or integrally connected can be mechanical or electrical; can be directly connected, or indirectly connected through an intermediate medium, can be the internal communication of the two components.
  • the electrostatic discharge circuit 11 includes a first discharge unit, a second discharge unit 6, and a third discharge unit 7.
  • the first discharge unit includes a first transistor and a second transistor, a source of the first transistor is connected to a high level terminal, and a gate and a drain of the first transistor are connected to form a first a second transistor having a gate and a drain connected to form a second pole, the first pole being connected to the second pole and connected to an electrostatic input terminal 4, a source of the second transistor Connected to a low-level terminal; the input end of the second discharge unit 6 is connected to the electrostatic input terminal 4, and the output end of the second discharge unit 6 is connected to a common terminal 3; the third discharge An input of the unit 7 is connected to the electrostatic input 4, and an output of the third discharge unit 7 is connected to the common 3.
  • Both the second discharge unit 6 and the third discharge unit 7 cooperate with the first discharge unit, and the second discharge can be respectively performed outside the first discharge unit regardless of whether the positive input terminal 4 has a positive or negative large voltage.
  • the unit 6 and the third discharge unit 7 increase the ESD discharge current path, and the speed and the number of the discharge are increased, thereby achieving better protection effect on the display panel and prolonging the service life.
  • the display panel includes a substrate 10, a signal line, and an electrostatic discharge circuit 11.
  • An active switch is disposed on the substrate 10; the signal line is disposed on the substrate 10, and coupled to the active switch, the signal line includes a plurality of scan lines 14 and a plurality of data lines 15, and a plurality of The data line 15 and the plurality of scan lines 14 are sequentially intersected to form a plurality of pixel regions 16; the substrate 10 is provided with an electrostatic discharge circuit 11, a gate drive circuit 12 and a source drive circuit 13, and a horizontally arranged scan
  • the line 14 and the vertically disposed data line 15 are coupled to their corresponding circuits, which may be, for example, thin film transistors.
  • the high level terminal, the low level terminal, the electrostatic input terminal 4, and the common terminal 3 are coupled to components of the display panel.
  • the second discharge unit 6 includes a first conductive line connected to the common end 3 at one end, and the common end 3 is grounded; or the second discharge unit 6 includes one end and the public
  • the first conductive line connected to the common terminal 3 is connected to the common voltage terminal of the display panel.
  • the conductive line used between the high-level terminal (VGH) 1 and the low-level terminal (VGL) 2 requires a smaller line width, which is equivalent to having a relatively large resistance and a relative discharge current. It is also relatively small, and the ability of the first discharge unit to exert a separate discharge may not be sufficient.
  • the first conductive line is used for the ground (GND) connection; or the first conductive line is used for the common voltage terminal (VCOM) connection, and its line width is much larger than the line width of VGH and VGL, so it can be drained.
  • the current will be larger than originally designed to achieve better protection.
  • the third discharge unit 7 includes a second conductive line connected to the common end 3 at one end, and the common end 3 is connected to the ground; or the third discharge unit 7 includes a first end connected to the common end 3 Two conductive lines, the common end 3 being connected to a common voltage end of the display panel.
  • the second conductive line is used for the ground (GND) connection, or the second conductive line is used for the common voltage terminal (VCOM) connection, and its line width is much larger than the line width of VGH and VGL, so it can be drained.
  • the current will be larger than originally designed to achieve better protection.
  • the display panel includes a gate integrated circuit, and the high-level terminal and the low-level terminal are respectively connected to a transistor-on voltage terminal of the gate integrated circuit and a transistor-off voltage terminal.
  • the electrostatic discharge circuit 11 includes a first discharge unit, a second discharge unit 6, and a third discharge unit 7.
  • the first discharge unit includes a first transistor and a second transistor, a source of the first transistor is connected to a high level terminal, and a gate and a drain of the first transistor are connected to form a first a second transistor having a gate and a drain connected to form a second pole, the first pole being connected to the second pole and connected to an electrostatic input terminal 4, a source of the second transistor Connected to a low-level terminal; the input end of the second discharge unit 6 is connected to the electrostatic input terminal 4, and the output end of the second discharge unit 6 is connected to a common terminal 3; the third discharge An input of the unit 7 is connected to the electrostatic input 4, and an output of the third discharge unit 7 is connected to the common 3.
  • Both the second discharge unit 6 and the third discharge unit 7 cooperate with the first discharge unit, and the second discharge can be respectively performed outside the first discharge unit regardless of whether the positive input terminal 4 has a positive or negative large voltage.
  • the unit 6 and the third discharge unit 7 increase the ESD discharge current path, and the speed and the number of the discharge are increased, thereby achieving better protection effect on the display panel and prolonging the service life.
  • the second discharge unit 6 includes a third transistor and a first capacitor 63.
  • the input terminal and the control terminal of the third transistor are connected to the electrostatic input terminal 4, and the output terminal of the third transistor is The common end 3 is connected; the first end of the first capacitor 63 is connected to the electrostatic input end 4, and the second end of the first capacitor 63 is connected to the control end of the third transistor.
  • the third discharge unit 7 includes a fourth transistor and a second capacitor 73, An input end and a control end of the fourth transistor are connected to the electrostatic input terminal 4, and an output end of the fourth transistor is connected to the common terminal 3; a first end of the second capacitor 73 and the electrostatic input end 4 is connected, and the second end of the second capacitor 73 is connected to the control end of the fourth transistor.
  • the second discharge unit 6 and the third discharge unit 7 are respectively discharged through the third transistor and the fourth transistor, and the setting is simple, effective and reliable.
  • the capacitor has a characteristic of blocking DC, AC, high frequency, and low frequency. When the voltage is around VGL to VGH, the second discharge unit 6 and the third discharge unit 7 do not participate.
  • the second discharge unit 6 can work normally, and does not generate a current that leaves the VGL through the second transistor; for example, when there is a negative large voltage instantaneously
  • the third discharge unit 7 can operate normally. Therefore, if the input voltage of the PIN is between VGL and VGH, since the capacitor can be regarded as an open circuit in the DC current, the capacitor and the transistor will not operate.
  • the first discharge unit includes a first N-type transistor 51 and a second P-type transistor 52, and the source of the first N-type transistor 51 is connected to the high level.
  • An end connection, a gate and a drain of the first N-type transistor 51 are connected to form a first pole, and a gate and a drain of the second P-type transistor 52 are connected to form a second pole, the first pole Connected to the second pole and connected to the electrostatic input terminal 4, the source of the second P-type transistor 52 is connected to the low-level terminal;
  • the source of the fourth P-type transistor 71 is connected to the gate of the second P-type transistor 52, the drain of the fourth P-type transistor 71 is connected to the common terminal 3, and the common terminal 3 is connected to the ground.
  • the first end of the second capacitor 73 is connected to the electrostatic input terminal 4, and the second end of the second capacitor 73 is connected to the gate of the fourth P-type transistor 71.
  • the potential of the point between the second end of the first capacitor 63 and the gate of the third N-type transistor 61 also increases at the same time under the capacitive coupling effect, and the third N-type transistor 61 also Turn on, at this time the positive large voltage of the PIN can be discharged to GND. Since the trace of GND is generally thicker than VGL, the corresponding resistance value is much smaller than VGL, so the second discharge current 82 is greater than the first discharge current 81. When a negative large voltage comes in at the moment of the PIN, the second P-type transistor 52 is turned on, and a fourth discharge current 91 is generated.
  • the second end of the second capacitor 73 also becomes negative at the same time, and the fourth P-type transistor 71 Also turned on, the fifth discharge current 92 is generated, at which time the negative large voltage of the PIN can be drained to the GND. Since the trace of GND is generally thicker than VGL, the corresponding resistance value is much smaller than VGL, so the fifth discharge current 92 is greater than the fourth discharge current 91.
  • the electrostatic discharge circuit 11 includes a first discharge unit, a second discharge unit 6, and a third discharge unit 7.
  • the first discharge unit includes a first transistor and a second transistor, a source of the first transistor is connected to a high level terminal, and a gate and a drain of the first transistor are connected to form a first a second transistor having a gate and a drain connected to form a second pole, the first pole being connected to the second pole and connected to an electrostatic input terminal 4, a source of the second transistor Connected to a low-level terminal; the input end of the second discharge unit 6 is connected to the electrostatic input terminal 4, and the output end of the second discharge unit 6 is connected to a common terminal 3; the third discharge An input of the unit 7 is connected to the electrostatic input 4, and an output of the third discharge unit 7 is connected to the common 3.
  • Both the second discharge unit 6 and the third discharge unit 7 cooperate with the first discharge unit, and the second discharge can be respectively performed outside the first discharge unit regardless of whether the positive input terminal 4 has a positive or negative large voltage.
  • the unit 6 and the third discharge unit 7 increase the ESD discharge current path, and the speed and the number of the discharge are increased, thereby achieving better protection effect on the display panel and prolonging the service life.
  • the second discharge unit 6 includes a third transistor, a first capacitor 63 and a fifth transistor, and an input terminal and a control terminal of the third transistor are connected to the electrostatic input terminal 4, and the third transistor An output end is connected to the common end 3; a first end of the first capacitor 63 is connected to the electrostatic input end 4, and a second end of the first capacitor 63 is connected to a control end of the third transistor; An input end of the fifth transistor is connected to a second end of the first capacitor 63, a control end of the fifth transistor is connected to the high level terminal, an output end of the fifth transistor is a low-level terminal is connected; the third discharge unit 7 includes a fourth transistor, a second capacitor 73 and a sixth transistor, and the input terminal and the control terminal of the fourth transistor are connected to the electrostatic input terminal 4.
  • the output end of the fourth transistor is connected to the common terminal 3; the first end of the second capacitor 73 is connected to the electrostatic input terminal 4, and the second end of the second capacitor 73 is opposite to the first a control terminal of the four transistors; the sixth crystal An input end of the body tube is connected to the second end of the second capacitor 73, a control end of the sixth transistor is connected to the low level terminal, and an output end of the sixth transistor is opposite to the high level Terminal connection.
  • the second discharge unit 6 and the third discharge unit 7 are respectively discharged through the third transistor and the fourth transistor, and the setting is simple, effective and reliable.
  • the capacitor has the characteristics of blocking DC, AC, high frequency, and low frequency.
  • the second discharge unit 6 and the third discharge unit 7 are not involved. With the effect.
  • the voltage range is not VGL ⁇ VGH, for example, when there is a positive large voltage in an instant, the second discharge unit 6 can work normally, and does not generate a current that leaves the VGL through the second transistor; for example, when there is a negative large voltage instantaneously
  • the third discharge unit 7 can operate normally.
  • the capacitor can be regarded as an open circuit in the DC current, the capacitor and the transistor will not operate.
  • the conduction of the fifth transistor further completes the discharge function of the second discharge unit 6, while pulling the potential of the second end of the first capacitor 63 to be consistent with the common terminal 3, so that when the voltage is around VGL to VGH
  • the third transistor does not turn on the discharge and affects the normal operation of the protection circuit.
  • the conduction of the sixth transistor further completes the discharge function of the third discharge unit 7, while pulling the potential of the second end of the second capacitor 73 to be consistent with the common terminal 3, so that when the voltage is around VGL to VGH
  • the fourth transistor does not turn on the discharge and affects the normal operation of the protection circuit.
  • FIG. 4 can be regarded as the actual equivalent circuit of FIG.
  • the first discharge unit includes a first N-type transistor 51 and a second P-type transistor 52, and a source of the first N-type transistor 51 is connected to the high-level terminal, the first N-type
  • the gate and the drain of the transistor 51 are connected to form a first pole
  • the gate and the drain of the second P-type transistor 52 are connected to form a second pole
  • the first pole is connected to the second pole and Connected to the electrostatic input terminal 4
  • the source of the second P-type transistor 52 is connected to the low-level terminal
  • the second discharge unit 6 includes a third N-type transistor 61, a first capacitor 63.
  • a fifth N-type transistor 62 a source of the third N-type transistor 61 is connected to a gate of the first N-type transistor 51, and a drain of the third N-type transistor 61 and the common terminal 3 Connecting, the common terminal 3 is connected to the ground, the first end of the first capacitor 63 is connected to the electrostatic input terminal 4, and the second end of the first capacitor 63 is connected to the gate of the third N-type transistor 61.
  • the third discharge unit 7 includes a fourth P-type transistor 71, and a a second capacitor 73, a sixth P-type transistor 72, a source of the fourth P-type transistor 71 is connected to a gate of the second P-type transistor 52, and a drain of the fourth P-type transistor 71
  • the common end 3 is connected, the common end 3 is connected to the ground, the first end of the second capacitor 73 is connected to the electrostatic input end 4, and the second end of the second capacitor 73 is connected to the fourth P
  • the gate of the transistor 71 is connected, the source of the sixth P-type transistor 72 is connected to the second end of the second capacitor 73, and the gate of the sixth P-type transistor 72 is connected to the low level.
  • the drain of the sixth P-type transistor 72 and the high level terminal connection Since the PIN potential becomes high instantaneously, the potential of the point between the second end of the capacitor and the gate connection of the third N-type transistor 61 also becomes larger at the time of the capacitive coupling effect, and the third N-type transistor 61 is also turned on. At this time, the positive large voltage of the PIN can be discharged to the GND. Since the trace of GND is generally thicker than VGL, the corresponding resistance value is much smaller than VGL, so the second discharge current 82 is greater than the first discharge current 81.
  • the fifth N-type transistor 62 also pulls the potential of the point between the second end of the first capacitor 63 and the gate connection of the third N-type transistor 61 to GND. Therefore, when a large positive voltage comes in at the moment of the PIN, the current discharged is the sum of the first discharge current 81, the second discharge current 82 and the third discharge current 83, which is larger than the first discharge unit. The total discharge current is large and has a better protection effect. Since the PIN potential instantaneously becomes negative, under the capacitive coupling effect, the second end of the second capacitor 73 also becomes negative at the same time, the fourth P-type transistor 71 is also turned on, and the fifth discharge current 92 is generated, and the PIN is negatively large at this time.
  • the voltage can be drained to GND. Since the trace of GND is generally thicker than VGL, the corresponding resistance value is much smaller than VGL, so the fifth discharge current 92 is greater than the fourth discharge current 91.
  • the sixth P-type transistor 72 is also turned on at the same time, the first discharge current 81 is generated, and the second end of the second capacitor 73 is pulled to VGH. Therefore, when a large negative voltage comes in at the moment of the PIN, the current discharged is the fourth discharge current 91, and the sum of the fifth discharge current 92 and the sixth discharge current 93 is also larger, compared to the single discharge unit alone. The total discharge current is large and has a better protection effect.
  • the second discharge unit 6 and the third discharge unit 7 may also be disposed as follows:
  • the second discharge unit 6 includes a third P-type transistor, a first capacitor 63, and a fifth N-type transistor 62.
  • a source of the triple P-type transistor is connected to a gate of the first N-type transistor 51
  • a drain of the third P-type transistor is connected to the common terminal 3
  • the common terminal 3 is grounded
  • the A first end of a capacitor 63 is connected to the electrostatic input terminal 4
  • a second end of the first capacitor 63 is connected to a gate of the third P-type transistor
  • a source of the fifth N-type transistor 62 Connected to the second end of the first capacitor 63, the gate of the fifth N-type transistor 62 is connected to the high-level terminal, the drain of the fifth N-type transistor 62 and the low-voltage a flat terminal connection
  • the third discharge unit 7 includes a fourth N-type transistor, a second capacitor 73, a sixth P-type transistor 72,
  • the material of the substrate 10 may be glass, plastic or the like.
  • the display panel includes a liquid crystal panel, an OLED (Organic Light-Emitting Diode) panel, a QLED (Quantum Dot Light Emitting Diodes) panel, a curved panel, or a plasma panel.
  • the liquid crystal panel is exemplified, and the liquid crystal panel includes an array.
  • the array substrate is disposed opposite to the color filter substrate, and the liquid crystal and the spacer unit are disposed between the array substrate and the color filter substrate (PS, photo spacer), a thin film transistor (TFT, Thin Film Transistor) is disposed on the array substrate, and a color filter layer is disposed on the color filter substrate.
  • TFT Thin Film Transistor
  • the color filter substrate may include a TFT array, and the color film and the TFT array may be formed on the same substrate 10, and the array substrate may include a color filter layer.
  • the display panel of the present application may be a curved type panel.
  • the present embodiment discloses a display device 30.
  • the display device 30 includes the control unit 31 and the display panel 32 of the present application.
  • the display panel is taken as an example for detailed description. It should be noted that the above description of the structure of the display panel is also applicable to the display of the embodiment of the present application.
  • the display device of the embodiment of the present application is a liquid crystal display
  • the liquid crystal display includes a backlight module, and the backlight module can be used as a light source for supplying sufficient light source with uniform brightness and distribution.
  • the backlight module of the embodiment can be For the front light type, it may also be a backlight type. It should be noted that the backlight module of the embodiment is not limited thereto.

Abstract

一种静电放电电路（11）和显示面板（32），静电放电电路（11）包括：第一放电单元，包括一个第一晶体管（51）和一个第二晶体管（52），第一晶体管（51）的源极与一高电平接线端（VGH，1）连接，第一晶体管（51）的栅极和漏极、第二晶体管（52）的栅极和漏极与一静电输入端（4）连接，第二晶体管（52）的源极与一低电平接线端（VGL，2）连接；第二放电单元（6）的输入端与静电输入端（4）连接，第二放电单元（6）的输出端与公共端（3）连接；以及第三放电单元（7）的输入端与静电输入端（4）连接，第三放电单元（7）的输出端与公共端（3）连接。

Description

静电放电电路和显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种静电放电电路和显示面板。
背景技术
液晶显示器具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶面板及背光模组(backlight module)。液晶面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，并在两片玻璃基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
其中，薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)由于具有低的功耗、优异的画面品质以及较高的生产良率等性能，目前已经逐渐占据了显示领域的主导地位。同样，薄膜晶体管液晶显示器包含液晶面板和背光模组，液晶面板包括彩膜基板(Color Filter Substrate，CF Substrate，也称彩色滤光片基板)和薄膜晶体管阵列基板(Thin Film Transistor Substrate，TFT Substrate)，上述基板的相对内侧存在透明电极。两片基板之间夹一层液晶分子(Liquid Crystal，LC)。
然而，静电放电(即Electrostatic Discharge，简称ESD)超过一定的电压可使集成电路芯片介质击穿，芯线熔断，漏电流增大加速老化，电性能参数改变等，因而ESD的防护相当重要。
发明内容
本申请所要解决的技术问题是提供一种保护电路可靠有效的静电放电电路。
此外，本申请还提供一种包括以上静电放电电路的显示面板。
本申请的目的是通过以下技术方案来实现的：
一种静电放电电路，所述静电放电电路包括第一放电单元、第二放电单元以及第三放电单元。所述第一放电单元包括一个第一晶体管和一个第二晶体管，所述第一晶体管的源极与一高电平接线端连接，所述第一晶体管的栅极和漏极相连接形成第一极，所述第二晶体管的栅极和漏极相连接形成第二 极，所述第一极与所述第二极相连接并与一静电输入端连接，所述第二晶体管的源极与一低电平接线端连接；所述第二放电单元的输入端与所述静电输入端连接，所述第二放电单元的输出端与一公共端连接；所述第三放电单元的输入端与所述静电输入端连接，所述第三放电单元的输出端与所述公共端连接。
其中，所述第二放电单元包括一端与所述公共端连接的第一导电线，所述公共端接地连接；或者，所述第二放电单元包括一端与所述公共端连接的第一导电线，所述静电放电电路设置在显示面板上，所述公共端与所述显示面板的公共电压端连接。高电平接线端(VGH)与低电平接线端(VGL)之间的所用的导电线所需的线宽较小，这样相当于会有一个比较大的电阻，相对的泄流电流也比较小，第一放电单元单独发挥泄流的能力可能不够。而第一导电线用于接地端(GND)连接；或者，第一导电线用于公共电压端(VCOM)连接，它的线宽都远远大于VGH、VGL的线宽，所以可以排泄掉的电流会比原本来的大，以达到更好的防护效果。
其中，所述第三放电单元包括一端与所述公共端连接的第二导电线，所述公共端接地连接；或者，所述第三放电单元包括一端与所述公共端连接的第二导电线，所述公共端与所述显示面板的公共电压端连接。高电平接线端(VGH)与低电平接线端(VGL)之间的所用的导电线所需的线宽较小，这样相当于会有一个比较大的电阻，相对的泄流电流也比较小，第一放电单元单独发挥泄流的能力可能不够。而第二导电线用于接地端(GND)连接；或者，第二导电线用于公共电压端(VCOM)连接，它的线宽都远远大于VGH、VGL的线宽，所以可以排泄掉的电流会比原本来的大，以达到更好的防护效果。
其中，所述第二放电单元包括一个第三晶体管，所述第三晶体管的输入端和控制端与所述静电输入端连接，所述第三晶体管的输出端与所述公共端连接；所述第三放电单元包括一个第四晶体管，所述第四晶体管的输入端和控制端与所述静电输入端连接，所述第四晶体管的输出端与所述公共端连接。第二放电单元通过第三晶体管泄流，设置简单，有效可靠；第三放电单元通过第四晶体管泄流，设置简单，有效可靠。
其中，所述第二放电单元包括一个第一电容，所述第一电容的第一端与所述静电输入端连接，所述第一电容的第二端与所述第三晶体管的控制端连 接；所述第三放电单元包括一个第二电容，所述第二电容的第一端与所述静电输入端连接，所述第二电容的第二端与所述第四晶体管的控制端连接。利用电容具有隔直流、通交流，通高频、阻低频的特性，电压笵围在VGL～VGH时，第二放电单元和第三放电单元不参与作用。同时电压笵围不在VGL～VGH时，例如瞬间有个正的大电压时，第二放电单元能够正常工作，不产生经第二晶体管留下VGL的电流；例如瞬间有个负的大电压时，第三放电单元能够正常工作。
其中，所述第二放电单元包括一个第五晶体管，所述第五晶体管的输入端与所述第一电容的第二端连接，所述第五晶体管的控制端与所述高电平接线端连接，所述第五晶体管的输出端与所述低电平接线端连接；所述第三放电单元包括一个第六晶体管，所述第六晶体管的输入端与所述第二电容的第二端连接，所述第六晶体管的控制端与所述低电平接线端连接，所述第六晶体管的输出端与所述高电平接线端连接。正电压时，第五晶体管的导通进一步完成第二放电单元的放电功用，同时将第一电容的第二端的电位拉到与公共端一致，这样当电压笵围在VGL～VGH时，第三晶体管不至于导通放电而影响保护电路的正常工作。负电压时，第六晶体管的导通进一步完成第三放电单元的放电功用，同时将第二电容的第二端的电位拉到与公共端一致，这样当电压笵围在VGL～VGH时，第四晶体管不至于导通放电而影响保护电路的正常工作。
其中，所述第一晶体管为第一N型晶体管，所述第二晶体管为第二P型晶体管，所述第三晶体管为第三N型晶体管，所述第四晶体管为第四P型晶体管，所述第五晶体管为第五N型晶体管，所述第六晶体管为第六P型晶体管。这里是静电放电电路的一个实施方式，明确具体采用的电元件以及连接关系。
其中，所述第一晶体管为第一N型晶体管，所述第二晶体管为第二P型晶体管，所述第三晶体管为第三P型晶体管，所述第四晶体管为第四N型晶体管，所述第五晶体管为第五N型晶体管，所述第六晶体管为第六P型晶体管。这里是静电放电电路的另一个实施方式，明确具体采用的电元件以及连接关系。
根据本申请的另一个方面，本申请还公开了一种静电放电电路，所述静电放电电路包括第一放电单元、第二放电单元以及第三放电单元。所述第一 放电单元包括一个第一N型晶体管和一个第二P型晶体管，所述第一N型晶体管的源极与一高电平接线端连接，所述第一N型晶体管的栅极和漏极相连接形成第一极，所述第二P型晶体管的栅极和漏极相连接形成第二极，所述第一极与所述第二极相连接并与一静电输入端连接，所述第二P型晶体管的源极与一低电平接线端连接；所述第二放电单元包括一个第三N型晶体管、一个第一电容、一个第五N型晶体管，所述第三N型晶体管的源极与所述第一N型晶体管的栅极连接，所述第三N型晶体管的漏极与一公共端连接，所述公共端接地连接，所述第一电容的第一端与所述静电输入端连接，所述第一电容的第二端与所述第三N型晶体管的栅极连接，所述第五N型晶体管的源极与所述第一电容的第二端连接，所述第五N型晶体管的栅极与所述高电平接线端连接，所述第五N型晶体管的漏极与所述低电平接线端连接，所述第二放电单元用于正电压作用时的放电；所述第三放电单元包括一个第四P型晶体管、一个第二电容、一个第六P型晶体管，所述第四P型晶体管的源极与所述第二P型晶体管的栅极连接，所述第四P型晶体管的漏极与所述公共端连接，所述公共端接地连接，所述第二电容的第一端与所述静电输入端连接，所述第二电容的第二端与所述第四P型晶体管的栅极连接，所述第六P型晶体管的源极与所述第二电容的第二端连接，所述第六P型晶体管的栅极与所述低电平接线端连接，所述第六P型晶体管的漏极与所述高电平接线端连接，所述第三放电单元用于负电压作用时的放电。
根据本申请的另一个方面，本申请还公开了一种显示面板，其所述显示面板包括基板、信号线以及静电放电电路。在所述基板上设置主动开关；所述信号线设置在所述基板上，与所述主动开关耦接，所述信号线包括多条扫描线和多条数据线，多条所述数据线与多条所述扫描线依次相交设置形成多个像素区；所述静电放电电路设置在所述基板上。
其中，所述显示面板还包括：栅极驱动电路和源极驱动电路，所述栅极驱动电路和所述源极驱动电路设置在所述基板上。
本申请由于第二放电单元和第三放电单元都与第一放电单元连接共同作用，不管静电输入端瞬间有个正的或者负的大电压进来都可以在第一放电单元外分别配合第二放电单元和第三放电单元增加ESD放电电流路径，泄流的速度和数量得以加大，实现对显示面板更好的保护效果，延长使用寿命。
附图说明
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请实施例一种显示面板的静电放电电路的示意图；
图2是本申请实施例一种显示面板的静电放电电路的示意图；
图3是本申请实施例一种显示面板的静电放电电路的示意图；
图4是本申请实施例一种显示面板的静电放电电路的示意图；
图5是本申请实施例一种显示面板的结构示意图；以及
图6是本申请实施例一种显示装置的结构示意图。
具体实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领 域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
下面结合附图和具体的实施例对本申请作进一步详细说明。
下面参考图1至图4描述本申请实施例的静电放电电路示意图。
作为本申请的一个实施例，如图1所示，所述静电放电电路11包括第一放电单元、第二放电单元6以及第三放电单元7。所述第一放电单元包括一个第一晶体管和一个第二晶体管，所述第一晶体管的源极与一高电平接线端连接，所述第一晶体管的栅极和漏极相连接形成第一极，所述第二晶体管的栅极和漏极相连接形成第二极，所述第一极与所述第二极相连接并与一静电输入端4连接，所述第二晶体管的源极与一低电平接线端连接；所述第二放电单元6的输入端与所述静电输入端4连接，所述第二放电单元6的输出端与一公共端3连接；所述第三放电单元7的输入端与所述静电输入端4连接，所述第三放电单元7的输出端与所述公共端3连接。第二放电单元6和第三放电单元7都与第一放电单元连接共同作用，不管静电输入端4瞬间有个正的或者负的大电压进来都可以在第一放电单元外分别配合第二放电单元6和第三放电单元7增加ESD放电电流路径，泄流的速度和数量得以加大，实现对显示面板更好的保护效果，延长使用寿命。如图5所示，所述显示面板包括：基板10、信号线以及静电放电电路11。在所述基板10上设置主动开关；所述信号线设置在所述基板10上，与所述主动开关耦接，所述信号线包括多条扫描线14和多条数据线15，多条所述数据线15与多条所述扫描线14依次相交设置形成多个像素区16；所述基板10上设置有静电放电电路11、栅极驱动电路12和源极驱动电路13，水平设置的扫描线14和竖直设置的数据线15与其相对应的电路耦合连接，所述主动开关例如可为薄膜晶体管。高电平接线端、低电平接线端、静电输入端4以及公共端3与显示面板的元器件耦合。
具体的，所述第二放电单元6包括一端与所述公共端3连接的第一导电线，所述公共端3接地连接；或者，所述第二放电单元6包括一端与所述公 共端3连接的第一导电线，所述公共端3与所述显示面板的公共电压端连接。高电平接线端(VGH)1与低电平接线端(VGL)2之间的所用的导电线所需的线宽较小，这样相当于会有一个比较大的电阻，相对的泄流电流也比较小，第一放电单元单独发挥泄流的能力可能不够。而第一导电线用于接地端(GND)连接；或者，第一导电线用于公共电压端(VCOM)连接，它的线宽都远远大于VGH、VGL的线宽，所以可以排泄掉的电流会比原本来的大，以达到更好的防护效果。所述第三放电单元7包括一端与所述公共端3连接的第二导电线，所述公共端3接地连接；或者，所述第三放电单元7包括一端与所述公共端3连接的第二导电线，所述公共端3与所述显示面板的公共电压端连接。而第二导电线用于接地端(GND)连接，或者，第二导电线用于公共电压端(VCOM)连接，它的线宽都远远大于VGH、VGL的线宽，所以可以排泄掉的电流会比原本来的大，以达到更好的防护效果。其中，所述显示面板包括栅极集成电路，所述高电平接线端、所述低电平接线端分别于所述栅极集成电路的晶体管开启电压端和晶体管关闭电压端连接。
作为本申请的又一个实施例，所述静电放电电路11包括第一放电单元、第二放电单元6以及第三放电单元7。所述第一放电单元包括一个第一晶体管和一个第二晶体管，所述第一晶体管的源极与一高电平接线端连接，所述第一晶体管的栅极和漏极相连接形成第一极，所述第二晶体管的栅极和漏极相连接形成第二极，所述第一极与所述第二极相连接并与一静电输入端4连接，所述第二晶体管的源极与一低电平接线端连接；所述第二放电单元6的输入端与所述静电输入端4连接，所述第二放电单元6的输出端与一公共端3连接；所述第三放电单元7的输入端与所述静电输入端4连接，所述第三放电单元7的输出端与所述公共端3连接。第二放电单元6和第三放电单元7都与第一放电单元连接共同作用，不管静电输入端4瞬间有个正的或者负的大电压进来都可以在第一放电单元外分别配合第二放电单元6和第三放电单元7增加ESD放电电流路径，泄流的速度和数量得以加大，实现对显示面板更好的保护效果，延长使用寿命。所述第二放电单元6包括一个第三晶体管和一个第一电容63，所述第三晶体管的输入端和控制端与所述静电输入端4连接，所述第三晶体管的输出端与所述公共端3连接；所述第一电容63的第一端与所述静电输入端4连接，所述第一电容63的第二端与所述第三晶体管的控制端连接。所述第三放电单元7包括一个第四晶体管和一个第二电容73，所述 第四晶体管的输入端和控制端与所述静电输入端4连接，所述第四晶体管的输出端与所述公共端3连接；所述第二电容73的第一端与所述静电输入端4连接，所述第二电容73的第二端与所述第四晶体管的控制端连接。第二放电单元6和第三放电单元7分别通过第三晶体管、第四晶体管泄流，设置简单，有效可靠。利用电容具有隔直流、通交流，通高频、阻低频的特性，电压笵围在VGL～VGH时，第二放电单元6和第三放电单元7不参与作用。同时电压笵围不在VGL～VGH时，例如瞬间有个正的大电压时，第二放电单元6能够正常工作，不产生经第二晶体管留下VGL的电流；例如瞬间有个负的大电压时，第三放电单元7能够正常工作。所以如果PIN的输入电压笵围在VGL～VGH间因为电容在直流电流中可视为开路，这个电容和晶体管是不会动作的。
具体的，如图2所示，所述第一放电单元包括一个第一N型晶体管51和一个第二P型晶体管52，所述第一N型晶体管51的源极与所述高电平接线端连接，所述第一N型晶体管51的栅极和漏极相连接形成第一极，所述第二P型晶体管52的栅极和漏极相连接形成第二极，所述第一极与所述第二极相连接并与所述静电输入端4连接，所述第二P型晶体管52的源极与所述低电平接线端连接；所述第三N型晶体管61的源极与第一N型晶体管51的栅极连接，所述第三N型晶体管61的漏极与所述公共端3连接，所述公共端3接地连接，所述第一电容63的第一端与所述静电输入端4连接，所述第一电容63的第二端与所述第三N型晶体管61的栅极连接。所述第四P型晶体管71的源极与第二P型晶体管52的栅极连接，所述第四P型晶体管71的漏极与所述公共端3连接，所述公共端3接地连接，所述第二电容73的第一端与所述静电输入端4连接，所述第二电容73的第二端与所述第四P型晶体管71的栅极连接。当PIN瞬间有个正的大电压进来时，则第一N型晶体管51导通，有第一放电电流81产生。由于PIN电位瞬间变高，电容耦合特效下，第一电容63的第二端与第三N型晶体管61的栅极连接之间的点的电位也同时变大，则第三N型晶体管61也导通，此时PIN的正的大电压可以往GND泄流。因为GND的走线通常比VGL粗，所以相对应的电阻值远小于VGL的，故第二放电电流82大于第一放电电流81。当PIN瞬间有个负的大电压进来时，则第二P型晶体管52导通，有第四放电电流91产生。由于PIN电位瞬间变负，电容耦合特效下，第二电容73的第二端也同时变负，则第四P型晶体管71 也导通，第五放电电流92产生，此时PIN的负的大电压可以往GND泄流。因为GND的走线通常比VGL粗，所以相对应的电阻值远小于VGL的，故第五放电电流92大于第四放电电流91。
作为本申请的又一个实施例，所述静电放电电路11包括第一放电单元、第二放电单元6以及第三放电单元7。所述第一放电单元包括一个第一晶体管和一个第二晶体管，所述第一晶体管的源极与一高电平接线端连接，所述第一晶体管的栅极和漏极相连接形成第一极，所述第二晶体管的栅极和漏极相连接形成第二极，所述第一极与所述第二极相连接并与一静电输入端4连接，所述第二晶体管的源极与一低电平接线端连接；所述第二放电单元6的输入端与所述静电输入端4连接，所述第二放电单元6的输出端与一公共端3连接；所述第三放电单元7的输入端与所述静电输入端4连接，所述第三放电单元7的输出端与所述公共端3连接。第二放电单元6和第三放电单元7都与第一放电单元连接共同作用，不管静电输入端4瞬间有个正的或者负的大电压进来都可以在第一放电单元外分别配合第二放电单元6和第三放电单元7增加ESD放电电流路径，泄流的速度和数量得以加大，实现对显示面板更好的保护效果，延长使用寿命。所述第二放电单元6包括一个第三晶体管、一个第一电容63和一个第五晶体管，所述第三晶体管的输入端和控制端与所述静电输入端4连接，所述第三晶体管的输出端与所述公共端3连接；所述第一电容63的第一端与所述静电输入端4连接，所述第一电容63的第二端与所述第三晶体管的控制端连接；所述第五晶体管的输入端与所述第一电容63的第二端连接，所述第五晶体管的控制端与所述高电平接线端连接，所述第五晶体管的输出端与所述低电平接线端连接；所述第三放电单元7包括一个第四晶体管、一个第二电容73和一个第六晶体管，所述第四晶体管的输入端和控制端与所述静电输入端4连接，所述第四晶体管的输出端与所述公共端3连接；所述第二电容73的第一端与所述静电输入端4连接，所述第二电容73的第二端与所述第四晶体管的控制端连接；所述第六晶体管的输入端与所述第二电容73的第二端连接，所述第六晶体管的控制端与所述低电平接线端连接，所述第六晶体管的输出端与所述高电平接线端连接。
第二放电单元6和第三放电单元7分别通过第三晶体管、第四晶体管泄流，设置简单，有效可靠。利用电容具有隔直流、通交流，通高频、阻低频的特性，电压笵围在VGL～VGH时，第二放电单元6和第三放电单元7不参 与作用。同时电压笵围不在VGL～VGH时，例如瞬间有个正的大电压时，第二放电单元6能够正常工作，不产生经第二晶体管留下VGL的电流；例如瞬间有个负的大电压时，第三放电单元7能够正常工作。所以如果PIN的输入电压笵围在VGL～VGH间因为电容在直流电流中可视为开路，这个电容和晶体管是不会动作的。正电压时，第五晶体管的导通进一步完成第二放电单元6的放电功用，同时将第一电容63的第二端的电位拉到与公共端3一致，这样当电压笵围在VGL～VGH时，第三晶体管不至于导通放电而影响保护电路的正常工作。负电压时，第六晶体管的导通进一步完成第三放电单元7的放电功用，同时将第二电容73的第二端的电位拉到与公共端3一致，这样当电压笵围在VGL～VGH时，第四晶体管不至于导通放电而影响保护电路的正常工作。
具体的，如图3、4所示，图4可以看作图3的实际等效电路。所述第一放电单元包括一个第一N型晶体管51和一个第二P型晶体管52，所述第一N型晶体管51的源极与所述高电平接线端连接，所述第一N型晶体管51的栅极和漏极相连接形成第一极，所述第二P型晶体管52的栅极和漏极相连接形成第二极，所述第一极与所述第二极相连接并与所述静电输入端4连接，所述第二P型晶体管52的源极与所述低电平接线端连接；所述第二放电单元6包括一个第三N型晶体管61、一个第一电容63、一个第五N型晶体管62，所述第三N型晶体管61的源极与第一N型晶体管51的栅极连接，所述第三N型晶体管61的漏极与所述公共端3连接，所述公共端3接地连接，所述第一电容63的第一端与所述静电输入端4连接，所述第一电容63的第二端与所述第三N型晶体管61的栅极连接，所述第五N型晶体管62的源极与所述第一电容63的第二端连接，所述第五N型晶体管62的栅极与所述高电平接线端连接，所述第五N型晶体管62的漏极与所述低电平接线端连接；所述第三放电单元7包括一个第四P型晶体管71、一个第二电容73、一个第六P型晶体管72，所述第四P型晶体管71的源极与所述第二P型晶体管52的栅极连接，所述第四P型晶体管71的漏极与所述公共端3连接，所述公共端3接地连接，所述第二电容73的第一端与所述静电输入端4连接，所述第二电容73的第二端与所述第四P型晶体管71的栅极连接，所述第六P型晶体管72的源极与所述第二电容73的第二端连接，所述第六P型晶体管72的栅极与所述低电平接线端连接，所述第六P型晶体管72的漏极与所述高电平接线端 连接。由于PIN电位瞬间变高，电容耦合特效下，电容的第二端与第三N型晶体管61的栅极连接之间的点的电位也同时变大，则第三N型晶体管61也导通，此时PIN的正的大电压可以往GND泄流。因为GND的走线通常比VGL粗，所以相对应的电阻值远小于VGL的，故第二放电电流82大于第一放电电流81。而第五N型晶体管62也会同时把第一电容63的第二端与第三N型晶体管61的栅极连接之间的点的电位拉到GND。所以当PIN瞬间有个大的正电压进来时，泄掉的电流为第一放电电流81、第二放电电流82与第三放电电流83的和值也更大，相比第一放电单元的单独作用总的泄流电流较大，有更好的保护效果。由于PIN电位瞬间变负，电容耦合特效下，第二电容73的第二端也同时变负，则第四P型晶体管71也导通，第五放电电流92产生，此时PIN的负的大电压可以往GND泄流。因为GND的走线通常比VGL粗，所以相对应的电阻值远小于VGL的，故第五放电电流92大于第四放电电流91。而第六P型晶体管72也会同时导通，第一放电电流81产生，再把第二电容73的第二端拉到VGH。所以当PIN瞬间有个大的负电压进来时，泄掉的电流为第四放电电流91、第五放电电流92与第六放电电流93的和值也更大，相比第一放电单元的单独作用总的泄流电流较大，有更好的保护效果。
当然，第二放电单元6和第三放电单元7也可以如下设置：所述第二放电单元6包括一个第三P型晶体管、一个第一电容63、一个第五N型晶体管62，所述第三P型晶体管的源极与所述第一N型晶体管51的栅极连接，所述第三P型晶体管的漏极与所述公共端3连接，所述公共端3接地连接，所述第一电容63的第一端与所述静电输入端4连接，所述第一电容63的第二端与所述第三P型晶体管的栅极连接，所述第五N型晶体管62的源极与所述第一电容63的第二端连接，所述第五N型晶体管62的栅极与所述高电平接线端连接，所述第五N型晶体管62的漏极与所述低电平接线端连接；所述第三放电单元7包括一个第四N型晶体管、一个第二电容73、一个第六P型晶体管72，所述第四N型晶体管的源极与第二P型晶体管52的栅极连接，所述第四N型晶体管的漏极与所述公共端3连接，所述公共端3接地连接，所述第二电容73的第一端与所述静电输入端4连接，所述第二电容73的第二端与所述第四N型晶体管的栅极连接，所述第六P型晶体管72的源极与所述第二电容73的第二端连接，所述第六P型晶体管72的栅极与所述低电平接线端连接，所述第六P型晶体管72的漏极与所述高电平接线端连接。
需要说明的是，在上述实施例中，所述基板10的材料可以选用玻璃、塑料等。
在上述实施例中，显示面板包括液晶面板、OLED(Organic Light-Emitting Diode)面板、QLED(Quantum Dot Light Emitting Diodes)面板、曲面面板、或等离子面板等，以液晶面板为例，液晶面板包括阵列基板(Thin Film Transistor Substrate，TFT Substrate)和彩膜基板(Color Filter Substrate，CF Substrate)，所述阵列基板与彩膜基板相对设置，所述阵列基板与彩膜基板之间设有液晶和间隔单元(PS，photo spacer)，所述阵列基板上设有薄膜晶体管(TFT，Thin Film Transistor)，彩膜基板上设有彩色滤光层。
在上述实施例中，彩膜基板可包括TFT阵列，彩膜及TFT阵列可形成于同一基板10上，阵列基板可包括彩色滤光层。
在上述实施例中，本申请的显示面板可为曲面型面板。
参考图6，本实施方式公开一种显示装置30。该显示装置30包括控制部件31、以及本申请所述的显示面板32，以上以显示面板为例进行详细说明，需要说明的是，以上对显示面板结构的描述同样适用于本申请实施例的显示装置中。其中，当本申请实施例的显示装置为液晶显示器时，液晶显示器包括有背光模组，背光模组可作为光源，用于供应充足的亮度与分布均匀的光源，本实施例的背光模组可以为前光式，也可以为背光式，需要说明的是，本实施例的背光模组并不限于此。
以上内容是结合具体的实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (20)

  1. 一种静电放电电路，包括：
    第一放电单元，所述第一放电单元包括一个第一晶体管和一个第二晶体管，所述第一晶体管的源极与一高电平接线端连接，所述第一晶体管的栅极和漏极相连接形成第一极，所述第二晶体管的栅极和漏极相连接形成第二极，所述第一极与所述第二极相连接并与一静电输入端连接，所述第二晶体管的源极与一低电平接线端连接；
    第二放电单元，所述第二放电单元的输入端与所述静电输入端连接，所述第二放电单元的输出端与一公共端连接，所述第二放电单元用于正电压作用时的放电；以及
    第三放电单元，所述第三放电单元的输入端与所述静电输入端连接，所述第三放电单元的输出端与所述公共端连接，所述第三放电单元用于负电压作用时的放电。
  2. 如权利要求1所述的静电放电电路，其中所述第二放电单元包括一端与所述公共端连接的第一导电线，所述公共端接地连接；或者，所述第二放电单元包括一端与所述公共端连接的第一导电线，所述静电放电电路设置在显示面板上，所述公共端与所述显示面板的公共电压端连接。
  3. 如权利要求1所述的静电放电电路，其中所述第三放电单元包括一端与所述公共端连接的第二导电线，所述公共端接地连接；或者，所述第三放电单元包括一端与所述公共端连接的第二导电线，所述公共端与所述显示面板的公共电压端连接。
  4. 如权利要求1所述的静电放电电路，其中所述第二放电单元包括一个第三晶体管，所述第三晶体管的输入端和控制端与所述静电输入端连接，所述第三晶体管的输出端与所述公共端连接；
    所述第三放电单元包括一个第四晶体管，所述第四晶体管的输入端和控制端与所述静电输入端连接，所述第四晶体管的输出端与所述公共端连接。
  5. 如权利要求4所述的静电放电电路，其中所述第二放电单元包括一个第一电容，所述第一电容的第一端与所述静电输入端连接，所述第一电容的第二端与所述第三晶体管的控制端连接；
    所述第三放电单元包括一个第二电容，所述第二电容的第一端与所述静 电输入端连接，所述第二电容的第二端与所述第四晶体管的控制端连接。
  6. 如权利要求5所述的静电放电电路，其中所述第二放电单元包括一个第五晶体管，所述第五晶体管的输入端与所述第一电容的第二端连接，所述第五晶体管的控制端与所述高电平接线端连接，所述第五晶体管的输出端与所述低电平接线端连接；
    所述第三放电单元包括一个第六晶体管，所述第六晶体管的输入端与所述第二电容的第二端连接，所述第六晶体管的控制端与所述低电平接线端连接，所述第六晶体管的输出端与所述高电平接线端连接。
  7. 如权利要求6所述的静电放电电路，其中所述第一晶体管为第一N型晶体管，所述第二晶体管为第二P型晶体管，所述第三晶体管为第三N型晶体管，所述第四晶体管为第四P型晶体管，所述第五晶体管为第五N型晶体管，所述第六晶体管为第六P型晶体管。
  8. 如权利要求6所述的静电放电电路，其中所述第一晶体管为第一N型晶体管，所述第二晶体管为第二P型晶体管，所述第三晶体管为第三P型晶体管，所述第四晶体管为第四N型晶体管，所述第五晶体管为第五N型晶体管，所述第六晶体管为第六P型晶体管。
  9. 一种静电放电电路，包括：
    第一放电单元，所述第一放电单元包括一个第一N型晶体管和一个第二P型晶体管，所述第一N型晶体管的源极与一高电平接线端连接，所述第一N型晶体管的栅极和漏极相连接形成第一极，所述第二P型晶体管的栅极和漏极相连接形成第二极，所述第一极与所述第二极相连接并与一静电输入端连接，所述第二P型晶体管的源极与一低电平接线端连接；
    第二放电单元，所述第二放电单元包括一个第三N型晶体管、一个第一电容、一个第五N型晶体管，所述第三N型晶体管的源极与所述第一N型晶体管的栅极连接，所述第三N型晶体管的漏极与一公共端连接，所述公共端接地连接，所述第一电容的第一端与所述静电输入端连接，所述第一电容的第二端与所述第三N型晶体管的栅极连接，所述第五N型晶体管的源极与所述第一电容的第二端连接，所述第五N型晶体管的栅极与所述高电平接线端连接，所述第五N型晶体管的漏极与所述低电平接线端连接，所述第二放电单元用于正电压作用时的放电；以及
    第三放电单元，所述第三放电单元包括一个第四P型晶体管、一个第二 电容、一个第六P型晶体管，所述第四P型晶体管的源极与所述第二P型晶体管的栅极连接，所述第四P型晶体管的漏极与所述公共端连接，所述公共端接地连接，所述第二电容的第一端与所述静电输入端连接，所述第二电容的第二端与所述第四P型晶体管的栅极连接，所述第六P型晶体管的源极与所述第二电容的第二端连接，所述第六P型晶体管的栅极与所述低电平接线端连接，所述第六P型晶体管的漏极与所述高电平接线端连接，所述第三放电单元用于负电压作用时的放电。
  10. 如权利要求9所述的静电放电电路，其中所述第二放电单元包括一端与所述公共端连接的第一导电线，所述公共端接地连接；或者，所述第二放电单元包括一端与所述公共端连接的第一导电线，所述静电放电电路设置在显示面板上，所述公共端与所述显示面板的公共电压端连接。
  11. 如权利要求9所述的静电放电电路，其中所述第三放电单元包括一端与所述公共端连接的第二导电线，所述公共端接地连接；或者，所述第三放电单元包括一端与所述公共端连接的第二导电线，所述公共端与所述显示面板的公共电压端连接。
  12. 一种显示面板，包括：
    基板，在所述基板上设置主动开关；
    信号线，所述信号线设置在所述基板上，与所述主动开关耦接，所述信号线包括多条扫描线和多条数据线，多条所述数据线与多条所述扫描线依次相交设置形成多个像素区；以及
    如权利要求1所述的静电放电电路；
    其中，所述静电放电电路设置在所述基板上。
  13. 如权利要求12所述的显示面板，还包括：
    栅极驱动电路和源极驱动电路，所述栅极驱动电路和所述源极驱动电路设置在所述基板上。
  14. 如权利要求12所述的显示面板，其中所述第二放电单元包括一端与所述公共端连接的第一导电线，所述公共端接地连接；或者，所述第二放电单元包括一端与所述公共端连接的第一导电线，所述静电放电电路设置在显示面板上，所述公共端与所述显示面板的公共电压端连接。
  15. 如权利要求12所述的显示面板，其中所述第三放电单元包括一端与所述公共端连接的第二导电线，所述公共端接地连接；或者，所述第三放电 单元包括一端与所述公共端连接的第二导电线，所述公共端与所述显示面板的公共电压端连接。
  16. 如权利要求12所述的显示面板，其中所述第二放电单元包括一个第三晶体管，所述第三晶体管的输入端和控制端与所述静电输入端连接，所述第三晶体管的输出端与所述公共端连接；
    所述第三放电单元包括一个第四晶体管，所述第四晶体管的输入端和控制端与所述静电输入端连接，所述第四晶体管的输出端与所述公共端连接。
  17. 如权利要求16所述的显示面板，其中所述第二放电单元包括一个第一电容，所述第一电容的第一端与所述静电输入端连接，所述第一电容的第二端与所述第三晶体管的控制端连接；
    所述第三放电单元包括一个第二电容，所述第二电容的第一端与所述静电输入端连接，所述第二电容的第二端与所述第四晶体管的控制端连接。
  18. 如权利要求17所述的显示面板，其中所述第二放电单元包括一个第五晶体管，所述第五晶体管的输入端与所述第一电容的第二端连接，所述第五晶体管的控制端与所述高电平接线端连接，所述第五晶体管的输出端与所述低电平接线端连接；
    所述第三放电单元包括一个第六晶体管，所述第六晶体管的输入端与所述第二电容的第二端连接，所述第六晶体管的控制端与所述低电平接线端连接，所述第六晶体管的输出端与所述高电平接线端连接。
  19. 如权利要求18所述的显示面板，其中所述第一晶体管为第一N型晶体管，所述第二晶体管为第二P型晶体管，所述第三晶体管为第三N型晶体管，所述第四晶体管为第四P型晶体管，所述第五晶体管为第五N型晶体管，所述第六晶体管为第六P型晶体管。
  20. 如权利要求18所述的显示面板，其中所述第一晶体管为第一N型晶体管，所述第二晶体管为第二P型晶体管，所述第三晶体管为第三P型晶体管，所述第四晶体管为第四N型晶体管，所述第五晶体管为第五N型晶体管，所述第六晶体管为第六P型晶体管。
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