WO2018196323A1 - 阵列基板、显示面板、显示设备及驱动方法 - Google Patents

阵列基板、显示面板、显示设备及驱动方法 Download PDF

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Publication number
WO2018196323A1
WO2018196323A1 PCT/CN2017/109689 CN2017109689W WO2018196323A1 WO 2018196323 A1 WO2018196323 A1 WO 2018196323A1 CN 2017109689 W CN2017109689 W CN 2017109689W WO 2018196323 A1 WO2018196323 A1 WO 2018196323A1
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Prior art keywords
gate
transistor
shift register
signal
array substrate
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PCT/CN2017/109689
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English (en)
French (fr)
Inventor
金志河
韩承佑
商广良
郑皓亮
姚星
韩明夫
王志冲
袁丽君
林允植
黄应龙
董学
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京东方科技集团股份有限公司
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Priority to US16/063,448 priority Critical patent/US10679565B2/en
Publication of WO2018196323A1 publication Critical patent/WO2018196323A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0414—Vertical resolution change

Definitions

  • Embodiments of the present disclosure relate to an array substrate, a display panel, a display device, and a driving method.
  • organic light-emitting diode (OLED) display panels have the characteristics of self-luminous, high contrast, low power consumption, wide viewing angle, fast response, flexible panel, wide temperature range, and simple manufacturing. Prospects. Due to the above characteristics, the organic light emitting diode (OLED) display panel can be applied to a device having a display function such as a mobile phone, a display, a notebook computer, a digital camera, an instrument meter, and the like.
  • the Gate-Driver on Array (GOA) technology directly integrates the gate driving circuit on the array substrate of the display device by a photolithography process, and the GOA circuit usually includes a plurality of cascaded shift registers, each of which Each of the shift registers corresponds to a gate line (for example, each shift register provides a scan driving signal to a gate line corresponding to one row or one column of pixels) to implement scan driving of the display panel.
  • This integrated technology can save the bonding area of the integrated circuit (IC) and the space of the fan-out area, thereby achieving a narrow border of the display panel, and at the same time reducing product cost and improving Product yield.
  • An embodiment of the present disclosure provides an array substrate including: a plurality of first pixel units arranged in an array in a first region; a first gate driving circuit; a second gate driving circuit; and the first gate a plurality of first gate lines connected to the driving circuit; and a plurality of second gate lines connected to the second gate driving circuit, wherein the first portion of the plurality of first pixel units and the plurality of a gate line is connected, and each of the first pixel units of the first portion is connected to one of the plurality of first gate lines; a second portion of the plurality of first pixel units and the plurality of The second gate lines are connected, and each of the first pixel units of the second portion is connected to one of the plurality of second gate lines.
  • the array substrate provided by the embodiment of the present disclosure further includes: array arrangement in the second area a plurality of second pixel units; a plurality of third pixel units arranged in an array in the third region; a plurality of third gate lines connected to the first gate driving circuit; and a second gate a plurality of fourth gate lines connected to the driving circuit, wherein a first one of the plurality of second pixel units is connected to the plurality of first gate lines, and each of the second pixel units of the first portion Connected to one of the plurality of first gate lines; a second one of the plurality of second pixel units is connected to the plurality of third gate lines, and each of the second portions of the second portion a pixel unit is connected to one of the plurality of third gate lines; a first one of the plurality of third pixel units is connected to the plurality of second gate lines, and each of the third portions of the first portion a pixel unit is connected to one of the plurality of second gate lines; a second one of the plurality of third pixel units is
  • the first pixel unit of the 2n-1th row and the second pixel unit of the 2n-1th row are connected to the nth first gate line;
  • the first pixel unit of the 2nth row and the third pixel unit of the 2nth row are connected to the nth second gate line;
  • the second pixel unit of the 2nth row and the nth row a triple gate line connection;
  • the third pixel unit of the 2n-1th row is connected to the nth fourth gate line;
  • n is an integer greater than 0, n ⁇ N/2, and N is a pixel unit in each region The total number of lines.
  • the first region is disposed between the second region and the third region.
  • the first gate driving circuit and the second gate driving circuit are disposed on opposite sides of the array substrate.
  • the first gate driving circuit includes a first shift register group, and the first shift register group includes a plurality of cascaded first shift registers, except In addition to the first stage and the last stage, the input end of the first shift register of the first stage is connected to the output end of the first shift register of the previous stage;
  • the second gate drive circuit includes a second shift register set, The second shift register set includes a plurality of cascaded second shift registers, the input of the second shift register of the second stage and the second shift register of the previous stage except the first stage and the last stage
  • the output of the first gate drive circuit further includes a third shift register set, the third shift register set includes a plurality of cascaded third shift registers, except the first stage and the last stage
  • the input end of the third shift register of the third stage is connected to the output end of the third shift register of the upper stage;
  • the second gate drive circuit further includes a fourth shift register set, the fourth shift The register set includes a plurality of first shifts of the
  • an output end of each of the first shift registers is correspondingly connected to one of the first gate lines, and each of the first shift registers is configured to respond to the first a clock signal outputs a first gate driving signal to one of the first gate lines; an output end of each of the second shift registers is correspondingly connected to one of the second gate lines, and each of the second shifts
  • the register is configured to output a second gate driving signal to one of the second gate lines in response to the second clock signal; an output end of each of the third shift registers is correspondingly connected to one of the third gate lines, each of the The third shift register is configured to output a third gate driving signal to one of the third gate lines in response to the third clock signal; one of an output end of each of the fourth shift registers and a fourth gate line Correspondingly, each of the fourth shift registers is configured to output a fourth gate drive signal to one of the fourth gate lines in response to a fourth clock signal.
  • the array substrate provided by the embodiment of the present disclosure further includes a first clock generator and a second clock generator, wherein the first clock generator is configured to provide the first to the first shift register a clock signal; the second clock generator is configured to provide the second clock signal to the second shift register; the first clock generator is further configured to provide the third shift register The third clock signal; and the second clock generator is further configured to provide the fourth clock signal to the fourth shift register.
  • the first clock generator is configured to provide the first to the first shift register a clock signal
  • the second clock generator is configured to provide the second clock signal to the second shift register
  • the first clock generator is further configured to provide the third shift register The third clock signal
  • the second clock generator is further configured to provide the fourth clock signal to the fourth shift register.
  • the array substrate provided by the embodiment of the present disclosure further includes: a clock controller respectively connected to the first clock generator and the second clock generator, configured to control the first clock generator to provide Timing of the first clock signal and the third clock signal, and timing of controlling the second clock signal and the fourth clock signal provided by the second clock generator.
  • a clock controller respectively connected to the first clock generator and the second clock generator, configured to control the first clock generator to provide Timing of the first clock signal and the third clock signal, and timing of controlling the second clock signal and the fourth clock signal provided by the second clock generator.
  • an array substrate provided by an embodiment of the present disclosure includes three display strips, each of the display strips including the first area, the second area, and the third area, and is located in the same display strip.
  • the number of rows of the first pixel unit in the first region, the number of rows of the second pixel unit in the second region, and the number of rows of the third pixel unit in the third region are equal.
  • each of the first shift register, the second shift register, the third shift register, and the fourth shift register includes: An input circuit is respectively connected to the input terminal and the pull-up node; a reset circuit is respectively connected to the pull-up node, the reset terminal and the first power terminal; an output circuit, and the pull-up node and the clock signal The output end and the output end are respectively connected; the output pull-down circuit is respectively connected to the output end, the pull-down node and the first power supply end; the pull-down node control circuit, and the pull-down node and the second power supply end And the first power terminals are respectively connected; and a storage capacitor is respectively connected to the pull-up node and the output end.
  • the input circuit includes a first transistor, a first pole of the first transistor is connected to the input end, a gate of the first transistor and the input An end connection, a second pole of the first transistor is connected to the pull-up node;
  • the reset circuit includes a second transistor, a first pole of the second transistor is connected to the pull-up node, and the second a gate of the transistor is coupled to the reset terminal, a second electrode of the second transistor is coupled to the first power terminal;
  • the output circuit includes a third transistor, a first pole of the third transistor and the a clock signal terminal is connected, a gate of the third transistor is connected to the pull-up node, a second pole of the third transistor is connected to the output terminal, and the output pull-down circuit includes a fourth transistor, a first pole of the fourth transistor is connected to the output terminal, a gate of the fourth transistor is connected to the pull-down node, and a second pole of the fourth transistor is connected to the first power terminal;
  • An embodiment of the present disclosure further provides a display panel including the array substrate provided by any embodiment of the present disclosure.
  • An embodiment of the present disclosure further provides a display device including the display panel provided by any embodiment of the present disclosure.
  • An embodiment of the present disclosure further provides a method of driving an array substrate provided by any one of the embodiments of the present disclosure, including: providing a first gate to a first portion of the first pixel unit through the first gate driving circuit Driving a signal; and providing, by the second gate driving circuit, a second gate driving signal to a second portion of the first pixel unit, wherein when the first region is in a high resolution mode, The timing of the first gate driving signal is different from the timing of the second gate driving signal; when the first region is in the low resolution mode, the timing of the first gate driving signal is the same as The timing of the second gate drive signal is the same.
  • FIG. 1 is a schematic diagram of an array substrate provided by an embodiment of the present disclosure
  • FIG. 2 is a second schematic view of an array substrate according to an embodiment of the present disclosure.
  • FIG. 3 is a third schematic view of an array substrate according to an embodiment of the present disclosure.
  • FIG. 4 is a fourth schematic diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a shift register in an array substrate according to an embodiment of the present disclosure.
  • FIG. 6 is a second schematic diagram of a shift register in an array substrate according to an embodiment of the present disclosure.
  • FIG. 7 is a timing chart of driving of the shift register shown in FIG. 6 according to an embodiment of the present disclosure.
  • FIG. 8A is a schematic diagram of a display of different resolutions of an array substrate sub-area according to an embodiment of the present disclosure
  • FIG. 8B is a driving timing diagram of the array substrate according to the embodiment of the present disclosure when the sub-area is displayed at different resolutions as shown in FIG. 8A;
  • FIG. 8B is a driving timing diagram of the array substrate according to the embodiment of the present disclosure when the sub-area is displayed at different resolutions as shown in FIG. 8A;
  • FIG. 9A is a second schematic diagram showing the display of different resolutions of the array substrate sub-areas according to an embodiment of the present disclosure.
  • FIG. 9B is a driving timing diagram of the array substrate according to the embodiment of the present disclosure when the sub-regions are displayed at different resolutions as shown in FIG. 9A; FIG.
  • FIG. 10 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 11 is a flowchart of a driving method of an array substrate according to an embodiment of the present disclosure.
  • the resolution of the display panel using the conventional gate driving circuit is fixed, the resolution cannot be adjusted according to actual needs, and selective driving cannot be realized in different areas of the display panel.
  • the display panel, the display device, and the driving method provided by the embodiments of the present disclosure can change the display resolution and can selectively drive different resolutions in different regions of the display panel.
  • an embodiment of the present disclosure provides an array substrate 10.
  • the array substrate 10 includes: a plurality of first pixel units P1 arranged in an array in the first area A1; a first gate driving circuit 110; a second gate driving circuit 120; and a first gate The plurality of first gate lines G1 connected to the driving circuit 110; and the plurality of second gate lines G2 connected to the second gate driving circuit 120.
  • a first portion of the plurality of first pixel units P1 is connected to the plurality of first gate lines G1, and each of the first pixel units P1 of the first portion is connected to one of the plurality of first gate lines G1; the plurality of first pixels
  • the second portion in the cell P1 is connected to the plurality of second gate lines G2, and each of the first pixel units P1 of the second portion is connected to one of the plurality of second gate lines G2.
  • the plurality of first pixel units P1 include a first subset and a second subset, wherein the first subset includes the first pixel unit P1 in the first portion of the plurality of first pixel units P1
  • the second subset includes a first pixel unit P1 of the second portion of the plurality of first pixel units P1.
  • the first pixel unit P1 of the 2n-1th row is connected to the nth first gate line G1; the first pixel unit P1 of the 2nth row is connected to the nth second gate line G2.
  • the embodiments of the present disclosure include, but are not limited to, the first pixel unit P1 of the 2n-1th row is connected to one of the first gate lines G1, and the first pixel unit P1 and the second gate line of the 2nth row are connected.
  • G2 In the case of one connection, the first pixel unit P1 of the 2n-1th row may be connected to one of the second gate lines G2, and the first pixel unit P1 of the 2nth row may be connected to one of the first gate lines G1.
  • the first pixel unit P1 of the same column shares the same data line (not shown), that is, the first pixel unit of the same column is connected to the same data line.
  • the timing of the first gate driving signal provided by the first gate driving circuit 110 through the first gate line G1 and the second gate provided by the second gate driving circuit 120 through the second gate line G2 The timing of the driving signals is the same, and the first pixel unit P1 of the 2n-1th row and the 2nth row of the same column will be turned on simultaneously with the first gate driving signal and the second gate driving signal, that is, receive the same data signal.
  • the first pixel unit P1 of the 2n-1st row and the 2nth row displays the same image, thereby reducing the resolution of the array substrate display.
  • the timing of the first gate driving signal provided by the first gate driving circuit 110 through the first gate line G1 and the second gate provided by the second gate driving circuit 120 through the second gate line G2 The timing of the driving signals is different, and the first pixel unit P1 of the same column may be sequentially turned on in response to the first gate driving signal and the second gate driving signal, that is, progressive scanning.
  • the first pixel unit P1 of the 2n-1st row and the 2nth row displays different images, thereby maintaining the resolution of the array substrate display.
  • the timing of the gate driving signals is the same, that is, the gate driving signals provided by the corresponding gate lines are the same, for example, the first gates provided by the first gate lines connected to the second pixel unit P1 of the 2n-1th row.
  • the pole drive signal is the same as the second gate drive signal provided by the second gate line connected to the 2nth row of the first pixel unit P1.
  • the low resolution mode is the FHD (2K pixel) mode and the high resolution mode is the UD (4K pixel) mode.
  • the array substrate 10 provided by the embodiment of the present disclosure further includes a plurality of second pixel units P2 arranged in an array in the second area A2; and a plurality of arrays arranged in the array in the third area A3.
  • a first portion of the plurality of second pixel units P2 is connected to the plurality of first gate lines G1, and each of the second pixel units P2 of the first portion is connected to one of the plurality of first gate lines G1; a plurality of second pixel units
  • the second portion of P2 is connected to the plurality of third gate lines G3, and each of the second pixel units P2 of the second portion is connected to one of the plurality of third gate lines G3;
  • the first of the plurality of third pixel units P3 One portion is connected to the plurality of second gate lines G2, and each of the third pixel units P3 of the first portion is connected to one of the plurality of second gate lines G2; the plurality of third pixel sheets
  • the second portion of the element P3 is connected to the plurality of fourth gate lines G4, and each of the third pixel units P3 of the second portion is connected to one of the plurality of fourth gate lines G4.
  • the plurality of second pixel units P2 include a first subset and a second subset, wherein the first subset includes a second pixel unit P2 in the first portion of the plurality of second pixel units P2
  • the second subset includes a second pixel unit P2 of the second portion of the plurality of second pixel units P2.
  • the plurality of third pixel units P3 include a first subset and a second subset, wherein the first subset includes a third pixel unit P3 in the first portion of the plurality of third pixel units P3,
  • the second subset includes the third pixel unit P3 in the second portion of the plurality of third pixel units P3.
  • the first pixel unit P1 of the 2n-1th row and the second pixel unit P2 of the 2n-1th row are connected to the nth first gate line G1; the first pixel unit P1 and the 2nth row of the 2nth row
  • the third pixel unit P3 is connected to the nth second gate line G2; the second pixel unit P2 of the 2nth row is connected to the nth third gate line G3; and the third pixel unit P3 of the 2n-1th row is n fourth gate lines G4 are connected; n is an integer greater than zero.
  • the first pixel unit P1 of the first row and the second pixel unit P2 of the first row are connected to the first first gate line G1; the first pixel unit P1 of the second row and the second The third pixel unit P3 of the row is connected to the first second gate line G2; the second pixel unit P2 of the second row is connected to the first third gate line G3; and the third pixel unit P3 of the first row is the first The fourth gate line G4 is connected.
  • the first pixel unit P1 of the third row and the second pixel unit P2 of the third row are connected to the second first gate line G1; the first pixel unit P1 of the fourth row
  • the third pixel unit P3 of the four rows is connected to the second second gate line G2; the second pixel unit P2 of the fourth row is connected to the second third gate line G3; and the third pixel unit P3 of the third row is Two fourth gate lines G4 are connected.
  • n is another integer greater than 0, and so on, it will not be repeated here.
  • the timing of the first gate driving signal outputted by the first gate driving circuit 110 through the first gate line G1 and the second gate driving circuit 120 passing through the second gate line The timing of the second gate drive signal output by G2 is the same; when the first region A1 is high resolution In the rate mode, the timing of the first gate driving signal outputted by the first gate driving circuit 110 through the first gate line G1 and the second gate driving signal outputted by the second gate driving circuit 120 through the second gate line G2 The timing is different.
  • the timing of the first gate driving signal output by the first gate driving circuit 110 through the first gate line G1 and the first gate driving circuit 110 passing through the third gate line The timing of the third gate driving signal outputted by G3 is the same; when the second region A2 is in the high resolution mode, the timing of the first gate driving signal output by the first gate driving circuit 110 through the first gate line G1 is the same as that of the first gate driving signal.
  • the timing of the third gate driving signal outputted by the gate driving circuit 110 through the third gate line G3 is different.
  • the timing of the second gate driving signal output by the second gate driving circuit 120 through the second gate line G2 and the second gate driving circuit 120 passing through the fourth gate line The timing of the fourth gate driving signal outputted by G4 is the same; when the third area A3 is in the high resolution mode, the timing of the second gate driving signal output by the second gate driving circuit 120 through the second gate line G2 is the same as that of the second gate driving signal The timing of the fourth gate driving signal output by the second gate driving circuit 120 through the fourth gate line G4 is different.
  • the display resolution can be changed and Selective driving of different resolutions can be performed in different regions of the array substrate (for example, the first region A1, the second region A2, and the third region A3), so that different resolutions can be displayed in different regions, and both can be balanced.
  • the user saves power while watching the experience.
  • the first area A1 is a high resolution mode
  • the second area A1 and the third area A3 are in a low resolution mode.
  • the first area A1 is disposed between the second area A2 and the third area A3.
  • embodiments of the present disclosure include, but are not limited to, the case where the array substrate 10 includes the first area A1, the second area A2, and the third area A3, and the array substrate 10 may also include a larger number of areas.
  • the first gate driving circuit 110 and the second gate driving circuit 120 are disposed on opposite sides of the array substrate 10.
  • the first gate driving circuit 110 and the second gate driving circuit 120 are disposed on opposite sides of the array substrate 10 to facilitate Circuit design and production to reduce costs.
  • the first gate driving circuit 110 includes a first shift register group, and the first shift register group includes a plurality of cascaded first shifts.
  • Bit register S1 In addition to the first stage and the last stage, the input terminal IN of the first shift register S1 of the present stage is connected to the output terminal OUT of the first shift register S1 of the previous stage.
  • the second gate driving circuit 120 includes a second shift register group, and the second shift register group includes a plurality of cascaded second shift registers S2, except for the first stage and the last stage, the second shift of the level
  • the input terminal IN of the bit register S2 is connected to the output terminal OUT of the second stage shift register S2 of the previous stage.
  • the first gate driving circuit 110 further includes a third shift register group including a plurality of cascaded third shift registers S3.
  • the input terminal IN of the third stage shift register S3 of the present stage is connected to the output terminal OUT of the third stage shift register S3 of the previous stage.
  • the second gate drive circuit 120 further includes a fourth shift register set including a plurality of cascaded first shift registers S4.
  • the input terminal IN of the fourth shift register S4 of the present stage is connected to the output terminal OUT of the fourth stage shift register S4 of the previous stage.
  • the reset terminal RE of the first shift register S1 of the present stage is connected to the output terminal OUT of the first shift register S1 of the next stage.
  • the reset terminal RE of the second shift register S2 of the present stage is connected to the output terminal OUT of the second shift register S2 of the next stage.
  • the reset terminal RE of the third shift register S3 of the present stage is connected to the output terminal OUT of the third stage shift register S3 of the next stage.
  • the reset terminal RE of the fourth shift register S4 of the present stage is connected to the output terminal OUT of the fourth stage shift register S4 of the next stage.
  • the input terminal IN of the first stage first shift register S1 is configured to receive the first trigger signal STV1.
  • the reset terminal RE of the last stage first shift register S1 is configured to receive the first reset signal RST1.
  • the input IN of the first stage second shift register S2 is configured to receive the second trigger signal STV2.
  • the reset terminal RE of the last stage second shift register S2 is configured to receive the second reset signal RST2.
  • the input terminal IN of the first stage third shift register S3 is configured to receive the third trigger signal STV3.
  • the reset terminal RE of the last stage third shift register S3 is configured to receive the third reset signal RST3.
  • the input terminal IN of the first stage fourth shift register S4 is configured to receive the fourth trigger signal STV4.
  • the reset terminal RE of the last stage fourth shift register S4 is configured to receive the fourth reset signal RST4.
  • each first shift register S1 is correspondingly connected to one of the first gate lines G1
  • each of the first shift registers S1 is The first gate drive signal is configured to be output to one of the first gate lines G1 in response to the first clock signal CK1.
  • the output terminal OUT of each second shift register S2 is correspondingly connected to one of the second gate lines G2, and each second shift register S2 is configured to output a second to one of the second gate lines G2 in response to the second clock signal CK2.
  • Gate drive signal is configured to be output to one of the first gate lines G1 in response to the first clock signal CK1.
  • each third shift register S3 is correspondingly connected to one of the third gate lines G3, and each third shift register S3 is configured to output a third to one of the third gate lines G3 in response to the third clock signal CK3.
  • the output terminal OUT of each fourth shift register S4 is correspondingly connected to one of the fourth gate lines G4, and each fourth shift register S4 is configured to output a fourth to one of the fourth gate lines G4 in response to the fourth clock signal CK4. Gate drive signal.
  • the first clock signal CK1 includes signals C11, C12, C13, and C14 which are sequentially arranged in time series output through different clock signal lines.
  • the second clock signal CK2 includes signals C21, C22, C23, and C24 which are sequentially arranged in time series output through different clock signal lines.
  • the third clock signal CK3 includes signals C31, C32, C33, and C34 which are sequentially arranged in time series output through different clock signal lines.
  • the fourth clock signal CK4 includes signals C41, C42, C43, and C44 which are sequentially arranged in time series output through different clock signal lines.
  • the same timing of the clock signals means that the sequentially arranged signals included in the clock signal are all the same.
  • the timing of the first clock signal CK1 is the same as the timing of the second clock signal CK2, which means that the timing of the signal C11 is the same as the timing of the signal C21, the timing of the signal C12 is the same as the timing of the signal C22, and the timing of the signal C13 is related to the signal C23.
  • the timing is the same, and the timing of signal C14 is the same as the timing of signal C24.
  • the same timing of two signals means that the voltages of the two signals are the same at the same time.
  • the array substrate 10 provided by the embodiment of the present disclosure further includes a first clock generator 130 and a second clock generator 140.
  • the first clock generator 130 is configured to provide a first clock signal CK1 to the first shift register S1 (eg, the clock signal terminal CLK of the first shift register S1);
  • the second clock generator 140 is configured to be second
  • the shift register S2 eg, the clock signal terminal CLK of the second shift register S2
  • the first clock generator 130 is also configured to be to the third shift register S3 (eg, a third shift)
  • the clock signal terminal CLK) of the register S3 provides the third clock signal CK3;
  • the second clock generator 140 is further configured to provide the fourth shift register S4 (eg, the clock signal terminal CLK of the fourth shift register S4) Four clock signals CK4.
  • first clock generator 130 and the second clock generator 140 may be further configured to provide the first trigger signal STV1, the first reset signal RST1, the second trigger signal STV2, the second reset signal RST2, and the third, respectively or together.
  • the first clock generator 130 is configured to provide the first clock signal CK1 to the first shift registers S1 of the stages through the four clock signal lines.
  • the first shift register S1 of the 4m-3th stage is configured to receive the signal C11 in the first clock signal CK1;
  • the first shift register S1 of the 4m-2th stage is configured to receive the signal in the first clock signal CK1 C12;
  • the first shift register S1 of the 4m-1th stage is configured to receive the signal C13 in the first clock signal CK1;
  • the first shift register S1 of the 4mth stage is configured to receive the signal in the first clock signal CK1 C14,
  • m is an integer greater than zero.
  • the second clock generator 140 is configured to provide the second clock signal CK2 to the second shift registers S2 of the respective stages through the four clock signal lines.
  • the second shift register S2 of the 4m-3th stage is configured to receive the signal C21 in the second clock signal CK2;
  • the second shift register S2 of the 4m-2th stage is configured to receive the signal in the second clock signal CK2 C22;
  • the second shift register S2 of the 4m-1th stage is configured to receive the signal C23 in the second clock signal CK2;
  • the second shift register S2 of the 4mth stage is configured to receive the signal in the second clock signal CK2 C24,
  • m is an integer greater than 0, m ⁇ N/8.
  • the first clock generator 130 is further configured to provide a third clock signal CK3 to each of the third shift registers S3 through the four clock signal lines.
  • the third shift register S3 of the 4m-3th stage is configured to receive the signal C31 in the third clock signal CK3;
  • the third shift register S3 of the 4m-2th stage is configured to receive the signal in the third clock signal CK3 C32;
  • the third shift register S3 of the 4m-1th stage is configured to receive the signal C33 in the third clock signal CK3;
  • the third shift register S3 of the 4mth stage is configured to receive the signal in the third clock signal CK3 C34,
  • m is an integer greater than 0, and m ⁇ N/8.
  • the second clock generator 140 is further configured to provide a fourth clock signal CK4 to the fourth shift register S4 of each stage through four clock signal lines.
  • the fourth shift register S4 of the 4m-3th stage is configured to receive the signal C41 in the fourth clock signal CK4; the fourth stage of the 4th-2th stage
  • the shift register S4 is configured to receive the signal C42 in the fourth clock signal CK4; the fourth shift register S4 of the 4m-1th stage is configured to receive the signal C43 in the fourth clock signal CK4; fourth in the 4th level
  • the shift register S4 is configured to receive the signal C44 in the fourth clock signal CK4, m being an integer greater than 0, m ⁇ N/8.
  • the embodiment of the present disclosure includes but is not limited to the situation shown in FIG. 3, and the first clock generator 130 may also be configured to provide the first clock to the first shift register S1 through two clock signal lines.
  • the signal CK1; the second clock generator 140 may also be configured to provide the second clock signal CK2 to the second shift register S2 through two clock signal lines; the first clock generator 130 may also be configured to pass two clock signals
  • the line provides a third clock signal CK3 to the third shift register S3; the second clock generator 140 can also be configured to provide the fourth clock signal CK4 to the fourth shift register S4 through the two clock signal lines, no longer Narration.
  • the array substrate 10 provided by the embodiment of the present disclosure further includes a clock controller 150.
  • the clock controller 150 is coupled to the first clock generator 130 and the second clock generator 140, respectively.
  • the clock controller 150 is configured to control timings of the first clock signal CK1 and the third clock signal CK3 provided by the first clock generator 130, and to control the second clock signal CK2 and the fourth clock signal provided by the second clock generator 140. Timing of CK4.
  • the clock controller 150 may be further configured to control the first trigger signal STV1, the first reset signal RST1, the second trigger signal STV2, and the second, respectively or jointly provided by the first clock generator 130 and the second clock generator 140. Timings of the reset signal RST2, the third trigger signal STV3, the third reset signal RST3, the fourth trigger signal STV4, and the fourth reset signal RST4.
  • first clock generator 130, the second clock generator 140, and the clock controller 150 may each be implemented by an application specific integrated circuit chip, or may be implemented by circuitry or by software, hardware (circuit), firmware, or any combination thereof.
  • first clock generator 130 and the second clock generator 140 can be implemented by the same integrated chip.
  • the clock controller 150 can be implemented in the first clock generator 130 or the second clock generator 140.
  • the first clock generator 130, the second clock generator 140, or the clock controller 150 can include a processor, a memory.
  • the processor may process the data signals, and may include various computing structures, such as a Complex Instruction Set Computer (CISC) structure, a Structured Reduced Instruction Set Computer (RISC) structure, or a combination of multiple instruction sets. Structure.
  • the processor can also be a microprocessor, such as an X86 processor or an ARM processor, or So digital processor (DSP) and so on.
  • the processor can control other components to perform the desired functions.
  • the memory may hold instructions and/or data executed by the processor.
  • the memory can include one or more computer program products, which can include various forms of computer readable storage media, such as volatile memory and/or nonvolatile memory.
  • the volatile memory may include, for example, a random access memory (RAM) and/or a cache or the like.
  • the nonvolatile memory may include, for example, a read only memory (ROM), a hard disk, a flash memory, or the like.
  • One or more computer program instructions can be stored on the computer readable storage medium, and the processor can execute the program instructions to implement a desired function (implemented by a processor) in an embodiment of the present disclosure.
  • Various applications and various data may also be stored in the computer readable storage medium, such as various data used and/or generated by the application, and the like.
  • the array substrate 10 provided by the embodiment of the present disclosure includes three display strips B1, B2, and B3 (for example, three display strips arranged one above another), each of which includes a first area A1, a second The number of rows of the first pixel unit P1 in the first region A1 in the region A2 and the third region A3, the number of rows of the second pixel unit P2 in the second region A2, and the number in the third region A3
  • the number of rows of the three-pixel unit P3 is equal.
  • embodiments of the present disclosure include, but are not limited to, the case where the array substrate includes three display strips, and the array substrate may also include other numbers (for example, four, five or more) display strips.
  • three first gate driving circuits 110 respectively connected to the three display strips B1, B2, and B3 may be connected together to work together; respectively, with three display strips B1, B2, and B3.
  • the three second gate drive circuits 120 correspondingly connected can be connected together to work together.
  • the output of the first shift register of the last stage in the first gate drive circuit correspondingly connected to the display strip B1 may be the first of the first stage of the first gate drive circuit correspondingly connected to the display strip B2.
  • the input end of the shift register is connected such that the signal outputted from the output end of the first shift register of the last stage of the first gate drive circuit correspondingly connected to the display strip B1 is used as the first gate connected to the display strip B2.
  • the first trigger signal STV1 of the first shift register of the first stage in the pole drive circuit For another example, the reset end of the first shift register of the last stage in the first gate driving circuit correspondingly connected to the display strip B1 may be the first stage of the first gate driving circuit corresponding to the display strip B2 An output terminal of a shift register is connected such that an output signal of the first shift register output of the first stage of the first gate driving circuit correspondingly connected to the display strip B2 is used as A first reset signal RST1 of the first shift register of the last stage of the first gate driving circuit with B1 correspondingly connected is displayed.
  • the first gate driving circuit or the other shift register in the second gate driving circuit corresponding to the different display bands may have a similar connection relationship, and details are not described herein again.
  • the first shift register S1, the second shift register S2, the third shift register S3, and the fourth shift register S4 may be represented by The shift register 100 shown in FIG. 5 is implemented.
  • each of the first shift register S1, the second shift register S2, the third shift register S3, and the fourth shift register S4 includes: an input circuit 111, a reset circuit 112, an output circuit 113, and an output pull-down The circuit 114, the pull-down node control circuit 115, and the storage capacitor Cst.
  • the input circuit 111 is respectively connected to the input terminal IN and the pull-up node PU; the reset circuit 112 is connected to the pull-up node PU, the reset terminal RE and the first power terminal VGL respectively; the output circuit 113 and the pull-up node PU, the clock signal terminal CLK and The output terminals OUT are respectively connected; the output terminal pull-down circuit 114 is respectively connected to the output terminal OUT, the pull-down node PD and the first power supply terminal VGL; the pull-down node control circuit 115 and the pull-down node PD, the second power supply terminal VDD and the first power supply terminal VGL respectively Connection; the storage capacitor Cst is connected to the pull-up node PU and the output terminal OUT, respectively.
  • the first power supply voltage provided by the first power supply terminal VGL is a low level voltage (for example, -5V, -1V, 0V or other value); the second power supply voltage provided by the second power supply terminal VDD is a high level voltage ( For example, 5V, 8V or other values).
  • the input circuit 111 includes a first transistor T1, and the first electrode of the first transistor T1 is connected to the input terminal IN, and the gate of the first transistor T1 is connected.
  • the pole is connected to the input terminal IN, and the second pole of the first transistor T1 is connected to the pull-up node PU.
  • the reset circuit 112 includes a second transistor T2, the first pole of the second transistor T2 is connected to the pull-up node PU, the gate of the second transistor T2 is connected to the reset terminal RE, and the second pole of the second transistor T2 is connected to the first power terminal. VGL connection.
  • the output circuit 113 includes a third transistor T3.
  • the first transistor of the third transistor T3 is connected to the clock signal terminal CLK, the gate of the third transistor T3 is connected to the pull-up node PU, and the second transistor of the third transistor T3 is connected to the output terminal OUT. connection.
  • the output pull-down circuit 114 includes a fourth transistor T4, the first pole of the fourth transistor T4 is connected to the output terminal OUT, the gate of the fourth transistor T4 is connected to the pull-down node PD, and the second pole of the fourth transistor T4 is connected to the first power source. End VGL connection.
  • the pull-down node control circuit 115 includes a fifth transistor T5 and a sixth transistor T6, the first pole of the fifth transistor T5 is connected to the second power terminal VDD, the gate of the fifth transistor T5 is connected to the second power terminal VDD, and the second pole of the fifth transistor T5 is connected to the pull-down node PD; the sixth transistor The first pole of T6 is connected to the pull-down node PD, the gate of the sixth transistor T6 is connected to the pull-up node PU, and the second pole of the sixth transistor T6 is connected to the first power supply terminal VGL.
  • the first end of the storage capacitor Cst is connected to the pull-up node PU, and the second end of the storage capacitor Cst is connected to the output terminal OUT.
  • the transistors used in the embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other switching devices having the same characteristics.
  • the source and drain of the transistor used here may be structurally symmetrical, so that the source and the drain may be structurally indistinguishable.
  • the first pole of the transistor of the embodiment of the present disclosure in order to distinguish the two poles of the transistor except the gate, one of the first poles and the other pole are directly described, so the first pole of all or part of the transistors in the embodiment of the present disclosure
  • the second pole is interchangeable as needed.
  • the first pole of the transistor of the embodiment of the present disclosure may be a source
  • the second pole may be a drain; or the first extreme drain of the transistor and the second source of the second.
  • the transistors can be divided into N-type and P-type transistors according to the characteristics of the transistors.
  • the turn-on voltage is a low level voltage (eg, 0V, -5V, or other value)
  • the turn-off voltage is a high level voltage (eg, 5V, 10V, or other value)
  • the turn-off voltage is a low level voltage (eg, 0V, -5V, or other value).
  • the embodiment of the present disclosure will be described by taking an example in which the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all N-type transistors. Based on the description and teachings of the implementation of the present disclosure, those skilled in the art can easily realize the implementation of the P-type transistor or the combination of the N-type and P-type transistors in the embodiments of the present disclosure without making creative efforts. These implementations are also within the scope of the present disclosure.
  • the shift register provided by the embodiment of the present disclosure includes but is not limited to the case shown in FIG. 6.
  • the shift register may further include other circuits, such as a circuit having a noise reduction function, etc., according to actual needs.
  • the input terminal IN receives the input signal of the high level
  • the first transistor T1 inputs the high level signal into the pull-up node PU
  • the third transistor T3 is turned on
  • the sixth transistor T6 is turned on
  • the sixth transistor T6 is turned on.
  • second The transistor T2 and the fourth transistor T4 are turned off.
  • the clock signal terminal CLK receives a high-level clock signal
  • the third transistor T3 transmits the high-level signal to the output terminal OUT; due to the bootstrap action of the storage capacitor Cst, the voltage of the pull-up node PU Further raising, the third transistor T3 is more fully turned on, and the high-level clock signal is output to the output terminal OUT through the third transistor T3.
  • the reset terminal RE receives the signal of the high level
  • the second transistor T2 is turned on, and the second transistor T2 transmits the first power supply voltage provided by the first power supply terminal VGL of the low level to the pull-up node PU
  • the sixth transistor T6 is turned off
  • the fifth transistor T5 transmits the second power supply voltage provided by the second power supply terminal VDD of the high level to the pull-down node PD
  • the fourth transistor T4 is turned on
  • the fourth transistor T4 turns the first power supply of the low level.
  • the first supply voltage provided by the terminal VGL is transmitted to the output terminal OUT.
  • the output terminal OUT can output a high level signal synchronously or substantially synchronously with the high level clock signal received by the clock signal terminal CLK.
  • the first gate driving circuit 110 and the first gate driving circuit 110 can be adjusted by adjusting clock signals (for example, the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4)
  • the respective gate driving signals output by the second gate driving circuit 120 thereby achieving a change in display resolution and selective driving of different resolutions in different regions of the array substrate. For example, this setup saves power.
  • FIG. 8A is a schematic diagram of a different resolution display of the array substrate sub-areas provided by the embodiment of the present disclosure
  • FIG. 8B is a diagram showing the array substrate provided by the embodiment of the present disclosure when performing sub-area different resolution display as shown in FIG. 8A. Drive timing diagram.
  • the three display strips each include three regions, i.e., the array substrate is divided into nine regions that are selectively changeable in resolution.
  • the upper left area, the middle middle area, and the lower right area are high resolution mode UD (4K pixels), and the other areas are low resolution mode FHD (2K pixels).
  • the timing of the first clock signal CK1 corresponding thereto, the timing of the second clock signal CK2, and the timing of the fourth clock signal CK4 are the same, and they are combined with the third clock signal.
  • the timing of CK3 is different.
  • the timing of the signal C11, the timing of the signal C21, and the timing of the signal C41 are the same, and they are different from the timing of the signal C31; the timing of the signal C12, the timing of the signal C22, and the timing of the signal C42 are the same, and they are different from the timing of the signal C32.
  • the upper left area is the high resolution mode UD
  • the upper middle area is the low resolution mode FHD
  • the timing of the first clock signal CK1 corresponding thereto is the same as the timing of the third clock signal CK3
  • the timing of the second clock signal CK2 is the same as the timing of the fourth clock signal CK4
  • the timing of one clock signal CK1 is different from the timing of the second clock signal CK2, so that the middle-middle region is the high-resolution mode UD, the left middle region, and the right middle region are the low-resolution mode FHD.
  • the timing of the first clock signal CK1 corresponding thereto, the timing of the second clock signal CK2, and the timing of the third clock signal CK3 are the same, and they are different from the timing of the fourth clock signal CK4.
  • the lower right area is the high resolution mode UD
  • the lower left area is the low resolution mode FHD.
  • FIG. 9A is a schematic diagram of a different resolution display of the array substrate sub-region provided by the embodiment of the present disclosure
  • FIG. 9B is a schematic diagram of the array substrate provided by the embodiment of the present disclosure when the sub-area is displayed at different resolutions as shown in FIG. 9A. Drive timing diagram.
  • the three display strips respectively include three regions, that is, the array substrate is divided into nine regions that can selectively change the resolution, so that the transformation of the nine region frame frequencies can be realized.
  • the frame frequency in the left middle area, the middle middle area, and the right middle area is 60 Hz
  • the frame frequency of other areas is 30 Hz.
  • the timing of the first clock signal CK1 corresponding thereto, the timing of the second clock signal CK2, the timing of the third clock signal CK3, and the timing of the fourth clock signal CK4 are both the same.
  • the timing of the first clock signal CK1 corresponding thereto is different from the timing of the third clock signal CK3, and the timing of the second clock signal CK2 is different from the timing of the fourth clock signal CK4.
  • the timing of the first clock signal CK1 corresponding thereto, the timing of the second clock signal CK2, the timing of the third clock signal CK3, and the timing of the fourth clock signal CK4 are the same.
  • the display manner of the array substrate 10 includes, but is not limited to, the cases shown in FIGS. 8A, 8B, 9A, and 9B. By adjusting the timing of each clock signal, selective driving of resolution in more cases can be realized. I will not repeat them here.
  • the embodiment of the present disclosure further provides a display panel 2, as shown in FIG. 10, the display panel 2 includes the array substrate 10 provided by any embodiment of the present disclosure.
  • the display panel 2 provided by the embodiment of the present disclosure may be a GOA (gate on array) display.
  • Display panel may be a GOA (gate on array) display.
  • the embodiment of the present disclosure further provides a display device 1.
  • the display device 1 includes the display panel 2 provided by any embodiment of the present disclosure.
  • the display device 1 may be any product or component having a display function such as an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or the like.
  • a display function such as an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or the like.
  • the display device 1 may further include a signal receiving circuit, a video signal decoding circuit, and the like so that the video signal may be received, processed, or may further include a modem circuit or an antenna or the like as needed. Connect to other device signals via network, wireless signals, etc.
  • the embodiment of the present disclosure further provides a method for driving the array substrate 10 provided by any embodiment of the present disclosure, including the following steps:
  • Step S10 providing a first gate driving signal to the first portion of the first pixel unit P1 through the first gate driving circuit 110;
  • Step S20 providing a second gate driving signal to the second portion of the first pixel unit P1 through the second gate driving circuit 120.
  • the timing of the first gate driving signal is different from the timing of the second gate driving signal; when the first region is in the low resolution mode The timing of the first gate driving signal is the same as the timing of the second gate driving signal.
  • the first and the first outputs of the first gate driving circuit 110 and the second gate driving circuit 120 can be adjusted by adjusting clock signals (for example, the first clock signal CK1 and the second clock signal CK2).
  • the two gate drive signals enable varying display resolutions and can be selectively driven at different resolutions in different regions of the array substrate.
  • the clock signal (eg, the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4) may be adjusted.
  • the respective gate driving signals output by the first gate driving circuit 110 and the second gate driving circuit 120 thereby realizing changing the display resolution and selectively driving different resolutions in different regions of the array substrate.

Abstract

一种阵列基板(10)、显示面板(2)、显示设备(1)及驱动方法。该阵列基板(10)包括：在第一区域(A1)中阵列排布的多个第一像素单元(P1)；第一栅极驱动电路(110)；第二栅极驱动电路(120)；与所述第一栅极驱动电路(110)连接的第一栅线(G1)；以及与所述第二栅极驱动电路(120)连接的第二栅线(G2)，其中，所述第一像素单元(P1)中的第一部分与所述第一栅线(G1)连接，且所述第一部分的每个所述第一像素单元(P1)与所述多条第一栅线(G1)之一连接；所述第一像素单元(P1)中的第二部分与所述第二栅线(G2)连接，且所述第二部分的每个所述第一像素单元(P1)与所述多条第二栅线(G2)之一连接。

Description

阵列基板、显示面板、显示设备及驱动方法 技术领域
本公开的实施例涉及一种阵列基板、显示面板、显示设备及驱动方法。
背景技术
在显示领域，有机发光二极管(OLED)显示面板具有自发光、对比度高、能耗低、视角广、响应速度快、可用于挠曲性面板、使用温度范围广、制造简单等特点，具有广阔的发展前景。由于上述特点，有机发光二极管(OLED)显示面板可以适用于手机、显示器、笔记本电脑、数码相机、仪器仪表等具有显示功能的装置。
随着显示技术的飞速发展，显示面板越来越向着高集成度和低成本的方向发展。栅极驱动电路基板(Gate-driver on Array，GOA)技术是通过光刻工艺将栅极驱动电路直接集成在显示装置的阵列基板上，GOA电路通常包括多个级联的移位寄存器，每个移位寄存器均对应一条栅线(例如，每个移位寄存器给与一行或一列像素对应的一条栅线提供扫描驱动信号)，以实现对显示面板的扫描驱动。这种集成技术可以节省栅极集成电路(Integrated Circuit，IC)的绑定(Bonding)区域以及扇出(Fan-out)区域的空间，从而实现显示面板的窄边框，同时可以降低产品成本、提高产品的良率。
发明内容
本公开的实施例提供一种阵列基板，包括：在第一区域中阵列排布的多个第一像素单元；第一栅极驱动电路；第二栅极驱动电路；与所述第一栅极驱动电路连接的多条第一栅线；以及与所述第二栅极驱动电路连接的多条第二栅线，其中，所述多个第一像素单元中的第一部分与所述多条第一栅线连接，且所述第一部分的每个所述第一像素单元与所述多条第一栅线之一连接；所述多个第一像素单元中的第二部分与所述多条第二栅线连接，且所述第二部分的每个所述第一像素单元与所述多条第二栅线之一连接。
例如，本公开实施例提供的阵列基板，还包括：在第二区域中阵列排布 的多个第二像素单元；在第三区域中阵列排布的多个第三像素单元；与所述第一栅极驱动电路连接的多条第三栅线；以及与所述第二栅极驱动电路连接的多条第四栅线，其中，所述多个第二像素单元中的第一部分与所述多条第一栅线连接，且所述第一部分的每个所述第二像素单元与所述多条第一栅线之一连接；所述多个第二像素单元中的第二部分与所述多条第三栅线连接，且所述第二部分的每个所述第二像素单元与所述多条第三栅线之一连接；所述多个第三像素单元中的第一部分与所述多条第二栅线连接，且所述第一部分的每个所述第三像素单元与所述多条第二栅线之一连接；所述多个第三像素单元中的第二部分与所述多条第四栅线连接，且所述第二部分的每个所述第三像素单元与所述多条第四栅线之一连接。
例如，在本公开实施例提供的阵列基板中，第2n-1行的所述第一像素单元和第2n-1行的所述第二像素单元与第n条所述第一栅线连接；第2n行的所述第一像素单元和第2n行的所述第三像素单元与第n条所述第二栅线连接；第2n行的所述第二像素单元与第n条所述第三栅线连接；第2n-1行的所述第三像素单元与第n条所述第四栅线连接；n为大于0的整数，n≤N/2，N为各区域中的像素单元的总行数。
例如，在本公开实施例提供的阵列基板中，所述第一区域设置在所述第二区域和所述第三区域之间。
例如，在本公开实施例提供的阵列基板中，所述第一栅极驱动电路和所述第二栅极驱动电路设置在所述阵列基板相对的两侧。
例如，在本公开实施例提供的阵列基板中，所述第一栅极驱动电路包括第一移位寄存器组，所述第一移位寄存器组包括级联的多个第一移位寄存器，除第一级和最后一级之外，本级第一移位寄存器的输入端与上一级第一移位寄存器的输出端连接；所述第二栅极驱动电路包括第二移位寄存器组，所述第二移位寄存器组包括级联的多个第二移位寄存器，除第一级和最后一级之外，本级第二移位寄存器的输入端与上一级第二移位寄存器的输出端连接；所述第一栅极驱动电路还包括第三移位寄存器组，所述第三移位寄存器组包括级联的多个第三移位寄存器，除第一级和最后一级之外，本级第三移位寄存器的输入端与上一级第三移位寄存器的输出端连接；所述第二栅极驱动电路还包括第四移位寄存器组，所述第四移位寄存器组包括级联的多个第一移 位寄存器，除第一级和最后一级之外，本级第四移位寄存器的输入端与上一级第四移位寄存器的输出端连接。
例如，在本公开实施例提供的阵列基板中，各所述第一移位寄存器的输出端与所述第一栅线之一对应连接，各所述第一移位寄存器被配置为响应于第一时钟信号向所述第一栅线之一输出第一栅极驱动信号；各所述第二移位寄存器的输出端与所述第二栅线之一对应连接，各所述第二移位寄存器被配置为响应于第二时钟信号向所述第二栅线之一输出第二栅极驱动信号；各所述第三移位寄存器的输出端与第三栅线之一对应连接，各所述第三移位寄存器被配置为响应于第三时钟信号向所述第三栅线之一输出第三栅极驱动信号；各所述第四移位寄存器的输出端与第四栅线之一对应连接，各所述第四移位寄存器被配置为响应于第四时钟信号向所述第四栅线之一输出第四栅极驱动信号。
例如，本公开实施例提供的阵列基板，还包括第一时钟发生器和第二时钟发生器，其中，所述第一时钟发生器被配置为向所述第一移位寄存器提供所述第一时钟信号；所述第二时钟发生器被配置为向所述第二移位寄存器提供所述第二时钟信号；所述第一时钟发生器还被配置为向所述第三移位寄存器提供所述第三时钟信号；以及所述第二时钟发生器还被配置为向所述第四移位寄存器提供所述第四时钟信号。
例如，本公开实施例提供的阵列基板，还包括：时钟控制器，分别与所述第一时钟发生器和所述第二时钟发生器连接，被配置为控制所述第一时钟发生器提供的第一时钟信号和第三时钟信号的时序、以及控制所述第二时钟发生器提供的第二时钟信号和第四时钟信号的时序。
例如，本公开实施例提供的阵列基板，包括三个显示带，每个所述显示带包括所述第一区域、所述第二区域和所述第三区域，且位于同一个显示带中的所述第一区域中所述第一像素单元的行数、所述第二区域中所述第二像素单元的行数以及所述第三区域中所述第三像素单元的行数相等。
例如，在本公开实施例提供的阵列基板中，所述第一移位寄存器、所述第二移位寄存器、所述第三移位寄存器以及所述第四移位寄存器中的每个包括：输入电路，与所述输入端和上拉节点分别连接；复位电路，与所述上拉节点、复位端及第一电源端分别连接；输出电路，与所述上拉节点、时钟信 号端及所述输出端分别连接；输出端下拉电路，与所述输出端、所述下拉节点及所述第一电源端分别连接；下拉节点控制电路，与所述下拉节点、第二电源端及所述第一电源端分别连接；以及存储电容，与所述上拉节点及所述输出端分别连接。
例如，在本公开实施例提供的阵列基板中，所述输入电路包括第一晶体管，所述第一晶体管的第一极与所述输入端连接，所述第一晶体管的栅极与所述输入端连接，所述第一晶体管的第二极与所述上拉节点连接；所述复位电路包括第二晶体管，所述第二晶体管的第一极与所述上拉节点连接，所述第二晶体管的栅极与所述复位端连接，所述第二晶体管的第二极与所述第一电源端连接；所述输出电路包括第三晶体管，所述第三晶体管的第一极与所述时钟信号端连接，所述第三晶体管的栅极与所述上拉节点连接，所述第三晶体管的第二极与所述输出端连接；所述输出端下拉电路包括第四晶体管，所述第四晶体管的第一极与所述输出端连接，所述第四晶体管的栅极与所述下拉节点连接，所述第四晶体管的第二极与所述第一电源端连接；所述下拉节点控制电路包括第五晶体管和第六晶体管，所述第五晶体管的第一极与所述第二电源端连接，所述第五晶体管的栅极与所述第二电源端连接，所述第五晶体管的第二极与所述下拉节点连接，所述第六晶体管的第一极与所述下拉节点连接，所述第六晶体管的栅极与所述上拉节点连接，所述第六晶体管的第二极与所述第一电源端连接；所述存储电容的第一端与所述上拉节点连接，所述存储电容的第二端与所述输出端连接。
本公开的实施例还提供一种显示面板，包括本公开任一实施例提供的阵列基板。
本公开的实施例还提供一种显示设备，包括本公开任一实施例提供的显示面板。
本公开的实施例还提供一种驱动本公开任一实施例提供的阵列基板的方法，包括：通过所述第一栅极驱动电路向所述第一像素单元中的第一部分提供第一栅极驱动信号；以及通过所述第二栅极驱动电路向所述第一像素单元中的第二部分提供第二栅极驱动信号，其中，当所述第一区域处于高分辨率模式时，所述第一栅极驱动信号的时序与所述第二栅极驱动信号的时序不同；当所述第一区域处于低分辨率模式时，所述第一栅极驱动信号的时序与所述 第二栅极驱动信号的时序相同。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，并非对本公开的限制。
图1是本公开实施例提供的阵列基板的示意图之一；
图2是本公开实施例提供的阵列基板的示意图之二；
图3是本公开实施例提供的阵列基板的示意图之三；
图4是本公开实施例提供的阵列基板的示意图之四；
图5是本公开实施例提供的阵列基板中移位寄存器的示意图之一；
图6是本公开实施例提供的阵列基板中移位寄存器的示意图之二；
图7是本公开实施例提供的如图6所示的移位寄存器的驱动时序图；
图8A是本公开实施例提供的阵列基板分区域进行不同分辨率显示的示意图之一；
图8B是本公开实施例提供的阵列基板进行如图8A所示的分区域不同分辨率显示时的驱动时序图；
图9A是本公开实施例提供的阵列基板分区域进行不同分辨率显示的示意图之二；
图9B是本公开实施例提供的阵列基板进行如图9A所示的分区域不同分辨率显示时的驱动时序图；
图10是本公开实施例提供的显示设备的示意图；以及
图11是本公开实施例提供的阵列基板的驱动方法的流程图。
具体实施方式
下面将结合附图，对本公开实施例中的技术方案进行清楚、完整地描述参考在附图中示出并在以下描述中详述的非限制性示例实施例，更加全面地说明本公开的示例实施例和它们的多种特征及有利细节。应注意的是，图中示出的特征不是必须按照比例绘制。本公开省略了已知材料、组件和工艺技术的描述，从而不使本公开的示例实施例模糊。所给出的示例仅旨在有利于 理解本公开示例实施例的实施，以及进一步使本领域技术人员能够实施示例实施例。因而，这些示例不应被理解为对本公开的实施例的范围的限制。
除非另外特别定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。此外，在本公开各个实施例中，相同或类似的参考标号表示相同或类似的构件。
应用传统的栅极驱动电路的显示面板的分辨率是固定的，不能根据实际需要调整分辨率，也无法在显示面板的不同区域实现选择性驱动。本公开实施例提供的显示面板、显示设备及驱动方法可以改变显示分辨率并可以在显示面板的不同区域进行不同分辨率的选择性驱动。
例如，本公开的实施例提供一种阵列基板10。如图1所示，阵列基板10包括：在第一区域A1中阵列排布的多个第一像素单元P1；第一栅极驱动电路110；第二栅极驱动电路120；与第一栅极驱动电路110连接的多条第一栅线G1；以及与第二栅极驱动电路120连接的多条第二栅线G2。多个第一像素单元P1中的第一部分与多条第一栅线G1连接，且该第一部分的每个第一像素单元P1与多条第一栅线G1之一连接；多个第一像素单元P1中的第二部分与多条第二栅线G2连接，且该第二部分的每个第一像素单元P1与多条第二栅线G2之一连接。例如，所述多个第一像素单元P1包括第一子集和第二子集，其中，所述第一子集包括所述多个第一像素单元P1的第一部分中的第一像素单元P1，所述第二子集包括所述多个第一像素单元P1的第二部分中的第一像素单元P1。
例如，继续参见图1，在本公开实施例提供的阵列基板10中，第2n-1行的第一像素单元P1与第一栅线G1之一连接；第2n行的第一像素单元P1与第二栅线G2之一连接，n为大于0的整数，n的最大值n(max)使得2*n(max)＝N,因此，n≤N/2，N为第一区域A1中的栅线的总数目。
又例如，第2n-1行的第一像素单元P1与第n条第一栅线G1连接；第2n行的第一像素单元P1与第n条第二栅线G2连接。
需要说明的是，本公开的实施例包括但不局限于第2n-1行的第一像素单元P1与第一栅线G1之一连接、第2n行的第一像素单元P1与第二栅线G2 之一连接的情形，也可以是第2n-1行的第一像素单元P1与第二栅线G2之一连接、第2n行的第一像素单元P1与第一栅线G1之一连接。
例如，同一列的第一像素单元P1共用同一条数据线(图中未示出)，也就是说，同一列的第一像素单元与同一条数据线连接。在低分辨率模式中，第一栅极驱动电路110通过第一栅线G1提供的第一栅极驱动信号的时序和第二栅极驱动电路120通过第二栅线G2提供的第二栅极驱动信号的时序相同，同一列第2n-1行和第2n行的第一像素单元P1将同时分别响应于第一栅极驱动信号和第二栅极驱动信号开启，即接收相同的数据信号。此时，第2n-1行和第2n行的第一像素单元P1显示相同的图像，从而降低了阵列基板显示的分辨率。在高分辨率模式中，第一栅极驱动电路110通过第一栅线G1提供的第一栅极驱动信号的时序和第二栅极驱动电路120通过第二栅线G2提供的第二栅极驱动信号的时序不同，同一列的第一像素单元P1可以分别响应于第一栅极驱动信号和第二栅极驱动信号顺序开启，即进行逐行扫描。此时，第2n-1行和第2n行的第一像素单元P1显示不同的图像，从而保持了阵列基板显示的分辨率。
例如，栅极驱动信号的时序相同指的是相对应的栅线提供的栅极驱动信号均相同，例如，与第2n-1行第一像素单元P1连接的第一栅线提供的第一栅极驱动信号和与第2n行第一像素单元P1连接的第二栅线提供的第二栅极驱动信号均相同。
例如，低分辨率模式是FHD(2K像素)模式，高分辨率模式是UD(4K像素)模式。
例如，如图2所示，本公开实施例提供的阵列基板10还包括在第二区域A2中阵列排布的多个第二像素单元P2；在第三区域A3中阵列排布的多个第三像素单元P3；与第一栅极驱动电路110连接的多条第三栅线G3；以及与第二栅极驱动电路120连接的多条第四栅线G4。多个第二像素单元P2中的第一部分与多条第一栅线G1连接，且第一部分的每个第二像素单元P2与多条第一栅线G1之一连接；多个第二像素单元P2中的第二部分与多条第三栅线G3连接，且第二部分的每个第二像素单元P2与多条第三栅线G3之一连接；多个第三像素单元P3中的第一部分与多条第二栅线G2连接，且第一部分的每个第三像素单元P3与多条第二栅线G2之一连接；多个第三像素单 元P3中的第二部分与多条第四栅线G4连接，且第二部分的每个第三像素单元P3与多条第四栅线G4之一连接。
例如，所述多个第二像素单元P2包括第一子集和第二子集，其中，所述第一子集包括所述多个第二像素单元P2的第一部分中的第二像素单元P2，所述第二子集包括所述多个第二像素单元P2的第二部分中的第二像素单元P2。所述多个第三像素单元P3包括第一子集和第二子集，其中，所述第一子集包括所述多个第三像素单元P3的第一部分中的第三像素单元P3，所述第二子集包括所述多个第三像素单元P3的第二部分中的第三像素单元P3。
例如，继续参见图2，在本公开实施例提供的阵列基板10中，第2n-1行的第一像素单元P1和第2n-1行的第二像素单元P2与第一栅线G1之一连接；第2n行的第一像素单元P1和第2n行的第三像素单元P3与第二栅线G2之一连接；第2n行的第二像素单元P2与第三栅线G3之一连接；第2n-1行的第三像素单元P3与第四栅线G4之一连接；n为大于0的整数，n≤N/2，N为各区域中的像素单元的总行数或各区域中的栅线的总数目。
又例如，第2n-1行的第一像素单元P1和第2n-1行的第二像素单元P2与第n条第一栅线G1连接；第2n行的第一像素单元P1和第2n行的第三像素单元P3与第n条第二栅线G2连接；第2n行的第二像素单元P2与第n条第三栅线G3连接；第2n-1行的第三像素单元P3与第n条第四栅线G4连接；n为大于0的整数。例如，当n＝1时，第1行的第一像素单元P1和第1行的第二像素单元P2与第1条第一栅线G1连接；第2行的第一像素单元P1和第2行的第三像素单元P3与第1条第二栅线G2连接；第2行的第二像素单元P2与第1条第三栅线G3连接；第1行的第三像素单元P3与第1条第四栅线G4连接。又例如，当n＝2时，第3行的第一像素单元P1和第3行的第二像素单元P2与第2条第一栅线G1连接；第4行的第一像素单元P1和第4行的第三像素单元P3与第2条第二栅线G2连接；第4行的第二像素单元P2与第2条第三栅线G3连接；第3行的第三像素单元P3与第2条第四栅线G4连接。例如，当n为大于0的其它整数时，依次类推，在此不再赘述。
例如，当第一区域A1为低分辨率模式时，第一栅极驱动电路110通过第一栅线G1输出的第一栅极驱动信号的时序与第二栅极驱动电路120通过第二栅线G2输出的第二栅极驱动信号的时序相同；当第一区域A1为高分辨 率模式时，第一栅极驱动电路110通过第一栅线G1输出的第一栅极驱动信号的时序与第二栅极驱动电路120通过第二栅线G2输出的第二栅极驱动信号的时序不同。
例如，当第二区域A2为低分辨率模式时，第一栅极驱动电路110通过第一栅线G1输出的第一栅极驱动信号的时序与第一栅极驱动电路110通过第三栅线G3输出的第三栅极驱动信号的时序相同；当第二区域A2为高分辨率模式时，第一栅极驱动电路110通过第一栅线G1输出的第一栅极驱动信号的时序与第一栅极驱动电路110通过第三栅线G3输出的第三栅极驱动信号的时序不同。
例如，当第三区域A3为低分辨率模式时，第二栅极驱动电路120通过第二栅线G2输出的第二栅极驱动信号的时序与第二栅极驱动电路120通过第四栅线G4输出的第四栅极驱动信号的时序相同；当第三区域A3为高分辨率模式时，第二栅极驱动电路120通过第二栅线G2输出的第二栅极驱动信号的时序与第二栅极驱动电路120通过第四栅线G4输出的第四栅极驱动信号的时序不同。
例如，通过调整第一栅极驱动信号的时序、第二栅极驱动信号的时序、第三栅极驱动信号的时序和第四栅极驱动信号的时序之间的关系，可以改变显示分辨率并可以在阵列基板的不同区域(例如，第一区域A1、第二区域A2和第三区域A3)进行不同分辨率的选择性驱动，从而可以实现在不同的区域显示不同的分辨率，可以在兼顾用户观看体验的同时节约电能。
例如，当用户观看第一区域A1时，第一区域A1为高分辨率模式，第二区域A1和第三区域A3为低分辨率模式。
例如，继续参见图2，在本公开实施例提供的阵列基板10中，第一区域A1设置在第二区域A2和第三区域A3之间。
例如，本公开的实施例包括但不局限于阵列基板10包括第一区域A1、第二区域A2和第三区域A3的情形，阵列基板10也可以包括更多数量的区域。
例如，在本公开实施例提供的阵列基板10中，第一栅极驱动电路110和第二栅极驱动电路120设置在阵列基板10相对的两侧。例如，第一栅极驱动电路110和第二栅极驱动电路120设置在阵列基板10相对的两侧可以便于 电路设计和生产，减少成本。
例如，如图3所示，在本公开实施例提供的阵列基板10中，第一栅极驱动电路110包括第一移位寄存器组，第一移位寄存器组包括级联的多个第一移位寄存器S1。除第一级和最后一级之外，本级第一移位寄存器S1的输入端IN与上一级第一移位寄存器S1的输出端OUT连接。第二栅极驱动电路120包括第二移位寄存器组，第二移位寄存器组包括级联的多个第二移位寄存器S2，除第一级和最后一级之外，本级第二移位寄存器S2的输入端IN与上一级第二移位寄存器S2的输出端OUT连接。
第一栅极驱动电路110还包括第三移位寄存器组，第三移位寄存器组包括级联的多个第三移位寄存器S3。除第一级和最后一级之外，本级第三移位寄存器S3的输入端IN与上一级第三移位寄存器S3的输出端OUT连接。第二栅极驱动电路120还包括第四移位寄存器组，第四移位寄存器组包括级联的多个第一移位寄存器S4。除第一级和最后一级之外，本级第四移位寄存器S4的输入端IN与上一级第四移位寄存器S4的输出端OUT连接。
例如，如图3所示，除第一级和最后一级之外，本级第一移位寄存器S1的复位端RE与下一级第一移位寄存器S1的输出端OUT连接。除第一级和最后一级之外，本级第二移位寄存器S2的复位端RE与下一级第二移位寄存器S2的输出端OUT连接。除第一级和最后一级之外，本级第三移位寄存器S3的复位端RE与下一级第三移位寄存器S3的输出端OUT连接。除第一级和最后一级之外，本级第四移位寄存器S4的复位端RE与下一级第四移位寄存器S4的输出端OUT连接。
例如，如图3所示，第一级第一移位寄存器S1的输入端IN被配置为接收第一触发信号STV1。最后一级第一移位寄存器S1的复位端RE被配置为接收第一复位信号RST1。第一级第二移位寄存器S2的输入端IN被配置为接收第二触发信号STV2。最后一级第二移位寄存器S2的复位端RE被配置为接收第二复位信号RST2。第一级第三移位寄存器S3的输入端IN被配置为接收第三触发信号STV3。最后一级第三移位寄存器S3的复位端RE被配置为接收第三复位信号RST3。第一级第四移位寄存器S4的输入端IN被配置为接收第四触发信号STV4。最后一级第四移位寄存器S4的复位端RE被配置为接收第四复位信号RST4。
例如，如图3所示，在本公开实施例提供的阵列基板10中，各第一移位寄存器S1的输出端OUT与第一栅线G1之一对应连接，各第一移位寄存器S1被配置为响应于第一时钟信号CK1向第一栅线G1之一输出第一栅极驱动信号。各第二移位寄存器S2的输出端OUT与第二栅线G2之一对应连接，各第二移位寄存器S2被配置为响应于第二时钟信号CK2向第二栅线G2之一输出第二栅极驱动信号。各第三移位寄存器S3的输出端OUT与第三栅线G3之一对应连接，各第三移位寄存器S3被配置为响应于第三时钟信号CK3向第三栅线G3之一输出第三栅极驱动信号。各第四移位寄存器S4的输出端OUT与第四栅线G4之一对应连接，各第四移位寄存器S4被配置为响应于第四时钟信号CK4向第四栅线G4之一输出第四栅极驱动信号。
例如，如图3所示，第一时钟信号CK1包括通过不同时钟信号线输出的在时序上顺次排布的信号C11、C12、C13和C14。第二时钟信号CK2包括通过不同时钟信号线输出的在时序上顺次排布的信号C21、C22、C23和C24。第三时钟信号CK3包括通过不同时钟信号线输出的在时序上顺次排布的信号C31、C32、C33和C34。第四时钟信号CK4包括通过不同时钟信号线输出的在时序上顺次排布的信号C41、C42、C43和C44。
例如，时钟信号的时序相同指的是时钟信号中包括的顺次排布的信号均对应相同。例如，第一时钟信号CK1的时序与第二时钟信号CK2的时序相同指的是信号C11的时序与信号C21的时序相同、信号C12的时序与信号C22的时序相同、信号C13的时序与信号C23的时序相同、信号C14的时序与信号C24的时序相同。
例如，两个信号时序相同是指该两个信号在同一时间的电压相同。
例如，如图3所示，本公开实施例提供的阵列基板10还包括第一时钟发生器130和第二时钟发生器140。第一时钟发生器130被配置为向第一移位寄存器S1(例如，第一移位寄存器S1的时钟信号端CLK)提供第一时钟信号CK1；第二时钟发生器140被配置为向第二移位寄存器S2(例如，第二移位寄存器S2的时钟信号端CLK)提供第二时钟信号CK2；第一时钟发生器130还被配置为向第三移位寄存器S3(例如，第三移位寄存器S3的时钟信号端CLK)提供第三时钟信号CK3；以及第二时钟发生器140还被配置为向第四移位寄存器S4(例如，第四移位寄存器S4的时钟信号端CLK)提供第 四时钟信号CK4。
例如，第一时钟发生器130和第二时钟发生器140还可以被配置为分别或共同提供第一触发信号STV1、第一复位信号RST1、第二触发信号STV2、第二复位信号RST2、第三触发信号STV3、第三复位信号RST3、第四触发信号STV4和第四复位信号RST4等。
例如，如图3所示，第一时钟发生器130被配置为通过四条时钟信号线向各级第一移位寄存器S1提供第一时钟信号CK1。第4m-3级的第一移位寄存器S1被配置为接收第一时钟信号CK1中的信号C11；第4m-2级的第一移位寄存器S1被配置为接收第一时钟信号CK1中的信号C12；第4m-1级的第一移位寄存器S1被配置为接收第一时钟信号CK1中的信号C13；第4m级的第一移位寄存器S1被配置为接收第一时钟信号CK1中的信号C14，m为大于0的整数。例如，各区域中(例如A1中)的栅线的总数目为N，m的最大值m(max)使得8*m(max)＝N,因此，m≤N/8。
例如，如图3所示，第二时钟发生器140被配置为通过四条时钟信号线向各级第二移位寄存器S2提供第二时钟信号CK2。第4m-3级的第二移位寄存器S2被配置为接收第二时钟信号CK2中的信号C21；第4m-2级的第二移位寄存器S2被配置为接收第二时钟信号CK2中的信号C22；第4m-1级的第二移位寄存器S2被配置为接收第二时钟信号CK2中的信号C23；第4m级的第二移位寄存器S2被配置为接收第二时钟信号CK2中的信号C24，m为大于0的整数，m≤N/8。
例如，如图3所示，第一时钟发生器130还被配置为通过四条时钟信号线向各级第三移位寄存器S3提供第三时钟信号CK3。第4m-3级的第三移位寄存器S3被配置为接收第三时钟信号CK3中的信号C31；第4m-2级的第三移位寄存器S3被配置为接收第三时钟信号CK3中的信号C32；第4m-1级的第三移位寄存器S3被配置为接收第三时钟信号CK3中的信号C33；第4m级的第三移位寄存器S3被配置为接收第三时钟信号CK3中的信号C34，m为大于0的整数，m≤N/8。
例如，如图3所示，第二时钟发生器140还被配置为通过四条时钟信号线向各级第四移位寄存器S4提供第四时钟信号CK4。第4m-3级的第四移位寄存器S4被配置为接收第四时钟信号CK4中的信号C41；第4m-2级的第四 移位寄存器S4被配置为接收第四时钟信号CK4中的信号C42；第4m-1级的第四移位寄存器S4被配置为接收第四时钟信号CK4中的信号C43；第4m级的第四移位寄存器S4被配置为接收第四时钟信号CK4中的信号C44，m为大于0的整数，m≤N/8。
需要说明的是，本公开的实施例包括但不局限于图3所示的情形，第一时钟发生器130也可以被配置为通过两条时钟信号线向第一移位寄存器S1提供第一时钟信号CK1；第二时钟发生器140也可以被配置为通过两条时钟信号线向第二移位寄存器S2提供第二时钟信号CK2；第一时钟发生器130也可以被配置为通过两条时钟信号线向第三移位寄存器S3提供第三时钟信号CK3；第二时钟发生器140也可以被配置为通过两条时钟信号线向第四移位寄存器S4提供第四时钟信号CK4，在此不再赘述。
例如，如图3所示，本公开实施例提供的阵列基板10还包括时钟控制器150。时钟控制器150分别与第一时钟发生器130和第二时钟发生器140连接。时钟控制器150被配置为控制第一时钟发生器130提供的第一时钟信号CK1和第三时钟信号CK3的时序、以及控制第二时钟发生器140提供的第二时钟信号CK2和第四时钟信号CK4的时序。
例如，时钟控制器150还可以被配置为控制第一时钟发生器130和第二时钟发生器140分别或共同提供的第一触发信号STV1、第一复位信号RST1、第二触发信号STV2、第二复位信号RST2、第三触发信号STV3、第三复位信号RST3、第四触发信号STV4和第四复位信号RST4的时序。
例如，第一时钟发生器130、第二时钟发生器140和时钟控制器150可以分别由专用集成电路芯片实现，也可以由电路或者采用软件、硬件(电路)、固件或其任意组合方式实现。例如，第一时钟发生器130和第二时钟发生器140可以由同一块集成芯片实现。又例如，时钟控制器150可以集成在第一时钟发生器130或第二时钟发生器140中实现。
又例如，第一时钟发生器130、第二时钟发生器140或时钟控制器150可以包括处理器、存储器。在本公开的实施例中，处理器可以处理数据信号，可以包括各种计算结构，例如复杂指令集计算机(CISC)结构、结构精简指令集计算机(RISC)结构或者一种实行多种指令集组合的结构。在一些实施例中，处理器也可以是微处理器，例如X86处理器或ARM处理器，或者可 以是数字处理器(DSP)等。处理器可以控制其它组件以执行期望的功能。在本公开的实施例中，存储器可以保存处理器执行的指令和/或数据。例如，存储器可以包括一个或多个计算机程序产品，所述计算机程序产品可以包括各种形式的计算机可读存储介质，例如易失性存储器和/或非易失性存储器。所述易失性存储器例如可以包括随机存取存储器(RAM)和/或高速缓冲存储器(cache)等。所述非易失性存储器例如可以包括只读存储器(ROM)、硬盘、闪存等。在所述计算机可读存储介质上可以存储一个或多个计算机程序指令，处理器可以运行所述程序指令，以实现本公开实施例中(由处理器实现)期望的功能。在所述计算机可读存储介质中还可以存储各种应用程序和各种数据，例如所述应用程序使用和/或产生的各种数据等。
例如，如图4所示，本公开实施例提供的阵列基板10包括三个显示带B1、B2和B3(例如上下排列的三个显示带)，每个显示带包括第一区域A1、第二区域A2和第三区域A3，且位于同一个显示带中的第一区域A1中第一像素单元P1的行数、第二区域A2中第二像素单元P2的行数以及第三区域A3中第三像素单元P3的行数相等。
需要说明的是，本公开的实施例包括但不局限于阵列基板包括三个显示带的情形，阵列基板也可以包括其它数量(例如，4个，5个或更多)的显示带。
例如，如图4所示，分别与三个显示带B1、B2和B3对应连接的三个第一栅极驱动电路110可以连接在一起从而协同工作；分别与三个显示带B1、B2和B3对应连接的三个第二栅极驱动电路120可以连接在一起从而协同工作。例如，与显示带B1对应连接的第一栅极驱动电路中最后一级的第一移位寄存器的输出端可以和与显示带B2对应连接的第一栅极驱动电路中第一级的第一移位寄存器的输入端连接，从而使与显示带B1对应连接的第一栅极驱动电路中最后一级的第一移位寄存器的输出端输出的信号作为与显示带B2对应连接的第一栅极驱动电路中第一级的第一移位寄存器的第一触发信号STV1。又例如，与显示带B1对应连接的第一栅极驱动电路中最后一级的第一移位寄存器的复位端可以和与显示带B2对应连接的第一栅极驱动电路中第一级的第一移位寄存器的输出端连接，从而使与显示带B2对应连接的第一栅极驱动电路中第一级的第一移位寄存器输出端的输出信号作为与 显示带B1对应连接的第一栅极驱动电路中最后一级的第一移位寄存器的第一复位信号RST1。类似的，与不同显示带对应连接的第一栅极驱动电路或第二栅极驱动电路中的其它移位寄存器也可以具有类似的连接关系，在此不再赘述。
例如，如图5所示，在本公开实施例提供的阵列基板10中，第一移位寄存器S1、第二移位寄存器S2、第三移位寄存器S3以及第四移位寄存器S4可以由图5所示的移位寄存器100实现。例如，第一移位寄存器S1、第二移位寄存器S2、第三移位寄存器S3以及第四移位寄存器S4中的每个包括：输入电路111、复位电路112、输出电路113、输出端下拉电路114、下拉节点控制电路115和存储电容Cst。输入电路111与输入端IN和上拉节点PU分别连接；复位电路112与上拉节点PU、复位端RE及第一电源端VGL分别连接；输出电路113与上拉节点PU、时钟信号端CLK及输出端OUT分别连接；输出端下拉电路114与输出端OUT、下拉节点PD及第一电源端VGL分别连接；下拉节点控制电路115与下拉节点PD、第二电源端VDD及第一电源端VGL分别连接；存储电容Cst与上拉节点PU及输出端OUT分别连接。
例如，第一电源端VGL提供的第一电源电压为低电平电压(例如，-5V、-1V，0V或其他数值)；第二电源端VDD提供的第二电源电压为高电平电压(例如，5V，8V或其他数值)。
例如，参见图5和图6，在本公开实施例提供的阵列基板10中，输入电路111包括第一晶体管T1，第一晶体管T1的第一极与输入端IN连接，第一晶体管T1的栅极与输入端IN连接，第一晶体管T1的第二极与上拉节点PU连接。复位电路112包括第二晶体管T2，第二晶体管T2的第一极与上拉节点PU连接，第二晶体管T2的栅极与复位端RE连接，第二晶体管T2的第二极与第一电源端VGL连接。输出电路113包括第三晶体管T3，第三晶体管T3的第一极与时钟信号端CLK连接，第三晶体管T3的栅极与上拉节点PU连接，第三晶体管T3的第二极与输出端OUT连接。输出端下拉电路114包括第四晶体管T4，第四晶体管T4的第一极与输出端OUT连接，第四晶体管T4的栅极与下拉节点PD连接，第四晶体管T4的第二极与第一电源端VGL连接。下拉节点控制电路115包括第五晶体管T5和第六晶体管 T6，第五晶体管T5的第一极与第二电源端VDD连接，第五晶体管T5的栅极与第二电源端VDD连接，第五晶体管T5的第二极与下拉节点PD连接；第六晶体管T6的第一极与下拉节点PD连接，第六晶体管T6的栅极与上拉节点PU连接，第六晶体管T6的第二极与第一电源端VGL连接。存储电容Cst的第一端与上拉节点PU连接，存储电容Cst的第二端与输出端OUT连接。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极，所以本公开实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。例如，本公开实施例所述的晶体管的第一极可以为源极，第二极可以为漏极；或者，晶体管的第一极为漏极，第二极为源极。此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V或其他数值)，关闭电压为高电平电压(例如，5V、10V或其他数值)；当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其他数值)，关闭电压为低电平电压(例如，0V、-5V或其他数值)。本公开的实施例以第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5和第六晶体管T6均为N型晶体管为例进行说明。基于本公开对该实现方式的描述和教导，本领域普通技术人员在没有做出创造性劳动前提下能够容易想到本公开实施例采用P型晶体管或N型和P型晶体管组合的实现方式，因此，这些实现方式也是在本公开的保护范围内的。
需要说明的是，本公开的实施例提供的移位寄存器包括但不局限于图6所示的情形，根据实际需要，移位寄存器还可以包括其它电路，例如具有降噪功能的电路等。
例如，接下来介绍图6所示的移位寄存器的工作原理，参见图6和图7。
在第一时段t1，输入端IN接收到高电平的输入信号，第一晶体管T1将该高电平信号输入上拉节点PU，第三晶体管T3开启，第六晶体管T6开启，第六晶体管T6将第一电源端VGL的低电平电压输入到下拉节点PD，第二 晶体管T2和第四晶体管T4关闭。
在第二时段t2，时钟信号端CLK接收到高电平的时钟信号，第三晶体管T3将该高电平信号传输到输出端OUT；由于存储电容Cst的自举作用，上拉节点PU的电压进一步升高，使得第三晶体管T3更充分地开启，高电平的时钟信号通过第三晶体管T3输出到输出端OUT。
在第三时段t3，复位端RE接收到高电平的信号，第二晶体管T2开启，第二晶体管T2将低电平的第一电源端VGL提供的第一电源电压传输到上拉节点PU，第六晶体管T6关闭，第五晶体管T5将高电平的第二电源端VDD提供的第二电源电压传输到下拉节点PD，第四晶体管T4开启，第四晶体管T4将低电平的第一电源端VGL提供的第一电源电压传输到输出端OUT。
例如，通过上述工作过程可以看出，在第二时段t2，输出端OUT可以与时钟信号端CLK接收到的高电平时钟信号同步或基本同步输出高电平信号。
例如，在阵列基板10中，可以通过调整时钟信号(例如，第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3和第四时钟信号CK4)来调整第一栅极驱动电路110和第二栅极驱动电路120输出的各个栅极驱动信号，进而实现改变显示分辨率并可以在阵列基板的不同区域进行不同分辨率的选择性驱动。例如，这种设置方式可以节省电能。
例如，图8A是本公开实施例提供的阵列基板分区域进行不同分辨率显示的示意图之一；图8B是本公开实施例提供的阵列基板进行如图8A所示的分区域不同分辨率显示时的驱动时序图。
例如，参见图8A和图8B，三个显示带分别包括三个区域，即阵列基板被分为九个可选择变更分辨率的区域。例如，在左上区域、中中区域和右下区域为高分辨率模式UD(4K像素)，其它区域为低分辨率模式FHD(2K像素)。在这种情况下，位于上方的第一显示带中，与其对应的第一时钟信号CK1的时序、第二时钟信号CK2的时序和第四时钟信号CK4的时序相同，而且它们与第三时钟信号CK3的时序不同。即信号C11的时序、信号C21的时序和信号C41的时序相同，而且它们与信号C31的时序不同；信号C12的时序、信号C22的时序和信号C42的时序相同，而且它们与信号C32的时序不同；信号C13的时序、信号C23的时序和信号C43的时序相同，而 且它们与信号C33的时序不同；信号C14的时序、信号C24的时序和信号C44的时序相同，而且它们与信号C34的时序不同。这样即可实现左上区域为高分辨率模式UD、中上区域和右上区域为低分辨率模式FHD。例如，位于中间的第二显示带中，与其对应的第一时钟信号CK1的时序和第三时钟信号CK3的时序相同，第二时钟信号CK2的时序和第四时钟信号CK4的时序相同，而且第一时钟信号CK1的时序与第二时钟信号CK2的时序不同，这样即可实现中中区域为高分辨率模式UD、左中区域和右中区域为低分辨率模式FHD。例如，位于下方的第三显示带中，与其对应的第一时钟信号CK1的时序、第二时钟信号CK2的时序和第三时钟信号CK3的时序相同，而且它们与第四时钟信号CK4的时序不同，这样即可实现右下区域为高分辨率模式UD、左下区域和中下区域为低分辨率模式FHD。
例如，图9A是本公开实施例提供的阵列基板分区域进行不同分辨率显示的示意图之二；图9B是本公开实施例提供的阵列基板进行如图9A所示的分区域不同分辨率显示时的驱动时序图。
例如，参见图9A和图9B，三个显示带分别包括三个区域，即阵列基板被分为九个可选择变更分辨率的区域，从而可以实现九个区域帧频的变换。例如，在左中区域、中中区域和右中区域的帧频为60Hz，其它区域的帧频为30Hz。在这种情况下，位于上方的第一显示带中，与其对应的第一时钟信号CK1的时序、第二时钟信号CK2的时序、第三时钟信号CK3的时序和第四时钟信号CK4的时序均相同。例如，位于中间的第二显示带中，与其对应的第一时钟信号CK1的时序和第三时钟信号CK3的时序不同，第二时钟信号CK2的时序和第四时钟信号CK4的时序不同。例如，位于下方的第三显示带中，与其对应的第一时钟信号CK1的时序、第二时钟信号CK2的时序、第三时钟信号CK3的时序和第四时钟信号CK4的时序均相同。
需要说明的是，阵列基板10的显示方式包括但不局限于图8A、8B、9A和9B所示的情形，通过调整各个时钟信号的时序，可以实现更多情况的分辨率的选择性驱动，在此不再赘述。
本公开的实施例还提供一种显示面板2，如图10所示，显示面板2包括本公开任一实施例提供的阵列基板10。
例如，本公开实施例提供的显示面板2可以是GOA(gate on array)显 示面板。
本公开的实施例还提供一种显示设备1，如图10所示，显示设备1包括本公开任一实施例提供的显示面板2。
例如，显示设备1可以为电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
例如，在本公开的至少一个实施例中，显示设备1还可以包括信号接收电路、视频信号解码电路等从而可以接收、处理视频信号，或者根据需要还可以包括调制解调电路或天线等从而可以通过网络、无线信号等与其他设备信号连接。
本公开的实施例还提供一种驱动本公开任一实施例提供的阵列基板10的方法，包括如下步骤：
步骤S10：通过第一栅极驱动电路110向第一像素单元P1中的第一部分提供第一栅极驱动信号；以及
步骤S20：通过第二栅极驱动电路120向第一像素单元P1中的第二部分提供第二栅极驱动信号。
例如，当所述第一区域处于高分辨率模式时，所述第一栅极驱动信号的时序与所述第二栅极驱动信号的时序不同；当所述第一区域处于低分辨率模式时，所述第一栅极驱动信号的时序与所述第二栅极驱动信号的时序相同。
例如，该驱动方法中，可以通过调整时钟信号(例如，第一时钟信号CK1、第二时钟信号CK2)来调整第一栅极驱动电路110和第二栅极驱动电路120输出的第一和第二栅极驱动信号，进而实现改变显示分辨率并可以在阵列基板的不同区域进行不同分辨率的选择性驱动。
例如，当阵列基板还包括第二区域和第三区域时，可以通过调整时钟信号(例如，第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3和第四时钟信号CK4)来调整第一栅极驱动电路110和第二栅极驱动电路120输出的各个栅极驱动信号，进而实现改变显示分辨率并可以在阵列基板的不同区域进行不同分辨率的选择性驱动。
虽然上文中已经用一般性说明及具体实施方式，对本公开作了详尽的描述，但在本公开实施例基础上，可以对之作一些修改或改进，这对本领域技术人员而言是显而易见的。因此，在不偏离本公开精神的基础上所做的这些 修改或改进，均属于本公开要求保护的范围。
本公开要求于2017年4月27日递交的中国专利申请第201710289041.0号的优先权，在此全文引用上述中国专利申请公开的内容以作为本公开的一部分。

Claims (15)

  1. 一种阵列基板，包括：
    在第一区域中阵列排布的多个第一像素单元；
    第一栅极驱动电路；
    第二栅极驱动电路；
    与所述第一栅极驱动电路连接的多条第一栅线；以及
    与所述第二栅极驱动电路连接的多条第二栅线，其中，
    所述多个第一像素单元中的第一部分与所述多条第一栅线连接，且所述第一部分的每个所述第一像素单元与所述多条第一栅线之一连接；
    所述多个第一像素单元中的第二部分与所述多条第二栅线连接，且所述第二部分的每个所述第一像素单元与所述多条第二栅线之一连接。
  2. 根据权利要求1所述的阵列基板，还包括：
    在第二区域中阵列排布的多个第二像素单元；
    在第三区域中阵列排布的多个第三像素单元；
    与所述第一栅极驱动电路连接的多条第三栅线；以及
    与所述第二栅极驱动电路连接的多条第四栅线，其中，
    所述多个第二像素单元中的第一部分与所述多条第一栅线连接，且所述第一部分的每个所述第二像素单元与所述多条第一栅线之一连接；
    所述多个第二像素单元中的第二部分与所述多条第三栅线连接，且所述第二部分的每个所述第二像素单元与所述多条第三栅线之一连接；
    所述多个第三像素单元中的第一部分与所述多条第二栅线连接，且所述第一部分的每个所述第三像素单元与所述多条第二栅线之一连接；
    所述多个第三像素单元中的第二部分与所述多条第四栅线连接，且所述第二部分的每个所述第三像素单元与所述多条第四栅线之一连接。
  3. 根据权利要求2所述的阵列基板，其中，
    第2n-1行的所述第一像素单元和第2n-1行的所述第二像素单元与第n条所述第一栅线连接；
    第2n行的所述第一像素单元和第2n行的所述第三像素单元与第n条所述第二栅线连接；
    第2n行的所述第二像素单元与第n条所述第三栅线连接；
    第2n-1行的所述第三像素单元与第n条所述第四栅线连接；
    n为大于0的整数，n≤N/2，N为各区域中的像素单元的总行数。
  4. 根据权利要求2所述的阵列基板，其中，所述第一区域设置在所述第二区域和所述第三区域之间。
  5. 根据权利要求1-4任一项所述的阵列基板，其中，所述第一栅极驱动电路和所述第二栅极驱动电路设置在所述阵列基板相对的两侧。
  6. 根据权利要求1-4任一项所述的阵列基板，其中，
    所述第一栅极驱动电路包括第一移位寄存器组，所述第一移位寄存器组包括级联的多个第一移位寄存器，除第一级和最后一级之外，本级第一移位寄存器的输入端与上一级第一移位寄存器的输出端连接；
    所述第二栅极驱动电路包括第二移位寄存器组，所述第二移位寄存器组包括级联的多个第二移位寄存器，除第一级和最后一级之外，本级第二移位寄存器的输入端与上一级第二移位寄存器的输出端连接；
    所述第一栅极驱动电路还包括第三移位寄存器组，所述第三移位寄存器组包括级联的多个第三移位寄存器，除第一级和最后一级之外，本级第三移位寄存器的输入端与上一级第三移位寄存器的输出端连接；
    所述第二栅极驱动电路还包括第四移位寄存器组，所述第四移位寄存器组包括级联的多个第一移位寄存器，除第一级和最后一级之外，本级第四移位寄存器的输入端与上一级第四移位寄存器的输出端连接。
  7. 根据权利要求6所述的阵列基板，其中，
    各所述第一移位寄存器的输出端与所述第一栅线之一对应连接，各所述第一移位寄存器被配置为响应于第一时钟信号向所述第一栅线之一输出第一栅极驱动信号；
    各所述第二移位寄存器的输出端与所述第二栅线之一对应连接，各所述第二移位寄存器被配置为响应于第二时钟信号向所述第二栅线之一输出第二栅极驱动信号；
    各所述第三移位寄存器的输出端与第三栅线之一对应连接，各所述第三移位寄存器被配置为响应于第三时钟信号向所述第三栅线之一输出第三栅极驱动信号；
    各所述第四移位寄存器的输出端与第四栅线之一对应连接，各所述第四移位寄存器被配置为响应于第四时钟信号向所述第四栅线之一输出第四栅极驱动信号。
  8. 根据权利要求7所述的阵列基板，还包括第一时钟发生器和第二时钟发生器，其中，
    所述第一时钟发生器被配置为向所述第一移位寄存器提供所述第一时钟信号；
    所述第二时钟发生器被配置为向所述第二移位寄存器提供所述第二时钟信号；
    所述第一时钟发生器还被配置为向所述第三移位寄存器提供所述第三时钟信号；以及
    所述第二时钟发生器还被配置为向所述第四移位寄存器提供所述第四时钟信号。
  9. 根据权利要求8所述的阵列基板，还包括：
    时钟控制器，分别与所述第一时钟发生器和所述第二时钟发生器连接，被配置为控制所述第一时钟发生器提供的第一时钟信号和第三时钟信号的时序、以及控制所述第二时钟发生器提供的第二时钟信号和第四时钟信号的时序。
  10. 根据权利要求2-4任一项所述的阵列基板，包括三个显示带，每个所述显示带包括所述第一区域、所述第二区域和所述第三区域，且位于同一个显示带中的所述第一区域中所述第一像素单元的行数、所述第二区域中所述第二像素单元的行数以及所述第三区域中所述第三像素单元的行数相等。
  11. 根据权利要求7所述的阵列基板，其中，所述第一移位寄存器、所述第二移位寄存器、所述第三移位寄存器以及所述第四移位寄存器中的每个包括：
    输入电路，与所述输入端和上拉节点分别连接；
    复位电路，与所述上拉节点、复位端及第一电源端分别连接；
    输出电路，与所述上拉节点、时钟信号端及所述输出端分别连接；
    输出端下拉电路，与所述输出端、所述下拉节点及所述第一电源端分别连接；
    下拉节点控制电路，与所述下拉节点、第二电源端及所述第一电源端分别连接；以及
    存储电容，与所述上拉节点及所述输出端分别连接。
  12. 根据权利要求11所述的阵列基板，其中，
    所述输入电路包括第一晶体管，所述第一晶体管的第一极与所述输入端连接，所述第一晶体管的栅极与所述输入端连接，所述第一晶体管的第二极与所述上拉节点连接；
    所述复位电路包括第二晶体管，所述第二晶体管的第一极与所述上拉节点连接，所述第二晶体管的栅极与所述复位端连接，所述第二晶体管的第二极与所述第一电源端连接；
    所述输出电路包括第三晶体管，所述第三晶体管的第一极与所述时钟信号端连接，所述第三晶体管的栅极与所述上拉节点连接，所述第三晶体管的第二极与所述输出端连接；
    所述输出端下拉电路包括第四晶体管，所述第四晶体管的第一极与所述输出端连接，所述第四晶体管的栅极与所述下拉节点连接，所述第四晶体管的第二极与所述第一电源端连接；
    所述下拉节点控制电路包括第五晶体管和第六晶体管，所述第五晶体管的第一极与所述第二电源端连接，所述第五晶体管的栅极与所述第二电源端连接，所述第五晶体管的第二极与所述下拉节点连接，所述第六晶体管的第一极与所述下拉节点连接，所述第六晶体管的栅极与所述上拉节点连接，所述第六晶体管的第二极与所述第一电源端连接；
    所述存储电容的第一端与所述上拉节点连接，所述存储电容的第二端与所述输出端连接。
  13. 一种显示面板，包括如权利要求1-12任一项所述的阵列基板。
  14. 一种显示设备，包括如权利要求13任一项所述的显示面板。
  15. 一种驱动如权利要求1-12任一项所述的阵列基板的方法，包括：
    通过所述第一栅极驱动电路向所述第一像素单元中的第一部分提供第一栅极驱动信号；以及
    通过所述第二栅极驱动电路向所述第一像素单元中的第二部分提供第二栅极驱动信号，其中，
    当所述第一区域处于高分辨率模式时，所述第一栅极驱动信号的时序与所述第二栅极驱动信号的时序不同；
    当所述第一区域处于低分辨率模式时，所述第一栅极驱动信号的时序与所述第二栅极驱动信号的时序相同。
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