WO2022160160A1 - 栅极驱动电路及其驱动方法和显示面板 - Google Patents

栅极驱动电路及其驱动方法和显示面板 Download PDF

Info

Publication number
WO2022160160A1
WO2022160160A1 PCT/CN2021/074092 CN2021074092W WO2022160160A1 WO 2022160160 A1 WO2022160160 A1 WO 2022160160A1 CN 2021074092 W CN2021074092 W CN 2021074092W WO 2022160160 A1 WO2022160160 A1 WO 2022160160A1
Authority
WO
WIPO (PCT)
Prior art keywords
shift register
transistor
clock
register unit
terminal
Prior art date
Application number
PCT/CN2021/074092
Other languages
English (en)
French (fr)
Inventor
刘伟星
秦纬
彭宽军
王铁石
张春芳
张慧
李昌峰
张舜航
侯凯
王洪润
刘立伟
林允植
滕万鹏
李小龙
郭凯
徐智强
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180000088.5A priority Critical patent/CN115398518A/zh
Priority to US17/609,504 priority patent/US11837133B2/en
Priority to PCT/CN2021/074092 priority patent/WO2022160160A1/zh
Publication of WO2022160160A1 publication Critical patent/WO2022160160A1/zh
Priority to US18/491,531 priority patent/US20240105091A1/en

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a gate driving circuit, a driving method of the gate driving circuit, and a display panel.
  • a gate driving circuit is usually used to drive a plurality of sub-pixels for display.
  • a gate driving circuit generates a gate driving signal, and the gate driving signal is supplied to a plurality of sub-pixels, so that the sub-pixels are turned on.
  • a data signal is applied to the turned-on subpixels to drive the subpixels to emit light.
  • a gate driving circuit generally includes a plurality of shift registers connected in cascade to generate a plurality of output signals shifted in sequence as gate driving signals.
  • the conventional technology cannot flexibly control the display resolution of different areas on the display panel.
  • a gate driving circuit comprising a plurality of driving units connected in cascade, each driving unit comprising:
  • a mode control circuit connected to the N shift register units, the mode control circuit being configured to receive a control signal for the drive unit, and to pair with one of a plurality of resolution modes under the control of the control signal
  • the N shift register units are connected.
  • the plurality of resolution modes include a first resolution mode, a second resolution mode, and a third resolution mode
  • the mode control circuit is configured to:
  • the N shift register units are divided into M groups, the M groups are connected in cascade, and the shift register units in each group are connected in parallel;
  • the N shift register units are connected in parallel.
  • the N shift register units include a first shift register unit, a second shift register unit, a third shift register unit and a fourth shift register unit, each shift register unit
  • the bit register unit has a cascaded input and a first cascaded output, and the mode control circuit is configured to:
  • the first cascaded output of the nth shift register unit is connected to the cascaded input of the n+1th shift register unit, and the stage of the nth shift register unit is connected
  • the cascade input terminal is disconnected from the cascade input terminal of the n+1th shift register unit, wherein 1 ⁇ n ⁇ N-1;
  • the first cascaded output terminal of the first shift register unit is disconnected from the cascaded input terminal of the second shift register unit, and the first cascaded The output terminal is connected with the cascaded input terminal of the third shift register unit, the first cascaded output terminal of the third shift register unit is disconnected from the cascaded input terminal of the fourth shift register unit, and the first cascaded input terminal of the shift register unit is disconnected.
  • the cascade input of the bit register unit is connected with the cascade input of the second shift register unit, and the cascade input of the third shift register unit is connected with the cascade input of the fourth shift register unit;
  • the first cascaded output of the nth shift register unit is disconnected from the cascaded input of the n+1th shift register unit, and the nth shift register unit is The cascaded input terminal of is connected to the cascaded input terminal of the n+1th shift register unit.
  • the first shift register unit, the second shift register unit, the third shift register unit and the fourth shift register unit each further have a reset terminal and a second cascaded output terminal
  • the mode control circuit further is configured as:
  • the reset terminal of the nth shift register unit is connected to the second cascade output terminal of the n+1th shift register unit, and the reset terminal of the nth shift register unit is connected to The reset terminal of the n+1th shift register unit is disconnected,
  • the reset terminal of the first shift register unit is disconnected from the second cascade output terminal of the second shift register unit, and the reset terminal of the second shift register unit is connected to the third shift register unit.
  • the second cascade output terminal of the bit register unit is connected, the reset terminal of the third shift register unit is disconnected from the second cascade output terminal of the fourth shift register unit, and the reset terminal of the first shift register unit is disconnected. connect with the reset terminal of the second shift register unit, disconnect the reset terminal of the second shift register unit from the reset terminal of the third shift register unit, and connect the reset terminal of the third shift register unit to the fourth shift register unit the reset terminal connection of the shift register cell;
  • the reset terminal of the nth shift register unit is disconnected from the second cascade output terminal of the n+1th shift register unit, and the reset terminal of the nth shift register unit is reset The terminal is connected to the reset terminal of the n+1th shift register unit.
  • control signal includes a first control signal, a second control signal, a third control signal and a fourth control signal
  • mode control circuit includes:
  • the first transistor the gate of the first transistor is connected to receive the first control signal, the first pole of the first transistor is connected to the first cascade output terminal of the first shift register unit, and the second pole of the first transistor is connected to the second Cascade input of the shift register unit;
  • the second transistor the gate of the second transistor is connected to receive the second control signal, the first pole of the second transistor is connected to the cascade input terminal of the first shift register unit, and the second pole of the second transistor is connected to the second shift register unit Cascade input of register unit;
  • the third transistor the gate of the third transistor is connected to receive the third control signal, the first pole of the third transistor is connected to the first cascade output terminal of the second shift register unit, and the second pole of the third transistor is connected to the third Cascade input of the shift register unit;
  • the fourth transistor the gate of the fourth transistor is connected to receive the fourth control signal, the first pole of the fourth transistor is connected to the cascade input terminal of the first shift register unit, and the second pole of the fourth transistor is connected to the third shift register Cascade input of register unit;
  • the fifth transistor the gate of the fifth transistor is connected to the first control signal, the first pole of the fifth transistor is connected to the first cascade output terminal of the third shift register unit, and the second pole of the fifth transistor is connected to the fourth shift register unit. cascaded inputs of bit register cells;
  • the sixth transistor the gate of the sixth transistor is connected to receive the second control signal, the first pole of the sixth transistor is connected to the cascade input terminal of the third shift register unit, and the second pole of the sixth transistor is connected to the fourth transistor. Cascade input.
  • control signal further includes a fifth control signal
  • mode control circuit further includes:
  • the seventh transistor the gate of the seventh transistor is connected to receive the first control signal, the first pole of the seventh transistor is connected to the reset terminal of the first shift register unit, and the second pole of the seventh transistor is connected to the second shift register unit
  • the eighth transistor the gate of the eighth transistor is connected to receive the fifth control signal, the first pole of the eighth transistor is connected to the reset terminal of the first shift register unit, and the second pole of the eighth transistor is connected to the second shift register unit the reset terminal;
  • the ninth transistor the gate of the ninth transistor is connected to receive the third control signal, the first pole of the ninth transistor is connected to the reset terminal of the second shift register unit, and the second pole of the ninth transistor is connected to the third shift register unit
  • the tenth transistor the gate of the tenth transistor is connected to receive the fourth control signal, the first pole of the tenth transistor is connected to the reset terminal of the second shift register unit, and the second pole of the tenth transistor is connected to the third shift register unit the reset terminal;
  • the eleventh transistor the gate of the eleventh transistor is connected to receive the first control signal, the first pole of the eleventh transistor is connected to the reset terminal of the third shift register unit, and the second pole of the eleventh transistor is connected to the fourth a second cascaded output of the shift register unit;
  • the twelfth transistor the gate of the twelfth transistor is connected to receive the second control signal, the first pole of the twelfth transistor is connected to the reset terminal of the third shift register unit, and the second pole of the twelfth transistor is connected to the fourth Reset terminal of the shift register unit.
  • the first cascaded output terminal of the Nth shift register unit in the ith stage driving unit is connected to the cascaded input terminal of the first shift register unit in the i+1th stage driving unit.
  • the reset terminal of the Nth shift register unit in the i-th level driving unit is connected to the second cascade output terminal of the first shift register unit in the i+1-th level driving unit.
  • the plurality of driving units are divided into groups, and each group of driving units is connected to a group of control signal lines to receive control signals for the group of driving units.
  • each shift register unit includes a first shift register, a second shift register, and a third shift register, wherein,
  • the input end of the first shift register is used as the cascaded input end of the shift register unit, and the output end of the first shift register is used as the second cascaded output end of the shift register unit;
  • the input of the second shift register is connected to the output of the first shift register
  • the input end of the third shift register is connected to the output end of the second shift register, and the output end of the third shift register serves as the first cascaded output end of the shift register unit.
  • each of the first shift register, second shift register, and third shift register includes:
  • an input subcircuit connected to the input of the shift register and the pull-up node, and configured to provide a signal from the input to the pull-up node;
  • An output subcircuit is connected to the pull-up node, the clock signal terminal and the output terminal of the shift register, and is configured to provide a signal of the clock signal terminal to the clock signal terminal under the control of the potential of the pull-up node output;
  • control subcircuit connected to the pull-up node, the output terminal and the pull-down node of the shift register, and configured to control the potential of the pull-down node based on the potential of the pull-up node, and to control the potential of the pull-down node when the pull-down node
  • the potential control of the node pulls down the potential of the output terminal.
  • each of the first shift register, the second shift register, and the third shift register further includes:
  • a reset subcircuit connected to the pull-up node and the reset terminal of the shift register, and configured to reset the pull-up node according to a reset signal of the reset terminal, wherein the reset of the third shift register in the shift register unit
  • the terminal is used as the reset terminal of the shift register unit.
  • a method for driving a gate driving circuit according to the first aspect of the present disclosure comprising:
  • the mode control circuit of each drive unit in the plurality of drive units receives a control signal for the drive unit, and connects the N shift register units in one of a plurality of resolution modes under the control of the control signal ,
  • the connected N shift register units in each drive unit generate output signals.
  • the plurality of resolution modes include a first resolution mode, a second resolution mode, and a third resolution mode, wherein,
  • the mode control circuit cascades N shift register units, and the N shift register units generate sequentially shifted output signals;
  • the mode control circuit divides the N shift register units into M groups, connects the M groups in cascade, and connects the shift register units in each group in parallel, each The shift register cells in the group generate output signals in parallel, and the set of output signals generated by the m+1 group of shift register cells is shifted relative to the set of output signals generated by the mth group of shift register cells, where m is an integer and 1 ⁇ m ⁇ M-1;
  • the mode control circuit connects the N shift register units in parallel, and the N shift register units generate output signals in parallel.
  • the N shift register units include a first shift register unit, a second shift register unit, a third shift register unit and a fourth shift register unit, wherein,
  • the mode control circuit connects the first cascaded output terminal of the nth shift register unit with the cascaded input terminal of the n+1th shift register unit, and The cascade input terminal of the bit register unit is disconnected from the cascade input terminal of the n+1th shift register, wherein 1 ⁇ n ⁇ N-1;
  • the mode control circuit disconnects the first cascaded output of the first shift register unit from the cascaded input of the second shift register unit, and the second shift register unit
  • the cascaded input terminal of the first shift register unit is connected to the cascaded input terminal of the first shift register unit;
  • the first cascaded output terminal of the second shift register unit is connected to the cascaded input terminal of the third shift register unit, and the third
  • the cascaded input of the shift register unit is disconnected from the cascaded input of the second shift register unit; and the first cascaded output of the third shift register unit is connected with the cascaded input of the fourth shift register unit disconnecting the input to connect the cascaded input of the third shift register unit with the cascaded input of the fourth shift register unit;
  • the mode control circuit disconnects the first cascaded output of the nth shift register unit from the cascaded input of the n+1th shift register unit, and switches the nth shift register unit
  • the cascade input terminal of the bit register unit is connected to the cascade input terminal of the n+1th shift register unit.
  • the method further includes:
  • the mode control circuit connects the reset terminal of the nth shift register unit with the second cascaded output terminal of the n+1th shift register, and resets the reset terminal of the nth shift register unit The terminal is disconnected from the reset terminal of the n+1th shift register unit,
  • the mode control circuit disconnects the reset terminal of the first shift register unit from the second cascaded output terminal of the second shift register unit, and connects the reset terminal of the second shift register unit with the second cascade output terminal of the second shift register unit.
  • the second cascade output terminal of the third shift register unit is connected, and the mode control circuit disconnects the reset terminal of the third shift register unit from the second cascade output terminal of the fourth shift register unit, and the first shift register unit is connected to the second cascade output terminal.
  • the reset terminal of the bit register unit is connected to the reset terminal of the second shift register unit, and the reset terminal of the third shift register unit is connected to the reset terminal of the fourth shift register unit;
  • the mode control circuit disconnects the reset terminal of the nth shift register unit from the second cascade output terminal of the n+1th shift register unit, and connects the nth shift register unit The reset terminal of the unit is connected to the reset terminal of the n+1th shift register unit.
  • the mode control circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, wherein,
  • the first control signal and the third control signal are at the first level
  • the second control signal and the fourth control signal are at the second level
  • the first transistor, the third transistor and the fifth transistor conduct on, and the second transistor, the fourth transistor and the sixth transistor are off;
  • the second control signal and the third control signal are at the first level
  • the first control signal and the fourth control signal are at the second level
  • the second transistor, the third transistor and the sixth transistor conduct on, the first transistor, the fourth transistor and the fifth transistor are off
  • the second control signal and the fourth control signal are at the first level
  • the first control signal and the third control signal are at the second level
  • the second transistor, the fourth transistor and the sixth transistor conduct On, the first transistor, the third transistor and the fifth transistor are off.
  • the mode control circuit further includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor, wherein,
  • the fifth control signal is at the second level, the seventh transistor, the ninth transistor and the eleventh transistor are turned on, and the eighth transistor, the tenth transistor and the twelfth transistor are turned off;
  • the fifth control signal is at the first level
  • the eighth transistor, the ninth transistor and the twelfth transistor are turned on, and the seventh transistor, the tenth transistor and the eleventh transistor are turned off;
  • the fifth control signal is at the second level, the tenth transistor and the twelfth transistor are turned on, and the seventh transistor, the eighth transistor, the ninth transistor and the eleventh transistor are turned off.
  • a gate driving circuit comprising:
  • each start-up signal line is connected to the first-stage shift register in the corresponding driving unit;
  • K clock signal lines connected to the plurality of shift registers in each drive unit, where K is an integer greater than 1;
  • a mode control circuit connected to the K clock signal lines, the mode control circuit is configured to receive K initial clock signals and control signals, and under the control of the control signals, use a first resolution mode, a second resolution mode One of the rate mode and the third resolution mode is used to generate K clock signals based on the K initial clock signals, and the generated K clock signals are respectively provided to the K clock signal lines.
  • the mode control circuit is configured to:
  • K second clock signals divided into 2M groups are generated based on the K initial clock signals, the plurality of second clock signals in each group are synchronized, and the m+1th group of second clock signals is relatively is shifted by the mth group of second clock signals;
  • K third clock signals divided into M groups are generated based on the K initial clock signals, the plurality of third clock signals in each group are synchronized, and the m'+1th group of third clock signals Shifted relative to the m'th group of third clock signals, where M is an integer greater than 1, m and m' are both integers, 1 ⁇ m ⁇ 2M-1, and 1 ⁇ m' ⁇ M-1.
  • control signal includes a first control signal, a second control signal, a third control signal and a fourth control signal
  • mode control circuit includes:
  • the first clock input terminal to the eighth clock input terminal are respectively connected to receive 8 initial clock signals
  • the first clock output terminal to the eighth clock output terminal are connected with the eight clock signal lines in one-to-one correspondence;
  • the first mode control subcircuit is configured to connect the second clock input end to the second clock output end, connect the fourth clock input end to the fourth clock output end, and connect the seventh clock input end to the fourth clock output end under the control of the first control signal.
  • the clock input terminal is connected with the seventh clock output terminal, and the eighth clock input terminal is connected with the eighth clock output terminal;
  • the second mode control subcircuit is configured to connect the third clock input end with the third clock output end and connect the sixth clock input end with the sixth clock output end under the control of the second control signal;
  • the third mode control subcircuit is configured to connect the first clock output end to the second clock output end, connect the third clock output end to the fourth clock output end, and connect the fifth clock output end under the control of the third control signal
  • the output terminal is connected with the sixth clock output terminal, and the seventh clock output terminal is connected with the eighth clock output terminal;
  • the fourth mode control subcircuit is configured to connect the second clock output terminal with the third clock output terminal and connect the sixth clock output terminal with the seventh clock output terminal under the control of the fourth control signal.
  • the first mode control subcircuit includes:
  • the gate of the first transistor is connected to receive the first control signal, the first pole of the first transistor is connected to the second clock input terminal, and the second pole of the first transistor is connected to the second clock output terminal;
  • the gate of the second transistor is connected to receive the first control signal, the first pole of the second transistor is connected to the fourth clock input terminal, and the second pole of the second transistor is connected to the fourth clock output terminal;
  • the gate of the third transistor is connected to receive the first control signal, the first pole of the third transistor is connected to the seventh clock input terminal, and the second pole of the third transistor is connected to the seventh clock output terminal;
  • the fourth transistor the gate of the fourth transistor is connected to receive the first control signal, the first pole of the fourth transistor is connected to the eighth clock input terminal, and the second pole of the fourth transistor is connected to the eighth clock output terminal.
  • the second mode control subcircuit includes:
  • the gate of the fifth transistor is connected to receive the second control signal, the first pole of the fifth transistor is connected to the third clock input terminal, and the second pole is connected to the third clock output terminal;
  • the sixth transistor the gate of the sixth transistor is connected to receive the second control signal, the first pole of the sixth transistor is connected to the sixth clock input terminal, and the second pole of the sixth transistor is connected to the sixth clock output terminal.
  • the third mode control subcircuit includes:
  • a seventh transistor the gate of the seventh transistor is connected to receive the third control signal, the first pole of the seventh transistor is connected to the first clock output terminal, and the second pole is connected to the second clock output terminal;
  • an eighth transistor the gate of the eighth transistor is connected to receive the third control signal, the first pole of the eighth transistor is connected to the third clock output terminal, and the second pole is connected to the fourth clock output terminal;
  • the gate of the ninth transistor is connected to receive the third control signal, the first pole of the ninth transistor is connected to the fifth clock output terminal, and the second pole is connected to the sixth clock output terminal;
  • the tenth transistor the gate of the tenth transistor is connected to receive the third control signal, the first pole of the tenth transistor is connected to the seventh clock output terminal, and the second pole is connected to the eighth clock output terminal.
  • the fourth mode control subcircuit includes:
  • the gate of the eleventh transistor is connected to receive the fourth control signal, the first pole of the eleventh transistor is connected to the second clock output terminal, and the second pole is connected to the third clock output terminal;
  • the twelfth transistor the gate of the twelfth transistor is connected to receive the fourth control signal, the first pole of the twelfth transistor is connected to the sixth clock output terminal, and the second pole is connected to the seventh clock output terminal.
  • the output terminal of the nth stage shift register is connected to the input terminal of the n+1th stage shift register, and the output terminal of the n+1th stage shift register is connected to the nth stage shift register the reset side of the register, where n is an integer greater than or equal to 1;
  • the plurality of shift registers in each driving unit are divided into at least one group, each group includes K shift registers connected in cascade, and the clock signal terminals of the K shift registers are connected to the K clock signal lines. connected one by one.
  • a method for driving a gate driving circuit according to the third aspect of the present disclosure comprising:
  • the mode control circuit generates K clock signals based on the K initial clock signals in one of multiple resolution modes under the control of the control signal, and provides the generated K clock signals to the K clock signal lines respectively ;as well as
  • the plurality of resolution modes include a first resolution mode, a second resolution mode, and a third resolution mode, wherein,
  • the mode control circuit In the first resolution mode, the mode control circuit generates K first clock signals shifted sequentially based on the K initial clock signals and provides them to the K clock signal lines respectively;
  • the mode control circuit In the second resolution mode, the mode control circuit generates K second clock signals based on the K initial clock signals and provides them to the K clock signal lines respectively.
  • the K second clock signals are divided into 2M groups, each group being divided into 2M groups.
  • a plurality of second clock signals in are synchronized, and the m+1th group of second clock signals is shifted with respect to the mth group of second clock signals;
  • the mode control circuit In the third resolution mode, the mode control circuit generates K third clock signals based on the K initial clock signals and provides them to the K clock signal lines respectively, the K third clock signals are divided into M groups, each group A plurality of third clock signals in are synchronized, and the m'+1th group of third clock signals is shifted relative to the m'th group of third clock signals, where M is an integer greater than 1, and m and m' are both integers, 1 ⁇ m ⁇ 2M-1, and 1 ⁇ m' ⁇ M-1.
  • the first mode control subcircuit connects the second clock input terminal to the second clock output terminal, connects the fourth clock input terminal to the fourth clock output terminal, and connects the seventh clock input terminal to the fourth clock output terminal
  • the seventh clock output terminal is connected, and the eighth clock input terminal is connected with the eighth clock output terminal
  • the second mode control sub-circuit connects the third clock input terminal with the third clock output terminal, and the sixth clock input terminal is connected with the third clock output terminal.
  • the second mode control subcircuit connects the third clock input terminal to the third clock output terminal, and the sixth clock input terminal to the sixth clock output terminal; the third mode control subcircuit connects the third clock input terminal to the sixth clock output terminal;
  • the first clock output is connected to the second clock output, the third clock output is connected to the fourth clock output, the fifth clock output is connected to the sixth clock output, and the seventh clock output is connected to the fourth clock output.
  • the third mode control subcircuit connects the first clock output end to the second clock output end, connects the third clock output end to the fourth clock output end, and connects the fifth clock output end to the third clock output end Six clock output terminals are connected, and the seventh clock output terminal is connected with the eighth clock output terminal; the fourth mode control sub-circuit connects the second clock output terminal with the third clock output terminal, and the sixth clock output terminal is connected with the third clock output terminal. Seven clock output connections.
  • the first control signal and the second control signal are at the first level
  • the third control signal and the fourth control signal are at the second level
  • the first transistor, the second transistor, the third The transistor, the fourth transistor, the fifth transistor and the sixth transistor are turned on
  • the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor and the twelfth transistor are turned off;
  • the first control signal and the fourth control signal are at the second level
  • the second control signal and the third control signal are at the first level
  • the fourth transistor, the eleventh transistor, and the twelfth transistor are turned off
  • the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor are turned on;
  • the first control signal and the second control signal are at the second level
  • the third control signal and the fourth control signal are at the first level
  • the fourth, fifth, and sixth transistors are turned off
  • the seventh, eighth, ninth, tenth, eleventh, and twelfth transistors are turned on.
  • the K initial clock signals are periodic signals with a duty cycle of 50%, wherein the k+1 th initial clock signal is shifted by a unit scan time relative to the k th initial clock signal, and the effective level of each initial clock signal The duration is 4 times the unit scan time.
  • the K initial clock signals are periodic signals with a duty ratio of 12.5%, wherein the k+1 th initial clock signal is shifted by a unit scan time relative to the k th initial clock signal, and the active level of each initial clock signal Duration is the unit scan time.
  • a gate driving circuit comprising:
  • each drive unit including a plurality of shift register units connected in cascade, in the plurality of shift register units, the cascaded output terminal of the nth shift register unit is connected to the n+dth the cascade input terminal of the stage shift register unit;
  • a plurality of start-up signal lines are connected with the plurality of driving units in one-to-one correspondence, wherein each start-up signal line is connected to the cascade input end of the first d-stage shift register unit in the corresponding driving unit, wherein n and d are both is an integer greater than or equal to 1;
  • each shift register unit includes a first shift register, a second shift register, and a third shift register, wherein,
  • the input end of the first shift register is used as the cascade input end of the shift register unit, the output end of the first shift register is connected to the input end of the second shift register, and the output end of the second shift register is connected to the third shift register.
  • the input of the shift register and the output of the third shift register as the cascaded output of the shift register unit;
  • the clock signal terminal of the first shift register, the clock signal terminal of the second shift register and the clock signal terminal of the third shift register are used as the clock signal terminal of the shift register unit.
  • each driving unit is divided into at least one group, and each group includes K shift register units connected in cascade, among the K shift register units:
  • the clock signal terminals of the first shift register and the third shift register of the kth shift register unit are connected to the kth clock signal line, wherein k is an integer, and 1 ⁇ k ⁇ K;
  • the clock signal terminal of the second shift register of the kth shift register unit is connected to the k+dth clock signal line in the case of k ⁇ 2/K, and is connected to the k+dth clock signal line in the case of 2/K ⁇ k ⁇ K
  • each of the first shift register, second shift register, and third shift register includes:
  • an input subcircuit connected to the input of the shift register and the pull-up node, and configured to provide a signal from the input to the pull-up node;
  • An output subcircuit is connected to the pull-up node, the clock signal terminal and the output terminal of the shift register, and is configured to provide a signal of the clock signal terminal to the clock signal terminal under the control of the potential of the pull-up node output;
  • control subcircuit connected to the pull-up node, the output terminal and the pull-down node of the shift register, and configured to control the potential of the pull-down node based on the potential of the pull-up node, and to control the potential of the pull-down node when the pull-down node
  • the potential control of the node pulls down the potential of the output terminal.
  • a method for driving a gate driving circuit according to the fifth aspect of the present disclosure comprising:
  • the applied activation signal enables the driving unit connected to the at least one activation signal line to activate, and the plurality of shift registers in the activated driving unit generate output signals according to the clock signals on the K clock signal lines.
  • the K first clock signals shifted in sequence are respectively applied to the K clock signal lines, and the first clock signal is applied to at least one of the plurality of enabling signal lines.
  • a start signal For example, in the first resolution mode, the K first clock signals shifted in sequence are respectively applied to the K clock signal lines, and the first clock signal is applied to at least one of the plurality of enabling signal lines.
  • K second clock signals are respectively applied to the K clock signal lines, and a second start signal is applied to at least one start signal line of the plurality of start signal lines, wherein the The K second clock signals are divided into 2M groups, the plurality of second clock signals in each group are synchronized, and the m+1th group of second clock signals is shifted relative to the mth group of second clock signals;
  • K third clock signals are respectively applied to the K clock signal lines, and a third activation signal is applied to at least one of the plurality of activation signal lines, wherein the The K third clock signals are divided into M groups, the plurality of third clock signals in each group are synchronized, and the m'+1th group of third clock signals is shifted relative to the m'th group of third clock signals, where M is For an integer greater than 1, m and m' are both integers, 1 ⁇ m ⁇ 2M-1, and 1 ⁇ m' ⁇ M-1.
  • the first clock signal, the second clock signal and the third clock signal are all periodic signals with a duty cycle of 50%, wherein,
  • the active level duration in the signal period of the first clock signal is 4H, wherein the k+1 th first clock signal is shifted by H relative to the k th first clock signal, wherein H represents the unit scan time;
  • the active level duration in the signal period of the second clock signal is 2H, wherein m+1 groups of second clock signals are shifted by H relative to the mth group of second clock signals;
  • the active level duration within the signal period of the third clock signal is H, wherein the m'+1 group of third clock signals is shifted by H relative to the m'th group of third clock signals.
  • the active level duration of the first enable signal is 4H
  • the active level duration of the second enable signal is 2H
  • the active level duration of the third enable signal is H.
  • the plurality of driving units include a first driving unit, a second driving unit, and a third driving unit
  • the plurality of activation signal lines include connection with the first driving unit, the second driving unit, and the third driving unit, respectively.
  • the first start signal line, the second start signal line and the third start signal line are connected, wherein,
  • K clock signals are applied to the K clock signal lines in the first resolution mode and the first activation signal is applied to the second activation signal lines, and the second driving unit responds to the applied first activation signal according to the The applied K clock signals produce an output signal;
  • K clock signals are applied to the K clock signal lines in the second resolution mode or the third resolution mode, and the second activation signal or the third activation signal is applied to the first activation signal line, and the first driving unit generating an output signal according to the applied K clock signals in response to the applied second enable signal or the third enable signal;
  • K clock signals are applied to the K clock signal lines in the first resolution mode and the first activation signal is applied to the second activation signal lines, and the second driving unit responds to the applied first activation signal according to the The applied K clock signals produce an output signal;
  • the K clock signals are applied to the K clock signal lines in the second resolution mode or the third resolution mode and the third activation signal is applied to the third activation signal line, and the third driving unit responds to the applied A third enable signal to generate an output signal based on the K clock signals applied.
  • a display panel including the above gate driving circuit.
  • FIG. 1 shows a schematic diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 2A shows a circuit diagram of a shift register according to an embodiment of the present disclosure.
  • FIG. 2B shows a circuit diagram of a shift register according to another embodiment of the present disclosure.
  • FIG. 3 shows a block diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 4 shows an example block diagram of the gate driving circuit of FIG. 3 .
  • FIG. 5A shows an equivalent schematic diagram of the gate driving circuit of FIG. 4 in the first resolution mode.
  • FIG. 5B shows a signal timing diagram of the gate driving circuit of FIG. 4 in the first resolution mode.
  • FIG. 6A shows an equivalent schematic diagram of the gate driving circuit of FIG. 4 in the second resolution mode.
  • FIG. 6B shows a signal timing diagram of the gate driving circuit of FIG. 4 in the second resolution mode.
  • FIG. 7A shows an equivalent schematic diagram of the gate driving circuit of FIG. 4 in a third resolution mode.
  • FIG. 7B shows a signal timing diagram of the gate driving circuit of FIG. 4 in the third resolution mode.
  • FIG. 8A shows an equivalent schematic diagram of the gate driving circuit of FIG. 4 in the second resolution and the third resolution mode.
  • FIG. 8B shows a signal timing diagram of the gate driving circuit of FIG. 4 in the second resolution and the third resolution mode.
  • FIG. 9 shows another example structure diagram of the gate driving circuit of FIG. 3 .
  • FIG. 10 shows a structural diagram of a gate driving circuit according to another embodiment of the present disclosure.
  • FIG. 11 shows an example circuit diagram of a mode control circuit in the gate drive circuit of FIG. 10 .
  • FIG. 12 shows a timing diagram of the initial clock signal received by the gate drive circuit of FIG. 10 .
  • FIG. 13 shows a signal timing diagram of the gate driving circuit of FIG. 10 in the first resolution mode.
  • FIG. 14 shows a signal timing diagram of the gate driving circuit of FIG. 10 in the second resolution mode.
  • FIG. 15 shows a signal timing diagram of the gate driving circuit of FIG. 10 in a third resolution mode.
  • FIG. 16 shows an example of a signal timing diagram of the gate driving circuit of FIG. 10 in the first resolution, second resolution and third resolution modes.
  • FIG. 17 shows another example of a signal timing diagram of the gate driving circuit of FIG. 10 in the first resolution, second resolution and third resolution modes.
  • FIG. 18 shows a block diagram of a gate driving circuit according to yet another embodiment of the present disclosure.
  • FIG. 19 shows an example block diagram of the gate drive circuit of FIG. 18 .
  • FIG. 20 shows a signal timing diagram of the gate driving circuit of FIG. 19 in the first resolution mode.
  • FIG. 21 shows a signal timing diagram of the gate driving circuit of FIG. 19 in the second resolution mode.
  • FIG. 22 shows a signal timing diagram of the gate driving circuit of FIG. 19 in the third resolution mode.
  • FIG. 23 shows a timing diagram of a start-up signal of the gate drive circuit of FIG. 19 .
  • connection may mean that two components are directly connected, or may mean that two components are connected via one or more other components.
  • the two components may be connected or coupled by wired or wireless means.
  • first level and “second level” are only used to distinguish the amplitudes of the two levels from being different.
  • first level is a high level
  • second level is a low level as an example for description.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors, field effect transistors, or other devices with the same characteristics.
  • the thin film transistor used in the embodiments of the present disclosure may be an oxide semiconductor transistor or a low temperature polysilicon (LTPS, Low Temperature Poly-silicon) thin film transistor. Since the source electrode and the drain electrode of the thin film transistor used here are symmetrical, the source electrode and the drain electrode can be interchanged. In the embodiments of the present disclosure, one of the source electrode and the drain electrode is referred to as the first electrode, and the other of the source electrode and the drain electrode is referred to as the second electrode. In the following examples, an N-type thin film transistor is used as an example for description. Those skilled in the art can understand that the embodiments of the present disclosure can obviously be applied to the case of P-type thin film transistors.
  • FIG. 1 shows a schematic diagram of a display panel according to an embodiment of the present disclosure.
  • the display panel includes pixel units PXL arranged in an array, and each pixel unit PXL includes a plurality of sub-pixels, which are red sub-pixels R, green sub-pixels G, and blue sub-pixels B in this embodiment.
  • each row of pixel units PXL includes three rows of sub-pixels, wherein the red sub-pixels R are arranged in the first row, the green sub-pixels G are arranged in the second row, and the blue sub-pixels are arranged in the third row.
  • the display panel further includes a gate driving circuit 100.
  • the gate driving circuit 100 is connected to the pixel units of the plurality of rows through a plurality of gate lines G1, G2, . . . GX.
  • the pixel R is connected to the green sub-pixel G of the pixel unit PXL in the first row through the gate line G2, connected to the blue sub-pixel B of the pixel unit PXL of the first row through the gate line G3, and so on.
  • the gate driving circuit 100 of the embodiment of the present disclosure may include a plurality of shift registers, and the shift registers of the embodiment of the present disclosure will be exemplified below with reference to FIG. 2A and FIG. 2B .
  • FIG. 2A shows a circuit diagram of a shift register according to an embodiment of the present disclosure.
  • the shift register may include an input sub-circuit 10 , an output sub-circuit 20 and a control sub-circuit 30 .
  • the input sub-circuit 10 connects the input terminal IN of the shift register and the pull-up node PU, and can provide the signal of the input terminal IN to the pull-up node PU.
  • the input sub-circuit 10 may include a transistor M1, the gate and the first electrode of the transistor M1 are connected to the input terminal IN, and the second electrode is connected to the pull-up node PU.
  • the output sub-circuit 20 is connected to the pull-up node PU, the clock signal terminal CK of the shift register and the output terminal OUT of the shift register, and can provide the signal of the clock signal terminal CK to the output terminal OUT under the control of the potential of the pull-up node PU .
  • the output subcircuit 20 may include a transistor M7 and a capacitor C1.
  • the gate of the transistor M7 is connected to the pull-up node PU, the first pole is connected to the clock signal terminal CK, and the second pole is connected to the output terminal OUT.
  • One end of the capacitor C1 is connected to the pull-up node PU, and the other end is connected to the output end OUT.
  • the control sub-circuit 30 is connected to the pull-up node PU, the output terminal OUT and the pull-down node PD of the shift register, and can control the potential of the pull-down node PD based on the potential of the pull-up node, and pull down the potential of the output terminal OUT under the control of the potential of the pull-down node PD. potential.
  • the control subcircuit 30 may include transistors M2, M4 and M6 and a capacitor C2. The gate and the first electrode of the transistor M2 are connected to the control terminal CKB, and the second electrode is connected to the pull-down node PD.
  • the gate of the transistor M4 is connected to the pull-up node PU, the first electrode is connected to the reference signal terminal VGL, and the second electrode is connected to the pull-down node PD.
  • the gate of the transistor M6 is connected to the pull-down node PD, the first electrode is connected to the reference signal terminal VGL, and the second electrode is connected to the output terminal OUT.
  • One end of the capacitor C2 is connected to the gate of the transistor M6, and the other end is connected to the first electrode of the transistor M6.
  • control sub-circuit 30 may further include a transistor M3, the gate of the transistor M3 is connected to the pull-down node PD, the first electrode is connected to the reference signal terminal VGL, and the second electrode is connected to the pull-up node PU.
  • control sub-circuit 30 may further include a transistor M5, the gate of the transistor M5 is connected to the output terminal OUT, the first electrode is connected to the reference signal terminal VGL, and the second electrode is connected to the pull-down node PD.
  • the transistor M1 When the input signal of the input terminal IN is at a high level, the transistor M1 is turned on, thereby providing the high level of the input terminal IN to the pull-up node PU, and the transistor M7 is turned on; when the input signal of the input terminal IN becomes a low level, Capacitor C1 keeps the pull-up node PU high.
  • the pull-up node PU is at a high level, the high level of the clock signal at the clock signal terminal CK arrives, and the turned-on transistor M7 provides the high level of the clock signal terminal CK to the output terminal OUT, thereby generating a high level of output signal.
  • the high level of the output terminal OUT turns on the transistor M5 and pulls down the pull-down node PD to a low level.
  • the clock signal of the clock signal terminal CK is at a low level
  • the control terminal CKB is at a high level
  • the turned-on transistor M7 provides the low level of the clock signal terminal CK to the output terminal OUT, thereby generating a low-level output signal , and then turn off the transistor M5; and the high level of the control terminal CKB turns on the transistor M2, so that the pull-down node PD becomes a high level.
  • the high level of the pull-down node PD turns on the transistor M3, thereby pulling the pull-up node PU to a low level.
  • FIG. 2B shows a circuit diagram of a shift register according to another embodiment of the present disclosure.
  • the shift register of FIG. 2B is similar in structure to the shift register of FIG. 2A , and the difference is at least in that the shift register of FIG. 2B further includes a reset sub-circuit 40 .
  • the different parts will be mainly described in detail below.
  • the shift register includes an input sub-circuit 10, an output sub-circuit 20', a control sub-circuit 30', and a reset sub-circuit 40.
  • the input sub-circuit 10 may adopt the same structure as the above-mentioned input sub-circuit 10, and details are not repeated here.
  • the reset subcircuit 40 is connected to the pull-up node PU and the reset terminal RST, and can reset the pull-up node PU according to the reset signal of the reset terminal RST.
  • the reset sub-circuit 40 includes a transistor M8, the gate of the transistor M8 is connected to the reset terminal RST, and the first electrode is connected to the first reference signal terminal LVGL.
  • the reset sub-circuit 40 may further include a transistor M9, the gate of the transistor M9 is connected to the total reset terminal TRST, the first electrode is connected to the first reference signal terminal LVGL, and the second electrode is connected to the pull-up node PU.
  • the output subcircuit 20' includes a first output subcircuit, a second output subcircuit and a third output subcircuit.
  • the first output sub-circuit may include a transistor M10, the gate of the transistor M10 is connected to the pull-up node, the first pole is connected to the first clock signal terminal CK1, and the second pole is connected to the first output terminal OUT1.
  • the second output sub-circuit may have the same structure as the above-mentioned output sub-circuit 20, including the transistor M7 and the capacitor C1.
  • the first pole of the transistor M7 is connected to the second clock signal terminal CK2, and the second pole is connected to the second output terminal OUT2.
  • the third output sub-circuit may include a transistor M11 and a capacitor C3, wherein the gate of the transistor M11 is connected to the pull-up node PU, the first pole is connected to the third clock signal terminal CK3, and the second pole is connected to the third output terminal OUT; one end of the capacitor C3 The gate of the transistor M11 is connected, and the other end is connected to the second electrode of the transistor M11. At least one of the second output terminal OUT2 and the third output terminal OUT3 may be used to connect with a sub-pixel to apply a gate driving signal thereto.
  • the first output terminal OUT1 can be used to connect with other shift registers, so as to realize the cascade connection of shift registers.
  • the control subcircuit 30' may include a first control subcircuit and a second control subcircuit.
  • the first control sub-circuit may have the same structure as the above-mentioned control sub-circuit 30, including transistors M2, M3, M4, M5 and M6.
  • the gate and first electrode of the transistor M2 are connected to the first control terminal CKA, and the second electrode is connected to the first pull-down node PD_A.
  • the gate of the transistor M3 is connected to the first pull-down node PD_A, the first electrode is connected to the pull-up node PU, and the second electrode is connected to the first reference signal terminal LVGL.
  • the gate of the transistor M4 is connected to the pull-up node PU, the first electrode is connected to the first reference signal terminal LVGL, and the second electrode is connected to the first pull-down node PD_A.
  • the gate of the transistor M5 is connected to the second output terminal OUT, the first electrode is connected to the first reference signal terminal LVGL, and the second electrode is connected to the first pull-down node PD_A.
  • the gate of the transistor M6 is connected to the first pull-down node PD_A, the first electrode is connected to the second reference signal terminal VGL, and the second electrode is connected to the second output terminal OUT2.
  • the second control subcircuit may include transistors M12, M13, M14, M15, M16 and M17.
  • the gate and first electrode of the transistor M12 are connected to the second control terminal CKB, and the second electrode is connected to the second pull-down node PD_B.
  • the gate of the transistor M13 is connected to the pull-up node PU, the first electrode is connected to the first reference signal terminal VGL, and the second electrode is connected to the second pull-down node PD_B.
  • the gate of the transistor M14 is connected to the second pull-down node PD_B, the first electrode is connected to the first reference signal terminal LVGL, and the second electrode is connected to the first output terminal OUT1.
  • the gate of the transistor M15 is connected to the second pull-down node PD_B, the first electrode is connected to the first reference signal terminal VGL, and the second electrode is connected to the third output terminal OUT3.
  • the gate of the transistor M16 is connected to the second pull-down node PD_B, the first electrode is connected to the first reference signal terminal LVGL, and the second electrode is connected to the pull-up node PU.
  • the gate of the transistor M17 is connected to the third output terminal OUT3, the first electrode is connected to the first reference signal terminal LVGL, and the second electrode is connected to the second pull-down node PD_B.
  • the control sub-circuit 30' may further include transistors M18 and M19, wherein the gates of the transistors M18 and M19 are both connected to the input terminal IN, the first poles of the transistors M18 and M19 are both connected to the first reference signal terminal LVGL, and the first pole of the transistor M18 is connected to the first reference signal terminal LVGL.
  • the second electrode of the transistor M19 is connected to the first pull-down node PD_A, and the second electrode of the transistor M19 is connected to the second pull-down node PD_B.
  • the control sub-circuit 30' may further include a transistor M20, the gate of the transistor M20 is connected to the first pull-down node PD_A, the first electrode is connected to the first reference signal terminal LVGL, and the second electrode is connected to the first output terminal OUT1.
  • shift register is exemplified above with a specific structure, embodiments of the present disclosure are not limited thereto, and any suitable shift register may be employed as desired.
  • FIG. 3 shows a block diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • the gate driving circuit 100 includes a plurality of driving units, such as driving units DU1 and DU2 , which are connected in cascade.
  • Each driving unit includes N shift register units and mode control circuits, where N is an integer greater than 1.
  • the driving unit DU1 includes shift register units 120_1 , 120_2 , 120_3 and 120_4 and a mode control circuit 110_1
  • the driving unit DU2 includes shift register units 120_5 , 120_6 , 120_7 , 120_8 and 110_2 .
  • Each shift register unit may include multiple shift registers, as will be described in detail below.
  • the mode control circuit 110_1 is connected with the shift register units 120_1, 120_2, 120_3 and 120_4.
  • the mode control circuit 110_1 may receive the control signal SW_1 for the driving unit DU1, and connect the shift register units 120_1, 120_2, 120_3 and 120_4 in one of a plurality of resolution modes under the control of the control signal SW_1.
  • the mode control circuit 110_2 is connected to the shift register units 120_5, 120_6, 120_7 and 120_8.
  • the mode control circuit 110_2 may receive the control signal SW_2 for the driving unit DU2, and connect the shift register units 120_5, 120_6, 120_7 and 120_8 in one of a plurality of resolution modes under the control of the control signal SW_2.
  • the plurality of resolution modes may include a first resolution mode, a second resolution mode, and a third resolution mode.
  • the operations in the three resolution modes are described below by taking the drive unit DU1 as an example.
  • the mode control circuit 110_1 may cascade the shift register units 120_1, 120_2, 120_3 and 120_4.
  • the mode control circuit 110_1 may divide the shift register units 120_1, 120_2, 120_3 and 120_4 into M groups, connect the M groups in cascade, and parallelize the shift register units in each group connect.
  • the shift register units 120_1 and 120_2 are divided into a first group
  • the shift register units 120_3 and 120_4 are divided into a second group
  • the first group and the second group are connected in cascade
  • the shift register unit 120_1 in the first group and 120_2 are connected in parallel
  • the shift register units 120_3 and 120_4 in the second group are connected in parallel.
  • the mode control circuit 110_1 may connect the shift register units 120_1, 120_2, 120_3 and 120_4 in parallel.
  • the operation of the driving unit DU2 under the three resolutions is similar to that of the driving unit DU1, which will not be repeated here.
  • FIG. 4 shows an example block diagram of the gate driving circuit of FIG. 3 .
  • the gate driving circuit 100A includes driving units DU1 and DU2.
  • each shift register unit includes a first shift register, a second shift register and a third shift register.
  • Each of the first shift register, the second shift register and the third shift register may adopt the shift register structure of any of the above-mentioned embodiments, for example, may all be implemented as shift registers as shown in FIG. 2A .
  • the shift register unit 120_1 (first shift register unit) includes shift registers GOA1, GOA2 and GOA3 as the first shift register, the second shift register and the third shift register, respectively, and the shift register
  • the register unit 120_2 (the second shift register unit) includes shift registers GOA4, GOA5 and GOA6 as the first shift register, the second shift register and the third shift register, respectively, and the shift register unit 120_3 (the third shift register)
  • the register unit) includes shift registers GOA7, GOA8 and GOA9 as the first shift register, the second shift register and the third shift register, respectively
  • the shift register unit 120_4 (the fourth shift register unit) includes the shift register GOA10 , GOA11 and GOA12 as the first shift register, the second shift register and the third shift register, respectively.
  • the shift register unit 120_5 (first shift register unit) includes shift registers GOA13, GOA14 and GOA15
  • the shift register unit 120_6 includes shift register GOA16 , GOA17 and GOA18
  • the shift register unit 120_7 (third shift register unit) includes shift registers GOA19, GOA20 and GOA21
  • the shift register unit 120_8 (fourth shift register unit) includes shift registers GOA22, GOA23 and GOA24 .
  • Each shift register cell has a cascaded input and a first cascaded output.
  • the input terminal IN of the shift register GOA1 is used as the cascade input terminal of the shift register unit 120_1 to receive the start signal STV; the input terminal IN of the shift register GOA2 is connected to the shift register unit 120_1.
  • the output end OUT of the register GOA1 is connected; the input end IN of the shift register GOA3 is connected with the output end OUT of the shift register GOA2, and the output end OUT of the shift register GOA3 serves as the first cascade output end of the shift register unit 120_1.
  • the connection manner of each shift register in the shift register units 120_2 , 120_3 and 120_4 of the driving unit DU1 is similar to that of the shift register unit 120_1 , and details are not repeated here.
  • the input terminal IN of the shift register GOA13 is used as the cascade input terminal of the shift register unit 120_5 to receive the cascaded output signal from the drive unit DU1;
  • the shift register The input terminal IN of GOA14 is connected with the output terminal OUT of the shift register GOA13;
  • the input terminal IN of the shift register GOA15 is connected with the output terminal OUT of the shift register GOA14, and the output terminal OUT of the shift register GOA15 is used as the output terminal of the shift register unit 120_5.
  • the connection manner of each shift register in the shift register units 120_6, 120_7 and 120_8 of the driving unit DU2 is similar to that of the shift register unit 120_5, and details are not repeated here.
  • the first cascaded output terminal of the shift register unit 120_4 in the driving unit DU1 ie the output terminal of the shift register GOA12
  • the cascaded input terminal of the shift register unit 120_5 in the driving unit DU2 That is, the input terminal of the shift register GOA13
  • the mode control circuit may include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor, and the control signal for each driving unit may include the first control signal , a second control signal, a third control signal and a fourth control signal.
  • the mode control circuit 110_1 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6;
  • the control signal for the driving unit DU1 SW_1 may include a first control signal SW1, a second control signal SW2, a third control signal SW3 and a fourth control signal SW4.
  • the gate of the first transistor T1 is connected to receive the first control signal SW1, and the first pole of the first transistor T1 is connected to the first cascaded output terminal of the first shift register unit 120_1 (ie, the output terminal OUT of the shift register GOA3).
  • the second pole of the first transistor T1 is connected to the cascaded input terminal of the second shift register unit 120_2 (ie, the input terminal IN of the shift register GOA4).
  • the gate of the second transistor T2 is connected to receive the second control signal SW2, the first pole of the second transistor T2 is connected to the cascaded input terminal of the first shift register unit 120_1 (ie the input terminal IN of the shift register GOA1), the first The second pole of the two transistors T2 is connected to the cascade input terminal of the second shift register unit 120_2 (ie, the input terminal IN of the shift register GOA4).
  • the gate of the third transistor T3 is connected to receive the third control signal SW3, and the first pole of the third transistor T3 is connected to the first cascaded output terminal of the second shift register unit 120_2 (ie, the output terminal OUT of the shift register GOA6).
  • the second pole of the third transistor T3 is connected to the cascade input terminal of the third shift register unit 120_3 (ie, the input terminal IN of the shift register GOA7 ).
  • the gate of the fourth transistor T4 is connected to receive the fourth control signal SW4, the first pole of the fourth transistor T4 is connected to the cascade input terminal of the first shift register unit 120_2 (ie, the input terminal IN of the shift register GOA1), the The second pole of the four transistors T4 is connected to the cascade input terminal of the third shift register unit 120_3 (ie, the input terminal IN of the shift register GOA7).
  • the gate of the fifth transistor T5 is connected to the first control signal SW1, the first pole of the fifth transistor T5 is connected to the first cascade output terminal of the third shift register unit 120_3 (ie the output terminal OUT of the shift register GOA9), The second pole of the fifth transistor T5 is connected to the cascade input terminal of the fourth shift register unit 120_4 (ie, the input terminal IN of the shift register GOA10).
  • the gate of the sixth transistor T6 is connected to receive the second control signal SW2, the first pole of the sixth transistor T6 is connected to the cascade input terminal of the third shift register unit 120_3 (ie, the input terminal IN of the shift register GOA7), the The second pole of the six transistors T6 is connected to the cascade input terminal of the fourth transistor T4 (ie, the input terminal IN of the shift register GOA10).
  • the mode control circuit 110_2 may include a first transistor T1', a second transistor T2', a third transistor T3', a fourth transistor T4', a fifth transistor T5' and a sixth transistor T6' ;
  • the control signal SW_2 for the driving unit DU2 may include a first control signal SW1', a second control signal SW2', a third control signal SW3' and a fourth control signal SW4'.
  • connection mode of the first transistor T1', the second transistor T2', the third transistor T3', the fourth transistor T4', the fifth transistor T5' and the sixth transistor T6' is the same as that of the first transistor T1,
  • the second transistor T2 , the third transistor T3 , the fourth transistor T4 , the fifth transistor T5 , and the sixth transistor T6 are similar, and will not be repeated here.
  • the plurality of driving units in the gate driving circuit 100A may be divided into a plurality of groups, and each group of driving units is connected to a group of control signal lines to receive control signals for the group of driving units, so that the group is connected to the group. Display driver in different resolution modes.
  • the driving units DU1 and DU2 are divided into different groups, for example, the driving unit DU1 is divided into the first group for display driving in the first resolution mode, and the driving unit DU2 is divided into To the second group for display driving in the first resolution mode, the boundary between the first group and the second group is shown by the dashed-dotted line in FIG. 4 .
  • the driving units DU1 in the first group may be connected to the first to fourth control signal lines to receive control signals SW1 to SW4 for the driving units of the first group, respectively; the driving units DU2 in the second group may be connected The fifth to eighth control signal lines respectively receive control signals SW1 ′ to SW4 ′ for the second group of driving units.
  • the gate of the first transistor T1 of the driving unit DU1 and the gate of the first transistor T1 ′ of the driving unit DU2 may both be connected to the first control
  • the signal line is to receive the same first control signal, in this case the first control signal SW1 for the drive unit DU1 and the first control signal for the drive unit DU2 are the same signal.
  • the gate of the second transistor T2 of the driving unit DU1 and the gate of the first transistor T2' of the driving unit DU2 may be connected to the second control signal line to receive the same second control signal
  • the third of the driving unit DU1 The gate of the transistor T3 and the gate of the third transistor T3 ′ of the driving unit DU2 may be connected to the third control signal line to receive the same third control signal
  • the gate of the fourth transistor T4' may be connected to the fourth control signal line to receive the same fourth control signal.
  • 0 represents a low level and 1 represents a high level. However, embodiments of the present disclosure are not limited thereto. In some embodiments, 0 may represent a high level, and 1 may represent a low level.
  • the first control signal SW1 and the third control signal SW3 are at a high level, and the second control signal SW2 and the fourth control signal SW4 are at a low level, so that the In the mode control circuit 110_1, the transistors T1, T3, and T5 are turned on, and the transistors T2, T4, and T6 are turned off, so that the equivalent circuit structure shown in FIG. 5A is obtained.
  • the transistor T1 is turned on so that the first cascade output terminal of the first shift register unit 120_1 is connected to the cascade input terminal of the second shift register unit 120_2, and the transistor T2 is turned off so that the first shift register unit 120_2 is turned off.
  • the cascade input of cell 120_1 is disconnected from the cascade input of second shift register cell 120_2.
  • transistor T3 is turned on so that the first cascaded output of the second shift register unit 120_2 is connected to the cascaded input of the third shift register unit 120_3, and transistors T2 and T4 are turned off so that the second shift register unit
  • the cascade input terminal of 120_2 is disconnected from the cascade input terminal of the third shift register unit 120_3;
  • the transistor T5 is turned on so that the first cascade output terminal of the third shift register unit 120_3 is connected to the fourth shift register unit 120_4
  • the cascading input terminal of 1 is connected, and the transistor T6 is turned off so that the cascading input terminal of the third shift register unit 120_3 is disconnected from the cascade input terminal of the fourth shift register unit 120_4. In this way, the cascade connection of the shift register cells 120_1 to 120_4 is achieved.
  • the shift register GOA1 can generate an output signal G1 in response to the input of the start signal STV, and the output signal G1 is provided as an input signal to the shift register GOA2 , so that the shift register GOA2 generates the output signal G2 shifted with respect to the output signal G1, and so on, to obtain sequentially shifted output signals G1 to G12.
  • the gate driving circuit can scan the sub-pixels in the display area row by row, so as to perform display driving with the highest first resolution.
  • the first control signal SW1 and the second control signal SW4 are at a low level, and the second control signal SW2 and the third control signal SW3 are at a high level, so that the In the mode control circuit 110_1, the transistors T1, T4, and T5 are turned off, and the transistors T2, T3, and T6 are turned on, so that the equivalent circuit structure shown in FIG. 6A is obtained.
  • the transistor T1 is turned off so that the first cascaded output terminal of the first shift register unit 120_1 is disconnected from the cascaded input terminal of the second shift register unit 120_2, and the transistor T2 is turned on so that the second shift register unit 120_2 is turned on.
  • the cascaded input terminal of the bit register unit 120_2 is connected to the cascaded input terminal of the first shift register unit 120_1; the transistor T3 is turned on so that the first cascaded output terminal of the second shift register unit 120_2 is connected to the third shift register unit
  • the cascade input terminal of 120_3 is connected, and the fourth transistor T4 is turned off, so that the cascade input terminal of the third shift register unit 120_3 is disconnected from the cascade input terminal of the second shift register unit 120_2;
  • the first cascaded output terminal of the three shift register unit 120_3 is disconnected from the cascaded input terminal of the fourth shift register unit 120_4, and the transistor T6 is turned on so that the cascaded input terminal of the third shift register unit is connected to the fourth shift register unit.
  • the shift registers GOA1 and GOA4 can generate outputs in parallel in response to the input of the start signal STV Signals G1 and G4.
  • Output signals G1 and G4 are provided as input signals to shift registers GOA2 and GOA5, respectively, such that shift register GOA2 produces output signal G2 shifted relative to output signal G1 and shift register GOA5 produces output signal G4 shifted relative to output signal G4.
  • Output signals G2 and G5 are provided as input signals to shift registers GOA3 and GOA6, respectively, such that shift register GOA3 produces output signal G3 shifted relative to output signal G2, and shift register GOA6 produces output signal G5 shifted relative to output signal G5. bit output signal G5.
  • the shift register units 120_1 and 120_2 of the first group generate output signals in parallel, that is, the output signals G1 to G3 generated by the shift register unit 120_1 are respectively associated with the output signals G4 to G3 generated by the shift register unit 120_2 G6 sync.
  • the output signal G6 is provided as an input signal to shift register GOA7 in shift register unit 120_3 and GOA10 in shift register unit 120_4 so that shift register units 120_3 and 120_4 generate two sets of outputs in parallel in a manner similar to that described above signal, and the output signals G7 to G12 are shifted with respect to the output signals G1 to G6, respectively. In this way, it is achieved that the set of output signals generated by the second set of shift register units 120_3 and 120_4 is shifted relative to the set of output signals generated by the first set of shift register units 120_1 and 120_2.
  • the gate driving circuit can realize grouped scanning of the sub-pixels in the display area by generating the output signal as shown in FIG. 6B . For example, taking every two rows of pixel units as a group, first scan the red sub-pixels in the first and second rows of pixel units at the same time, then scan the green sub-pixels in the two rows of pixel units at the same time, and finally scan the two rows of pixels at the same time. The blue subpixel in the cell. After the first and second rows of pixel cells are scanned, the third and fourth rows of pixel cells are scanned in the same manner. Thereby, display driving with a second resolution lower than the first resolution can be realized, for example, the second resolution can be half of the first resolution.
  • the first control signal SW1 and the third control signal SW3 are at a low level, and the second control signal SW2 and the fourth control signal SW4 are at a high level, so that the In the mode control circuit 110_1, the transistors T1, T3, and T5 are turned off, and the transistors T2, T4, and T6 are turned on, so that the equivalent circuit structure shown in FIG. 7A is obtained.
  • the transistor T1 is turned off so that the first cascaded output terminal of the first shift register unit 120_1 is disconnected from the cascaded input terminal of the second shift register unit 120_2, and the transistor T2 is turned on so that the first shift register unit 120_2 is turned on.
  • the cascade input of the bit register unit 120_1 is connected to the cascade input of the second shift register unit 120_2.
  • transistor T3 is turned off so that the first cascade output of the second shift register unit 120_2 is disconnected from the cascade input of the third shift register unit 120_3, and transistors T2 and T4 are turned on so that the second shift register
  • the cascade input terminal of the register unit 120_2 is connected to the cascade input terminal of the third shift register unit 120_3;
  • the transistor T5 is turned off so that the first cascade output terminal of the third shift register unit 120_3 is connected to the fourth shift register unit 120_4
  • the cascading input terminal of 120_3 is disconnected, and the transistor T6 is turned on, so that the cascading input terminal of the third shift register unit 120_3 is connected to the cascading input terminal of the fourth shift register unit 120_4.
  • parallel connection of the shift register units 120_1 to 120_4 is achieved.
  • the shift registers GOA1, GO4, GOA7 and GOA10 can generate output signals G1, G4, G7 and G10 in parallel in response to the input of the start signal STV;
  • the output signals G1, G4, G7 and G10 are supplied as input signals to the shift registers GOA2, GOA5, GOA8 and GOA11, respectively, so that the shift registers GOA2, GOA5, GOA8 and GOA11 generate shifted output signals G2, G5, GOA11 in parallel.
  • output signals G2, G5, G8 and G11 are supplied as input signals to shift registers GOA3, GOA6, GOA9 and GOA12, respectively, so that shift registers GOA3, GOA6, GOA9 and GOA12 generate shifted output signals in parallel G3, G6, G9 and G12. In this way, it is achieved that the shift register units 120_1 to 120_4 generate output signals in parallel.
  • the gate driving circuit can realize grouped scanning of the sub-pixels in the display area by generating the output signal as shown in FIG. 7B . For example, taking every four rows of pixel units as a group, first scan the red sub-pixels in the first to fourth rows of pixel units at the same time, then scan the green sub-pixels in the four rows of pixel units at the same time, and finally scan the four rows of pixels at the same time. The blue subpixel in the cell. After the first to fourth rows of pixel units are scanned, the fifth to eighth rows of pixel units are scanned in the same manner. Thereby, display driving with a third resolution lower than the second resolution can be realized, for example, the third-year resolution can be half of the second resolution.
  • FIG. 8A shows an equivalent schematic diagram of the gate driving circuit 100A of FIG. 4 in the second resolution and the third resolution mode.
  • the sub-pixels in the display area may be divided into multiple groups, for example, the sub-pixels located in the multiple rows of the central area in the display area are divided into the first group, and the sub-pixels located in the areas on both sides of the central area along the column direction are divided into the first group.
  • the multiple rows of sub-pixels are divided into a second group and a third group, respectively.
  • the multiple driving units in the gate driving circuit of the embodiments of the present disclosure are also divided into multiple groups accordingly, and each group of driving units is connected to a group of sub-pixels, so that each group of sub-pixels can be independently driven to display at different resolutions. For example, the sub-pixels driving the central area are displayed at a higher resolution, while the sub-pixels driving the two side areas are displayed at a lower resolution.
  • the driving unit DU1 and the driving unit DU2 are respectively divided into two groups that perform display driving in different resolution modes.
  • the mode control circuit 110_1 in the driving unit DU1 can connect the shift register units 120_1 to 120_4 in the second resolution mode under the control of the control signals SW1 to SW4, so as to obtain, etc. as shown in FIG. 6A . effective circuit structure.
  • the mode control circuit 110_2 in the driving unit DU2 can connect the shift register units 120_5 to 120_8 in the third resolution mode under the control of the control signals SW1' to SW4' to obtain the equivalent circuit structure as shown in FIG. 7A .
  • the drive unit DU1 is connected in cascade with the drive unit DU2, so that the output signal G12 of the shift register GOA12 is supplied as an input signal to the shift registers GOA13, GOA16, GOA19 and GOA22 of the drive unit DU2.
  • the shift register units 120_1 to 120_4 connected in the second resolution mode generate output signals G1 to G12 as shown in FIG. 6B.
  • the output signal G12 of the shift register GOA12 is supplied as an input signal to the shift registers GOA13, GOA16, GOA19 and GOA22 of the drive unit DU2, so that the shift register units 120_5 to 120_8 connected in the third resolution mode produce a result similar to that of FIG. 7B
  • the output signals G13 to G24 are shown.
  • the driving unit DU1 can drive the multiple rows of sub-pixels connected to it to display at the second resolution
  • the driving unit DU2 can drive the multiple rows of sub-pixels connected to it to display at the third resolution, thereby realizing Multi-resolution display of sub-regions.
  • the second resolution mode shortens the scanning time (the time required for the gate driving circuit to scan all the sub-pixels), and in this embodiment, the scanning time is shortened by half ; while the third resolution mode further shortens the scan time compared to the second resolution.
  • the time length of one frame is constant, the scan time is shortened, so that the blanking period is correspondingly increased.
  • FIG. 9 shows another example structure diagram of the gate driving circuit of FIG. 3 .
  • the gate driving circuit 100B of FIG. 9 is similar to the gate driving circuit 100A of FIG. 4 , except that each shift register unit further has a reset terminal and the mode control circuit is also connected to the reset terminal of each shift register unit.
  • each shift register unit further has a reset terminal and the mode control circuit is also connected to the reset terminal of each shift register unit.
  • the mode control circuit is also connected to the reset terminal of each shift register unit.
  • the driving unit DU1 includes four shift register units, wherein the first shift register unit includes shift registers GOA1 to GOA3, and the second shift register unit includes shift registers GOA4 to GOA6 , the third shift register unit includes shift registers GOA7 to GOA9, and the fourth shift register unit includes shift registers GOA10 to GOA12.
  • each shift register in the shift register unit of FIG. 9 also has a reset terminal RST, which can be implemented by, for example, the shift register described above with reference to FIG. 2B .
  • RST reset terminal
  • the output of the first shift register can be used as the second cascaded output of the shift register unit
  • the output of the third shift register and the reset The terminals are respectively used as the first cascade output terminal and the reset terminal of the shift register unit.
  • the output end of the shift register GOA1 is used as the second cascade output end of the shift register unit 120_1, and the output end of the shift register GOA3 is used as the first stage of the shift register unit 120_1
  • the output end of the shift register GOA4 is used as the second cascade connection of the shift register unit 120_2.
  • the output terminal of the shift register GOA6 is used as the first cascade output terminal of the shift register unit 120_2
  • the reset terminal RST of the shift register GOA4 is used as the reset terminal of the shift register unit 120_2, and so on.
  • the reset terminal of the fourth shift register unit of the drive unit DU1 (ie the reset terminal RST of the shift register GOA12) and the second cascade output terminal of the first shift register unit in the drive unit DU2 (ie the reset terminal of the shift register GOA13)
  • the output terminal OUT is connected to realize the cascade connection of the driving unit DU1 and the driving unit DU2.
  • the mode control circuit includes a first mode control sub-circuit 1101 and a second mode control sub-circuit 1102 .
  • the first mode control sub-circuit 1101 has the same structure as the above-mentioned mode control circuit 110_1, and includes the first transistor T1 to the sixth transistor T6, and details are not described herein again.
  • the second mode control sub-circuit 1102 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11 and a twelfth transistor T12.
  • the gate of the seventh transistor T7 is connected to receive the first control signal SW1, the first pole is connected to the reset terminal of the first shift register unit (ie, the reset terminal RST of the shift register GOA3), and the second pole is connected to the second shift register The second cascaded output of the cell (ie the output of the shift register GOA4).
  • the gate of the eighth transistor T8 is connected to receive the fifth control signal SW5, the first pole is connected to the reset terminal of the first shift register unit (ie, the reset terminal RST of the shift register GOA3), and the second pole is connected to the second shift register The reset terminal of the unit (ie, the reset terminal RST of the shift register GOA6).
  • the gate of the ninth transistor T9 is connected to receive the third control signal SW3, the first pole is connected to the reset terminal of the second shift register unit (ie, the reset terminal RST of the shift register GOA6), and the second pole is connected to the third shift register The second cascaded output of the cell (ie the output OUT of the shift register GOA7).
  • the gate of the tenth transistor T10 is connected to receive the fourth control signal SW4, the first pole is connected to the reset terminal of the second shift register unit (ie, the reset terminal RST of the shift register GOA6), and the second pole is connected to the third shift register The reset terminal of the unit (ie, the reset terminal of the shift register GOA9).
  • the gate of the eleventh transistor T11 is connected to receive the first control signal SW1, the first pole is connected to the reset terminal of the third shift register unit (ie, the reset terminal RST of the shift register GOA9), and the second pole is connected to the fourth shift register unit The second cascaded output of the register unit (ie the output of the shift register GOA10).
  • the gate of the twelfth transistor T12 is connected to receive the second control signal SW2, the first pole is connected to the reset terminal of the third shift register unit (ie the reset terminal RST of the shift register GOA9), and the second pole is connected to the fourth shift register unit The reset terminal of the register unit (ie, the reset terminal RST of the shift register GOA12).
  • Second Resolution Mode third resolution mode SW1 1 0 0 SW2 0 1 1 SW3 1 1 0 SW4 0 0 1 SW5 0 1 0
  • 0 represents a low level and 1 represents a high level.
  • embodiments of the present disclosure are not limited thereto.
  • 0 may represent a high level
  • 1 may represent a low level.
  • the first control signal SW1 and the third control signal SW3 are at a high level, and the second control signal SW2, the fourth control signal SW4 and the fifth control signal SW5 are at a low level flat.
  • the first mode control subcircuit 1101 cascades the respective shift registers in the manner described above with reference to FIG. 5A.
  • the second mode control subcircuit 1102 connects the reset terminal of the nth shift register unit to the second cascade output terminal of the n+1th shift register unit, and connects the reset terminal of the nth shift register unit to all The reset terminal of the n+1th shift register unit is disconnected, where 1 ⁇ n ⁇ 3. As shown in FIG.
  • the transistors T7, T9 and T11 are turned on when the first control signal SW1 and the third control signal SW3 are at a high level, and the second control signal SW2, the fourth control signal SW4 and the fifth control signal SW5 are at a low level
  • the level turns off the transistors T8, T10 and T12, thereby connecting the reset terminal RST of the shift register GOA3 to the output terminal OUT of the shift register GOA4, and connecting the reset terminal RST of the shift register GOA3 to the reset terminal of the shift register GOA6.
  • Disconnect connect the reset terminal RST of the shift register GOA6 with the output terminal OUT of the shift register GOA7, and disconnect the reset terminal RST of the shift register GOA6 from the reset terminal RST of the shift register GOA9; connect the shift register The reset terminal RST of GOA9 is connected to the output terminal OUT of the shift register GOA10, and the reset terminal RST of the shift register GOA9 is disconnected from the reset terminal RST of the shift register GOA12.
  • the second control signal SW2, the third control signal SW3 and the fifth control signal SW5 are at a high level, and the first control signal SW1 and the fourth control signal SW4 are at a low level flat.
  • the first mode control subcircuit 1101 groups the respective shift registers in the manner described above with reference to FIG. 6A.
  • the second mode control sub-circuit 1102 connects the reset terminal of the first shift register unit (ie the reset terminal RST of the shift register GOA3 ) with the second cascaded output terminal of the second shift register unit (ie the output of the shift register GOA4 )
  • the terminal OUT) is disconnected, and the reset terminal of the second shift register unit (ie the reset terminal RST of the shift register GOA6) and the second cascade output terminal of the third shift register unit (ie the output of the shift register GOA7) terminal OUT) to connect the reset terminal of the third shift register unit (ie the reset terminal RST of the shift register GOA9) with the second cascade output terminal of the fourth shift register unit (ie the output terminal OUT of the shift register GOA10) ) is disconnected, the reset terminal of the first shift register unit (that is, the reset terminal RST of the shift register GOA3) is connected with the reset terminal of the second shift register unit (that is, the reset terminal RST of the shift register GOA6), and the The reset terminal of the second shift register unit
  • the second control signal SW2 and the fourth control signal SW4 are at a high level, and the first control signal SW1, the third control signal SW3 and the fifth control signal SW5 are at a low level flat.
  • the first mode control subcircuit 1101 connects the respective shift registers in parallel in the manner described above with reference to FIG. 7A.
  • the second mode control subcircuit 1102 disconnects the reset terminal of the nth shift register unit from the second cascaded output terminal of the n+1th shift register unit, and connects the reset terminal of the nth shift register unit It is connected to the reset terminal of the n+1th shift register unit, wherein 1 ⁇ n ⁇ 3. As shown in FIG.
  • the transistors T10 and T12 are turned on when the second control signal SW2 and the fourth control signal SW4 are at a high level, and the first control signal SW1 , the third control signal SW3 and the fifth control signal SW5 are at a low level
  • the transistors T7, T8, T9, and T11 are turned off, so that the reset terminal RST of the shift register GOA3 is disconnected from the output terminal OUT of the shift register GOA4, and the reset terminal RST of the shift register GOA3 is connected to the shift register GOA6.
  • the reset terminal is disconnected, the reset terminal RST of the shift register GOA6 is disconnected from the output terminal OUT of the shift register GOA7, and the reset terminal RST of the shift register GOA9 is disconnected from the output terminal OUT of the shift register GOA10.
  • Disconnect the reset terminal RST of the shift register GOA3 from the reset terminal RST of the shift register GOA6 connect the reset terminal RST of the shift register GOA6 to the reset terminal RST of the shift register GOA9, and connect the reset terminal of the shift register GOA9.
  • RST is connected to the reset terminal RST of the shift register GOA12.
  • FIG. 10 shows a structural diagram of a gate driving circuit according to another embodiment of the present disclosure.
  • the gate driving circuit 200 includes a plurality of driving units, and each driving unit includes a plurality of shift registers connected in cascade.
  • the driving unit DU1 includes a plurality of shift registers GOA1 , GOA2 , . . . GOA8 connected in cascade
  • the driving unit DU2 includes a plurality of shift registers GOA9 , GOA10 , .
  • the driving unit DU1 includes 8 shift registers for illustration, however, the embodiments of the present disclosure are not limited thereto, and each driving unit may include other numbers of shift registers as required.
  • the respective shift registers GOA1, GOA2, . . . may adopt a shift register structure according to any embodiment of the present disclosure, eg, implemented by the shift registers described above with reference to FIG. 2B.
  • the gate driving circuit 200 further includes a plurality of start-up signal lines connected to the plurality of driving units in one-to-one correspondence, such as a start-up signal line STV1 connected with the driving unit DU1 and a start-up signal line STV2 connected with the driving unit DU2.
  • the start signal line STV1 is connected to the first stage shift register GOA1 in the driving unit DU1
  • the start signal line STV2 is connected to the first stage shift register GOA9 in the driving unit DU2.
  • the gate drive circuit 200 also includes a mode control circuit 210 .
  • the mode control circuit 210 is connected to the K clock signal lines CLK1 to CLK8.
  • the mode control circuit 210 may receive K initial clock signals clk1 to clk8 and a control signal SW under the control of the control signal SW based on one of the first resolution mode, the second resolution mode and the third resolution mode.
  • the K initial clock signals clk1 to clk8 generate K clock signals, and the generated K clock signals are supplied to the K clock signal lines CLK1 to CLK8 respectively.
  • the mode control circuit 210 may generate sequentially shifted K first clock signals based on the K initial clock signals.
  • the mode control circuit 210 may generate K second clock signals divided into 2M groups based on the K initial clock signals, the plurality of second clock signals in each group are synchronized, and the m+1th group The second clock signal is shifted relative to the mth group of second clock signals.
  • the mode control circuit 210 may generate K third clock signals divided into M groups based on the K initial clock signals, the plurality of third clock signals in each group are synchronized, and the m'+1th The third group of clock signals is shifted relative to the m'th group of third clock signals, where M is an integer greater than 1, m and m' are both integers, 1 ⁇ m ⁇ 2M-1, and 1 ⁇ m' ⁇ M -1.
  • each driving unit the output of the n-th shift register is connected to the input of the n+1-th shift register, and the output of the n+1-th shift register is connected to the n+1-th shift register.
  • the plurality of shift registers in each driving unit are divided into at least one group, each group includes K shift registers connected in cascade, and the clock signal terminals of the K shift registers are connected to the K clock signal lines. connected one by one.
  • the output terminal OUT of the first-stage shift register GOA1 is connected to the input terminal IN of the second-stage shift register GOA2, and the output terminal OUT of the second-stage shift register GOA2 is connected to The reset terminal RST of the first stage shift register GOA1; the output terminal OUT of the second stage shift register GOA2 is connected to the input terminal IN of the third shift register GOA3, and the output terminal OUT of the third stage shift register GOA3 is connected to the first stage shift register GOA3.
  • the first-stage shift registers GOA1 to the eighth-stage shift registers GOA8 are grouped into a group, and the respective clock signal terminals of the first-stage shift registers GOA1 to the eighth-stage shift registers GOA8 CK is connected to the clock signal lines CLK1 to CLK8 in one-to-one correspondence.
  • the driving unit DU1 includes more shift registers, for example, 16 shift registers
  • the shift registers of the first stage to the eighth stage may be divided into a first group and integrated with the clock signal lines CLK1 to CLK8 in the above-described manner Connected in a one-to-one correspondence, the shift registers of the ninth stage to the sixteenth stage are divided into a second group and connected in a one-to-one correspondence with the clock signal lines CLK1 to CLK8 in the above-described manner.
  • the driving unit DU2 shown in FIG. 10 the first-stage shift register GOA9, the second-stage shift register GOA10 . .
  • FIG. 11 shows an example circuit diagram of a mode control circuit in the gate drive circuit of FIG. 10 .
  • the mode control circuit 210 includes a first clock input terminal to an eighth clock input terminal, which are respectively connected to receive eight initial clock signals clk1 to clk8 .
  • the mode control circuit 210 further includes a first clock output terminal to an eighth clock output terminal, which are connected to the eight clock signal lines CLK1 to CLK8 in one-to-one correspondence.
  • the first clock input terminal and the first clock output terminal of the mode control circuit 210 may be connected, for example, the first clock signal line CLK1 may be implemented to receive the first initial clock signal clk1.
  • the first to eighth clock input terminals will be denoted by clk1 to clk8, and the first to eighth clock output terminals will be denoted by CLK1 to CLK8, respectively.
  • the mode control circuit 210 further includes a first mode control subcircuit 2101 , a second mode control subcircuit 2102 , a third mode control subcircuit 2103 and a second mode control subcircuit 2104 .
  • the first mode control sub-circuit 2101 can connect the second clock input end clk2 to the second clock output end CLK8, and connect the fourth clock input end clk4 to the fourth clock output end CLK4 under the control of the first control signal SW1,
  • the seventh clock input terminal clk7 is connected to the seventh clock output terminal CLK7
  • the eighth clock input terminal clk8 is connected to the eighth clock output terminal CLK8.
  • the first mode control sub-circuit 2101 includes a first transistor T1 , a second transistor T2 , a third transistor T3 and a fourth transistor T4 .
  • the gates of the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 are all connected to receive the first control signal SW1.
  • the first pole of the first transistor T1 is connected to the second clock input terminal clk2, and the second pole is connected to the second clock output terminal CLK2.
  • the first pole of the second transistor T2 is connected to the fourth clock input terminal clk4, and the second pole is connected to the fourth clock output terminal CLK4.
  • the first pole of the third transistor T3 is connected to the seventh clock input terminal clk7, and the second pole is connected to the seventh clock output terminal CLK7.
  • the first pole of the fourth transistor T4 is connected to the eighth clock input terminal clk8, and the second pole is connected to the eighth clock output terminal CLK8.
  • the second mode control sub-circuit 2102 can connect the third clock input terminal clk3 to the third clock output terminal CLK3 and the sixth clock input terminal clk6 to the sixth clock output terminal CLK6 under the control of the second control signal SW2 .
  • the second mode control sub-circuit 2102 includes a fifth transistor T5 and a sixth transistor T6.
  • the gates of the fifth transistor T5 and the sixth transistor T6 are both connected to receive the second control signal SW2.
  • the first pole of the fifth transistor T5 is connected to the third clock input terminal clk3, and the second pole is connected to the third clock output terminal CLK3.
  • the first pole of the sixth transistor T6 is connected to the sixth clock input terminal clk6, and the second pole is connected to the sixth clock output terminal CLK6.
  • the third mode control subcircuit 2103 can connect the first clock output terminal CLK1 to the second clock output terminal CLK2 under the control of the third control signal SW3, connect the third clock output terminal CLK3 to the fourth clock output terminal CLK4, and connect the The fifth clock output terminal CLK5 is connected to the sixth clock output terminal CLK6, and the seventh clock output terminal CLK7 is connected to the eighth clock output terminal CLK8.
  • the third mode control sub-circuit 2103 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9 and a tenth transistor T10. Gates of the seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 are all connected to receive the third control signal SW3.
  • the first pole of the seventh transistor T7 is connected to the first clock output terminal CLK1, and the second pole is connected to the second clock output terminal CLK2.
  • the first pole of the eighth transistor T8 is connected to the third clock output terminal CLK3, and the second pole is connected to the fourth clock output terminal CLK4.
  • the first pole of the ninth transistor T9 is connected to the fifth clock output terminal CLK5, and the second pole is connected to the sixth clock output terminal CLK6.
  • the first pole of the tenth transistor T10 is connected to the seventh clock output terminal CLK7, and the second pole is connected to the eighth clock output terminal CLK8.
  • the fourth mode control sub-circuit 2104 can connect the second clock output terminal CLK2 to the third clock output terminal CLK3 and the sixth clock output terminal CLK6 to the seventh clock output terminal CLK7 under the control of the fourth control signal SW4.
  • the fourth mode control sub-circuit 2104 includes an eleventh transistor T11 and a twelfth transistor T12.
  • the gates of the eleventh transistor T11 and the twelfth transistor T12 are both connected to receive the fourth control signal SW4.
  • the first pole of the eleventh transistor T11 is connected to the second clock output terminal CLK2, and the second pole is connected to the third clock output terminal CLK3.
  • the first pole of the twelfth transistor T12 is connected to the sixth clock output terminal CLK6, and the second pole is connected to the seventh clock output terminal CLK7.
  • the mode control circuit 210 generates K clock signals based on the K initial clock signals clk1 to clk8 in one of multiple resolution modes under the control of the control signal, and provides the generated K clock signals respectively to the K clock signal lines CLK1 to CLK8.
  • a start-up signal is applied to at least one start-up signal line (eg, STV1 ) among the plurality of start-up signal lines STV1 and STV2 to start the driving unit connected to the at least one start-up signal line.
  • the plurality of shift registers GOA1 to GOA8 in the activated driving unit DU1 respectively generate the output signal G1 according to the clock signals on the clock signal lines CLK1 to CLK8 to G8.
  • the plurality of shift registers GOA9, GOA10, . . . in the activated driving unit DU2 generate output signals according to the clock signals on the clock signal lines CLK1 to CLK8, respectively.
  • the driving method of the gate driving circuit 200 will be described in detail below with reference to Table 3 and FIGS. 12 to 17 in conjunction with FIGS. 10 and 11 .
  • a driving unit DU1 in FIG. 10 is taken as an example for description.
  • the working principle of the driving unit DU2 is similar to that of the driving unit DU1 , and details are not repeated here.
  • 0 represents a low level and 1 represents a high level.
  • embodiments of the present disclosure are not limited thereto.
  • 0 may represent a high level
  • 1 may represent a low level.
  • FIG. 12 shows a timing diagram of the initial clock signal received by the gate drive circuit of FIG. 10 .
  • the initial clock signals clk1 to clk8 are sequentially shifted clock signals, wherein the k+1 th initial clock signal is shifted by a unit scan time H with respect to the k th initial clock signal, and each initial clock signal clk1 to clk8
  • the active level duration is 4H.
  • the unit scan time may be the time required to scan one row of sub-pixels.
  • the first control signal SW1 and the second control signal SW2 are at a high level
  • the third control signal SW3 and the fourth control signal SW4 are at a low level.
  • the first transistor T1 , the second transistor T2 , the third transistor T3 , the fourth transistor T4 , the fifth transistor T5 and the sixth transistor T6 are turned on
  • the seventh transistor T7 , the eighth transistor T8 and the ninth transistor T9 are turned on.
  • the tenth transistor T10 , the eleventh transistor T11 and the twelfth transistor T12 are turned off.
  • the first mode control subcircuit 2101 connects the second clock input terminal clk2 to the second clock output terminal CLK2, connects the fourth clock input terminal clk4 to the fourth clock output terminal CLK4, and connects the seventh clock input terminal clk7 to the seventh clock
  • the output terminal CLK7 is connected, and the eighth clock input terminal clk8 is connected with the eighth clock output terminal CLK8.
  • the second mode control subcircuit 2102 connects the third clock input terminal clk3 to the third clock output terminal CLK3, and connects the sixth clock input terminal clk6 to the sixth clock output terminal CLK6.
  • the mode control circuit generates sequentially shifted eight first clock signals based on the initial clock signals clk1 to clk8 and supplies them to the clock signal lines CLK1 to CLK8 , respectively.
  • the shift registers GOA1 to GOA8 in FIG. 10 generate sequentially shifted output signals G1 to G8 based on the clock signals on the clock signal lines CLK1 to CLK8 , as shown in FIG. 13 .
  • the first control signal SW1 and the fourth control signal SW4 are at a low level, and the second control signal SW2 and the third control signal SW3 are at a high level.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the eleventh transistor T11 and the twelfth transistor T12 are turned off, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the The eight transistors T8, the ninth transistor T9 and the tenth transistor T10 are turned on.
  • the second mode control subcircuit 2102 connects the third clock input terminal clk3 to the third clock output terminal CLK3, and connects the sixth clock input terminal clk6 to the sixth clock output terminal CLK6.
  • the third mode control sub-circuit 2103 connects the first clock output terminal CLK1 to the second clock output terminal CLK2, connects the third clock output terminal CLK3 to the fourth clock output terminal CLK4, and connects the fifth clock output terminal CLK5 to the sixth clock output terminal CLK5
  • the output terminal CLK6 is connected, and the seventh clock output terminal CLK7 is connected with the eighth clock output terminal CLK8.
  • the mode control circuit generates eight second clock signals based on the initial clock signals clk1 to clk8 and supplies them to the clock signal lines CLK1 to CLK8, respectively.
  • the second clock signal on the clock signal line CLK1 is synchronized with the second clock signal on CLK2, the second clock signal on the clock signal line CLK3 is synchronized with the second clock signal on CLK4, and so on.
  • the second clock signal on the second set of clock signal lines CLK3 and CLK4 is shifted relative to the second clock signal on the first set of clock signal lines CLK1 and CLK2, the second clock on the third set of clock signal lines CLK5 and CLK6
  • the signals are shifted relative to the second clock signal on the second set of clock signal lines CLK3 and CLK4, and the second clock signal on the fourth set of clock signal lines CLK7 and CLK8 relative to the third set of clock signal lines CLK5 and CLK6. shifted by the second clock signal.
  • the shift registers GOA1 to GOA8 in FIG. 10 accordingly generate output signals G1 to G8 based on the clock signals on the clock signal lines CLK1 to CLK8, as shown in FIG. 14, the output signals G1 and G2 are synchronized, and the output signals G3 and G4 are synchronized, Either of the output signals G3 and G4 is shifted relative to either of the output signals G1 and G2, and so on.
  • the first control signal SW1 and the second control signal SW2 are at a low level, and the third control signal SW3 and the fourth control signal SW4 are at a high level.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10, the eleventh transistor T11 and the twelfth transistor T12 are turned on.
  • the third mode control sub-circuit 2103 connects the first clock output terminal CLK1 to the second clock output terminal CLK2, connects the third clock output terminal CLK3 to the fourth clock output terminal CLK4, and connects the fifth clock output terminal CLK5 to the sixth clock output terminal CLK5
  • the output terminal CLK6 is connected, and the seventh clock output terminal CLK7 is connected with the eighth clock output terminal CLK8.
  • the fourth mode control subcircuit 2104 connects the second clock output terminal CLK2 to the third clock output terminal CLK3, and connects the sixth clock output terminal CLK6 to the seventh clock output terminal CLK7.
  • the mode control circuit generates eight third clock signals based on the initial clock signals clk1 to clk8 and supplies them to the clock signal lines CLK1 to CLK8.
  • the eight third clock signals are divided into M groups, and the plurality of third clock signals in each group are synchronized.
  • the first group includes the clock signal lines CLK1 to CLK4
  • the second group includes the clock signal lines CLK5 to CLK8.
  • the third clock signals on the first group of clock signal lines CLK1 to CLK4 are synchronized with each other
  • the third clock signals on the second group of clock signal lines CLK5 to CLK8 are synchronized with each other.
  • the third clock signals on the second set of clock signal lines CLK5 to CLK8 are shifted relative to the third clock signals on the first set of clock signal lines CLK1 to CLK4.
  • the shift registers GOA1 to GOA8 in FIG. 10 accordingly generate output signals G1 to G8 based on the clock signals on the clock signal lines CLK1 to CLK8, as shown in FIG. 15, the output signals G1 to G4 are synchronized with each other, and the output signals G5 to G8 are synchronized , any of the output signals G1 to G4 is shifted relative to any of the output signals G5 to G8, and so on.
  • FIG. 16 shows an example of a signal timing diagram of the gate driving circuit of FIG. 10 in the first resolution mode, the second resolution mode and the third resolution mode.
  • the first resolution mode is a display mode of 8K resolution
  • the second resolution mode is a display mode of 4K resolution
  • the third resolution mode is a display mode of 2K resolution as an example for description .
  • the embodiments of the present disclosure are not limited thereto, and the first resolution mode, the second resolution mode and the third resolution mode may be set to display modes of other resolutions as required.
  • the mode control circuit in the first period P1, the mode control circuit generates 8 clock signals sequentially shifted as shown in FIG. 13 in the first resolution mode and supplies them to the clock signal lines CLK1 to CLK8, respectively, and the shift register GOA1, GOA2, . . . produce output signals shifted in the same order.
  • the mode control circuit In the second period P2, the mode control circuit generates 8 clock signals sequentially shifted in 4 groups as shown in FIG. 14 in the second resolution mode and supplies them to the clock signal lines CLK1 to CLK8, the shift registers GOA1, GOA2 respectively , ... to generate the output signal G1 which is also divided into 4 groups and shifted sequentially.
  • the mode control circuit In the third period P3, the mode control circuit generates 8 clock signals sequentially shifted in 2 groups as shown in FIG. 15 in the third resolution mode and supplies them to the clock signal lines CLK1 to CLK8, the shift registers GOA1, GOA2 respectively , ... to generate output signals that are also sequentially shifted in 2 groups.
  • FIG. 17 shows another example of a signal timing diagram of the gate driving circuit of FIG. 10 in the first resolution, second resolution and third resolution modes.
  • the embodiment of FIG. 17 is similar to that of FIG. 16 , except that the initial clock signals clk1 to clk8 are periodic signals with a duty ratio of 12.5%, wherein the k+1 th initial clock signal is shifted by the unit scan time H relative to the k th initial clock signal , the effective level duration of each initial signal is the unit scan time H.
  • the clock signals CLK1 and CLK8 generated based on the initial clock signals clk1 to clk8 are also periodic signals with a duty ratio of 12.5%, wherein the k+1 th clock signal is shifted by the unit scan time H relative to the k th clock signal, and each clock
  • the active level duration of the signal is the unit scan time H.
  • the active level duration of the correspondingly generated output signal is H.
  • the effective level duration of the output signal generated by each stage of the shift register is 4H, and the shift between each other is H, which makes the The pixels can be precharged for a period of time before writing data signals to the row of sub-pixels.
  • the method of FIG. 17 produces both the active level duration of the output signal and the shift between the output signals by H, removing the precharging process.
  • FIG. 18 shows a block diagram of a gate driving circuit according to yet another embodiment of the present disclosure.
  • FIG. 19 shows an example block diagram of the gate drive circuit of FIG. 18 .
  • the sub-pixels in the display area may be divided into multiple groups by region, for example, the sub-pixels located in the middle region are divided into the first group, and the sub-pixels located in the two side regions are respectively divided into the second group and the third group.
  • the gate driving circuit 300 may include a plurality of driving units, such as driving units DU1 , DU2 and DU3 .
  • the driving unit DU2 may be connected to the above-mentioned first group of sub-pixels
  • the driving unit DU1 may be connected to the above-mentioned second group of sub-pixels
  • the driving unit DU3 may be connected to the above-mentioned third group of sub-pixels.
  • Each of the drive units DU1, DU2 and DU3 includes a plurality of shift register units connected in cascade.
  • the drive unit DU1 comprises cascade-connected shift register units 320_1, 320_2, . . . 320_Y.
  • Each shift register unit may include a first shift register, a second shift register and a third shift register.
  • the shift register unit 320_1 includes shift registers GOA1, GOA2, and GOA3 as the first shift register, the second shift register, and the third shift register, respectively
  • the shift register unit 320_2 includes shift registers GOA4, GOA5, and GOA6, respectively As the first shift register, the second shift register and the third shift register, and so on.
  • the above-mentioned shift register may adopt the shift register structure of any embodiment of the present disclosure, for example, to be implemented by the shift register described above with reference to FIG. 2A or FIG. 2B .
  • the input terminal IN of the first shift register GOA1 is used as the cascade input terminal of the shift register unit 320_1
  • the output terminal OUT of the first shift register GOA1 is connected to the input of the second shift register GOA2 terminal IN
  • the output terminal OUT of the second shift register GOA2 is connected to the input terminal IN of the third shift register GOA3
  • the output terminal OUT of the third shift register GOA3 serves as the cascade output terminal of the shift register unit 320_1.
  • the clock signal terminal CK of the first shift register GOA1, the clock signal terminal CK of the second shift register GOA2 and the clock signal terminal CK of the third shift register GOA3 are used as the clock signal terminal of the shift register unit 320_1.
  • the other shift register units 320_2, 320_3, . . . have similar structures, which will not be repeated here.
  • the cascade output terminal of the first stage shift register unit 320_1 (ie the output terminal OUT of the shift register GOA3) is connected to the cascade connection of the fifth stage shift register unit 320_5
  • the input terminal (ie the input terminal IN of the shift register GOA13); the cascaded output terminal of the second stage shift register unit 320_2 (ie the output terminal OUT of the shift register GOA6) is connected to the stage of the sixth stage shift register unit 320_6 connected to the input terminal (ie, the input terminal IN of the shift register GOA16), and so on.
  • the gate driving circuit 300 further includes a plurality of start-up signal lines STV1 , STV2 and STV3 , and the start-up signal lines STV1 , STV2 and STV3 are connected to the driving units DU1 , DU2 and DU3 in one-to-one correspondence.
  • Each enable signal line is connected to the cascade input terminal of the first d-stage shift register unit in the corresponding driving unit.
  • the enable signal line STV1 is connected to the cascade input terminals (ie, the input terminals IN of GOA1, GOA4, GOA7 and GOA10) of the first 4-stage shift register units 320_1, 320_2, 320_3 and 320_4 in the driving unit DU1.
  • the gate driving circuit 300 further includes K clock signal lines, eg, clock signal lines CLK1 to CLK8.
  • the clock signal lines CLK1 to CLK8 are connected to clock signal terminals of the plurality of shift register units in each of the drive units DU1, DU2, and DU3.
  • the shift register units in each drive unit may be divided into at least one group, each group including K shift register units connected in cascade, the first shift register and the third shift register of the kth shift register unit
  • the clock signal terminal of is connected to the kth clock signal line, where k is an integer and 1 ⁇ k ⁇ K.
  • every 8 shift register units are grouped into one group, wherein the first group includes the cascade-connected shift register units 320_1 to 320_8.
  • the clock signal terminals CK of the first shift register GOA1 and the third shift register GOA3 in the first shift register unit 320_1 are connected to the first clock signal line CLK1, and the first shift register in the second shift register unit 320_2
  • the clock signal terminals CK of GOA4 and the third shift register GOA6 are connected to the second clock signal line CLK2
  • the clock signal terminals CK of the first shift register GOA7 and the third shift register GOA9 in the third shift register unit 320_3 are connected to to the third clock signal line CLK3, and so on.
  • the clock signal terminal of the second shift register of the kth shift register unit is connected to the k+dth clock signal line in the case of k ⁇ 2/K, and is connected to the k-dth clock signal line in the case of 2/K ⁇ k ⁇ K clock signal line.
  • the clock signal terminal CK of the second shift register GOA2 of the first shift register unit 320_1 is connected to the fifth clock signal line CLK5, and the clock signal terminal CK of the second shift register GOA5 of the second shift register unit 320_2 is connected to The sixth clock signal line CLK6, the clock signal terminal CK of the second shift register GOA8 of the third shift register unit 320_3 is connected to the seventh clock signal line CLK7, the second shift register GOA11 of the fourth shift register unit 320_4.
  • the clock signal terminal CK is connected to the eighth clock signal line CLK8, the clock signal terminal CK of the second shift register GOA14 of the fifth shift register unit 320_5 is connected to the first clock signal line CLK1, and so on.
  • the K clock signals may be respectively applied to the K clock signal lines in one of multiple resolution modes, and an enable signal may be applied to at least one enable signal line of the plurality of enable signal lines.
  • the applied activation signal enables the driving unit connected to the at least one activation signal line to activate, and the plurality of shift registers in the activated driving unit generate output signals according to the clock signals on the K clock signal lines.
  • the driving method of the gate driving circuit 300 described above will be described below with reference to FIGS. 20 to 23 .
  • the following description will be given by taking the driving unit DU1 connected to the start signal line STV1 as an example.
  • FIG. 20 shows a signal timing diagram of the gate driving circuit of FIG. 19 in the first resolution mode.
  • first clock signals on the clock signal lines CLK1 to CLK8 may be periodic signals with a duty cycle of 50%, and the active level duration in each signal period is 4H, wherein the k+1 first clock signal is relative to the kth
  • the first clock signal is shifted by H, where H represents the unit scan time.
  • the first clock signal on the second clock signal line CLK2 is shifted by H with respect to the first clock signal on the first clock signal line CLK1, and the first clock signal on the third clock signal line CLK3 is shifted with respect to the second clock signal line
  • the first clock signal on CLK2 is shifted by H, and so on.
  • the active level duration of the first enable signal may be 4H.
  • the shift registers GOA1, GOA2 and GOA3 in the first shift register unit 320_1 are generated based on the first clock signal on the first clock signal line CLK1, the fifth clock signal line CLK5 and the first clock signal line CLK1, respectively Output signals G1, G2 and G3, wherein output signal G2 is shifted by 4H relative to output signal G1 and output signal G3 is shifted by 4H relative to output signal G2.
  • the shift registers GOA4, GOA5 and GOA6 in the second shift register unit 320_2 generate output signals G4, GOA5 and GOA6 based on the first clock signals on the second clock signal line CLK2, the sixth clock signal line CLK6 and the second clock signal line CLK2, respectively.
  • G5 and G6 where output signal G4 is shifted by H relative to output signal G1, output signal G5 is shifted by 4H relative to output signal G4, and output signal G6 is shifted by 4H relative to output signal G5.
  • the shift registers GOA7, GOA8 and GOA9 in the third shift register unit 320_3 generate output signals G7, GOA8 and GOA9 based on the first clock signals on the third clock signal line CLK3, the seventh clock signal line CLK7 and the third clock signal line CLK3, respectively.
  • G8 and G9 where output signal G7 is shifted by H relative to output signal G4, output signal G8 is shifted by 4H relative to output signal G7, output signal G9 is shifted by 4H relative to output signal G8, and so on.
  • FIG. 21 shows a signal timing diagram of the gate driving circuit of FIG. 19 in the second resolution mode.
  • the second clock signals are respectively applied to the clock signal lines CLK1 to CLK8, and the second start signal is applied to the start signal line STV1.
  • the second clock signals on the clock signal lines CLK1 to CLK8 may also be periodic signals with a duty cycle of 50%. Different from the first clock signal, the active level duration in each signal period is 2H. The active level duration of the second start signal may be 2H.
  • the second clock signals on the clock signal lines CLK1 and CLK2 are synchronized, the second clock signals on the clock signal lines CLK3 and CLK4 are synchronized, the second clock signals on the clock signal lines CLK5 and CLK6 are synchronized, and the second clock signals on the clock signal lines CLK7 and CLK8 are synchronized.
  • the second clock signal is synchronized.
  • the second clock signals on the clock signal lines CLK3 and CLK4 are shifted by H relative to the second clock signals on the clock signal lines CLK1 and CLK2.
  • the second clock signals on clock signal lines CLK5 and CLK6 are shifted by H relative to the second clock signals on clock signal lines CLK3 and CLK4.
  • the second clock signal on clock signal lines CLK7 and CLK8 is shifted by H relative to the second clock signal on clock signal lines CLK5 and CLK6, and so on.
  • the shift registers GOA1, GOA2 and GOA3 in the first shift register unit 320_1 are generated based on the first clock signal on the first clock signal line CLK1, the fifth clock signal line CLK5 and the first clock signal line CLK1, respectively Output signals G1, G2 and G3, wherein output signal G2 is shifted by 2H relative to output signal G1 and output signal G3 is shifted by 2H relative to output signal G2.
  • the shift registers GOA4, GOA5 and GOA6 in the second shift register unit 320_2 generate output signals G4, GOA5 and GOA6 based on the first clock signals on the second clock signal line CLK2, the sixth clock signal line CLK6 and the second clock signal line CLK2, respectively.
  • G5 and G6 where output signal G4 is synchronized with output signal G1, output signal G5 is shifted by 2H relative to output signal G4, and output signal G6 is shifted by 2H relative to output signal G5.
  • the shift registers GOA7, GOA8 and GOA9 in the third shift register unit 320_3 generate output signals G7, GOA8 and GOA9 based on the first clock signals on the third clock signal line CLK3, the seventh clock signal line CLK7 and the third clock signal line CLK3, respectively.
  • G8 and G9 where output signal G7 is shifted by H relative to output signal G4, output signal G8 is shifted by 2H relative to output signal G7, output signal G9 is shifted by 2H relative to output signal G8, and so on.
  • FIG. 22 shows a signal timing diagram of the gate driving circuit of FIG. 19 in the third resolution mode.
  • third clock signals are respectively applied to the clock signal lines CLK1 to CLK8, and a third start signal is applied to the start signal line STV1.
  • the third clock signal is also a periodic signal with a duty cycle of 50%. Different from the first clock signal, the duration of the active level in the signal period of the third clock signal is H.
  • the third clock signals on the clock signal lines CLK1 to CLK8 may be divided into M groups, eg, 2 groups, wherein the first group includes the third clock signals on the clock signal lines CLK1 to CLK4, and the second group includes the clock signal lines CLK5 to CLK8 on the third clock signal.
  • the third clock signals on the clock signal lines CLK1 to CLK4 are synchronized with each other, the third clock signals on the clock signal lines CLK5 to CLK8 are synchronized with each other, and the third clock signals on the clock signal lines CLK5 to CLK8 are synchronized with each other with respect to the clock signal lines CLK1 to CLK4 is shifted by H on the third clock signal.
  • the active level duration of the third enable signal may be H.
  • the shift registers GOA1, GOA2 and GOA3 in the first shift register unit 320_1 are generated based on the first clock signal on the first clock signal line CLK1, the fifth clock signal line CLK5 and the first clock signal line CLK1, respectively Output signals G1, G2 and G3, wherein output signal G2 is shifted by H relative to output signal G1 and output signal G3 is shifted by H relative to output signal G2.
  • the shift registers GOA4, GOA5 and GOA6 in the second shift register unit 320_2 generate output signals G4, GOA5 and GOA6 based on the first clock signals on the second clock signal line CLK2, the sixth clock signal line CLK6 and the second clock signal line CLK2, respectively.
  • G5 and G6 where output signal G4 is synchronized with output signal G1, output signal G5 is shifted by H relative to output signal G4, and output signal G6 is shifted by H relative to output signal G5.
  • the shift registers GOA7, GOA8 and GOA9 in the third shift register unit 320_3 generate output signals G7, GOA8 and GOA9 based on the first clock signals on the third clock signal line CLK3, the seventh clock signal line CLK7 and the third clock signal line CLK3, respectively.
  • G8 and G9 where output signal G7 is synchronized with output signal G4, output signal G8 is shifted by H relative to output signal G7, and output signal G9 is shifted by H relative to output signal G8.
  • the shift registers GOA10, GOA11, and GOA12 in the fourth shift register unit 320_4 generate output signals G10, G10, GOA10, GOA11, and GOA12 based on the first clock signals on the fourth clock signal line CLK4, the eighth clock signal line CLK8, and the fourth clock signal line CLK4, respectively.
  • G11 and G12 where output signal G10 is synchronized with output signal G7, output signal G11 is shifted by H relative to output signal G10, and output signal G12 is shifted by H relative to output signal G11.
  • FIG. 23 shows a timing diagram of a start-up signal of the gate drive circuit of FIG. 19 .
  • the first drive unit DU1 is connected to the first start signal line STV1
  • the second drive unit DU2 is connected to the second start signal line STV2
  • the third drive unit DU3 is connected to the third start signal line STV3 connection.
  • the second driving unit DU2 is controlled to operate in the first resolution mode.
  • the clock signal may be applied to the clock signal lines CLK1 to CLK8 and the first start signal may be applied to the second start signal line STV2 as shown in FIG. 20 .
  • the second driving unit DU2 generates the output signals G(X+1), G(X+2 as shown in FIG. 20 according to the clock signals on the clock signal lines CLK1 to CLK8 in response to the start signal on the second start signal line STV2 ), ...G2X.
  • the first driving unit DU1 is controlled to operate in the second resolution mode or the third resolution mode.
  • a clock signal may be applied to the clock signal lines CLK1 to CLK8 and a second start signal may be applied to the first start signal line STV1 as shown in FIG. 21, and the first drive unit DU1 responds to the second start on the first start signal line STV1
  • the output signals G1, G2, G3, . . . as shown in FIG. 21 are generated according to the clock signals on the clock signal lines CLK1 to CLK8.
  • a clock signal may be applied to the clock signal lines CLK1 to CLK8 and a third start signal may be applied to the first start signal line STV1 as shown in FIG.
  • the first driving unit DU1 responds to the first start signal line STV1 on the The third enable signal to generate output signals G1, G2, G3, . . . GX as shown in FIG. 22 according to the clock signals on the clock signal lines CLK1 to CLK8.
  • the second driving unit DU2 is controlled again to operate in the first resolution mode.
  • the clock signal may be applied to the clock signal lines CLK1 to CLK8 and the first start signal may be applied to the second start signal line STV2 as shown in FIG. 20, and the second drive unit DU2 responds to the first start on the second start signal line STV2
  • the output signals G(X+1), G(X+2), . . . G2X shown in FIG. 20 are generated according to K clock signals on the clock signal lines CLK1 to CLK8.
  • the third driving unit DU3 is controlled to operate in the second resolution mode or the third resolution mode.
  • the clock signal may be applied to the clock signal lines CLK1 to CLK8 and the second start signal may be applied to the third start signal line STV3 as shown in FIG. 21, and the third drive unit DU3 responds to the second start on the third start signal line STV3
  • the output signals G(2X+1), G(2X+2), . . . G3X shown in FIG. 21 are generated according to the signals on the clock signal lines CLK1 to CLK8.
  • the clock signal may be applied to the clock signal lines CLK1 to CLK8 and the third start signal may be applied to the third start signal line STV3 as shown in FIG.
  • the third drive unit DU3 responds to the third start signal line STV3 on the third start signal line STV3.
  • the output signals G(2X+1), G(2X+2), . . . G3X shown in FIG. 22 are generated according to the third enable signal of the clock signal lines CLK1 to CLK8.
  • the driving unit DU2 drives the sub-pixels in the central area twice with a higher first resolution, while the driving units DU1 and DU3 drive the two sub-pixels with a lower second or third resolution.
  • the sub-pixels in the side area are respectively driven once for display.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Shift Register Type Memory (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

提供了一种栅极驱动电路（100）及其驱动方法和显示面板。栅极驱动电路（100）包括级联连接的多个驱动单元（DU1、DU2），每个驱动单元（DU1、DU2）包括：N个移位寄存器单元（120_1……120_8）；以及模式控制电路（110_1、110_2），与N个移位寄存器单元（120_1……120_8）连接，模式控制电路（110_1、110_2）被配置为接收针对该驱动单元（DU1、DU2）的控制信号（SW1、SW2），并在控制信号（SW1、SW2）的控制下以多个分辨率模式之一对N个移位寄存器单元（120_1……120_8）进行连接。

Description

栅极驱动电路及其驱动方法和显示面板 技术领域
本公开涉及显示技术领域，具体涉及一种栅极驱动电路、栅极驱动电路的驱动方法和显示面板。
背景技术
在显示技术中，通常利用栅极驱动电路来驱动多个子像素进行显示。例如栅极驱动电路产生栅极驱动信号，栅极驱动信号被提供给多个子像素，使得子像素开启。向开启的子像素施加数据信号，以使驱动子像素发光。栅极驱动电路通常包括级联连接的多个移位寄存器，以产生顺次移位的多个输出信号作为栅极驱动信号。然而传统技术无法灵活控制显示面板上不同区域的显示分辨率。
发明内容
根据本公开的第一方面，提供了一种栅极驱动电路，包括级联连接的多个驱动单元，每个驱动单元包括：
N个移位寄存器单元；以及
模式控制电路，与所述N个移位寄存器单元连接，所述模式控制电路被配置为接收针对该驱动单元的控制信号，并在所述控制信号的控制下以多个分辨率模式之一对所述N个移位寄存器单元进行连接。
例如，所述多个分辨率模式包括第一分辨率模式、第二分辨率模式和第三分辨率模式，所述模式控制电路被配置为：
在第一分辨率模式下，将所述N个移位寄存器单元级联连接；
在第二分辨率模式下，将所述N个移位寄存器单元分为M组，将所述M组级联连接，并且将每组中的移位寄存器单元并行连接；
在第三分辨率模式下，将所述N个移位寄存器单元并行连接。
例如，N＝4，M＝2，所述N个移位寄存器单元包括第一移位寄存器单元、第二移位寄存器单元、第三移位寄存器单元和第四移位寄存器单元，每个移位寄存器单元具有级联输入端和第一级联输出端，所述模式控制电路被配置为：
在第一分辨率模式下，将第n移位寄存器单元的第一级联输出端与第n+1移位寄存器单元的级联输入端连接，并将所述第n移位寄存器单元的级联输入端与所述第n+1移位寄存器单元的级联输入端断开连接，其中1≤n≤N-1；
在第二分辨率模式下，将第一移位寄存器单元的第一级联输出端与第二移位寄存器单元的级联输入端断开连接，将第二移位寄存器单元的第一级联输出端与第三移位寄存器单元的级联输入端连接，将第三移位寄存器单元的第一级联输出端与第四移位寄存器单元的级联输入端断开连接，将第一移位寄存器单元的级联输入端与第二移位寄存器单元的级联输入端连接，并且将第三移位寄存器单元的级联输入端与第四移位寄存器单元的级联输入端连接；以及
在第三分辨率模式下，将第n移位寄存器单元的第一级联输出端与第n+1移位寄存器单元的级联输入端断开连接，并将所述第n移位寄存器单元的级联输入端与所述第n+1移位寄存器单元的级联输入端连接。
例如，所述第一移位寄存器单元、第二移位寄存器单元、第三移位寄存器单元和第四移位寄存器单元各自还具有复位端和第二级联输出端，所述模式控制电路还被配置为：
在第一分辨率模式下，将第n移位寄存器单元的复位端与第n+1移位寄存器单元的第二级联输出端连接，并将所述第n移位寄存器单元的复位端与所述第n+1移位寄存器单元的复位端断开连接，
在第二分辨率模式下，将第一移位寄存器单元的复位端与第二移位寄存器单元的第二级联输出端断开连接，将第二移位寄存器单元的复位端与第三移位寄存器单元的第二级联输出端连接，将第三移位寄存器单元的复位端与第四移位寄存器单元的第二级联输出端断开连接，将第一移位寄存器单元的复位端与第二移位寄存器单元的复位端连接，将第二移位寄存器单元的复位端与第三移位寄存器单元的复位端断开连接，并且将第三移位寄存器单元的复位端与第四移位寄存器单元的复位端连接；以及
在第三分辨率模式下，将第n移位寄存器单元的复位端与第n+1移位寄存器单元的第二级联输出端断开连接，并将所述第n移位寄存器单元的复位端与所述第n+1移位寄存器单元的复位端连接。
例如，所述控制信号包括第一控制信号、第二控制信号、第三控制信号和第四控制信号，所述模式控制电路包括：
第一晶体管，第一晶体管的栅极连接为接收第一控制信号，第一晶体管的第一极 连接第一移位寄存器单元的第一级联输出端，第一晶体管的第二极连接第二移位寄存器单元的级联输入端；
第二晶体管，第二晶体管的栅极连接为接收第二控制信号，第二晶体管的第一极连接第一移位寄存器单元的级联输入端，第二晶体管的第二极连接第二移位寄存器单元的级联输入端；
第三晶体管，第三晶体管的栅极连接为接收第三控制信号，第三晶体管的第一极连接第二移位寄存器单元的第一级联输出端，第三晶体管的第二极连接第三移位寄存器单元的级联输入端；
第四晶体管，第四晶体管的栅极连接为接收第四控制信号，第四晶体管的第一极连接第一移位寄存器单元的级联输入端，第四晶体管的第二极连接第三移位寄存器单元的级联输入端；
第五晶体管，第五晶体管的栅极连接为第一控制信号，第五晶体管的第一极连接第三移位寄存器单元的第一级联输出端，第五晶体管的第二极连接第四移位寄存器单元的级联输入端；以及
第六晶体管，第六晶体管的栅极连接为接收第二控制信号，第六晶体管的第一极连接第三移位寄存器单元的级联输入端，第六晶体管的第二极连接第四晶体管的级联输入端。
例如，所述控制信号还包括第五控制信号，所述模式控制电路还包括：
第七晶体管，第七晶体管的栅极连接为接收第一控制信号，第七晶体管的第一极连接第一移位寄存器单元的复位端，第七晶体管的第二极连接第二移位寄存器单元的第二级联输出端；
第八晶体管，第八晶体管的栅极连接为接收第五控制信号，第八晶体管的第一极连接第一移位寄存器单元的复位端，第八晶体管的第二极连接第二移位寄存器单元的复位端；
第九晶体管，第九晶体管的栅极连接为接收第三控制信号，第九晶体管的第一极连接第二移位寄存器单元的复位端，第九晶体管的第二极连接第三移位寄存器单元的第二级联输出端；
第十晶体管，第十晶体管的栅极连接为接收第四控制信号，第十晶体管的第一极连接第二移位寄存器单元的复位端，第十晶体管的第二极连接第三移位寄存器单元的复位端；
第十一晶体管，第十一晶体管的栅极连接为接收第一控制信号，第十一晶体管的第一极连接第三移位寄存器单元的复位端，第十一晶体管的第二极连接第四移位寄存器单元的第二级联输出端；以及
第十二晶体管，第十二晶体管的栅极连接为接收第二控制信号，第十二晶体管的第一极连接第三移位寄存器单元的复位端，第十二晶体管的第二极连接第四移位寄存器单元的复位端。
例如，第i级驱动单元中的第N移位寄存器单元的第一级联输出端与第i+1级驱动单元中的第一移位寄存器单元的级联输入端连接。
例如，第i级驱动单元中的第N移位寄存器单元的复位端与第i+1级驱动单元中的第一移位寄存器单元的第二级联输出端连接。
例如，所述多个驱动单元被划分为多组，每组驱动单元连接一组控制信号线以接收针对该组驱动单元的控制信号。
例如，每个移位寄存器单元包括第一移位寄存器、第二移位寄存器和第三移位寄存器，其中，
所述第一移位寄存器的输入端作为所述移位寄存器单元的级联输入端，所述第一移位寄存器的输出端作为所述移位寄存器单元的第二级联输出端；
所述第二移位寄存器的输入端与所述第一移位寄存器的输出端连接；并且
所述第三移位寄存器的输入端与所述第二移位寄存器的输出端连接，所述第三移位寄存器的输出端作为所述移位寄存器单元的第一级联输出端。
例如，所述第一移位寄存器、第二移位寄存器和第三移位寄存器中的每一个包括：
输入子电路，连接所述移位寄存器的输入端和上拉节点，并且被配置为将输入端的信号提供至上拉节点；
输出子电路，连接所述上拉节点、所述移位寄存器的时钟信号端和输出端，并且被配置为在所述上拉节点的电位的控制下将所述时钟信号端的信号提供至所述输出端；
控制子电路，连接所述上拉节点、所述输出端和所述移位寄存器的下拉节点，并且被配置为基于所述上拉节点的电位控制所述下拉节点的电位，并在所述下拉节点的电位控制下下拉所述输出端的电位。
例如，所述第一移位寄存器、第二移位寄存器和第三移位寄存器中的每一个还包括：
复位子电路，连接所述上拉节点和所述移位寄存器的复位端，并且被配置为根据 所述复位端的复位信号将上拉节点复位，其中移位寄存器单元中第三移位寄存器的复位端作为所述移位寄存器单元的复位端。
根据本公开的第二方面，提供了根据本公开第一方面的栅极驱动电路的驱动方法，包括：
多个驱动单元中每个驱动单元的模式控制电路接收针对该驱动单元的控制信号，并在所述控制信号的控制下以多个分辨率模式之一对所述N个移位寄存器单元进行连接，
每个驱动单元中连接后的N个移位寄存器单元产生输出信号。
例如，所述多个分辨率模式包括第一分辨率模式、第二分辨率模式和第三分辨率模式，其中，
在第一分辨率模式下，模式控制电路将N个移位寄存器单元级联连接，所述N个移位寄存器单元产生顺序移位的输出信号；
在第二分辨率模式下，所述模式控制电路将所述N个移位寄存器单元分为M组，将所述M组级联连接，并且将每组中的移位寄存器单元并行连接，每组中的移位寄存器单元并行地产生输出信号，且第m+1组移位寄存器单元产生的一组输出信号相对于第m组移位寄存器单元产生的一组输出信号而移位，其中m为整数且1≤m≤M-1；
在第三分辨率模式下，所述模式控制电路将所述N个移位寄存器单元并行连接，所述N个移位寄存器单元并行地产生输出信号。
例如，N＝4，M＝2，所述N个移位寄存器单元包括第一移位寄存器单元、第二移位寄存器单元、第三移位寄存器单元和第四移位寄存器单元，其中，
在第一分辨率模式下，所述模式控制电路将第n移位寄存器单元的第一级联输出端与第n+1移位寄存器单元的级联输入端连接，并将所述第n移位寄存器单元的级联输入端与所述第n+1移位寄存器的级联输入端断开连接，其中1≤n≤N-1；
在第二分辨率模式下，所述模式控制电路将第一移位寄存器单元的第一级联输出端与第二移位寄存器单元的级联输入端断开连接，将第二移位寄存器单元的级联输入端与第一移位寄存器单元的级联输入端连接；将第二移位寄存器单元的第一级联输出端与第三移位寄存器单元的级联输入端连接，将第三移位寄存器单元的级联输入端与第二移位寄存器单元的级联输入端断开连接；并且将第三移位寄存器单元的第一级联输出端与第四移位寄存器单元的级联输入端断开连接，将第三移位寄存器单元的级联输入端与第四移位寄存器单元的级联输入端连接；以及
在第三分辨率模式下，模式控制电路将第n移位寄存器单元的第一级联输出端与第n+1移位寄存器单元的级联输入端断开连接，并将所述第n移位寄存器单元的级联输入端与所述第n+1移位寄存器单元的级联输入端连接。
例如，所述方法还包括：
在第一分辨率模式下，模式控制电路将第n移位寄存器单元的复位端与第n+1移位寄存器的第二级联输出端连接，并将所述第n移位寄存器单元的复位端与所述第n+1移位寄存器单元的复位端断开连接，
在第二分辨率模式下，模式控制电路将第一移位寄存器单元的复位端与第二移位寄存器单元的第二级联输出端断开连接，将第二移位寄存器单元的复位端与第三移位寄存器单元的第二级联输出端连接，模式控制电路将第三移位寄存器单元的复位端与第四移位寄存器单元的第二级联输出端断开连接，将第一移位寄存器单元的复位端与第二移位寄存器单元的复位端连接，并且将第三移位寄存器单元的复位端与第四移位寄存器单元的复位端连接；以及
在第三分辨率模式下，模式控制电路将第n移位寄存器单元的复位端与第n+1移位寄存器单元的第二级联输出端断开连接，并将所述第n移位寄存器单元的复位端与所述第n+1移位寄存器单元的复位端连接。
例如，所述模式控制电路包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管和第六晶体管，其中，
在第一分辨率模式下，第一控制信号和第三控制信号为第一电平，第二控制信号和第四控制信号为第二电平，第一晶体管、第三晶体管和第五晶体管导通，并且第二晶体管、第四晶体管和第六晶体管关断；
在第二分辨率模式下，第二控制信号和第三控制信号为第一电平，第一控制信号和第四控制信号为第二电平，第二晶体管、第三晶体管和第六晶体管导通，第一晶体管、第四晶体管和第五晶体管关断；以及
在第三分辨率模式下，第二控制信号和第四控制信号为第一电平，第一控制信号和第三控制信号为第二电平，第二晶体管、第四晶体管和第六晶体管导通，第一晶体管、第三晶体管和第五晶体管关断。
例如，所述模式控制电路还包括第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管和第十二晶体管，其中，
在第一分辨率模式下，第五控制信号为第二电平，第七晶体管、第九晶体管和第 十一晶体管导通，第八晶体管、第十晶体管和第十二晶体管关断；
在第二分辨率模式下，第五控制信号为第一电平，第八晶体管、第九晶体管和第十二晶体管导通，第七晶体管、第十晶体管和第十一晶体管关断；以及
在第三分辨率模式下，第五控制信号为第二电平，第十晶体管和第十二晶体管导通，第七晶体管、第八晶体管、第九晶体管和第十一晶体管关断。
根据本公开的第三方面，提供了一种栅极驱动电路，包括：
多个驱动单元，每个驱动单元包括级联连接的多个移位寄存器；
多条启动信号线，与所述多个驱动单元一一对应地连接，其中每条启动信号线连接至对应驱动单元中的第一级移位寄存器；
K条时钟信号线，与每个驱动单元中的多个移位寄存器连接，其中K为大于1的整数；以及
模式控制电路，与所述K条时钟信号线连接，所述模式控制电路被配置为接收K个初始时钟信号和控制信号，在所述控制信号的控制下以第一分辨率模式、第二分辨率模式和第三分辨率模式之一来基于所述K个初始时钟信号产生K个时钟信号，并将产生的K个时钟信号分别提供给所述K条时钟信号线。
例如，所述模式控制电路被配置为：
在第一分辨率模式下，基于所述K个初始时钟信号产生顺序移位的K个第一时钟信号；
在第二分辨率模式下，基于所述K个初始时钟信号产生分成2M组的K个第二时钟信号，每组中的多个第二时钟信号同步，第m+1组第二时钟信号相对于第m组第二时钟信号而移位；
在第三分辨率模式下，基于所述K个初始时钟信号产生分成M组的K个第三时钟信号，每组中的多个第三时钟信号同步，第m’+1组第三时钟信号相对于第m’组第三时钟信号而移位，其中M为大于1的整数，m和m’均为整数，1≤m≤2M-1，且1≤m’≤M-1。
例如，K＝8，M＝2，所述控制信号包括第一控制信号、第二控制信号、第三控制信号和第四控制信号，所述模式控制电路包括：
第一时钟输入端至第八时钟输入端，分别连接为接收8个初始时钟信号；
第一时钟输出端至第八时钟输出端，与8条时钟信号线一一对应地连接；
第一模式控制子电路，被配置为在第一控制信号的控制下，将第二时钟输入端与 第二时钟输出端连接，将第四时钟输入端与第四时钟输出端连接，将第七时钟输入端与第七时钟输出端连接，以及将第八时钟输入端与第八时钟输出端连接；
第二模式控制子电路，被配置为在第二控制信号的控制下，将第三时钟输入端与第三时钟输出端连接，以及将第六时钟输入端与第六时钟输出端连接；
第三模式控制子电路，被配置为在第三控制信号的控制下将第一时钟输出端与第二时钟输出端连接，将第三时钟输出端与第四时钟输出端连接，将第五时钟输出端与第六时钟输出端连接，以及将第七时钟输出端与第八时钟输出端连接；
第四模式控制子电路，被配置为在第四控制信号的控制下将第二时钟输出端与第三时钟输出端连接，以及将第六时钟输出端与第七时钟输出端连接。
例如，所述第一模式控制子电路包括：
第一晶体管，第一晶体管的栅极连接为接收第一控制信号，第一晶体管的第一极连接第二时钟输入端，第一晶体管的第二极连接第二时钟输出端；
第二晶体管，第二晶体管的栅极连接为接收第一控制信号，第二晶体管的第一极连接第四时钟输入端，第二晶体管的第二极连接第四时钟输出端；
第三晶体管，第三晶体管的栅极连接为接收第一控制信号，第三晶体管的第一极连接第七时钟输入端，第三晶体管的第二极连接第七时钟输出端；以及
第四晶体管，第四晶体管的栅极连接为接收第一控制信号，第四晶体管的第一极连接第八时钟输入端，第四晶体管的第二极连接第八时钟输出端。
例如，所述第二模式控制子电路包括：
第五晶体管，第五晶体管的栅极连接为接收第二控制信号，第五晶体管的第一极连接第三时钟输入端，第二极连接第三时钟输出端；以及
第六晶体管，第六晶体管的栅极连接为接收第二控制信号，第六晶体管的第一极连接第六时钟输入端，第六晶体管的第二极连接第六时钟输出端。
例如，所述第三模式控制子电路包括：
第七晶体管，第七晶体管的栅极连接为接收第三控制信号，第七晶体管的第一极连接第一时钟输出端，第二极连接第二时钟输出端；
第八晶体管，第八晶体管的栅极连接为接收第三控制信号，第八晶体管的第一极连接第三时钟输出端，第二极连接第四时钟输出端；
第九晶体管，第九晶体管的栅极连接为接收第三控制信号，第九晶体管的第一极连接第五时钟输出端，第二极连接第六时钟输出端；以及
第十晶体管，第十晶体管的栅极连接为接收第三控制信号，第十晶体管的第一极连接第七时钟输出端，第二极连接第八时钟输出端。
例如，所述第四模式控制子电路包括：
第十一晶体管，第十一晶体管的栅极连接为接收第四控制信号，第十一晶体管的第一极连接第二时钟输出端，第二极连接第三时钟输出端；以及
第十二晶体管，第十二晶体管的栅极连接为接收第四控制信号，第十二晶体管的第一极连接第六时钟输出端，第二极连接第七时钟输出端。
例如，在每个驱动单元中，第n级移位寄存器的输出端连接至第n+1级移位寄存器的输入端，第n+1级移位寄存器的输出端连接至第n级移位寄存器的复位端，其中n为大于或等于1的整数；并且
每个驱动单元中的多个移位寄存器分为至少一组，每组包括级联连接的K个移位寄存器，所述K个移位寄存器的时钟信号端与所述K条时钟信号线一一对应地连接。
根据本公开的第四方面，提供了一种根据本公开第三方面的栅极驱动电路的驱动方法，包括：
模式控制电路在控制信号的控制下以多种分辨率模式之一来基于所述K个初始时钟信号产生K个时钟信号，并将产生的K个时钟信号分别提供给所述K条时钟信号线；以及
向多条启动信号线中的至少一条启动信号线施加启动信号，以启动与所述至少一条启动信号线连接的驱动单元，被启动的驱动单元中的多个移位寄存器根据所述K条时钟信号线上的时钟信号来产生输出信号。
例如，所述多个分辨率模式包括第一分辨率模式、第二分辨率模式和第三分辨率模式，其中，
在第一分辨率模式下，模式控制电路基于K个初始时钟信号产生顺序移位的K个第一时钟信号并分别提供给K条时钟信号线；
在第二分辨率模式下，模式控制电路基于K个初始时钟信号产生K个第二时钟信号并分别提供给所述K条时钟信号线，所述K个第二时钟信号分成2M组，每组中的多个第二时钟信号同步，第m+1组第二时钟信号相对于第m组第二时钟信号而移位；
在第三分辨率模式下，模式控制电路基于K个初始时钟信号产生K个第三时钟信号并分别提供给所述K条时钟信号线，所述K个第三时钟信号分成M组，每组中的多个第三时钟信号同步，第m’+1组第三时钟信号相对于第m’组第三时钟信号而移位， 其中M为大于1的整数，m和m’均为整数，1≤m≤2M-1，且1≤m’≤M-1。
例如，K＝8，M＝2，其中，
在第一分辨率模式下，第一模式控制子电路将第二时钟输入端与第二时钟输出端连接，将第四时钟输入端与第四时钟输出端连接，将第七时钟输入端与第七时钟输出端连接，以及将第八时钟输入端与第八时钟输出端连接；第二模式控制子电路将第三时钟输入端与第三时钟输出端连接，以及将第六时钟输入端与第六时钟输出端连接；
在第二分辨率模式下，第二模式控制子电路将第三时钟输入端与第三时钟输出端连接，以及将第六时钟输入端与第六时钟输出端连接；第三模式控制子电路将第一时钟输出端与第二时钟输出端连接，将第三时钟输出端与第四时钟输出端连接，将第五时钟输出端与第六时钟输出端连接，以及将第七时钟输出端与第八时钟输出端连接；
在第三分辨率模式下，第三模式控制子电路将第一时钟输出端与第二时钟输出端连接，将第三时钟输出端与第四时钟输出端连接，将第五时钟输出端与第六时钟输出端连接，以及将第七时钟输出端与第八时钟输出端连接；第四模式控制子电路将第二时钟输出端与第三时钟输出端连接，以及将第六时钟输出端与第七时钟输出端连接。
例如，在第一分辨率模式下，第一控制信号和第二控制信号为第一电平，第三控制信号和第四控制信号为第二电平，第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管和第六晶体管导通，第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管和第十二晶体管关断；
在第二分辨率模式下，第一控制信号和第四控制信号为第二电平，第二控制信号和第三控制信号为第一电平，第一晶体管、第二晶体管、第三晶体管、第四晶体管、第十一晶体管和第十二晶体管关断，第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管和第十晶体管导通；
在第三分辨率模式下，第一控制信号和第二控制信号为第二电平，第三控制信号和第四控制信号为第一电平，第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管和第六晶体管关断，第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管和第十二晶体管导通。
例如，所述K个初始时钟信号是占空比为50％的周期信号，其中第k+1初始时钟信号相对于第k初始时钟信号移位单位扫描时间，每个初始时钟信号的有效电平持续时间为4倍单位扫描时间。
例如，所述K个初始时钟信号是占空比为12.5％的周期信号，其中第k+1初始时 钟信号相对于第k初始时钟信号移位单位扫描时间，每个初始时钟信号的有效电平持续时间为单位扫描时间。
根据本公开的第五方面，提供了一种栅极驱动电路，包括：
多个驱动单元，每个驱动单元包括级联连接的多个移位寄存器单元，在所述多个移位寄存器单元中，第n级移位寄存器单元的级联输出端连接至第n+d级移位寄存器单元的级联输入端；
多条启动信号线，与所述多个驱动单元一一对应地连接，其中每条启动信号线连接至对应驱动单元中的前d级移位寄存器单元的级联输入端，其中n和d均为大于或等于1的整数；
K条时钟信号线，与每个驱动单元中的多个移位寄存器单元的时钟信号端连接，其中K＝2d。
例如，每个移位寄存器单元包括第一移位寄存器、第二移位寄存器和第三移位寄存器，其中，
第一移位寄存器的输入端作为移位寄存器单元的级联输入端，第一移位寄存器的输出端连接至第二移位寄存器的输入端，第二移位寄存器的输出端连接至第三移位寄存器的输入端，第三移位寄存器的输出端作为所述移位寄存器单元的级联输出端；并且
第一移位寄存器的时钟信号端、第二移位寄存器的时钟信号端和第三移位寄存器的时钟信号端作为所述移位寄存器单元的时钟信号端。
例如，每个驱动单元中的多个移位寄存器单元分为至少一组，每组包括级联连接的K个移位寄存器单元，在所述K个移位寄存器单元中：
第k移位寄存器单元的第一移位寄存器和第三移位寄存器的时钟信号端连接至第k时钟信号线，其中k为整数，且1≤k≤K；
所述第k移位寄存器单元的第二移位寄存器的时钟信号端在k≤2/K的情况下连接至第k+d时钟信号线，在2/K＜k≤K的情况下连接至第k-d时钟信号线。
例如，所述第一移位寄存器、第二移位寄存器和第三移位寄存器中的每一个包括：
输入子电路，连接所述移位寄存器的输入端和上拉节点，并且被配置为将输入端的信号提供至上拉节点；
输出子电路，连接所述上拉节点、所述移位寄存器的时钟信号端和输出端，并且被配置为在所述上拉节点的电位的控制下将所述时钟信号端的信号提供至所述输出端；
控制子电路，连接所述上拉节点、所述输出端和所述移位寄存器的下拉节点，并且被配置为基于所述上拉节点的电位控制所述下拉节点的电位，并在所述下拉节点的电位控制下下拉所述输出端的电位。
例如，K＝8，d＝4。
根据本公开的第六方面，提供了一种根据本公开第五方面的栅极驱动电路的驱动方法，包括：
以多种分辨率模式之一，向K条时钟信号线分别施加K个时钟信号并且向所述多条启动信号线中的至少一条启动信号线施加启动信号，
所施加的启动信号使得与所述至少一条启动信号线连接的驱动单元启动，启动的驱动单元中的多个移位寄存器根据所述K条时钟信号线上的时钟信号来产生输出信号。
例如，在第一分辨率模式下，向所述K条时钟信号线分别施加顺次移位的K个第一时钟信号，并且向所述多条启动信号线中的至少一条启动信号线施加第一启动信号；
在第二分辨率模式下，向所述K条时钟信号线分别施加K个第二时钟信号，并且向所述多条启动信号线中的至少一条启动信号线施加第二启动信号，其中所述K个第二时钟信号分为2M组，每组中的多个第二时钟信号同步，第m+1组第二时钟信号相对于第m组第二时钟信号而移位；
在第三分辨率模式下，向所述K条时钟信号线分别施加K个第三时钟信号，并且向所述多条启动信号线中的至少一条启动信号线施加第三启动信号，其中所述K个第三时钟信号分为M组，每组中的多个第三时钟信号同步，第m’+1组第三时钟信号相对于第m’组第三时钟信号而移位，其中M为大于1的整数，m和m’均为整数，1≤m≤2M-1，且1≤m’≤M-1。
例如，第一时钟信号、第二时钟信号和第三时钟信号均为占空比50％的周期信号，其中，
第一时钟信号的信号周期内的有效电平持续时间为4H，其中第k+1个第一时钟信号相对于第k个第一时钟信号而移位H，其中H表示单位扫描时间；
第二时钟信号的信号周期内的有效电平持续时间为2H，其中m+1组第二时钟信号相对于第m组第二时钟信号而移位H；
第三时钟信号的信号周期内的有效电平持续时间为H，其中m’+1组第三时钟信号相对于第m’组第三时钟信号而移位H。
例如，第一启动信号的有效电平持续时间为4H，第二启动信号的有效电平持续时 间为2H，第三启动信号的有效电平持续时间为H。
例如，所述多个驱动单元包括第一驱动单元、第二驱动单元和第三驱动单元，所述多条启动信号线包括分别与所述第一驱动单元、第二驱动单元和第三驱动单元连接的第一启动信号线、第二启动信号线和第三启动信号线，其中，
在第一时段，以第一分辨率模式向K条时钟信号线施加K个时钟信号并且向第二启动信号线施加第一启动信号，第二驱动单元响应于所施加的第一启动信号来根据所施加的K个时钟信号产生输出信号；
在第二时段，以第二分辨率模式或第三分辨率模式向K条时钟信号线施加K个时钟信号并且向第一启动信号线施加第二启动信号或第三启动信号，第一驱动单元响应于所施加的第二启动信号或第三启动信号来根据所施加的K个时钟信号产生输出信号；
在第三时段，以第一分辨率模式向K条时钟信号线施加K个时钟信号并且向第二启动信号线施加第一启动信号，第二驱动单元响应于所施加的第一启动信号来根据所施加的K个时钟信号产生输出信号；
在第四时段，以第二分辨率模式或第三分辨率模式向K条时钟信号线施加K个时钟信号并且向第三启动信号线施加第三启动信号，第三驱动单元响应于所施加的第三启动信号来根据所施加的K个时钟信号产生输出信号。
例如，K＝8，M＝2。
根据本公开的第七方面，提供了一种显示面板，包括上述栅极驱动电路。
附图说明
图1示出了根据本公开实施例的显示面板的示意图。
图2A示出了根据本公开一实施例的移位寄存器的电路图。
图2B示出了根据本公开另一实施例的移位寄存器的电路图。
图3示出了根据本公开一实施例的栅极驱动电路的框图。
图4示出了图3的栅极驱动电路的示例结构图。
图5A示出了图4的栅极驱动电路在第一分辨率模式下的等效示意图。
图5B示出了图4的栅极驱动电路在第一分辨率模式下的信号时序图。
图6A示出了图4的栅极驱动电路在第二分辨率模式下的等效示意图。
图6B示出了图4的栅极驱动电路在第二分辨率模式下的信号时序图。
图7A示出了图4的栅极驱动电路在第三分辨率模式下的等效示意图。
图7B示出了图4的栅极驱动电路在第三分辨率模式下的信号时序图。
图8A示出了图4的栅极驱动电路在第二分辨率和第三分辨率模式下的等效示意图。
图8B示出了图4的栅极驱动电路在第二分辨率和第三分辨率模式下的信号时序图。
图9示出了图3的栅极驱动电路的另一示例结构图。
图10示出了根据本公开另一实施例的栅极驱动电路的结构图。
图11示出了图10的栅极驱动电路中的模式控制电路的示例电路图。
图12示出了图10的栅极驱动电路接收的初始时钟信号的时序图。
图13示出了图10的栅极驱动电路在第一分辨率模式下的信号时序图。
图14示出了图10的栅极驱动电路在第二分辨率模式下的信号时序图。
图15示出了图10的栅极驱动电路在第三分辨率模式下的信号时序图。
图16示出了图10的栅极驱动电路在第一分辨率、第二分辨率和第三分辨率模式下的信号时序图的一个示例。
图17示出了图10的栅极驱动电路在第一分辨率、第二分辨率和第三分辨率模式下的信号时序图的另一示例。
图18示出了根据本公开又一实施例的栅极驱动电路的框图。
图19示出了图18的栅极驱动电路的示例结构图。
图20示出了图19的栅极驱动电路在第一分辨率模式下的信号时序图。
图21示出了图19的栅极驱动电路在第二分辨率模式下的信号时序图。
图22示出了图19的栅极驱动电路在第三分辨率模式下的信号时序图。
图23示出了图19的栅极驱动电路的启动信号的时序图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部。基于所描述的本公开实施例，本领域普通技术人员在无需创造性劳动的前提下获得的所有其他实施例都属于本公开保护的范围。应注意，贯穿附图，相同的元素由相同或相近的附图标记来表示。在以下描述中，一些具体实施例仅用于描述目的，而不应该理解为对本公开有任何限制，而只是本公开实施例的示例。在可能导致对本公开的理解造成混淆时，将省略常规结构或配置。应注意，图中各部件的形状和尺寸不反映真实大小和比例，而仅示意本公开实施例的内容。
除非另外定义，本公开实施例使用的技术术语或科学术语应当是本领域技术人员所理解的通常意义。本公开实施例中使用的“第一”、“第二”以及类似词语并不表示任何顺序、数量或重要性，而只是用于区分不同的组成部分。
此外，在本公开实施例的描述中，术语“相连”或“连接至”可以是指两个组件直接连接，也可以是指两个组件之间经由一个或多个其他组件相连。此外，这两个组件可以通过有线或无线方式相连或相耦合。
此外，在本公开实施例的描述中，术语“第一电平”和“第二电平”仅用于区别两个电平的幅度不同。例如，下文中以“第一电平”为高电平、“第二电平”为低电平为例进行描述。本领域技术人员可以理解，本公开不局限于此。
本公开实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。优选地，本公开实施例中使用的薄膜晶体管可以是氧化物半导体晶体管或低温多晶硅(LTPS，Low Temperature Poly-silicon)薄膜晶体管。由于这里采用的薄膜晶体管的源极、漏极是对称的，所以其源极、漏极可以互换。在本公开实施例中，将源极和漏极中的一个称为第一极，将源极和漏极中的另一个称为第二极。在以下示例中以N型薄膜晶体管为例进行描述。本领域技术人员可以理解，本公开实施例显然可以应用于P型薄膜晶体管的情况。
图1示出了根据本公开实施例的显示面板的示意图。如图1所示，显示面板包括布置成阵列的像素单元PXL，每个像素单元PXL包括多个子像素，在本实施例中为红色子像素R、绿色子像素G和蓝色子像素B。在图1中，每行像素单元PXL包括三行子像素，其中红色子像素R排成第一行，绿色子像素G排成第二行，蓝色子像素排成第三行。显示面板还包括栅极驱动电路100，栅极驱动电路100通过多条栅极线G1，G2，…GX与多行像素单元连接，例如通过栅极线G1与第一行像素单元PXL的红色子像素R连接，通过栅极线G2与第一行像素单元PXL的绿色子像素G连接，通过栅极线G3与第一行像素单元PXL的蓝色子像素B连接，以此类推。
本公开实施例的栅极驱动电路100可以包括多个移位寄存器，下面将参考图2A和图2B来对本公开实施例的移位寄存器进行示例说明。
图2A示出了根据本公开一实施例的移位寄存器的电路图。如图2A所示，移位寄存器可以包括输入子电路10、输出子电路20和控制子电路30。
输入子电路10连接移位寄存器的输入端IN和上拉节点PU，可以将输入端IN的信号提供至上拉节点PU。在图2A中，输入子电路10可以包括晶体管M1，晶体管M1 的栅极和第一极连接输入端IN，第二极连接上拉节点PU。
输出子电路20连接上拉节点PU、移位寄存器的时钟信号端CK和移位寄存器的输出端OUT，可以在上拉节点PU的电位的控制下将时钟信号端CK的信号提供至输出端OUT。在图2A中，输出子电路20可以包括晶体管M7和电容C1。晶体管M7的栅极连接上拉节点PU，第一极连接时钟信号端CK，第二极连接输出端OUT。电容C1的一端连接上拉节点PU，另一端连接输出端OUT。
控制子电路30连接上拉节点PU、输出端OUT和移位寄存器的下拉节点PD，可以基于上拉节点的电位控制下拉节点PD的电位，并在下拉节点PD的电位控制下下拉输出端OUT的电位。在图2A中，控制子电路30可以包括晶体管M2、M4和M6以及电容C2。晶体管M2的栅极和第一极连接控制端CKB，第二极连接下拉节点PD。晶体管M4的栅极连接上拉节点PU，第一极连接参考信号端VGL，第二极连接下拉节点PD。晶体管M6的栅极连接下拉节点PD，第一极连接参考信号端VGL，第二极连接输出端OUT。电容C2的一端连接晶体管M6的栅极，另一端连接晶体管M6的第一极。在一些实施例中，控制子电路30还可以包括晶体管M3，晶体管M3的栅极连接下拉节点PD，第一极连接参考信号端VGL，第二极连接上拉节点PU。在一些实施例中，控制子电路30还可以包括晶体管M5，晶体管M5的栅极连接输出端OUT，第一极连接参考信号端VGL，第二极连接下拉节点PD。
当输入端IN的输入信号为高电平时，晶体管M1导通，从而将输入端IN的高电平提供至上拉节点PU，晶体管M7导通；当输入端IN的输入信号变为低电平时，电容C1使得上拉节点PU保持高电平。在上拉节点PU为高电平期间，时钟信号端CK的时钟信号的高电平到来，导通的晶体管M7将时钟信号端CK的高电平提供至输出端OUT，从而产生高电平的输出信号。输出端OUT的高电平使晶体管M5导通，将下拉节点PD下拉至低电平。此后，时钟信号端CK的时钟信号为低电平，控制端CKB为高电平，导通的晶体管M7将时钟信号端CK的低电平提供至输出端OUT，从而产生低电平的输出信号，进而使晶体管M5关断；而控制端CKB的高电平使晶体管M2导通，从而使下拉节点PD变为高电平。下拉节点PD的高电平使晶体管M3导通，从而将上拉节点PU下拉至低电平。
图2B示出了根据本公开另一实施例的移位寄存器的电路图。图2B的移位寄存器与图2A的移位寄存器结构类似，区别至少在于图2B的移位寄存器还包括复位子电路40。为了简化描述，下面将主要对区别部分进行详细说明。
如图2B所示，移位寄存器包括输入子电路10、输出子电路20’、控制子电路30’和复位子电路40。
输入子电路10可以与上述输入子电路10采用相同结构，这里不再赘述。
复位子电路40连接上拉节点PU和复位端RST，可以根据复位端RST的复位信号将上拉节点PU复位。在图2B中，复位子电路40包括晶体管M8，晶体管M8的栅极连接复位端RST，第一极连接第一参考信号端LVGL。复位子电路40还可以包括晶体管M9，晶体管M9的栅极连接总复位端TRST，第一极连接第一参考信号端LVGL，第二极连接上拉节点PU。
输出子电路20’包括第一输出子电路、第二输出子电路和第三输出子电路。第一输出子电路可以包括晶体管M10，晶体管M10的栅极连接上拉节点，第一极连接第一时钟信号端CK1，第二极连接第一输出端OUT1。第二输出子电路可以与上述输出子电路20具有相同结构，包括晶体管M7和电容C1。晶体管M7的第一极连接第二时钟信号端CK2，第二极连接第二输出端OUT2。第三输出子电路可以包括晶体管M11和电容C3，其中晶体管M11的栅极连接上拉节点PU，第一极连接第三时钟信号端CK3，第二极连接第三输出端OUT；电容C3的一端连接晶体管M11的栅极，另一端连接晶体管M11的第二极。第二输出端OUT2和第三输出端OUT3中的至少之一可以用于与子像素连接以向其施加栅极驱动信号。第一输出端OUT1可以用于与其他移位寄存器连接，以实现移位寄存器的级联。
控制子电路30’可以包括第一控制子电路和第二控制子电路。第一控制子电路可以与上述控制子电路30具有相同结构，包括晶体管M2、M3、M4、M5和M6。晶体管M2的栅极和第一极连接第一控制端CKA，第二极连接第一下拉节点PD_A。晶体管M3的栅极连接第一下拉节点PD_A，第一极连接上拉节点PU，第二极连接第一参考信号端LVGL。晶体管M4的栅极连接上拉节点PU，第一极连接第一参考信号端LVGL，第二极连接第一下拉节点PD_A。晶体管M5的栅极连接第二输出端OUT，第一极连接第一参考信号端LVGL，第二极连接第一下拉节点PD_A。晶体管M6的栅极连接第一下拉节点PD_A，第一极连接第二参考信号端VGL，第二极连接第二输出端OUT2。第二控制子电路可以包括晶体管M12、M13、M14、M15、M16和M17。晶体管M12的栅极和第一极连接第二控制端CKB，第二极连接第二下拉节点PD_B。晶体管M13的栅极连接上拉节点PU，第一极连接第一参考信号端VGL，第二极连接第二下拉节点PD_B。晶体管M14的栅极连接第二下拉节点PD_B，第一极连接第一参考信号端LVGL，第二极 连接第一输出端OUT1。晶体管M15的栅极连接第二下拉节点PD_B，第一极连接第一参考信号端VGL，第二极连接第三输出端OUT3。晶体管M16的栅极连接第二下拉节点PD_B，第一极连接第一参考信号端LVGL，第二极连接上拉节点PU。晶体管M17的栅极连接第三输出端OUT3，第一极连接第一参考信号端LVGL，第二极连接第二下拉节点PD_B。控制子电路30’还可以包括晶体管M18和M19，其中晶体管M18和M19的栅极均连接至输入端IN，晶体管M18和M19的第一极均连接至第一参考信号端LVGL，晶体管M18的第二极连接第一下拉节点PD_A，晶体管M19的第二极连接第二下拉节点PD_B。控制子电路30’还可以包括晶体管M20，晶体管M20的栅极连接第一下拉节点PD_A，第一极连接第一参考信号端LVGL，第二极连接第一输出端OUT1。
虽然上文以特定的结构对移位寄存器进行了示例说明，然而本公开的实施例不限于此，可以根据需要采用任何合适的移位寄存器。
图3示出了根据本公开一实施例的栅极驱动电路的框图。
如图3所示，栅极驱动电路100包括级联连接的多个驱动单元，例如驱动单元DU1和DU2。每个驱动单元和包括N个移位寄存器单元和模式控制电路，N为大于1的整数。例如N＝4的情况下，驱动单元DU1包括移位寄存器单元120_1、120_2、120_3和120_4和模式控制电路110_1，驱动单元DU2包括移位寄存器单元120_5、120_6、120_7和120_8和110_2。每个移位寄存器单元可以包括多个移位寄存器，下文将对此进行详细说明。
在驱动单元DU1中，模式控制电路110_1与移位寄存器单元120_1、120_2、120_3和120_4连接。模式控制电路110_1可以接收针对驱动单元DU1的控制信号SW_1，并在控制信号SW_1的控制下以多个分辨率模式之一对移位寄存器单元120_1、120_2、120_3和120_4进行连接。
在驱动单元DU2中，模式控制电路110_2与移位寄存器单元120_5、120_6、120_7和120_8连接。模式控制电路110_2可以接收针对驱动单元DU2的控制信号SW_2，并在控制信号SW_2的控制下以多个分辨率模式之一对移位寄存器单元120_5、120_6、120_7和120_8进行连接。
例如所述多个分辨率模式可以包括第一分辨率模式、第二分辨率模式和第三分辨率模式。下面以驱动单元DU1为例对三种分辨率模式下的操作进行说明。
在第一分辨率模式下，模式控制电路110_1可以将移位寄存器单元120_1、120_2、120_3和120_4级联连接。
在第二分辨率模式下，模式控制电路110_1可以将移位寄存器单元120_1、120_2、120_3和120_4分为M组，将所述M组级联连接，并且将每组中的移位寄存器单元并行连接。例如将移位寄存器单元120_1和120_2分为第一组，将移位寄存器单元120_3和120_4分为第二组，第一组和第二组级联连接，第一组中的移位寄存器单元120_1和120_2并行连接，第二组中移位寄存器单元120_3和120_4并行连接。
在第三分辨率模式下，模式控制电路110_1可以将移位寄存器单元120_1、120_2、120_3和120_4并行连接。
驱动单元DU2在三种分辨率下的操作与驱动单元DU1类似，这里不再赘述。
图4示出了图3的栅极驱动电路的示例结构图。
如图4所示，栅极驱动电路100A包括驱动单元DU1和DU2。在每个驱动单元DU1和DU2中，每个移位寄存器单元包括第一移位寄存器、第二移位寄存器和第三移位寄存器。第一移位寄存器、第二移位寄存器和第三移位寄存器中的每一个可以采用上述任意实施例的移位寄存器结构，例如可以均实现为如图2A所示的移位寄存器。在驱动单元DU1中，移位寄存器单元120_1(第一移位寄存器单元)包括移位寄存器GOA1、GOA2和GOA3分别作为第一移位寄存器、第二移位寄存器和第三移位寄存器，移位寄存器单元120_2(第二移位寄存器单元)包括移位寄存器GOA4、GOA5和GOA6分别作为第一移位寄存器、第二移位寄存器和第三移位寄存器，移位寄存器单元120_3(第三移位寄存器单元)包括移位寄存器GOA7、GOA8和GOA9分别作为第一移位寄存器、第二移位寄存器和第三移位寄存器，移位寄存器单元120_4(第四移位寄存器单元)包括移位寄存器GOA10、GOA11和GOA12分别作为第一移位寄存器、第二移位寄存器和第三移位寄存器。类似地，在驱动单元DU2中，移位寄存器单元120_5(第一移位寄存器单元)包括移位寄存器GOA13、GOA14和GOA15，移位寄存器单元120_6(第二移位寄存器单元)包括移位寄存器GOA16、GOA17和GOA18，移位寄存器单元120_7(第三移位寄存器单元)包括移位寄存器GOA19、GOA20和GOA21，移位寄存器单元120_8(第四移位寄存器单元)包括移位寄存器GOA22、GOA23和GOA24。
每个移位寄存器单元具有级联输入端和第一级联输出端。
例如，在驱动单元DU1的移位寄存器单元120_1中，移位寄存器GOA1的输入端IN作为移位寄存器单元120_1的级联输入端以接收启动信号STV；移位寄存器GOA2的输入端IN与移位寄存器GOA1的输出端OUT连接；移位寄存器GOA3的输入端IN与移位寄存器GOA2的输出端OUT连接，移位寄存器GOA3的输出端OUT作为移位 寄存器单元120_1的第一级联输出端。驱动单元DU1的移位寄存器单元120_2、120_3和120_4中各个移位寄存器的连接方式与移位寄存器单元120_1类似，这里不再赘述。
类似地，在在驱动单元DU2的移位寄存器单元120_5中，移位寄存器GOA13的输入端IN作为移位寄存器单元120_5的级联输入端以接收来自驱动单元DU1的级联输出信号；移位寄存器GOA14的输入端IN与移位寄存器GOA13的输出端OUT连接；移位寄存器GOA15的输入端IN与移位寄存器GOA14的输出端OUT连接，移位寄存器GOA15的输出端OUT作为移位寄存器单元120_5的第一级联输出端。驱动单元DU2的移位寄存器单元120_6、120_7和120_8中各个移位寄存器的连接方式与移位寄存器单元120_5类似，这里不再赘述。
如图4所示，驱动单元DU1中的移位寄存器单元120_4的第一级联输出端(即移位寄存器GOA12的输出端)与驱动单元DU2中的移位寄存器单元120_5的级联输入端(即，移位寄存器GOA13的输入端)连接，从而实现驱动单元DU1与DU2的级联连接。
在每个驱动单元中，模式控制电路可以包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管和第六晶体管，针对每个驱动单元的控制信号可以包括第一控制信号、第二控制信号第三控制信号和第四控制信号。
例如在驱动单元DU1中，模式控制电路110_1可以包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5和第六晶体管T6；针对驱动单元DU1的控制信号SW_1可以包括第一控制信号SW1、第二控制信号SW2、第三控制信号SW3和第四控制信号SW4。
第一晶体管T1的栅极连接为接收第一控制信号SW1，第一晶体管T1的第一极连接第一移位寄存器单元120_1的第一级联输出端(即移位寄存器GOA3的输出端OUT)，第一晶体管T1的第二极连接第二移位寄存器单元120_2的级联输入端(即移位寄存器GOA4的输入端IN)。
第二晶体管T2的栅极连接为接收第二控制信号SW2，第二晶体管T2的第一极连接第一移位寄存器单元120_1的级联输入端(即移位寄存器GOA1的输入端IN)，第二晶体管T2的第二极连接第二移位寄存器单元120_2的级联输入端(即移位寄存器GOA4的输入端IN)。
第三晶体管T3的栅极连接为接收第三控制信号SW3，第三晶体管T3的第一极连接第二移位寄存器单元120_2的第一级联输出端(即移位寄存器GOA6的输出端OUT)， 第三晶体管T3的第二极连接第三移位寄存器单元120_3的级联输入端(即移位寄存器GOA7的输入端IN)。
第四晶体管T4的栅极连接为接收第四控制信号SW4，第四晶体管T4的第一极连接第一移位寄存器单元120_2的级联输入端(即移位寄存器GOA1的输入端IN)，第四晶体管T4的第二极连接第三移位寄存器单元120_3的级联输入端(即移位寄存器GOA7的输入端IN)。
第五晶体管T5的栅极连接为第一控制信号SW1，第五晶体管T5的第一极连接第三移位寄存器单元120_3的第一级联输出端(即移位寄存器GOA9的输出端OUT)，第五晶体管T5的第二极连接第四移位寄存器单元120_4的级联输入端(即移位寄存器GOA10的输入端IN)。
第六晶体管T6的栅极连接为接收第二控制信号SW2，第六晶体管T6的第一极连接第三移位寄存器单元120_3的级联输入端(即移位寄存器GOA7的输入端IN)，第六晶体管T6的第二极连接第四晶体管T4的级联输入端(即移位寄存器GOA10的输入端IN)。
类似地，在驱动单元DU2中，模式控制电路110_2可以包括第一晶体管T1’、第二晶体管T2’、第三晶体管T3’、第四晶体管T4’、第五晶体管T5’和第六晶体管T6’；针对驱动单元DU2的控制信号SW_2可以包括第一控制信号SW1’、第二控制信号SW2’、第三控制信号SW3’和第四控制信号SW4’。第一晶体管T1’、第二晶体管T2’、第三晶体管T3’、第四晶体管T4’、第五晶体管T5’和第六晶体管T6’的连接方式与模式控制电路110_1中的第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5和第六晶体管T6类似，这里不再赘述。
在一些实施例中，栅极驱动电路100A中的多个驱动单元可以被划分为多组，每组驱动单元连接一组控制信号线以接收针对该组驱动单元的控制信号，从而使组与组之间以不同分辨率模式进行显示驱动。
在图4中栅极驱动电路100A中驱动单元DU1和DU2被划分到不同的组，例如将驱动单元DU1划分到用于以第一分辨率模式进行显示驱动的第一组，将驱动单元DU2划分到用于以第一分辨率模式进行显示驱动的第二组，第一组和第二组之间的边界如图4中点划线所示。在这种情况下，第一组中的驱动单元DU1可以连接第一至第四控制信号线以分别接收针对第一组驱动单元的控制信号SW1至SW4；第二组中的驱动单元DU2可以连接第五至第八控制信号线以分别接收针对第二组驱动单元的控制信号SW1’至 SW4’。
在一些实施例中，如果驱动单元DU1和DU2被划分到同一组，则驱动单元DU1的第一晶体管T1的栅极与驱动单元DU2的第一晶体管T1’的栅极可以均连接到第一控制信号线以接收相同的第一控制信号，在这种情况下针对驱动单元DU1的第一控制信号SW1与针对驱动单元DU2的第一控制信号为同一信号。类似地，驱动单元DU1的第二晶体管T2的栅极与驱动单元DU2的第一晶体管T2’的栅极可以连接到第二控制信号线以接收相同的第二控制信号，驱动单元DU1的第三晶体管T3的栅极与驱动单元DU2的第三晶体管T3’的栅极可以连接到第三控制信号线以接收相同的第三控制信号，驱动单元DU1的第四晶体管T4的栅极与驱动单元DU2的第四晶体管T4’的栅极可以连接到第四控制信号线以接收相同的第四控制信号。
下面将参考表1来对图4的栅极驱动电路100A在不同分辨率模式下的操作进行说明。为了简明起见，将以一个驱动单元DU1为例来进行说明。
表1
  第一分辨率模式 第二分辨率模式 第三分辨率模式
SW1 1 0 0
SW2 0 1 1
SW3 1 1 0
SW4 0 0 1
在表1中，0表示低电平，1表示高电平。然而本公开的实施例不限于此，在一些实施例中，可以0表示高电平，1表示低电平。
在第一分辨率模式下，如表1所示，第一控制信号SW1和第三控制信号SW3为高电平，第二控制信号SW2和第四控制信号SW4为低电平，使得图4的模式控制电路110_1中，晶体管T1、T3、T5导通，晶体管T2、T4和T6关断，从而得到如图5A所示的等效电路结构。
如图5A所示，晶体管T1导通使得第一移位寄存器单元120_1的第一级联输出端与第二移位寄存器单元120_2的级联输入端连接，晶体管T2关断使得第一移位寄存器单元120_1的级联输入端与第二移位寄存器单元120_2的级联输入端断开连接。类似地，晶体管T3导通使得第二移位寄存器单元120_2的第一级联输出端与第三移位寄存器单元120_3的级联输入端连接，晶体管T2和T4关断使得第二移位寄存器单元120_2的级联输入端与第三移位寄存器单元120_3的级联输入端断开连接；晶体管T5导通使得第 三移位寄存器单元120_3的第一级联输出端与第四移位寄存器单元120_4的级联输入端连接，晶体管T6关断使得第三移位寄存器单元120_3的级联输入端与第四移位寄存器单元120_4的级联输入端断开连接。通过这种方式，实现了移位寄存器单元120_1至120_4的级联连接。
如图5B所示，在图5A所示的等效电路结构下，移位寄存器GOA1可以响应于启动信号STV的输入而产生输出信号G1，该输出信号G1作为输入信号被提供给移位寄存器GOA2，使得移位寄存器GOA2产生相对于输出信号G1而移位的输出信号G2，以此类推，得到顺序移位的输出信号G1至G12。结合图1，栅极驱动电路通过产生如图5B所示的输出信号，可以实现对显示区内子像素的逐行顺序扫描，从而以最高的第一分辨率来进行显示驱动。
在第二分辨率模式下，如表1所示，第一控制信号SW1和第二控制信号SW4为低电平，第二控制信号SW2和第三控制信号SW3为高电平，使得图4的模式控制电路110_1中，晶体管T1、T4和T5关断，晶体管T2、T3和T6导通，从而得到如图6A所示的等效电路结构。
如图6A所示，晶体管T1关断使得第一移位寄存器单元120_1的第一级联输出端与第二移位寄存器单元120_2的级联输入端断开连接，晶体管T2导通使得第二移位寄存器单元120_2的级联输入端与第一移位寄存器单元120_1的级联输入端连接；晶体管T3导通使得第二移位寄存器单元120_2的第一级联输出端与第三移位寄存器单元120_3的级联输入端连接，第四晶体管T4关断使得第三移位寄存器单元120_3的级联输入端与第二移位寄存器单元120_2的级联输入端断开连接；晶体管T5关断使得第三移位寄存器单元120_3的第一级联输出端与第四移位寄存器单元120_4的级联输入端断开连接，晶体管T6导通使得第三移位寄存器单元的级联输入端与第四移位寄存器单元的级联输入端连接。通过这种方式，实现了将移位寄存器单元120_1至120_4分为2组，其中第一组包含并行连接的移位寄存器单元120_1和120_2，第二组包含并行连接的移位寄存器单元120_3和120_4，第一组和第二组之间级联连接。
如图6B所示，在图6A所示的等效电路结构下，第一组的移位寄存器单元120_1和120_2中，移位寄存器GOA1和GOA4可以响应于启动信号STV的输入而并行地产生输出信号G1和G4。输出信号G1和G4分别作为输入信号被提供给移位寄存器GOA2和GOA5，使得移位寄存器GOA2产生相对于输出信号G1而移位的输出信号G2，移位寄存器GOA5产生相对于输出信号G4而移位的输出信号G5。输出信号G2和G5分 别作为输入信号被提供给移位寄存器GOA3和GOA6，使得移位寄存器GOA3产生相对于输出信号G2而移位的输出信号G3，移位寄存器GOA6产生相对于输出信号G5而移位的输出信号G5。通过这种方式，使得第一组的移位寄存器单元120_1和120_2并行地产生输出信号，即移位寄存器单元120_1产生的输出信号G1至G3，分别与移位寄存器单元120_2产生的输出信号G4至G6同步。
输出信号G6作为输入信号被提供给移位寄存器单元120_3中的移位寄存器GOA7和移位寄存器单元120_4中的GOA10，使得移位寄存器单元120_3与120_4以类似于上述的方式并行地产生两组输出信号，而且输出信号G7至G12分别相对于输出信号G1至G6而移位。通过这种方式，实现了第二组移位寄存器单元120_3和120_4产生的一组输出信号相对于第一组移位寄存器单元120_1和120_2产生的一组输出信号而移位。
结合图1，栅极驱动电路通过产生如图6B所示的输出信号，可以实现对显示区子像素的分组扫描。例如将每两行像素单元作为一组，先同时扫描这第一和第二行像素单元中的红色子像素，然后同时扫描这两行像素单元中的绿色子像素，最后同时扫描这两行像素单元中的蓝色子像素。当扫描完第一和第二行像素单元之后，以同样的方式扫描第三行和第四行像素单元。由此，可以实现比第一分辨率低的第二分辨率的显示驱动，例如第二分辨率可以是第一分辨率的二分之一。
在第三分辨率模式下，如表1所示，第一控制信号SW1和第三控制信号SW3为低电平，第二控制信号SW2和第四控制信号SW4为高电平，使得图4的模式控制电路110_1中，晶体管T1、T3和T5关断，晶体管T2、T4和T6导通，从而得到如图7A所示的等效电路结构。
如图7A所示，晶体管T1关断使得第一移位寄存器单元120_1的第一级联输出端与第二移位寄存器单元120_2的级联输入端断开连接，晶体管T2导通使得第一移位寄存器单元120_1的级联输入端与第二移位寄存器单元120_2的级联输入端连接。类似地，晶体管T3关断使得第二移位寄存器单元120_2的第一级联输出端与第三移位寄存器单元120_3的级联输入端断开连接，晶体管T2和T4导通使得第二移位寄存器单元120_2的级联输入端与第三移位寄存器单元120_3的级联输入端连接；晶体管T5关断使得第三移位寄存器单元120_3的第一级联输出端与第四移位寄存器单元120_4的级联输入端断开连接，晶体管T6导通使得第三移位寄存器单元120_3的级联输入端与第四移位寄存器单元120_4的级联输入端连接。通过这种方式，实现了移位寄存器单元120_1至120_4的并行连接。
如图7B所示，在图7A所示的等效电路结构下，移位寄存器GOA1、GO4、GOA7和GOA10可以响应于启动信号STV的输入而并行地产生输出信号G1、G4、G7和G10；输出信号G1、G4、G7和G10作为输入信号被分别提供给移位寄存器GOA2、GOA5、GOA8和GOA11，使得移位寄存器GOA2、GOA5、GOA8和GOA11并行地产生移位的输出信号G2、G5、G8和G11；输出信号G2、G5、G8和G11作为输入信号被分别提供给移位寄存器GOA3、GOA6、GOA9和GOA12，使得移位寄存器GOA3、GOA6、GOA9和GOA12并行地产生移位的输出信号G3、G6、G9和G12。通过这种方式，实现了移位寄存器单元120_1至120_4并行地产生输出信号。
结合图1，栅极驱动电路通过产生如图7B所示的输出信号，可以实现对显示区子像素的分组扫描。例如将每四行像素单元作为一组，先同时扫描这第一至第四行像素单元中的红色子像素，然后同时扫描这4行像素单元中的绿色子像素，最后同时扫描这4行像素单元中的蓝色子像素。当扫描完第一至第四行像素单元之后，以同样的方式扫描第五至第八行像素单元。由此，可以实现比第二分辨率低的第三分辨率的显示驱动，例如第三年分辨率可以是第二分辨率的二分之一。
图8A示出了图4的栅极驱动电路100A在第二分辨率和第三分辨率模式下的等效示意图。在一些实施例中，可以将显示区内的子像素划分为多组，例如将显示区内位于中心区域的多行子像素划分为第一组，将沿着列方向位于中心区域两侧区域的多行子像素分别划分为第二组和第三组。本公开实施例的栅极驱动电路中的多个驱动单元也相应地划分为多组，每组驱动单元连接一组子像素，从而可以根据独立驱动各组子像素以不同分辨率进行显示。例如驱动中心区域的子像素以较高分辨率显示，而驱动两侧区域的子像素以较低分辨率显示。
如图8A所示，驱动单元DU1和驱动单元DU2被分别划分到了以不同分辨率模式进行显示驱动的两组。在这种情况下，例如驱动单元DU1中的模式控制电路110_1可以在控制信号SW1至SW4的控制下将移位寄存器单元120_1至120_4以第二分辨率模式连接，得到如图6A所示的等效电路结构。驱动单元DU2中的模式控制电路110_2可以在控制信号SW1’至SW4’的控制下将移位寄存器单元120_5至120_8以第三分辨率模式连接，得到如图7A所示的等效电路结构。驱动单元DU1与驱动单元DU2级联连接，使得移位寄存器GOA12的输出信号G12作为输入信号被提供至驱动单元DU2的移位寄存器GOA13、GOA16、GOA19和GOA22。
在工作过程中，如图8B所示，以第二分辨率模式连接的移位寄存器单元120_1至 120_4产生如图6B所示的输出信号G1至G12。移位寄存器GOA12的输出信号G12作为输入信号被提供至驱动单元DU2的移位寄存器GOA13、GOA16、GOA19和GOA22，使得以第三分辨率模式连接的移位寄存器单元120_5至120_8产生类似于图7B所示的输出信号G13至G24。通过这种方式，驱动单元DU1可以驱动与之连接的多行子像素以第二分辨率进行显示，驱动单元DU2可以驱动与之连接的多行子像素以第三分辨率进行显示，从而实现了分区域的多分辨率显示。从图8B可以看出，相比于第一分辨率模式，第二分辨率模式缩短了扫描时间(栅极驱动电路扫描全部子像素所需的时间)，在本实施例中扫描时间缩短了一半；而第三分辨率模式相比于第二分辨率进一步缩短了扫描时间。在一帧时间长度不变的情况下，扫描时间的缩短，使得消隐(blank)时段相应地增加。
图9示出了图3的栅极驱动电路的另一示例结构图。
图9的栅极驱动电路100B与图4的栅极驱动电路100A类似，区别至少在于各个移位寄存器单元还具有复位端并且模式控制电路还连接各个移位寄存器单元的复位端。为了简明起见，下面将主要对区别部分进行详细描述。
如图9所示，类似于图4，驱动单元DU1包括四个移位寄存器单元，其中第一移位寄存器单元包括移位寄存器GOA1至GOA3，第二移位寄存器单元包括移位寄存器GOA4至GOA6，第三移位寄存器单元包括移位寄存器GOA7至GOA9，第四移位寄存器单元包括移位寄存器GOA10至GOA12。
与图4不同的是，图9的移位寄存器单元中的各个移位寄存器还具有复位端RST，例如可以由以上参考图2B描述的移位寄存器来实现。在这种情况下，可以在每个移位寄存器单元中，将第一移位寄存器的输出端作为该移位寄存器单元的第二级联输出端，将第三移位寄存器的输出端和复位端分别作为该移位寄存器单元的第一级联输出端和复位端。例如，在移位寄存器单元120_1中，将移位寄存器GOA1的输出端作为移位寄存器单元120_1的第二级联输出端，将移位寄存器GOA3的输出端作为移位寄存器单元120_1的第一级联输出端，将移位寄存器GOA3的复位端RST作为移位寄存器单元120_1的复位端；在移位寄存器单元120_2中，将移位寄存器GOA4的输出端作为移位寄存器单元120_2的第二级联输出端，将移位寄存器GOA6的输出端作为移位寄存器单元120_2的第一级联输出端，将移位寄存器GOA4的复位端RST作为移位寄存器单元120_2的复位端，以此类推。驱动单元DU1的第四移位寄存器单元的复位端(即移位寄存器GOA12的复位端RST)与驱动单元DU2中的第一移位寄存器单元的第二 级联输出端(即移位寄存器GOA13的输出端OUT)连接，从而实现驱动单元DU1与驱动单元DU2的级联。
模式控制电路包括第一模式控制子电路1101和第二模式控制子电路1102。第一模式控制子电路1101与上述模式控制电路110_1具有相同结构，包括第一晶体管T1至第六晶体管T6，这里不再赘述。第二模式控制子电路1102包括第七晶体管T7、第八晶体管T8、第九晶体管T9、第十晶体管T10、第十一晶体管T11和第十二晶体管T12。第七晶体管T7的栅极连接为接收第一控制信号SW1，第一极连接第一移位寄存器单元的复位端(即移位寄存器GOA3的复位端RST)，第二极连接第二移位寄存器单元的第二级联输出端(即移位寄存器GOA4的输出端)。第八晶体管T8的栅极连接为接收第五控制信号SW5，第一极连接第一移位寄存器单元的复位端(即移位寄存器GOA3的复位端RST)，第二极连接第二移位寄存器单元的复位端(即移位寄存器GOA6的复位端RST)。第九晶体管T9的栅极连接为接收第三控制信号SW3，第一极连接第二移位寄存器单元的复位端(即移位寄存器GOA6的复位端RST)，第二极连接第三移位寄存器单元的第二级联输出端(即移位寄存器GOA7的输出端OUT)。第十晶体管T10的栅极连接为接收第四控制信号SW4，第一极连接第二移位寄存器单元的复位端(即移位寄存器GOA6的复位端RST)，第二极连接第三移位寄存器单元的复位端(即移位寄存器GOA9的复位端)。第十一晶体管T11的栅极连接为接收第一控制信号SW1，第一极连接第三移位寄存器单元的复位端(即移位寄存器GOA9的复位端RST)，第二极连接第四移位寄存器单元的第二级联输出端(即移位寄存器GOA10的输出端)。第十二晶体管T12的栅极连接为接收第二控制信号SW2，第一极连接第三移位寄存器单元的复位端(即移位寄存器GOA9的复位端RST)，第二极连接第四移位寄存器单元的复位端(即移位寄存器GOA12的复位端RST)。
下面将参考表2对图9的栅极驱动电路的驱动方法进行说明。
表2
  第一分辨率模式 第二分辨率模式 第三分辨率模式
SW1 1 0 0
SW2 0 1 1
SW3 1 1 0
SW4 0 0 1
SW5 0 1 0
在表2中，0表示低电平，1表示高电平。然而本公开的实施例不限于此，在一些实施例中，可以0表示高电平，1表示低电平。
在第一分辨率模式下，如表2所示，第一控制信号SW1和第三控制信号SW3为高电平，第二控制信号SW2、第四控制信号SW4和第五控制信号SW5为低电平。第一模式控制子电路1101按照以上参考图5A描述的方式将各个移位寄存器级联连接。第二模式控制子电路1102将第n移位寄存器单元的复位端与第n+1移位寄存器单元的第二级联输出端连接，并将所述第n移位寄存器单元的复位端与所述第n+1移位寄存器单元的复位端断开连接，其中1≤n≤3。如图9所示，第一控制信号SW1和第三控制信号SW3为高电平使晶体管T7、T9和T11导通，第二控制信号SW2、第四控制信号SW4和第五控制信号SW5为低电平使晶体管T8、T10和T12关断，从而将移位寄存器GOA3的复位端RST与移位寄存器GOA4的输出端OUT连接，将移位寄存器GOA3的复位端RST与移位寄存器GOA6的复位端断开连接；将移位寄存器GOA6的复位端RST与移位寄存器GOA7的输出端OUT连接，将移位寄存器GOA6的复位端RST与移位寄存器GOA9的复位端RST断开连接；将移位寄存器GOA9的复位端RST与移位寄存器GOA10的输出端OUT连接，将移位寄存器GOA9的复位端RST与移位寄存器GOA12的复位端RST断开连接。
在第二分辨率模式下，如表2所示，第二控制信号SW2、第三控制信号SW3和第五控制信号SW5为高电平，第一控制信号SW1和第四控制信号SW4为低电平。第一模式控制子电路1101按照以上参考图6A描述的方式将各个移位寄存器分组连接。第二模式控制子电路1102将第一移位寄存器单元的复位端(即移位寄存器GOA3的复位端RST)与第二移位寄存器单元的第二级联输出端(即移位寄存器GOA4的输出端OUT)断开连接，将第二移位寄存器单元的复位端(即移位寄存器GOA6的复位端RST)与第三移位寄存器单元的第二级联输出端(即移位寄存器GOA7的输出端OUT)连接，将第三移位寄存器单元的复位端(即移位寄存器GOA9的复位端RST)与第四移位寄存器单元的第二级联输出端(即移位寄存器GOA10的输出端OUT)断开连接，将第一移位寄存器单元的复位端(即移位寄存器GOA3的复位端RST)与第二移位寄存器单元的复位端(即移位寄存器GOA6的复位端RST)连接，将第二移位寄存器单元的复位端(即移位寄存器GOA6的复位端RST)与第三移位寄存器单元的复位端(即移位寄存器GOA9的复位端RST)断开连接，并且将第三移位寄存器单元的复位端(即移位寄存器GOA9的复位端RST)与第四移位寄存器单元的复位端(即移位寄存器 GOA12的复位端RST)连接。
在第三分辨率模式下，如表2所示，第二控制信号SW2和第四控制信号SW4为高电平，第一控制信号SW1、第三控制信号SW3和第五控制信号SW5为低电平。第一模式控制子电路1101按照以上参考图7A描述的方式将各个移位寄存器并行连接。第二模式控制子电路1102将第n移位寄存器单元的复位端与第n+1移位寄存器单元的第二级联输出端断开连接，并将所述第n移位寄存器单元的复位端与所述第n+1移位寄存器单元的复位端连接，其中1≤n≤3。如图9所示，第二控制信号SW2和第四控制信号SW4为高电平使晶体管T10和T12导通，第一控制信号SW1、第三控制信号SW3和第五控制信号SW5为低电平使晶体管T7、T8、T9、T11关断，从而将移位寄存器GOA3的复位端RST与移位寄存器GOA4的输出端OUT断开连接，将移位寄存器GOA3的复位端RST与移位寄存器GOA6的复位端断开连接，将移位寄存器GOA6的复位端RST与移位寄存器GOA7的输出端OUT断开连接，将移位寄存器GOA9的复位端RST与移位寄存器GOA10的输出端OUT断开连接，将移位寄存器GOA3的复位端RST与移位寄存器GOA6的复位端RST断开连接，将移位寄存器GOA6的复位端RST与移位寄存器GOA9的复位端RST连接，将移位寄存器GOA9的复位端RST与移位寄存器GOA12的复位端RST连接。
图10示出了根据本公开另一实施例的栅极驱动电路的结构图。
栅极驱动电路200包括多个驱动单元，每个驱动单元包括级联连接的多个移位寄存器。在图10中为了简明起见以两个驱动单元DU1和DU2为例进行了说明。如图10所示，驱动单元DU1包括级联连接的多个移位寄存器GOA1，GOA2，…GOA8，驱动单元DU2包括级联连接的多个移位寄存器GOA9，GOA10，…。为了便于描述以驱动单元DU1包括8个移位寄存器为了进行了说明，然而本公开实施例不限于此，各个驱动单元可以根据需要包括其他数量的移位寄存器。各个移位寄存器GOA1，GOA2，…可以采用根据本公开任意实施例的移位寄存器结构，例如由以上参考图2B描述的移位寄存器来实现。
栅极驱动电路200还包括与所述多个驱动单元一一对应地连接的多条启动信号线，例如与驱动单元DU1连接的启动信号线STV1和与驱动单元DU2连接的启动信号线STV2。启动信号线STV1连接至驱动单元DU1中的第一级移位寄存器GOA1，启动信号线STV2连接至驱动单元DU2中的第一级移位寄存器GOA9。
栅极驱动电路200还包括K条时钟信号线，其中K为大于1的整数。例如在图10 中K＝8，8条时钟信号线CLK1至CLK8与每个驱动单元DU1和DU2中的各个移位寄存器连接。
栅极驱动电路200还包括模式控制电路210。模式控制电路210与所述K条时钟信号线CLK1至CLK8连接。模式控制电路210可以接收K个初始时钟信号clk1至clk8和控制信号SW，在所述控制信号SW的控制下以第一分辨率模式、第二分辨率模式和第三分辨率模式之一来基于所述K个初始时钟信号clk1至clk8产生K个时钟信号，并将产生的K个时钟信号分别提供给所述K条时钟信号线CLK1至CLK8。例如，在第一分辨率模式下，模式控制电路210可以基于所述K个初始时钟信号产生顺序移位的K个第一时钟信号。在第二分辨率模式下，模式控制电路210可以基于所述K个初始时钟信号产生分成2M组的K个第二时钟信号，每组中的多个第二时钟信号同步，第m+1组第二时钟信号相对于第m组第二时钟信号而移位。在第三分辨率模式下，模式控制电路210可以基于所述K个初始时钟信号产生分成M组的K个第三时钟信号，每组中的多个第三时钟信号同步，第m’+1组第三时钟信号相对于第m’组第三时钟信号而移位，其中M为大于1的整数，m和m’均为整数，1≤m≤2M-1，且1≤m’≤M-1。
在一些实施例中，在每个驱动单元中，第n级移位寄存器的输出端连接至第n+1级移位寄存器的输入端，第n+1级移位寄存器的输出端连接至第n级移位寄存器的复位端，其中n为大于或等于1的整数。每个驱动单元中的多个移位寄存器分为至少一组，每组包括级联连接的K个移位寄存器，所述K个移位寄存器的时钟信号端与所述K条时钟信号线一一对应地连接。
例如在图10所示的驱动单元DU1中，第一级移位寄存器GOA1的输出端OUT连接至第二级移位寄存器GOA2的输入端IN，第二级移位寄存器GOA2的输出端OUT连接至第一级移位寄存器GOA1的复位端RST；第二级移位寄存器GOA2的输出端OUT连接至第三移位寄存器GOA3的输入端IN，第三级移位寄存器GOA3的输出端OUT连接至第二级移位寄存器GOA2的复位端RST，以此类推。在图10的驱动单元DU1中，将第一级移位寄存器GOA1至第八级移位寄存器GOA8分为一组，第一级移位寄存器GOA1至第八级移位寄存器GOA8各自的时钟信号端CK与时钟信号线CLK1至CLK8一一对应地连接。如果驱动单元DU1包括更多个移位寄存器，例如包括16个移位寄存器，则可以将第一级至第八级移位寄存器分为第一组并以上述方式与时钟信号线CLK1至CLK8一一对应地连接，将第九级至第十六级移位寄存器分为第二组并以上述方式与时钟信号线CLK1至CLK8一一对应地连接。在图10所示的驱动单元 DU2中，第一级移位寄存器GOA9、第二级移位寄存器GOA10……以类似于驱动单元1中的移位寄存器GOA1至GOA8的方式连接，这里不再赘述。
图11示出了图10的栅极驱动电路中的模式控制电路的示例电路图。
如图11所示，模式控制电路210包括第一时钟输入端至第八时钟输入端，分别连接为接收8个初始时钟信号clk1至clk8。模式控制电路210还包括第一时钟输出端至第八时钟输出端，与8条时钟信号线CLK1至CLK8一一对应地连接。在一些实施例中，模式控制电路210的第一时钟输入端与第一时钟输出端可以相连接，例如可以将第一时钟信号线CLK1实现为接收第一初始时钟信号clk1。为了便于描述，下面将分别用clk1至clk8来表示第一时钟输入端至第八时钟输入端，分别用CLK1至CLK8来表示第一时钟输出端至第八时钟输出端。
模式控制电路210还包括第一模式控制子电路2101、第二模式控制子电路2102、第三模式控制子电路2103和第二模式控制子电路2104。
第一模式控制子电路2101可以在第一控制信号SW1的控制下，将第二时钟输入端clk2与第二时钟输出端CLK8连接，将第四时钟输入端clk4与第四时钟输出端CLK4连接，将第七时钟输入端clk7与第七时钟输出端CLK7连接，以及将第八时钟输入端clk8与第八时钟输出端CLK8连接。例如在图11中，第一模式控制子电路2101包括第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4。第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4的栅极均连接为接收第一控制信号SW1。第一晶体管T1的第一极连接第二时钟输入端clk2，第二极连接第二时钟输出端CLK2。第二晶体管T2的第一极连接第四时钟输入端clk4，第二极连接第四时钟输出端CLK4。第三晶体管T3的第一极连接第七时钟输入端clk7，第二极连接第七时钟输出端CLK7。第四晶体管T4的第一极连接第八时钟输入端clk8，第二极连接第八时钟输出端CLK8。
第二模式控制子电路2102可以在第二控制信号SW2的控制下，将第三时钟输入端clk3与第三时钟输出端CLK3连接，以及将第六时钟输入端clk6与第六时钟输出端CLK6连接。例如在图11中，第二模式控制子电路2102包括第五晶体管T5和第六晶体管T6。第五晶体管T5和第六晶体管T6的栅极均连接为接收第二控制信号SW2。第五晶体管T5的第一极连接第三时钟输入端clk3，第二极连接第三时钟输出端CLK3。第六晶体管T6的第一极连接第六时钟输入端clk6，第二极连接第六时钟输出端CLK6。
第三模式控制子电路2103可以在第三控制信号SW3的控制下将第一时钟输出端CLK1与第二时钟输出端CLK2连接，将第三时钟输出端CLK3与第四时钟输出端CLK4 连接，将第五时钟输出端CLK5与第六时钟输出端CLK6连接，以及将第七时钟输出端CLK7与第八时钟输出端CLK8连接。例如在图11中，第三模式控制子电路2103包括第七晶体管T7、第八晶体管T8、第九晶体管T9和第十晶体管T10。第七晶体管T7、第八晶体管T8、第九晶体管T9和第十晶体管T10的栅极均连接为接收第三控制信号SW3。第七晶体管T7的第一极连接第一时钟输出端CLK1，第二极连接第二时钟输出端CLK2。第八晶体管T8的第一极连接第三时钟输出端CLK3，第二极连接第四时钟输出端CLK4。第九晶体管T9的第一极连接第五时钟输出端CLK5，第二极连接第六时钟输出端CLK6。第十晶体管T10的第一极连接第七时钟输出端CLK7，第二极连接第八时钟输出端CLK8。
第四模式控制子电路2104可以在第四控制信号SW4的控制下将第二时钟输出端CLK2与第三时钟输出端CLK3连接，以及将第六时钟输出端CLK6与第七时钟输出端CLK7连接。例如在图11中，第四模式控制子电路2104包括第十一晶体管T11和第十二晶体管T12。第十一晶体管T11和第十二晶体管T12的栅极均连接为接收第四控制信号SW4。第十一晶体管T11的第一极连接第二时钟输出端CLK2，第二极连接第三时钟输出端CLK3。第十二晶体管T12的第一极连接第六时钟输出端CLK6，第二极连接第七时钟输出端CLK7。
在工作时，模式控制电路210在控制信号的控制下以多种分辨率模式之一来基于所述K个初始时钟信号clk1至clk8产生K个时钟信号，并将产生的K个时钟信号分别提供给所述K条时钟信号线CLK1至CLK8。向多条启动信号线STV1和STV2中的至少一条启动信号线(例如STV1)施加启动信号，以启动与所述至少一条启动信号线连接的驱动单元。例如当启动信号线STV1上的启动信号将驱动单元DU1启动时，被启动的驱动单元DU1中的多个移位寄存器GOA1至GOA8分别根据时钟信号线CLK1至CLK8上的时钟信号来产生输出信号G1至G8。当启动信号线STV2上的启动信号将驱动单元DU2启动时，被启动的驱动单元DU2中的多个移位寄存器GOA9，GOA10，…分别根据时钟信号线CLK1至CLK8上的时钟信号来产生输出信号G9，G10，…。
下面将结合图10和图11，参考表3以及图12至图17来详细描述上述栅极驱动电路200的驱动方法。为了简明起见，以图10中的一个驱动单元DU1为例来进行说明。驱动单元DU2的工作原理与驱动单元DU1类似，这里不再赘述。
表3
  第一分辨率模式 第二分辨率模式 第三分辨率模式
SW1 1 0 0
SW2 1 1 0
SW3 0 1 1
SW4 0 0 1
在表3中，0表示低电平，1表示高电平。然而本公开的实施例不限于此，在一些实施例中，可以0表示高电平，1表示低电平。
图12示出了图10的栅极驱动电路接收的初始时钟信号的时序图。如图12所示，初始时钟信号clk1至clk8是顺序移位的时钟信号，其中第k+1初始时钟信号相对于第k初始时钟信号移位单位扫描时间H，每个初始时钟信号clk1至clk8的有效电平持续时间为4H。这里单位扫描时间可以是扫描一行子像素所需要的时间。
在第一分辨率模式下，如表3所示，第一控制信号SW1和第二控制信号SW2为高电平，第三控制信号SW3和第四控制信号SW4为低电平。图11中的第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5和第六晶体管T6导通，第七晶体管T7、第八晶体管T8、第九晶体管T9、第十晶体管T10、第十一晶体管T11和第十二晶体管T12关断。第一模式控制子电路2101将第二时钟输入端clk2与第二时钟输出端连接CLK2，将第四时钟输入端clk4与第四时钟输出端CLK4连接，将第七时钟输入端clk7与第七时钟输出端CLK7连接，以及将第八时钟输入端clk8与第八时钟输出端CLK8连接。第二模式控制子电路2102将第三时钟输入端clk3与第三时钟输出端CLK3连接，以及将第六时钟输入端clk6与第六时钟输出端CLK6连接。
通过这种方式，如图13所示，模式控制电路基于初始时钟信号clk1至clk8产生顺序移位的8个第一时钟信号并分别提供给时钟信号线CLK1至CLK8。图10中的移位寄存器GOA1至GOA8基于时钟信号线CLK1至CLK8上的时钟信号产生顺序移位的输出信号G1至G8，如图13所示。
在第二分辨率模式下，如表3所示，第一控制信号SW1和第四控制信号SW4为低电平，第二控制信号SW2和第三控制信号SW3为高电平，图11中的第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第十一晶体管T11和第十二晶体管T12关断，第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9和第十晶体管T10导通。第二模式控制子电路2102将第三时钟输入端clk3与 第三时钟输出端CLK3连接，以及将第六时钟输入端clk6与第六时钟输出端CLK6连接。第三模式控制子电路2103将第一时钟输出端CLK1与第二时钟输出端CLK2连接，将第三时钟输出端CLK3与第四时钟输出端CLK4连接，将第五时钟输出端CLK5与第六时钟输出端CLK6连接，以及将第七时钟输出端CLK7与第八时钟输出端CLK8连接。
通过这种方式，模式控制电路基于初始时钟信号clk1至clk8产生8个第二时钟信号并分别提供给时钟信号线CLK1至CLK8。如图14所示，时钟信号线CLK1至CLK8上的第二时钟信号分成2M组，例如M＝2的情况下分成4组，第一组包括时钟信号线CLK1和CLK2，第二组包括时钟信号线CLK3和CLK4，第三组包括时钟信号线CLK5和CLK6，第四组包括时钟信号线CLK7和CLK8。时钟信号线CLK1上的第二时钟信号与CLK2上的第二时钟信号同步，时钟信号线CLK3上的第二时钟信号与CLK4上的第二时钟信号同步，以此类推。第二组时钟信号线CLK3和CLK4上的第二时钟信号相对于第一组时钟信号线CLK1和CLK2上的第二时钟信号而移位，第三组时钟信号线CLK5和CLK6上的第二时钟信号相对于第二组时钟信号线CLK3和CLK4上的第二时钟信号而移位，第四组时钟信号线CLK7和CLK8上的第二时钟信号相对于第三组时钟信号线CLK5和CLK6上的第二时钟信号而移位。图10中的移位寄存器GOA1至GOA8基于时钟信号线CLK1至CLK8上的时钟信号相应地产生输出信号G1至G8，如图14所示，输出信号G1和G2同步，输出信号G3和G4同步，输出信号G3和G4中的任一个相对于输出信号G1和G2中的任一个而移位，以此类推。
在第三分辨率模式下，如表3所示，第一控制信号SW1和第二控制信号SW2为低电平，第三控制信号SW3和第四控制信号SW4为高电平，图11中的第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5和第六晶体管T6关断，第七晶体管T7、第八晶体管T8、第九晶体管T9、第十晶体管T10、第十一晶体管T11和第十二晶体管T12导通。第三模式控制子电路2103将第一时钟输出端CLK1与第二时钟输出端CLK2连接，将第三时钟输出端CLK3与第四时钟输出端CLK4连接，将第五时钟输出端CLK5与第六时钟输出端CLK6连接，以及将第七时钟输出端CLK7与第八时钟输出端CLK8连接。第四模式控制子电路2104将第二时钟输出端CLK2与第三时钟输出端CLK3连接，以及将第六时钟输出端CLK6与第七时钟输出端CLK7连接。
通过这种方式，模式控制电路基于初始时钟信号clk1至clk8产生8个第三时钟信号并提供给时钟信号线CLK1至CLK8。这8个第三时钟信号分成M组，每组中的多 个第三时钟信号同步。例如，如图15所示，M＝2的情况下，第一组包括时钟信号线CLK1至CLK4上，第二组包括时钟信号线CLK5至CLK8。第一组时钟信号线CLK1至CLK4上的第三时钟信号彼此同步，第二组时钟信号线CLK5至CLK8上的第三时钟信号彼此同步。第二组时钟信号线CLK5至CLK8上的第三时钟信号相对于第一组时钟信号线CLK1至CLK4上第三时钟信号而移位。图10中的移位寄存器GOA1至GOA8基于时钟信号线CLK1至CLK8上的时钟信号相应地产生输出信号G1至G8，如图15所示，输出信号G1至G4彼此同步，输出信号G5至G8同步，输出信号G1至G4中的任一个相对于输出信号G5至G8中的任一个而移位，以此类推。
图16示出了图10的栅极驱动电路在第一分辨率模式、第二分辨率模式和第三分辨率模式下的信号时序图的一个示例。在本实施例中，以第一分辨率模式为8K分辨率的显示模式，第二分辨率模式为4K分辨率的显示模式，第三分辨率模式为2K分辨率的显示模式为例来进行说明。然而本公开的实施例不限于此，第一分辨率模式、第二分辨率模式和第三分辨率模式可以根据需要设置成其他分辨率的显示模式。
如图16所示，在第一时段P1，模式控制电路以第一分辨率模式产生如图13所示的顺序移位的8个时钟信号并分别提供给时钟信号线CLK1至CLK8，移位寄存器GOA1，GOA2，…产生同样顺序移位的输出信号。在第二时段P2，模式控制电路以第二分辨率模式产生如图14所示的分4组顺序移位的8个时钟信号并分别提供给时钟信号线CLK1至CLK8，移位寄存器GOA1，GOA2，…产生同样分4组顺序移位的输出信号G1。在第三时段P3，模式控制电路以第三分辨率模式产生如图15所示的分2组顺序移位的8个时钟信号并分别提供给时钟信号线CLK1至CLK8，移位寄存器GOA1，GOA2，…产生同样分2组顺序移位的输出信号。
图17示出了图10的栅极驱动电路在第一分辨率、第二分辨率和第三分辨率模式下的信号时序图的另一示例。图17的实施例与图16类似，区别在于初始时钟信号clk1至clk8是占空比为12.5％的周期信号，其中第k+1初始时钟信号相对于第k初始时钟信号移位单位扫描时间H，每个初始信号的有效电平持续时间为单位扫描时间H。因此基于初始时钟信号clk1至clk8产生的时钟信号CLK1和CLK8同样是占空比为12.5％的周期信号，其中第k+1时钟信号相对于第k时钟信号移位单位扫描时间H，每个时钟信号的有效电平持续时间为单位扫描时间H。相应地产生的输出信号的有效电平持续时间为H。
在以上参考图12至图16描述的驱动方法中，每一级移位寄存器产生的输出信号的有效电平持续时间为4H，而彼此之间的移位为H，这使得与之连接的子像素可以先被 预充电一段时间，然后再向该行子像素写入数据信号。相比之下，图17的方法产生的输出信号的有效电平持续时间和输出信号之间的移位均为H，去除了该预充电过程。
图18示出了根据本公开又一实施例的栅极驱动电路的框图。图19示出了图18的栅极驱动电路的示例结构图。在一些实施例中，如上所述，可以将显示区的子像素按区域划分为多组，例如位于中间区域的子像素划分为第一组，位于两侧区域的子像素分别划分为第二组和第三组。
如图18和19所示，栅极驱动电路300可以包括多个驱动单元，例如驱动单元DU1、DU2和DU3。驱动单元DU2可以与上述第一组子像素连接，驱动单元DU1可以与上述第二组子像素连接，驱动单元DU3可以与上述第三组子像素连接。
每个驱动单元DU1、DU2和DU3包括级联连接的多个移位寄存器单元。例如驱动单元DU1包括级联连接的移位寄存器单元320_1，320_2，…320_Y。每个移位寄存器单元可以包括第一移位寄存器、第二移位寄存器和第三移位寄存器。例如移位寄存器单元320_1包括移位寄存器GOA1、GOA2和GOA3分别作为第一移位寄存器、第二移位寄存器和第三移位寄存器，移位寄存器单元320_2包括移位寄存器GOA4、GOA5和GOA6分别作为第一移位寄存器、第二移位寄存器和第三移位寄存器，以此类推。上述移位寄存器可以采用本公开任意实施例的移位寄存器结构，例如由以上参考图2A或图2B描述的移位寄存器来实现。在移位寄存器单元320_1中，第一移位寄存器GOA1的输入端IN作为移位寄存器单元320_1的级联输入端，第一移位寄存器GOA1的输出端OUT连接至第二移位寄存器GOA2的输入端IN，第二移位寄存器GOA2的输出端OUT连接至第三移位寄存器GOA3的输入端IN，第三移位寄存器GOA3的输出端OUT作为移位寄存器单元320_1的级联输出端。第一移位寄存器GOA1的时钟信号端CK、第二移位寄存器GOA2的时钟信号端CK和第三移位寄存器GOA3的时钟信号端CK作为移位寄存器单元320_1的时钟信号端。其他移位寄存器单元320_2，320_3，…具有类似的结构，这里不再赘述。
在移位寄存器单元320_1，320_2，…320_Y中，第n级移位寄存器单元的级联输出端连接至第n+d级移位寄存器单元的级联输入端，其中K＝2d。例如在K＝8的情况下，d＝4，第一级移位寄存器单元320_1的级联输出端(即移位寄存器GOA3的输出端OUT)连接至第五级移位寄存器单元320_5的级联输入端(即移位寄存器GOA13的输入端IN)；第二级移位寄存器单元320_2的级联输出端(即移位寄存器GOA6的输出端OUT)连接至第六级移位寄存器单元320_6的级联输入端(即移位寄存器GOA16的输入端 IN)，以此类推。
栅极驱动电路300还包括多条启动信号线STV1、STV2和STV3，启动信号线STV1、STV2和STV3与驱动单元DU1、DU2和DU3一一对应地连接。每条启动信号线连接至对应驱动单元中的前d级移位寄存器单元的级联输入端。例如，启动信号线STV1连接至驱动单元DU1中的前4级移位寄存器单元320_1、320_2、320_3和320_4的级联输入端(即，GOA1、GOA4、GOA7和GOA10的输入端IN)。
栅极驱动电路300还包括K条时钟信号线，例如时钟信号线CLK1至CLK8。时钟信号线CLK1至CLK8与每个驱动单元DU1、DU2和DU3中的多个移位寄存器单元的时钟信号端连接。例如每个驱动单元中的移位寄存器单元可以分为至少一组，每组包括级联连接的K个移位寄存器单元，第k移位寄存器单元的第一移位寄存器和第三移位寄存器的时钟信号端连接至第k时钟信号线，其中k为整数，且1≤k≤K。
例如在图19中，每8个移位寄存器单元分为一组，其中第一组包括级联连接的移位寄存器单元320_1至320_8。第一移位寄存器单元320_1中的第一移位寄存器GOA1和第三移位寄存器GOA3的时钟信号端CK连接至第一时钟信号线CLK1，第二移位寄存器单元320_2中的第一移位寄存器GOA4和第三移位寄存器GOA6的时钟信号端CK连接至第二时钟信号线CLK2，第三移位寄存器单元320_3中的第一移位寄存器GOA7和第三移位寄存器GOA9的时钟信号端CK连接至第三时钟信号线CLK3，以此类推。
第k移位寄存器单元的第二移位寄存器的时钟信号端在k≤2/K的情况下连接至第k+d时钟信号线，在2/K＜k≤K的情况下连接至第k-d时钟信号线。例如第一移位寄存器单元320_1的第二移位寄存器GOA2的时钟信号端CK连接至第五时钟信号线CLK5，第二移位寄存器单元320_2的第二移位寄存器GOA5的时钟信号端CK连接至第六时钟信号线CLK6，第三移位寄存器单元320_3的第二移位寄存器GOA8的时钟信号端CK连接至第七时钟信号线CLK7，第四移位寄存器单元320_4的第二移位寄存器GOA11的时钟信号端CK连接至第八时钟信号线CLK8，第五移位寄存器单元320_5的第二移位寄存器GOA14的时钟信号端CK连接至第一时钟信号线CLK1，以此类推。
在工作时，可以以多种分辨率模式之一向K条时钟信号线分别施加K个时钟信号并向所述多条启动信号线中的至少一条启动信号线施加启动信号。所施加的启动信号使得与所述至少一条启动信号线连接的驱动单元启动，启动的驱动单元中的多个移位寄存器根据所述K条时钟信号线上的时钟信号来产生输出信号。
下面将参考图20至图23来描述上述栅极驱动电路300的驱动方法。为了简明起见， 下面将以与启动信号线STV1连接的驱动单元DU1为例来进行说明。
图20示出了图19的栅极驱动电路在第一分辨率模式下的信号时序图。
如图20所示，在第一分辨率模式下，向时钟信号线CLK1至CLK8分别施加顺次移位的8个第一时钟信号，并且向启动信号线STV1施加第一启动信号。时钟信号线CLK1至CLK8上的第一时钟信号可以为占空比50％的周期信号，每个信号周期内有效电平持续时间为4H，其中第k+1个第一时钟信号相对于第k个第一时钟信号而移位H，其中H表示单位扫描时间。例如第二时钟信号线CLK2上的第一时钟信号相对于第一时钟信号线CLK1上的第一时钟信号移位H，第三时钟信号线CLK3上的第一时钟信号相对于第二时钟信号线CLK2上的第一时钟信号移位H，以此类推。第一启动信号的有效电平持续时间可以为4H。
结合图19，第一移位寄存器单元320_1中的移位寄存器GOA1、GOA2和GOA3分别基于第一时钟信号线CLK1、第五时钟信号线CLK5和第一时钟信号线CLK1上的第一时钟信号产生输出信号G1、G2和G3，其中输出信号G2相对于输出信号G1而移位4H，输出信号G3相对于输出信号G2而移位4H。第二移位寄存器单元320_2中的移位寄存器GOA4、GOA5和GOA6分别基于第二时钟信号线CLK2、第六时钟信号线CLK6和第二时钟信号线CLK2上的第一时钟信号产生输出信号G4、G5和G6，其中输出信号G4相对于输出信号G1而移位H，输出信号G5相对于输出信号G4而移位4H，输出信号G6相对于输出信号G5而移位4H。第三移位寄存器单元320_3中的移位寄存器GOA7、GOA8和GOA9分别基于第三时钟信号线CLK3、第七时钟信号线CLK7和第三时钟信号线CLK3上的第一时钟信号产生输出信号G7、G8和G9，其中输出信号G7相对于输出信号G4而移位H，输出信号G8相对于输出信号G7而移位4H，输出信号G9相对于输出信号G8而移位4H，以此类推。
图21示出了图19的栅极驱动电路在第二分辨率模式下的信号时序图。
如图21所示，在第二分辨率模式下，向时钟信号线CLK1至CLK8分别施加8个第二时钟信号，并且向启动信号线STV1施加第二启动信号。时钟信号线CLK1至CLK8上的第二时钟信号可以同样为占空比50％的周期信号，与第一时钟信号不同的是，每个信号周期内的有效电平持续时间为2H。第二启动信号的有效电平持续时间可以为2H。
时钟信号线CLK1至CLK8上的第二时钟信号可以分为2M组，例如M＝2的情况下分为4组，第一组包括时钟信号线CLK1和CLK2上的第二时钟信号，第二组包括时钟信号线CLK3和CLK4上的第二时钟信号，第三组包括时钟信号线CLK5和时钟信 号线CLK6上的第二时钟信号，第四组包括时钟信号线CLK7和CLK8上的第二时钟信号。时钟信号线CLK1和CLK2上的第二时钟信号同步，时钟信号线CLK3和CLK4上的第二时钟信号同步，时钟信号线CLK5和CLK6上的第二时钟信号同步，时钟信号线CLK7和CLK8上的第二时钟信号同步。时钟信号线CLK3和CLK4上的第二时钟信号相对于时钟信号线CLK1和CLK2上的第二时钟信号而移位H。时钟信号线CLK5和CLK6上的第二时钟信号相对于时钟信号线CLK3和CLK4上的第二时钟信号而移位H。时钟信号线CLK7和CLK8上的第二时钟信号相对于时钟信号线CLK5和CLK6上的第二时钟信号而移位H，以此类推。
结合图19，第一移位寄存器单元320_1中的移位寄存器GOA1、GOA2和GOA3分别基于第一时钟信号线CLK1、第五时钟信号线CLK5和第一时钟信号线CLK1上的第一时钟信号产生输出信号G1、G2和G3，其中输出信号G2相对于输出信号G1而移位2H，输出信号G3相对于输出信号G2而移位2H。第二移位寄存器单元320_2中的移位寄存器GOA4、GOA5和GOA6分别基于第二时钟信号线CLK2、第六时钟信号线CLK6和第二时钟信号线CLK2上的第一时钟信号产生输出信号G4、G5和G6，其中输出信号G4与输出信号G1同步，输出信号G5相对于输出信号G4而移位2H，输出信号G6相对于输出信号G5而移位2H。第三移位寄存器单元320_3中的移位寄存器GOA7、GOA8和GOA9分别基于第三时钟信号线CLK3、第七时钟信号线CLK7和第三时钟信号线CLK3上的第一时钟信号产生输出信号G7、G8和G9，其中输出信号G7相对于输出信号G4而移位H，输出信号G8相对于输出信号G7而移位2H，输出信号G9相对于输出信号G8而移位2H，以此类推。
图22示出了图19的栅极驱动电路在第三分辨率模式下的信号时序图。
如图22所示，在第三分辨率模式下，向时钟信号线CLK1至CLK8分别施加8个第三时钟信号，并且向启动信号线STV1施加第三启动信号。第三时钟信号同样为占空比50％的周期信号，与第一时钟信号不同的是，第三时钟信号的信号周期内的有效电平持续时间为H。时钟信号线CLK1至CLK8上的第三时钟信号可以分为M组，例如2组，其中第一组包括时钟信号线CLK1至CLK4上的第三时钟信号，第二组包括时钟信号线CLK5至CLK8上的第三时钟信号。时钟信号线CLK1至CLK4上的第三时钟信号彼此同步，时钟信号线CLK5至CLK8上的第三时钟信号彼此同步，时钟信号线CLK5至CLK8上的第三时钟信号相对于时钟信号线CLK1至CLK4上的第三时钟信号而移位H。第三启动信号的有效电平持续时间可以为H。
结合图19，第一移位寄存器单元320_1中的移位寄存器GOA1、GOA2和GOA3分别基于第一时钟信号线CLK1、第五时钟信号线CLK5和第一时钟信号线CLK1上的第一时钟信号产生输出信号G1、G2和G3，其中输出信号G2相对于输出信号G1而移位H，输出信号G3相对于输出信号G2而移位H。第二移位寄存器单元320_2中的移位寄存器GOA4、GOA5和GOA6分别基于第二时钟信号线CLK2、第六时钟信号线CLK6和第二时钟信号线CLK2上的第一时钟信号产生输出信号G4、G5和G6，其中输出信号G4与输出信号G1同步，输出信号G5相对于输出信号G4而移位H，输出信号G6相对于输出信号G5而移位H。第三移位寄存器单元320_3中的移位寄存器GOA7、GOA8和GOA9分别基于第三时钟信号线CLK3、第七时钟信号线CLK7和第三时钟信号线CLK3上的第一时钟信号产生输出信号G7、G8和G9，其中输出信号G7与输出信号G4同步，输出信号G8相对于输出信号G7而移位H，输出信号G9相对于输出信号G8而移位H。第四移位寄存器单元320_4中的移位寄存器GOA10、GOA11和GOA12分别基于第四时钟信号线CLK4、第八时钟信号线CLK8和第四时钟信号线CLK4上的第一时钟信号产生输出信号G10、G11和G12，其中输出信号G10与输出信号G7同步，输出信号G11相对于输出信号G10而移位H，输出信号G12相对于输出信号G11而移位H。
图23示出了图19的栅极驱动电路的启动信号的时序图。以图10的栅极驱动电路为例，第一驱动单元DU1与第一启动信号线STV1连接，第二驱动单元DU2与第二启动信号线STV2连接，第三驱动单元DU3与第三启动信号线STV3连接。
在第一时段P1，控制第二驱动单元DU2以第一分辨率模式工作。例如，可以如图20所示向时钟信号线CLK1至CLK8施加时钟信号并且向第二启动信号线STV2施加第一启动信号。第二驱动单元DU2响应于第二启动信号线STV2上的启动信号来根据时钟信号线CLK1至CLK8上的时钟信号产生如图20所示的输出信号G(X+1)，G(X+2)，…G2X。
在第二时段P2，控制第一驱动单元DU1以第二分辨率模式或第三分辨率模式工作。例如，可以如图21所示向时钟信号线CLK1至CLK8施加时钟信号并且向第一启动信号线STV1施加第二启动信号，第一驱动单元DU1响应于第一启动信号线STV1上的第二启动信号来根据时钟信号线CLK1至CLK8上的时钟信号产生如图21所示的输出信号G1，G2，G3，…。在一些实施例中，可以如图22所示向时钟信号线CLK1至CLK8施加时钟信号并且向第一启动信号线STV1施加第三启动信号，第一驱动单元DU1响 应于第一启动信号线STV1上的第三启动信号来根据时钟信号线CLK1至CLK8上的时钟信号产生如图22所示的输出信号G1，G2，G3，…GX。
在第三时段P3，再次控制第二驱动单元DU2以第一分辨率模式工作。例如，可以如图20所示向时钟信号线CLK1至CLK8施加时钟信号并且向第二启动信号线STV2施加第一启动信号，第二驱动单元DU2响应于第二启动信号线STV2上的第一启动信号来根据时钟信号线CLK1至CLK8上的K个时钟信号产生如图20所示的输出信号G(X+1)，G(X+2)，…G2X。
在第四时段，控制第三驱动单元DU3以第二分辨率模式或第三分辨率模式工作。例如，可以如图21所示向时钟信号线CLK1至CLK8施加时钟信号并且向第三启动信号线STV3施加第二启动信号，第三驱动单元DU3响应于第三启动信号线STV3上的第二启动信号来根据时钟信号线CLK1至CLK8上的产生如图21所示的输出信号G(2X+1)，G(2X+2)，…G3X。在一些实施例中，可以如图22所示向时钟信号线CLK1至CLK8施加时钟信号并且向第三启动信号线STV3施加第三启动信号，第三驱动单元DU3响应于第三启动信号线STV3上的第三启动信号来根据时钟信号线CLK1至CLK8上的产生如图22所示的输出信号G(2X+1)，G(2X+2)，…G3X。
可以看出，在上述过程中驱动单元DU2以较高的第一分辨率对中心区域的子像素进行了两次驱动，而驱动单元DU1和DU3以较低的第二或第三分辨率对两侧区域的子像素分别进行了一次显示驱动。由此可以实现显示面板的中心区域以较高分辨率显示，而两侧区域以较低分辨率显示。
本领域的技术人员可以理解，上面所描述的实施例都是示例性的，并且本领域的技术人员可以对其进行改进，各种实施例中所描述的结构在不发生结构或者原理方面的冲突的情况下可以进行自由组合。
在详细说明本公开的较佳实施例之后，熟悉本领域的技术人员可清楚的了解，在不脱离随附权利要求的保护范围与精神下可进行各种变化与改变，且本公开亦不受限于说明书中所举示例性实施例的实施方式。

Claims (44)

  1. 一种栅极驱动电路，包括级联连接的多个驱动单元，每个驱动单元包括：
    N个移位寄存器单元；以及
    模式控制电路，与所述N个移位寄存器单元连接，所述模式控制电路被配置为接收针对该驱动单元的控制信号，并在所述控制信号的控制下以多个分辨率模式之一对所述N个移位寄存器单元进行连接。
  2. 根据权利要求1所述的栅极驱动电路，其中，所述多个分辨率模式包括第一分辨率模式、第二分辨率模式和第三分辨率模式，所述模式控制电路被配置为：
    在第一分辨率模式下，将所述N个移位寄存器单元级联连接；
    在第二分辨率模式下，将所述N个移位寄存器单元分为M组，将所述M组级联连接，并且将每组中的移位寄存器单元并行连接；
    在第三分辨率模式下，将所述N个移位寄存器单元并行连接。
  3. 根据权利要求2所述的栅极驱动电路，其中，N＝4，M＝2，所述N个移位寄存器单元包括第一移位寄存器单元、第二移位寄存器单元、第三移位寄存器单元和第四移位寄存器单元，每个移位寄存器单元具有级联输入端和第一级联输出端，所述模式控制电路被配置为：
    在第一分辨率模式下，将第n移位寄存器单元的第一级联输出端与第n+1移位寄存器单元的级联输入端连接，并将所述第n移位寄存器单元的级联输入端与所述第n+1移位寄存器单元的级联输入端断开连接，其中1≤n≤N-1；
    在第二分辨率模式下，将第一移位寄存器单元的第一级联输出端与第二移位寄存器单元的级联输入端断开连接，将第二移位寄存器单元的第一级联输出端与第三移位寄存器单元的级联输入端连接，将第三移位寄存器单元的第一级联输出端与第四移位寄存器单元的级联输入端断开连接，将第一移位寄存器单元的级联输入端与第二移位寄存器单元的级联输入端连接，并且将第三移位寄存器单元的级联输入端与第四移位寄存器单元的级联输入端连接；以及
    在第三分辨率模式下，将第n移位寄存器单元的第一级联输出端与第n+1移位寄存器单元的级联输入端断开连接，并将所述第n移位寄存器单元的级联输入端与所述第n+1移位寄存器单元的级联输入端连接。
  4. 根据权利要求3所述的栅极驱动电路，其中，所述第一移位寄存器单元、第二移位寄存器单元、第三移位寄存器单元和第四移位寄存器单元各自还具有复位端和第 二级联输出端，所述模式控制电路还被配置为：
    在第一分辨率模式下，将第n移位寄存器单元的复位端与第n+1移位寄存器单元的第二级联输出端连接，并将所述第n移位寄存器单元的复位端与所述第n+1移位寄存器单元的复位端断开连接，
    在第二分辨率模式下，将第一移位寄存器单元的复位端与第二移位寄存器单元的第二级联输出端断开连接，将第二移位寄存器单元的复位端与第三移位寄存器单元的第二级联输出端连接，将第三移位寄存器单元的复位端与第四移位寄存器单元的第二级联输出端断开连接，将第一移位寄存器单元的复位端与第二移位寄存器单元的复位端连接，将第二移位寄存器单元的复位端与第三移位寄存器单元的复位端断开连接，并且将第三移位寄存器单元的复位端与第四移位寄存器单元的复位端连接；以及
    在第三分辨率模式下，将第n移位寄存器单元的复位端与第n+1移位寄存器单元的第二级联输出端断开连接，并将所述第n移位寄存器单元的复位端与所述第n+1移位寄存器单元的复位端连接。
  5. 根据权利要求3或4所述的栅极驱动电路，其中，所述控制信号包括第一控制信号、第二控制信号、第三控制信号和第四控制信号，所述模式控制电路包括：
    第一晶体管，第一晶体管的栅极连接为接收第一控制信号，第一晶体管的第一极连接第一移位寄存器单元的第一级联输出端，第一晶体管的第二极连接第二移位寄存器单元的级联输入端；
    第二晶体管，第二晶体管的栅极连接为接收第二控制信号，第二晶体管的第一极连接第一移位寄存器单元的级联输入端，第二晶体管的第二极连接第二移位寄存器单元的级联输入端；
    第三晶体管，第三晶体管的栅极连接为接收第三控制信号，第三晶体管的第一极连接第二移位寄存器单元的第一级联输出端，第三晶体管的第二极连接第三移位寄存器单元的级联输入端；
    第四晶体管，第四晶体管的栅极连接为接收第四控制信号，第四晶体管的第一极连接第一移位寄存器单元的级联输入端，第四晶体管的第二极连接第三移位寄存器单元的级联输入端；
    第五晶体管，第五晶体管的栅极连接为第一控制信号，第五晶体管的第一极连接第三移位寄存器单元的第一级联输出端，第五晶体管的第二极连接第四移位寄存器单元的级联输入端；以及
    第六晶体管，第六晶体管的栅极连接为接收第二控制信号，第六晶体管的第一极连接第三移位寄存器单元的级联输入端，第六晶体管的第二极连接第四晶体管的级联输入端。
  6. 根据权利要求5所述的栅极驱动电路，其中，所述控制信号还包括第五控制信号，所述模式控制电路还包括：
    第七晶体管，第七晶体管的栅极连接为接收第一控制信号，第七晶体管的第一极连接第一移位寄存器单元的复位端，第七晶体管的第二极连接第二移位寄存器单元的第二级联输出端；
    第八晶体管，第八晶体管的栅极连接为接收第五控制信号，第八晶体管的第一极连接第一移位寄存器单元的复位端，第八晶体管的第二极连接第二移位寄存器单元的复位端；
    第九晶体管，第九晶体管的栅极连接为接收第三控制信号，第九晶体管的第一极连接第二移位寄存器单元的复位端，第九晶体管的第二极连接第三移位寄存器单元的第二级联输出端；
    第十晶体管，第十晶体管的栅极连接为接收第四控制信号，第十晶体管的第一极连接第二移位寄存器单元的复位端，第十晶体管的第二极连接第三移位寄存器单元的复位端；
    第十一晶体管，第十一晶体管的栅极连接为接收第一控制信号，第十一晶体管的第一极连接第三移位寄存器单元的复位端，第十一晶体管的第二极连接第四移位寄存器单元的第二级联输出端；以及
    第十二晶体管，第十二晶体管的栅极连接为接收第二控制信号，第十二晶体管的第一极连接第三移位寄存器单元的复位端，第十二晶体管的第二极连接第四移位寄存器单元的复位端。
  7. 根据权利要求3或4所述的栅极驱动电路，其中，第i级驱动单元中的第N移位寄存器单元的第一级联输出端与第i+1级驱动单元中的第一移位寄存器单元的级联输入端连接。
  8. 根据权利要求7所述的栅极驱动电路，其中，第i级驱动单元中的第N移位寄存器单元的复位端与第i+1级驱动单元中的第一移位寄存器单元的第二级联输出端连接。
  9. 根据权利要求1所述的栅极驱动电路，其中，所述多个驱动单元被划分为多组， 每组驱动单元连接一组控制信号线以接收针对该组驱动单元的控制信号。
  10. 根据权利要求3或4所述的栅极驱动电路，其中，每个移位寄存器单元包括第一移位寄存器、第二移位寄存器和第三移位寄存器，其中，
    所述第一移位寄存器的输入端作为所述移位寄存器单元的级联输入端，所述第一移位寄存器的输出端作为所述移位寄存器单元的第二级联输出端；
    所述第二移位寄存器的输入端与所述第一移位寄存器的输出端连接；并且
    所述第三移位寄存器的输入端与所述第二移位寄存器的输出端连接，所述第三移位寄存器的输出端作为所述移位寄存器单元的第一级联输出端。
  11. 根据权利要求10所述的栅极驱动电路，其中，所述第一移位寄存器、第二移位寄存器和第三移位寄存器中的每一个包括：
    输入子电路，连接所述移位寄存器的输入端和上拉节点，并且被配置为将输入端的信号提供至上拉节点；
    输出子电路，连接所述上拉节点、所述移位寄存器的时钟信号端和输出端，并且被配置为在所述上拉节点的电位的控制下将所述时钟信号端的信号提供至所述输出端；
    控制子电路，连接所述上拉节点、所述输出端和所述移位寄存器的下拉节点，并且被配置为基于所述上拉节点的电位控制所述下拉节点的电位，并在所述下拉节点的电位控制下下拉所述输出端的电位。
  12. 根据权利要求11所述的栅极驱动电路，其中，所述第一移位寄存器、第二移位寄存器和第三移位寄存器中的每一个还包括：
    复位子电路，连接所述上拉节点和所述移位寄存器的复位端，并且被配置为根据所述复位端的复位信号将上拉节点复位，其中移位寄存器单元中第三移位寄存器的复位端作为所述移位寄存器单元的复位端。
  13. 一种根据权利要求1至12中任一项权利要求所述的栅极驱动电路的驱动方法，包括：
    多个驱动单元中每个驱动单元的模式控制电路接收针对该驱动单元的控制信号，并在所述控制信号的控制下以多个分辨率模式之一对所述N个移位寄存器单元进行连接，
    每个驱动单元中连接后的N个移位寄存器单元产生输出信号。
  14. 根据权利要求13所述的方法，其中，所述多个分辨率模式包括第一分辨率模式、第二分辨率模式和第三分辨率模式，其中，
    在第一分辨率模式下，模式控制电路将N个移位寄存器单元级联连接，所述N个移位寄存器单元产生顺序移位的输出信号；
    在第二分辨率模式下，所述模式控制电路将所述N个移位寄存器单元分为M组，将所述M组级联连接，并且将每组中的移位寄存器单元并行连接，每组中的移位寄存器单元并行地产生输出信号，且第m+1组移位寄存器单元产生的一组输出信号相对于第m组移位寄存器单元产生的一组输出信号而移位，其中m为整数且1≤m≤M-1；
    在第三分辨率模式下，所述模式控制电路将所述N个移位寄存器单元并行连接，所述N个移位寄存器单元并行地产生输出信号。
  15. 根据权利要求14所述的方法，其中，N＝4，M＝2，所述N个移位寄存器单元包括第一移位寄存器单元、第二移位寄存器单元、第三移位寄存器单元和第四移位寄存器单元，其中，
    在第一分辨率模式下，所述模式控制电路将第n移位寄存器单元的第一级联输出端与第n+1移位寄存器单元的级联输入端连接，并将所述第n移位寄存器单元的级联输入端与所述第n+1移位寄存器的级联输入端断开连接，其中1≤n≤N-1；
    在第二分辨率模式下，所述模式控制电路将第一移位寄存器单元的第一级联输出端与第二移位寄存器单元的级联输入端断开连接，将第二移位寄存器单元的级联输入端与第一移位寄存器单元的级联输入端连接；将第二移位寄存器单元的第一级联输出端与第三移位寄存器单元的级联输入端连接，将第三移位寄存器单元的级联输入端与第二移位寄存器单元的级联输入端断开连接；并且将第三移位寄存器单元的第一级联输出端与第四移位寄存器单元的级联输入端断开连接，将第三移位寄存器单元的级联输入端与第四移位寄存器单元的级联输入端连接；以及
    在第三分辨率模式下，模式控制电路将第n移位寄存器单元的第一级联输出端与第n+1移位寄存器单元的级联输入端断开连接，并将所述第n移位寄存器单元的级联输入端与所述第n+1移位寄存器单元的级联输入端连接。
  16. 根据权利要求15所述的方法，还包括：
    在第一分辨率模式下，模式控制电路将第n移位寄存器单元的复位端与第n+1移位寄存器的第二级联输出端连接，并将所述第n移位寄存器单元的复位端与所述第n+1移位寄存器单元的复位端断开连接，
    在第二分辨率模式下，模式控制电路将第一移位寄存器单元的复位端与第二移位寄存器单元的第二级联输出端断开连接，将第二移位寄存器单元的复位端与第三移位 寄存器单元的第二级联输出端连接，模式控制电路将第三移位寄存器单元的复位端与第四移位寄存器单元的第二级联输出端断开连接，将第一移位寄存器单元的复位端与第二移位寄存器单元的复位端连接，并且将第三移位寄存器单元的复位端与第四移位寄存器单元的复位端连接；以及
    在第三分辨率模式下，模式控制电路将第n移位寄存器单元的复位端与第n+1移位寄存器单元的第二级联输出端断开连接，并将所述第n移位寄存器单元的复位端与所述第n+1移位寄存器单元的复位端连接。
  17. 根据权利要求15所述的方法，其中，所述模式控制电路包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管和第六晶体管，其中，
    在第一分辨率模式下，第一控制信号和第三控制信号为第一电平，第二控制信号和第四控制信号为第二电平，第一晶体管、第三晶体管和第五晶体管导通，并且第二晶体管、第四晶体管和第六晶体管关断；
    在第二分辨率模式下，第二控制信号和第三控制信号为第一电平，第一控制信号和第四控制信号为第二电平，第二晶体管、第三晶体管和第六晶体管导通，第一晶体管、第四晶体管和第五晶体管关断；以及
    在第三分辨率模式下，第二控制信号和第四控制信号为第一电平，第一控制信号和第三控制信号为第二电平，第二晶体管、第四晶体管和第六晶体管导通，第一晶体管、第三晶体管和第五晶体管关断。
  18. 根据权利要求17所述的方法，其中，所述模式控制电路还包括第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管和第十二晶体管，其中，
    在第一分辨率模式下，第五控制信号为第二电平，第七晶体管、第九晶体管和第十一晶体管导通，第八晶体管、第十晶体管和第十二晶体管关断；
    在第二分辨率模式下，第五控制信号为第一电平，第八晶体管、第九晶体管和第十二晶体管导通，第七晶体管、第十晶体管和第十一晶体管关断；以及
    在第三分辨率模式下，第五控制信号为第二电平，第十晶体管和第十二晶体管导通，第七晶体管、第八晶体管、第九晶体管和第十一晶体管关断。
  19. 一种栅极驱动电路，包括：
    多个驱动单元，每个驱动单元包括级联连接的多个移位寄存器；
    多条启动信号线，与所述多个驱动单元一一对应地连接，其中每条启动信号线连接至对应驱动单元中的第一级移位寄存器；
    K条时钟信号线，与每个驱动单元中的多个移位寄存器连接，其中K为大于1的整数；以及
    模式控制电路，与所述K条时钟信号线连接，所述模式控制电路被配置为接收K个初始时钟信号和控制信号，在所述控制信号的控制下以第一分辨率模式、第二分辨率模式和第三分辨率模式之一来基于所述K个初始时钟信号产生K个时钟信号，并将产生的K个时钟信号分别提供给所述K条时钟信号线。
  20. 根据权利要求19所述的栅极驱动电路，其中，所述模式控制电路被配置为：
    在第一分辨率模式下，基于所述K个初始时钟信号产生顺序移位的K个第一时钟信号；
    在第二分辨率模式下，基于所述K个初始时钟信号产生分成2M组的K个第二时钟信号，每组中的多个第二时钟信号同步，第m+1组第二时钟信号相对于第m组第二时钟信号而移位；
    在第三分辨率模式下，基于所述K个初始时钟信号产生分成M组的K个第三时钟信号，每组中的多个第三时钟信号同步，第m’+1组第三时钟信号相对于第m’组第三时钟信号而移位，其中M为大于1的整数，m和m’均为整数，1≤m≤2M-1，且1≤m’≤M-1。
  21. 根据权利要求20所述的栅极驱动电路，其中，K＝8，M＝2，所述控制信号包括第一控制信号、第二控制信号、第三控制信号和第四控制信号，所述模式控制电路包括：
    第一时钟输入端至第八时钟输入端，分别连接为接收8个初始时钟信号；
    第一时钟输出端至第八时钟输出端，与8条时钟信号线一一对应地连接；
    第一模式控制子电路，被配置为在第一控制信号的控制下，将第二时钟输入端与第二时钟输出端连接，将第四时钟输入端与第四时钟输出端连接，将第七时钟输入端与第七时钟输出端连接，以及将第八时钟输入端与第八时钟输出端连接；
    第二模式控制子电路，被配置为在第二控制信号的控制下，将第三时钟输入端与第三时钟输出端连接，以及将第六时钟输入端与第六时钟输出端连接；
    第三模式控制子电路，被配置为在第三控制信号的控制下将第一时钟输出端与第二时钟输出端连接，将第三时钟输出端与第四时钟输出端连接，将第五时钟输出端与第六时钟输出端连接，以及将第七时钟输出端与第八时钟输出端连接；
    第四模式控制子电路，被配置为在第四控制信号的控制下将第二时钟输出端与第 三时钟输出端连接，以及将第六时钟输出端与第七时钟输出端连接。
  22. 根据权利要求21所述的栅极驱动电路，其中，所述第一模式控制子电路包括：
    第一晶体管，第一晶体管的栅极连接为接收第一控制信号，第一晶体管的第一极连接第二时钟输入端，第一晶体管的第二极连接第二时钟输出端；
    第二晶体管，第二晶体管的栅极连接为接收第一控制信号，第二晶体管的第一极连接第四时钟输入端，第二晶体管的第二极连接第四时钟输出端；
    第三晶体管，第三晶体管的栅极连接为接收第一控制信号，第三晶体管的第一极连接第七时钟输入端，第三晶体管的第二极连接第七时钟输出端；以及
    第四晶体管，第四晶体管的栅极连接为接收第一控制信号，第四晶体管的第一极连接第八时钟输入端，第四晶体管的第二极连接第八时钟输出端。
  23. 根据权利要求21所述的栅极驱动电路，其中，所述第二模式控制子电路包括：
    第五晶体管，第五晶体管的栅极连接为接收第二控制信号，第五晶体管的第一极连接第三时钟输入端，第二极连接第三时钟输出端；以及
    第六晶体管，第六晶体管的栅极连接为接收第二控制信号，第六晶体管的第一极连接第六时钟输入端，第六晶体管的第二极连接第六时钟输出端。
  24. 根据权利要求21所述的栅极驱动电路，其中，所述第三模式控制子电路包括：
    第七晶体管，第七晶体管的栅极连接为接收第三控制信号，第七晶体管的第一极连接第一时钟输出端，第二极连接第二时钟输出端；
    第八晶体管，第八晶体管的栅极连接为接收第三控制信号，第八晶体管的第一极连接第三时钟输出端，第二极连接第四时钟输出端；
    第九晶体管，第九晶体管的栅极连接为接收第三控制信号，第九晶体管的第一极连接第五时钟输出端，第二极连接第六时钟输出端；以及
    第十晶体管，第十晶体管的栅极连接为接收第三控制信号，第十晶体管的第一极连接第七时钟输出端，第二极连接第八时钟输出端。
  25. 根据权利要求21所述的栅极驱动电路，其中，所述第四模式控制子电路包括：
    第十一晶体管，第十一晶体管的栅极连接为接收第四控制信号，第十一晶体管的第一极连接第二时钟输出端，第二极连接第三时钟输出端；以及
    第十二晶体管，第十二晶体管的栅极连接为接收第四控制信号，第十二晶体管的第一极连接第六时钟输出端，第二极连接第七时钟输出端。
  26. 根据权利要求19至25中任一项权利要求所述的栅极驱动电路，其中，
    在每个驱动单元中，第n级移位寄存器的输出端连接至第n+1级移位寄存器的输入端，第n+1级移位寄存器的输出端连接至第n级移位寄存器的复位端，其中n为大于或等于1的整数；并且
    每个驱动单元中的多个移位寄存器分为至少一组，每组包括级联连接的K个移位寄存器，所述K个移位寄存器的时钟信号端与所述K条时钟信号线一一对应地连接。
  27. 一种根据权利要求19至26中任一项权利要求所述的栅极驱动电路的驱动方法，包括：
    模式控制电路在控制信号的控制下以多种分辨率模式之一来基于所述K个初始时钟信号产生K个时钟信号，并将产生的K个时钟信号分别提供给所述K条时钟信号线；以及
    向多条启动信号线中的至少一条启动信号线施加启动信号，以启动与所述至少一条启动信号线连接的驱动单元，被启动的驱动单元中的多个移位寄存器根据所述K条时钟信号线上的时钟信号来产生输出信号。
  28. 根据权利要求27所述的方法，其中，所述多个分辨率模式包括第一分辨率模式、第二分辨率模式和第三分辨率模式，其中，
    在第一分辨率模式下，模式控制电路基于K个初始时钟信号产生顺序移位的K个第一时钟信号并分别提供给K条时钟信号线；
    在第二分辨率模式下，模式控制电路基于K个初始时钟信号产生K个第二时钟信号并分别提供给所述K条时钟信号线，所述K个第二时钟信号分成2M组，每组中的多个第二时钟信号同步，第m+1组第二时钟信号相对于第m组第二时钟信号而移位；
    在第三分辨率模式下，模式控制电路基于K个初始时钟信号产生K个第三时钟信号并分别提供给所述K条时钟信号线，所述K个第三时钟信号分成M组，每组中的多个第三时钟信号同步，第m’+1组第三时钟信号相对于第m’组第三时钟信号而移位，其中M为大于1的整数，m和m’均为整数，1≤m≤2M-1，且1≤m’≤M-1。
  29. 根据权利要求28所述的方法，其中，K＝8，M＝2，其中，
    在第一分辨率模式下，第一模式控制子电路将第二时钟输入端与第二时钟输出端连接，将第四时钟输入端与第四时钟输出端连接，将第七时钟输入端与第七时钟输出端连接，以及将第八时钟输入端与第八时钟输出端连接；第二模式控制子电路将第三时钟输入端与第三时钟输出端连接，以及将第六时钟输入端与第六时钟输出端连接；
    在第二分辨率模式下，第二模式控制子电路将第三时钟输入端与第三时钟输出端 连接，以及将第六时钟输入端与第六时钟输出端连接；第三模式控制子电路将第一时钟输出端与第二时钟输出端连接，将第三时钟输出端与第四时钟输出端连接，将第五时钟输出端与第六时钟输出端连接，以及将第七时钟输出端与第八时钟输出端连接；
    在第三分辨率模式下，第三模式控制子电路将第一时钟输出端与第二时钟输出端连接，将第三时钟输出端与第四时钟输出端连接，将第五时钟输出端与第六时钟输出端连接，以及将第七时钟输出端与第八时钟输出端连接；第四模式控制子电路将第二时钟输出端与第三时钟输出端连接，以及将第六时钟输出端与第七时钟输出端连接。
  30. 根据权利要求29所述的方法，其中，
    在第一分辨率模式下，第一控制信号和第二控制信号为第一电平，第三控制信号和第四控制信号为第二电平，第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管和第六晶体管导通，第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管和第十二晶体管关断；
    在第二分辨率模式下，第一控制信号和第四控制信号为第二电平，第二控制信号和第三控制信号为第一电平，第一晶体管、第二晶体管、第三晶体管、第四晶体管、第十一晶体管和第十二晶体管关断，第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管和第十晶体管导通；
    在第三分辨率模式下，第一控制信号和第二控制信号为第二电平，第三控制信号和第四控制信号为第一电平，第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管和第六晶体管关断，第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管和第十二晶体管导通。
  31. 根据权利要求27至30中任一项权利要求所述的方法，其中，所述K个初始时钟信号是占空比为50％的周期信号，其中第k+1初始时钟信号相对于第k初始时钟信号移位单位扫描时间，每个初始时钟信号的有效电平持续时间为4倍单位扫描时间。
  32. 根据权利要求27至30中任一项权利要求所述的方法，其中，所述K个初始时钟信号是占空比为12.5％的周期信号，其中第k+1初始时钟信号相对于第k初始时钟信号移位单位扫描时间，每个初始时钟信号的有效电平持续时间为单位扫描时间。
  33. 一种栅极驱动电路，包括：
    多个驱动单元，每个驱动单元包括级联连接的多个移位寄存器单元，在所述多个移位寄存器单元中，第n级移位寄存器单元的级联输出端连接至第n+d级移位寄存器单元的级联输入端；
    多条启动信号线，与所述多个驱动单元一一对应地连接，其中每条启动信号线连接至对应驱动单元中的前d级移位寄存器单元的级联输入端，其中n和d均为大于或等于1的整数；
    K条时钟信号线，与每个驱动单元中的多个移位寄存器单元的时钟信号端连接，其中K＝2d。
  34. 根据权利要求33所述的栅极驱动电路，其中，每个移位寄存器单元包括第一移位寄存器、第二移位寄存器和第三移位寄存器，其中，
    第一移位寄存器的输入端作为移位寄存器单元的级联输入端，第一移位寄存器的输出端连接至第二移位寄存器的输入端，第二移位寄存器的输出端连接至第三移位寄存器的输入端，第三移位寄存器的输出端作为所述移位寄存器单元的级联输出端；并且
    第一移位寄存器的时钟信号端、第二移位寄存器的时钟信号端和第三移位寄存器的时钟信号端作为所述移位寄存器单元的时钟信号端。
  35. 根据权利要求34所述的栅极驱动电路，其中，每个驱动单元中的多个移位寄存器单元分为至少一组，每组包括级联连接的K个移位寄存器单元，在所述K个移位寄存器单元中：
    第k移位寄存器单元的第一移位寄存器和第三移位寄存器的时钟信号端连接至第k时钟信号线，其中k为整数，且1≤k≤K；
    所述第k移位寄存器单元的第二移位寄存器的时钟信号端在k≤2/K的情况下连接至第k+d时钟信号线，在2/K＜k≤K的情况下连接至第k-d时钟信号线。
  36. 根据权利要求34所述的栅极驱动电路，其中，所述第一移位寄存器、第二移位寄存器和第三移位寄存器中的每一个包括：
    输入子电路，连接所述移位寄存器的输入端和上拉节点，并且被配置为将输入端的信号提供至上拉节点；
    输出子电路，连接所述上拉节点、所述移位寄存器的时钟信号端和输出端，并且被配置为在所述上拉节点的电位的控制下将所述时钟信号端的信号提供至所述输出端；
    控制子电路，连接所述上拉节点、所述输出端和所述移位寄存器的下拉节点，并且被配置为基于所述上拉节点的电位控制所述下拉节点的电位，并在所述下拉节点的电位控制下下拉所述输出端的电位。
  37. 根据权利要求33至36中任一项权利要求所述的栅极驱动电路，其中K＝8，d＝4。
  38. 一种根据权利要求33至37中任一项权利要求所述的栅极驱动电路的驱动方法，包括：
    以多种分辨率模式之一，向K条时钟信号线分别施加K个时钟信号并且向所述多条启动信号线中的至少一条启动信号线施加启动信号，
    所施加的启动信号使得与所述至少一条启动信号线连接的驱动单元启动，启动的驱动单元中的多个移位寄存器根据所述K条时钟信号线上的时钟信号来产生输出信号。
  39. 根据权利要求38所述的方法，其中，
    在第一分辨率模式下，向所述K条时钟信号线分别施加顺次移位的K个第一时钟信号，并且向所述多条启动信号线中的至少一条启动信号线施加第一启动信号；
    在第二分辨率模式下，向所述K条时钟信号线分别施加K个第二时钟信号，并且向所述多条启动信号线中的至少一条启动信号线施加第二启动信号，其中所述K个第二时钟信号分为2M组，每组中的多个第二时钟信号同步，第m+1组第二时钟信号相对于第m组第二时钟信号而移位；
    在第三分辨率模式下，向所述K条时钟信号线分别施加K个第三时钟信号，并且向所述多条启动信号线中的至少一条启动信号线施加第三启动信号，其中所述K个第三时钟信号分为M组，每组中的多个第三时钟信号同步，第m’+1组第三时钟信号相对于第m’组第三时钟信号而移位，其中M为大于1的整数，m和m’均为整数，1≤m≤2M-1，且1≤m’≤M-1。
  40. 根据权利要求39所述的方法，其中，第一时钟信号、第二时钟信号和第三时钟信号均为占空比50％的周期信号，其中，
    第一时钟信号的信号周期内的有效电平持续时间为4H，其中第k+1个第一时钟信号相对于第k个第一时钟信号而移位H，其中H表示单位扫描时间；
    第二时钟信号的信号周期内的有效电平持续时间为2H，其中m+1组第二时钟信号相对于第m组第二时钟信号而移位H；
    第三时钟信号的信号周期内的有效电平持续时间为H，其中m’+1组第三时钟信号相对于第m’组第三时钟信号而移位H。
  41. 根据权利要求40所述的方法，其中，第一启动信号的有效电平持续时间为4H，第二启动信号的有效电平持续时间为2H，第三启动信号的有效电平持续时间为H。
  42. 根据权利要求38至41中任一项权利要求所述的方法，其中，所述多个驱动单元包括第一驱动单元、第二驱动单元和第三驱动单元，所述多条启动信号线包括分别 与所述第一驱动单元、第二驱动单元和第三驱动单元连接的第一启动信号线、第二启动信号线和第三启动信号线，其中，
    在第一时段，以第一分辨率模式向K条时钟信号线施加K个时钟信号并且向第二启动信号线施加第一启动信号，第二驱动单元响应于所施加的第一启动信号来根据所施加的K个时钟信号产生输出信号；
    在第二时段，以第二分辨率模式或第三分辨率模式向K条时钟信号线施加K个时钟信号并且向第一启动信号线施加第二启动信号或第三启动信号，第一驱动单元响应于所施加的第二启动信号或第三启动信号来根据所施加的K个时钟信号产生输出信号；
    在第三时段，以第一分辨率模式向K条时钟信号线施加K个时钟信号并且向第二启动信号线施加第一启动信号，第二驱动单元响应于所施加的第一启动信号来根据所施加的K个时钟信号产生输出信号；
    在第四时段，以第二分辨率模式或第三分辨率模式向K条时钟信号线施加K个时钟信号并且向第三启动信号线施加第三启动信号，第三驱动单元响应于所施加的第三启动信号来根据所施加的K个时钟信号产生输出信号。
  43. 根据权利要求38至41中任一项权利要求所述的方法，其中，K＝8，M＝2。
  44. 一种显示面板，包括根据权利要求1-12、19-26、33-37中任一项权利要求所述的栅极驱动电路。
PCT/CN2021/074092 2021-01-28 2021-01-28 栅极驱动电路及其驱动方法和显示面板 WO2022160160A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN202180000088.5A CN115398518A (zh) 2021-01-28 2021-01-28 栅极驱动电路及其驱动方法和显示面板
US17/609,504 US11837133B2 (en) 2021-01-28 2021-01-28 Gate driving circuit, method of driving gate driving circuit, and display panel
PCT/CN2021/074092 WO2022160160A1 (zh) 2021-01-28 2021-01-28 栅极驱动电路及其驱动方法和显示面板
US18/491,531 US20240105091A1 (en) 2021-01-28 2023-10-20 Gate driving circuit, method of driving gate driving circuit, and display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/074092 WO2022160160A1 (zh) 2021-01-28 2021-01-28 栅极驱动电路及其驱动方法和显示面板

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US17/609,504 A-371-Of-International US11837133B2 (en) 2021-01-28 2021-01-28 Gate driving circuit, method of driving gate driving circuit, and display panel
US18/491,531 Continuation US20240105091A1 (en) 2021-01-28 2023-10-20 Gate driving circuit, method of driving gate driving circuit, and display panel

Publications (1)

Publication Number Publication Date
WO2022160160A1 true WO2022160160A1 (zh) 2022-08-04

Family

ID=82654044

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/074092 WO2022160160A1 (zh) 2021-01-28 2021-01-28 栅极驱动电路及其驱动方法和显示面板

Country Status (3)

Country Link
US (2) US11837133B2 (zh)
CN (1) CN115398518A (zh)
WO (1) WO2022160160A1 (zh)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101777301A (zh) * 2010-01-15 2010-07-14 友达光电股份有限公司 栅极驱动电路
CN104978944A (zh) * 2015-08-06 2015-10-14 京东方科技集团股份有限公司 一种显示面板的驱动方法、显示面板及显示装置
CN106157873A (zh) * 2016-08-31 2016-11-23 昆山工研院新型平板显示技术中心有限公司 一种栅极驱动装置、驱动方法及显示面板
CN106548745A (zh) * 2017-01-19 2017-03-29 京东方科技集团股份有限公司 一种阵列基板、显示面板及显示装置
CN106710508A (zh) * 2017-02-17 2017-05-24 京东方科技集团股份有限公司 移位寄存器、栅线驱动方法、阵列基板和显示装置
WO2018149116A1 (zh) * 2017-02-17 2018-08-23 京东方科技集团股份有限公司 移位寄存器、栅线驱动方法、阵列基板和显示装置
CN109036246A (zh) * 2018-08-10 2018-12-18 京东方科技集团股份有限公司 一种显示面板、其显示方法及显示装置
US20190279574A1 (en) * 2017-04-27 2019-09-12 Bob Technology Group Co., Ltd. Array substrate, display panel, display device and driving method

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103680439B (zh) * 2013-11-27 2016-03-16 合肥京东方光电科技有限公司 一种栅极驱动电路和显示装置
CN109885273B (zh) 2019-03-08 2022-02-15 南昌黑鲨科技有限公司 图像显示系统及显示方法
CN109801586B (zh) * 2019-03-26 2021-01-26 京东方科技集团股份有限公司 显示控制器、显示控制方法及系统、显示装置
CN111816107B (zh) * 2019-04-11 2021-12-28 合肥京东方卓印科技有限公司 移位寄存器单元、栅极驱动电路及其方法、显示装置
KR102622270B1 (ko) * 2019-07-01 2024-01-09 보에 테크놀로지 그룹 컴퍼니 리미티드 디스플레이 패널, 디스플레이 디바이스 및 구동 방법
US11482168B2 (en) * 2019-08-08 2022-10-25 Hefei Boe Joint Technology Co., Ltd. Gate driving unit, gate driving circuit, display substrate, display panel and display device
EP4020448A4 (en) * 2019-08-21 2022-09-07 BOE Technology Group Co., Ltd. DISPLAY SUBSTRATE, DISPLAY DEVICE AND METHOD OF MAKING DISPLAY SUBSTRATE
CN111091775B (zh) * 2020-03-22 2020-09-01 深圳市华星光电半导体显示技术有限公司 一种显示面板以及电子设备
CN113971940B (zh) * 2020-07-24 2023-03-10 京东方科技集团股份有限公司 栅驱动电路和显示面板

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101777301A (zh) * 2010-01-15 2010-07-14 友达光电股份有限公司 栅极驱动电路
CN104978944A (zh) * 2015-08-06 2015-10-14 京东方科技集团股份有限公司 一种显示面板的驱动方法、显示面板及显示装置
CN106157873A (zh) * 2016-08-31 2016-11-23 昆山工研院新型平板显示技术中心有限公司 一种栅极驱动装置、驱动方法及显示面板
CN106548745A (zh) * 2017-01-19 2017-03-29 京东方科技集团股份有限公司 一种阵列基板、显示面板及显示装置
CN106710508A (zh) * 2017-02-17 2017-05-24 京东方科技集团股份有限公司 移位寄存器、栅线驱动方法、阵列基板和显示装置
WO2018149116A1 (zh) * 2017-02-17 2018-08-23 京东方科技集团股份有限公司 移位寄存器、栅线驱动方法、阵列基板和显示装置
US20190279574A1 (en) * 2017-04-27 2019-09-12 Bob Technology Group Co., Ltd. Array substrate, display panel, display device and driving method
CN109036246A (zh) * 2018-08-10 2018-12-18 京东方科技集团股份有限公司 一种显示面板、其显示方法及显示装置

Also Published As

Publication number Publication date
US20230129625A1 (en) 2023-04-27
US11837133B2 (en) 2023-12-05
CN115398518A (zh) 2022-11-25
US20240105091A1 (en) 2024-03-28

Similar Documents

Publication Publication Date Title
EP3571691B1 (en) Shift register unit, gate drive circuit and method of driving the same
US7880714B2 (en) Shift register and method for driving the same
JP5078533B2 (ja) ゲート線駆動回路
KR101167663B1 (ko) 게이트 구동 회로 및 이를 포함하는 액정 표시 장치
KR102383363B1 (ko) 게이트 구동 회로 및 이를 포함하는 표시 장치
WO2017181700A1 (zh) 移位寄存器单元、栅极驱动装置、显示装置和驱动方法
WO2015007052A1 (zh) Goa电路、阵列基板、显示装置及驱动方法
CN111477159B (zh) 显示基板、显示面板、显示装置和显示驱动方法
JPH10153986A (ja) 表示装置
CN108022560B (zh) 栅极驱动电路及其驱动方法、显示基板和显示装置
WO2020168798A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及其驱动方法和显示装置
TW201911272A (zh) 影像顯示面板及其閘極驅動電路
JP2009134814A (ja) シフトレジスタおよびそれを備える画像表示装置
WO2017063269A1 (zh) 栅极驱动基板和使用栅极驱动基板的液晶显示器
WO2021022540A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路、显示装置
WO2021190038A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路
WO2021016942A1 (zh) 显示面板、显示装置以及驱动方法
WO2022199167A1 (zh) 栅极驱动电路、驱动装置和显示装置
WO2021022437A1 (zh) 移位寄存器单元、栅极驱动电路、显示面板、显示装置以及驱动方法
JPH10171421A (ja) 画像表示装置、画像表示方法及び表示駆動装置並びにそれを用いた電子機器
WO2022160160A1 (zh) 栅极驱动电路及其驱动方法和显示面板
KR101319322B1 (ko) 액정표시장치
CN113314076B (zh) 移位寄存器单元、栅极驱动电路及其控制方法
US11462174B2 (en) Plurality of scan driver having shared scan lines and display apparatus including the same
JP4041144B2 (ja) 表示装置の駆動回路及び液晶表示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21921780

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 14.11.2023)

122 Ep: pct application non-entry in european phase

Ref document number: 21921780

Country of ref document: EP

Kind code of ref document: A1