WO2018196192A1 - 阵列基板制程和阵列基板 - Google Patents

阵列基板制程和阵列基板 Download PDF

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Publication number
WO2018196192A1
WO2018196192A1 PCT/CN2017/094547 CN2017094547W WO2018196192A1 WO 2018196192 A1 WO2018196192 A1 WO 2018196192A1 CN 2017094547 W CN2017094547 W CN 2017094547W WO 2018196192 A1 WO2018196192 A1 WO 2018196192A1
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Prior art keywords
layer
filter
photoresist
metal
organic photosensitive
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PCT/CN2017/094547
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English (en)
French (fr)
Inventor
陈猷仁
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惠科股份有限公司
重庆惠科金渝光电科技有限公司
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Priority to US15/743,813 priority Critical patent/US10522571B2/en
Publication of WO2018196192A1 publication Critical patent/WO2018196192A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/50—Protective arrangements

Definitions

  • the present disclosure relates to the field of display screen technology, for example, to an array substrate process and an array substrate.
  • More and more liquid crystal panels need to use a color filter on Array (COA) process on an array of Thin Film Transistors (TFTs) to improve the surface quality of the LCD panel or simplify the structure of the upper panel.
  • COA color filter on Array
  • TFTs Thin Film Transistors
  • planarization layer (Over Coat, OC) structure of the board in the In-Plane Switching (IPS) liquid crystal mode is simplified.
  • the Array process of the COA structure of the liquid crystal panel in the related art is as follows: the conventional COA structure performs the molding process of the first insulating layer after the gate, source and drain processes are completed; the color photoresist layer is completed (including Coating, exposure and development steps for red, green and blue photoresist; if it is a liquid crystal panel with white, red, green and blue (White, Red, Green, Blue, WRGB) technology, It is also necessary to perform the coating, exposure and development steps of the transparent photoresist layer.
  • the second insulating layer is formed, a photoresist layer (also called photoresist) is applied, and the photoresist layer is coated by a mask with a via hole.
  • a photoresist layer also called photoresist
  • PE pixel electrode
  • the thin film transistor liquid crystal display industry Due to the complicated process and huge equipment investment, the thin film transistor liquid crystal display industry has high production cost. With the increasingly fierce market competition, reducing the production cost of the display screen is an inevitable development direction of the flat panel display industry. Therefore, it is necessary to develop a new display panel production technology to reduce production costs and increase production efficiency.
  • the present disclosure provides an array substrate process and an array substrate, which can reduce the production cost of the display panel and improve production efficiency.
  • An array substrate process includes the following steps:
  • An array substrate comprising:
  • An ohmic contact layer on the active layer wherein the active layer and the ohmic contact layer have a slit as a channel of the thin film transistor; a source and a drain of the thin film transistor are located in the ohmic contact On the floor
  • the color photoresist layer comprising a plurality of filter layers
  • the pixel electrode layer is directly formed on the color photoresist layer.
  • a process for an array substrate comprising:
  • Depositing a color photoresist layer on the protective layer and exposing and developing the color photoresist layer including:
  • the color photoresist layer includes the first filter layer, the second filter layer, and the third filter layer;
  • the first organic photosensitive layer is a red organic photosensitive layer
  • the second organic photosensitive layer is a green organic photosensitive layer
  • the third organic photosensitive layer is a blue organic photosensitive layer
  • the first filter layer is a red filter layer
  • the second filter layer is a green filter layer
  • the third filter layer is a blue filter layer
  • the red filter layer, the green filter layer, and the blue filter layer are arranged side by side in the same plane.
  • FIG. 1 is a schematic diagram of a process flow of an array substrate process according to the embodiment
  • FIG. 3 is a longitudinal cross-sectional view of an array substrate provided by the embodiment.
  • FIG. 1 is a schematic diagram of a process flow of an array substrate process according to the embodiment
  • FIG. 2 is a flow chart of an array substrate process provided by the embodiment.
  • the embodiment provides a process for fabricating an array substrate, including the following steps.
  • step 100 a first metal layer is formed on a substrate 100, and the first metal layer is etched to form the gate 1 of the TFT.
  • step 200 an insulating layer 2 is deposited on the substrate 100 and the gate 1.
  • step 300 an active layer 3 and an ohmic contact layer 4 are sequentially deposited on the insulating layer 2.
  • step 400 the active layer 3 and the ohmic contact layer 4 are etched to form a via of the TFT.
  • a second metal layer is deposited on the ohmic contact layer 4 and the insulating layer 2, and the second metal layer is etched to form a source 5-1 and a drain 5 of the TFT. 2.
  • the left side is the source 5-1
  • the right side is the drain 5-2.
  • the left side is the drain 5-1
  • the right side is the source 5-2.
  • step 600 a protective layer 6 is deposited on the second metal layer and the insulating layer 2.
  • step 700 a color photoresist layer 7 is deposited on the protective layer 6, and the color photoresist layer is exposed and developed.
  • a transparent conductive layer is deposited on the color photoresist layer 7, and the transparent conductive layer is etched to form a pixel electrode layer, wherein the color photoresist layer 7 directly contacts the transparent conductive layer.
  • a first metal layer is formed on a substrate 100
  • the step of etching the first metal layer to form the TFT gate 1 includes: cleaning the substrate 100, forming a film, and glazing Resistance, exposure, development, etching, and photoresist removal.
  • a metal thin film that is, a first metal layer is formed by sputtering deposition on the surface of the clean substrate 100.
  • a layer of photoresist is uniformly coated on the formed first metal layer.
  • the ultraviolet light is irradiated through the mask to the photoresist on the first metal layer to expose the photoresist.
  • the exposed portion of the photoresist is dissolved by the developer, and the photoresist leaves a portion of the pattern to assume the desired shape.
  • the substrate is placed in a corresponding etching solution or etching gas to etch away the first metal layer not covered by the photoresist. as well as,
  • the residual photoresist is removed leaving a first metal layer of a desired shape to form a scan line, a gate 1 of the TFT, and a common electrode.
  • a second metal layer is deposited on the ohmic contact layer 4 and the insulating layer 2, and the second metal layer is etched to form a source 5-1 of the TFT.
  • the steps of the drain 5-2 include: film formation, upper photoresist, exposure, development, etching, and photoresist removal.
  • a metal thin film that is, a second metal layer is formed by sputtering deposition on the ohmic contact layer and the surface of the insulating layer.
  • a layer of photoresist is uniformly coated on the formed second metal layer.
  • the ultraviolet light is irradiated through the mask to the photoresist on the second metal layer to expose the photoresist.
  • the exposed portion of the photoresist is dissolved by the developer, and the photoresist leaves a portion of the pattern to assume the desired shape.
  • the substrate 100 is placed in a corresponding etching solution or etching gas to etch away the second metal layer not covered by the photoresist. as well as,
  • the residual photoresist is removed, leaving a second metal layer of a desired shape to form a data line, a source 5-1 and a drain 5 of the TFT defined on the ohmic contact layer. 2.
  • depositing a color photoresist layer 77 on the protective layer 6 and performing exposure and development includes the following steps.
  • a photosensitive first organic photosensitive layer is coated on the protective layer 6, and a first filter layer corresponding to the pixel is formed through a mask, exposure, and development.
  • a photosensitive second organic photosensitive layer is coated on the protective layer 6, and a second filter layer corresponding to the pixel is formed through a mask, exposure, and development. as well as
  • a photosensitive third organic photosensitive layer is coated on the protective layer 6, and a third filter layer corresponding to the pixel is formed through a mask, exposure, and development. among them,
  • the color photoresist layer includes a first filter layer, a second filter layer, and a third filter layer.
  • the first organic photosensitive layer mentioned in the above step is a red organic photosensitive layer
  • the second organic photosensitive layer is a green organic photosensitive layer
  • the third organic photosensitive layer is a blue organic photosensitive layer
  • One filter layer is a red filter layer
  • the second filter layer is a green filter layer
  • the third filter layer is a blue filter layer.
  • the color photoresist layer 7 is a combination of a color filter layer and a transparent filter layer (not shown).
  • the step of depositing a color photoresist layer 7 on the protective layer 6 and performing exposure and development may include:
  • a photosensitive blue organic photosensitive layer is coated on the protective layer 6, and a blue filter layer corresponding to the pixel is formed through a mask, exposure, and development.
  • a protective transparent organic photosensitive layer is coated on the protective layer 6, and a transparent filter layer corresponding to the pixel is formed through a mask, exposure, and development.
  • the color photoresist layer in the embodiment includes a red filter layer, a green filter layer, a blue filter layer, and a transparent filter layer.
  • the red filter layer, the green filter layer, the blue filter layer, and the transparent filter layer may be arranged side by side in the same plane.
  • the color photoresist layer 7 is exposed, developed, and etched by using a mask having a through hole, and the insulating layer 2 corresponding to the through-hole region of the mask is removed to form an opening 8.
  • the first metal layer and the second metal layer corresponding to the through-hole region of the mask may be exposed to the outside to form an array; or the protective layer 6 corresponding to the through-hole region of the mask may be removed to form an opening 8 and the mask
  • the second metal layer corresponding to the via area may be exposed to form an array.
  • a transparent conductive layer 9 is deposited on the color photoresist layer 7, and the transparent conductive layer 9 is exposed, developed, and etched.
  • the transparent conductive layer 9 is coupled to the first through the opening 8. At least one of a metal layer and a second metal layer to form the pixel electrode layer.
  • the film formation operation of the second insulating layer is not performed, and operations such as exposure, development, and removal of the photoresist layer may not be performed.
  • the insulating layer 2 and the protective layer 6 corresponding to the via region of the mask are removed by etching the formed color photoresist layer as a shield, and the subsequent pixel electrode process is continued.
  • the array substrate process of the present embodiment improves the efficiency and productivity of the production line by simplifying the structure and production process of the array substrate, thereby saving production equipment and mask costs and reducing production costs.
  • the present embodiment provides an array substrate including: a substrate 100, a gate of a thin film transistor, and an insulating layer 2.
  • the gate 1 of the thin film transistor is located on the substrate 100.
  • the insulating layer 2 is located on the substrate 100 and the gate electrode 1.
  • the active layer 3 is located on the insulating layer 2.
  • An ohmic contact layer 4 is located on the active layer 3, wherein the active layer and the ohmic contact layer have a slit as a channel of the thin film transistor.
  • a source 5-1 and a drain 5-2 of the thin film transistor are located on the ohmic contact layer.
  • the protective layer 6 is located on the source 5-1 and the drain 5-2 of the thin film transistor and the insulating layer 2.
  • a color photoresist layer 7 is disposed on the protective layer 6, and the color photoresist layer 7 includes a plurality of filter units.
  • a pixel electrode layer is directly formed on the color photoresist layer.
  • the color photoresist layer 7 includes a plurality of red filter layers, a plurality of green filter layers, and a plurality of blue filter layers distributed in the same plane.
  • the plurality of red filter layers, green filter layers, and blue filter layers are the above-described filter units.
  • the color photoresist layer 7 is a combination of a color filter layer and a transparent filter layer (not shown).
  • the color photoresist layer may include a plurality of red filter layers, a plurality of green filter layers, a plurality of blue filter layers, and a plurality of transparent filter layers distributed in the same plane.
  • the color photoresist layer 7 has an opening 8 formed by exposing, developing and etching, and removing the insulating layer 2 corresponding to the through-hole region of the mask to form the opening 8.
  • the first metal layer and the second metal layer corresponding to the via region of the mask may be exposed to the outside to form an array; or the color photoresist layer 7 is exposed, developed, and etched, and removed corresponding to the mask.
  • the protective layer 6 of the hole region forms the opening 8, and the second metal layer corresponding to the through-hole region of the mask can be exposed to form an array.
  • the pixel electrode includes a transparent conductive layer 9 which can be formed by exposure, development and etching, by coupling the opening 8 to at least one of the first metal layer and the second metal layer.
  • the embodiment provides a display panel including: a backlight module, a first substrate, a second substrate, and a liquid crystal layer.
  • the backlight module is configured to provide an illumination source.
  • the first substrate comprises: a substrate, a gate of the thin film transistor, an insulating layer, an active layer, an ohmic contact layer, a source and a drain of the thin film transistor, a protective layer, a color photoresist layer, a pixel electrode layer, a first alignment film, and a first substrate A polarizing plate.
  • a gate of the thin film transistor is located on a first side surface of the substrate.
  • An insulating layer is disposed on the substrate and the gate.
  • the active layer 3 is located on the insulating layer.
  • An ohmic contact layer is disposed on the active layer, wherein the active layer and the ohmic contact layer have a slit as a channel of the thin film transistor.
  • a source and a drain of the thin film transistor are located on the ohmic contact layer.
  • a protective layer is disposed on the source and the drain of the thin film transistor and the insulating layer.
  • a color photoresist layer is located on the protective layer.
  • the pixel electrode layer is directly formed on the color photoresist layer.
  • a first alignment film is on the pixel electrode layer. as well as,
  • the first polarizing plate is disposed on the second side of the substrate.
  • the second substrate is coupled to the first substrate.
  • the liquid crystal layer is filled between the first substrate and the second substrate.
  • the display panel provided in this embodiment further includes a black matrix layer, a second alignment film, and a second polarizing plate.
  • a black matrix layer is disposed on the inner side of the second substrate.
  • a second alignment film is disposed on the black matrix layer. And a second polarizing plate disposed on an outer side of the second substrate.
  • the color photoresist layer may include a plurality of red filter layers, a plurality of green filter layers, and a plurality of blue filter layers distributed in the same plane, or
  • the color photoresist layer includes a plurality of red filter layers, a plurality of green filter layers, a plurality of blue filter layers, and a plurality of transparent filter layers distributed in the same plane.
  • the film formation operation of the second insulating layer may not be performed, and the exposure, development, and removal of the photoresist layer may not be performed.
  • the operation is performed by etching the removed colored photoresist layer as a shield to remove the insulating layer and the protective layer corresponding to the via hole, and continuing the subsequent pixel electrode process.
  • Display surface of this embodiment By simplifying the structure of the array substrate and the production process, the board improves the efficiency and productivity of the production line, which saves production equipment and mask costs and reduces production costs.

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Abstract

一种阵列基板制程和阵列基板，其中，所述阵列基板制程包括：在一基板（100）上形成一第一金属层，蚀刻第一金属层，形成栅极（1）；沉积一绝缘层（2）与基板（100）及所述第一金属层上；于绝缘层（2）上，依次沉积一主动层（3）以及一欧姆接触层（4）；蚀刻主动层（3）及欧姆接触层（4）；于欧姆接触层（4）以及绝缘层（2）上沉积一第二金属层，并蚀刻第二金属层，形成源极（5-1）和漏极（5-2）；于第二金属层以及绝缘层（2）上沉积一保护层（6）；于保护层（6）上沉积一彩色光阻层（7）并进行曝光及显影；于彩色光阻层（7）上直接沉积一透明导电层，并蚀刻所述透明导电层，以形成像素电极层。

Description

阵列基板制程和阵列基板 技术领域
本公开涉及显示屏技术领域，例如涉及一种阵列基板制程和阵列基板。
背景技术
越来越多的液晶面板需要使用在薄膜晶体管(Thin-filmtransistor，TFT)的阵列上制作彩色滤光膜(Color Filter on Array，COA)的工艺来提升液晶面板曲面画质或简化上板的结构，例如，简化平面转换(In-Plane Switching，IPS)液晶模式上板的平坦化层(Over Coat，OC)结构。
相关技术中的液晶面板的COA结构的阵列(Array)制程工艺如下：传统COA结构在栅极、源极和漏极制程完成之后，进行第一绝缘层的成型工序；完成彩色光阻层(包括红色光阻、绿色光阻以及蓝色光阻)的涂布、曝光与显影步骤；如果是搭配了白、红、绿以及蓝四色(White，Red，Green，Blue，WRGB)技术的液晶面板，则还需要进行透明光阻层的涂布、曝光与显影步骤。彩色光阻层或透明光阻层结构形成之后进行第二绝缘层的成型工序，涂布光刻胶层(也叫光阻)，并利用带有通孔的掩膜板对光刻胶层进行曝光操作，显影与蚀刻以除去对应于通孔处的位于阵列上方的第一绝缘层以及第二绝缘层，除去光刻胶层以继续像素电极(Pixel Electrode，PE)制程。
薄膜晶体管液晶显示器产业由于工艺复杂且设备投资巨大，所以生产的成本很高，随着市场竞争日益激烈，降低显示屏的生产成本已是平板显示行业必然的发展方向。因此，需要研发一种新的显示面板的生产技术，以降低生产成本，提高生产效率。
发明内容
本公开提供一种阵列基板制程和阵列基板，可以降低显示面板的生产成本，提高生产效率。
一种阵列基板的制程，包括以下步骤：
在一基板上形成一第一金属层，蚀刻所述第一金属层，以形成薄膜晶体管 的栅极；
沉积一绝缘层于所述基板及所述栅极上；
于所述绝缘层上，依次沉积一主动层及一欧姆接触层；
蚀刻所述主动层及所述欧姆接触层，以形成所述薄膜晶体管的通道；
于所述欧姆接触层以及所述绝缘层上沉积一第二金属层，并蚀刻所述第二金属层以形成所述薄膜晶体管的源极与漏极；
于所述第二金属层以及所述绝缘层上沉积一保护层；
于所述保护层上沉积一彩色光阻层并对所述彩色光阻层进行曝光及显影；
于所述彩色光阻层上直接沉积一透明导电层，并蚀刻所述透明导电层，以形成像素电极层，其中所述彩色光阻层是直接接触所述透明导电层。
一种阵列基板，包括：
基板；
薄膜晶体管的栅极，位于所述基板上；
绝缘层，位于所述基板及所述栅极上；
主动层，位于所述绝缘层上；
欧姆接触层，位于所述主动层上，其中，所述主动层和所述欧姆接触层上具有刻缝，作为所述薄膜晶体管的通道；薄膜晶体管的源极与漏极，位于所述欧姆接触层上；
保护层，位于所述薄膜晶体管的源极与漏极及所述绝缘层上；
彩色光阻层，位于所述保护层上，所述彩色光阻层包含多个滤光层；以及
像素电极层，直接形成于所述彩色光阻层上。
一种阵列基板的制程，包括：
在一基板上形成一第一金属层，蚀刻所述第一金属层，以形成薄膜晶体管的栅极；
沉积一绝缘层于所述基板及所述栅极上；
于所述绝缘层上，依次沉积一主动层及一欧姆接触层；
蚀刻所述主动层及所述欧姆接触层，以形成所述薄膜晶体管的通道；
于所述欧姆接触层以及所述绝缘层上沉积一第二金属层，并蚀刻所述第二金属层以形成所述薄膜晶体管的源极与漏极；
于所述第二金属层以及所述绝缘层上沉积一保护层；
于所述保护层上沉积一彩色光阻层并对所述彩色光阻层进行曝光及显影；
于所述彩色光阻层上沉积一透明导电层，并蚀刻所述透明导电层，以形成像素电极层，其中所述彩色光阻层接触所述透明导电层；
所述于所述保护层上沉积一彩色光阻层并对所述彩色光阻层进行曝光及显影，包括：
在所述保护层上涂覆一层感光的第一有机感光层，通过掩模、曝光以及显影，形成与像素对应的第一滤光层；
在所述保护层上涂覆一层感光的第二有机感光层，通过掩模、曝光以及显影，形成与像素对应的第二滤光层；以及
在所述保护层上涂覆一层感光的第三有机感光层，通过掩模、曝光以及显影，形成与像素对应的第三滤光层；其中，
所述彩色光阻层包括所述第一滤光层、所述第二滤光层和所述第三滤光层；
所述第一有机感光层为红色有机感光层、所述第二有机感光层为绿色有机感光层，以及所述第三有机感光层为蓝色有机感光层；
所述第一滤光层为红色滤光层、所述第二滤光层为绿色滤光层，以及所述第三滤光层为蓝色滤光层；
所述红色滤光层、所述绿色滤光层和所述蓝色滤光层并排分布在同一平面内。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1是本实施例提供的一种阵列基板制程的工艺流程步骤示意图；
图2是本实施例提供的一种阵列基板制程的流程图；以及
图3是本实施例提供的一种阵列基板的纵向截面图。
具体实施方式
为了使本公开技术方案更加清楚明白，以下结合附图及实施例，对本公开进行详细说明。
图1是本实施例提供的一种阵列基板制程的工艺流程步骤示意图，图2是本实施例提供的一种阵列基板制程的流程图。如图1及图2所示，本实施例提供了一种阵列基板的制程，包括以下步骤。
在步骤100中，在一基板100上形成一第一金属层，蚀刻所述第一金属层，以形成TFT的栅极1。
在步骤200中，沉积一绝缘层2于所述基板100及所述栅极1上。
在步骤300中，于所述绝缘层2上，依次沉积一主动层3以及一欧姆接触层4。
在步骤400中，蚀刻所述主动层3及欧姆接触层4，以形成所述TFT的通道。
在步骤500中，于所述欧姆接触层4以及所述绝缘层2上沉积一第二金属层，并蚀刻所述第二金属层以形成所述TFT的源极5-1与漏极5-2。
图2中，以左侧为源极5-1，右侧为漏极5-2为例进行说明，还可以是左侧为漏极5-1，右侧为源极5-2。
在步骤600中，于所述第二金属层以及所述绝缘层2上沉积一保护层6。
在步骤700中，于所述保护层6上沉积一彩色光阻层7并对所述彩色光阻层进行曝光及显影。
在步骤800中，于所述彩色光阻层7上沉积一透明导电层，并蚀刻所述透明导电层，以形成像素电极层，其中所述彩色光阻层7直接接触所述透明导电层。
可选地，在所述步骤100中，在一基板100上形成一第一金属层，蚀刻所述第一金属层，以形成TFT栅极1的步骤包括：清洗基板100、成膜、上光阻、曝光、显影、蚀刻以及去光阻。
在清洗基板100过程中，去除基板100上的异物。
在成膜过程中，在干净的基板100表面，通过溅射沉积形成金属薄膜，即第一金属层。
在上光阻过程中，在已形成的第一金属层上面均匀涂覆一层光刻胶。
在曝光过程中，紫外线透过掩模板照射第一金属层上的光刻胶，以对光刻胶进行曝光操作。
在显影过程中，光刻胶曝光部分被显影液溶解，光刻胶留下部分图案呈现所需形状。
在蚀刻过程中，把基板放入对应腐蚀液或腐蚀气体中，腐蚀掉无光刻胶覆盖的第一金属层。以及，
在去光阻过程中，去除残余的光刻胶，留下所需形状的第一金属层，以形成扫描线、TFT的栅极1以及共通电极。
可选地，在步骤500中，于所述欧姆接触层4以及所述绝缘层2上沉积一第二金属层，并蚀刻所述第二金属层以形成所述TFT的源极5-1与漏极5-2的步骤包括：成膜、上光阻、曝光、显影、蚀刻以及去光阻。在成膜过程中，在欧姆接触层以及绝缘层表面，通过溅射沉积形成金属薄膜，即第二金属层。
在上光阻过程中，在已形成的第二金属层上面均匀涂覆一层光刻胶。
在曝光过程中，紫外线透过掩模板照射第二金属层上的光刻胶，以对光刻胶进行曝光操作。
在显影过程中，光刻胶曝光部分被显影液溶解，光刻胶留下部分图案呈现所需形状。
在蚀刻过程中，把基板100放入对应腐蚀液或腐蚀气体中，腐蚀掉无光刻胶覆盖的第二金属层。以及，
在去光阻过程中，去除残余的光刻胶，留下所需形状的第二金属层，以形成数据线、于欧姆接触层上定义出的TFT的源极5-1及漏极5-2。
可选地，在所述步骤700中，于所述保护层6上沉积一彩色光阻层77并进行曝光及显影，包括以下步骤。
在所述保护层6上涂覆一层感光的第一有机感光层，通过掩模、曝光以及显影，形成与像素对应的第一滤光层。
在所述保护层6上涂覆一层感光的第二有机感光层，通过掩模、曝光以及显影，形成与像素对应的第二滤光层。以及
在所述保护层6上涂覆一层感光的第三有机感光层，通过掩模、曝光以及显影，形成与像素对应的第三滤光层。其中，
彩色光阻层包括第一滤光层、第二滤光层和第三滤光层。
可选地，本实施例中，上述步骤中提及的第一有机感光层为红色有机感光层、第二有机感光层为绿色有机感光层、第三有机感光层为蓝色有机感光层；第一滤光层为红色滤光层、第二滤光层为绿色滤光层、第三滤光层为蓝色滤光层。经过上述三个步骤(顺序不限)，可以形成一彩色滤光层，所述彩色滤光层 即为本实施例中所述的彩色光阻层。所述红色滤光层、绿色滤光层以及蓝色滤光层可以并排分布在同一平面内。
可选地，如果显示面板是搭配了四色技术的液晶面板，则彩色光阻层7为彩色滤光层以及透明滤光层(图中未示出)的组合。步骤700中，于所述保护层6上沉积一彩色光阻层7并进行曝光及显影的步骤可以包括：
在所述保护层6上涂覆一层感光的红色有机感光层，通过掩模、曝光以及显影，形成与像素对应的红色滤光层；
在所述保护层6上涂覆一层感光的绿色有机感光层，通过掩模、曝光以及显影，形成与像素对应的绿色滤光层；
在所述保护层6上涂覆一层感光的蓝色有机感光层，通过掩模、曝光以及显影，形成与像素对应的蓝色滤光层。
在所述保护层6上涂覆一层感光的透明有机感光层，通过掩模、曝光以及显影，形成与像素对应的透明滤光层。
即，本实施例中所述彩色光阻层包括红色滤光层、绿色滤光层、蓝色滤光层以及透明滤光层。所述红色滤光层、绿色滤光层、蓝色滤光层以及透明滤光层可以并排分布在同一平面内。
可选地，在所述步骤800中，利用具有通孔的掩膜板对彩色光阻层7进行曝光、显影与蚀刻操作，除去对应于掩膜板通孔区域的绝缘层2形成一开口8，与掩膜板通孔区域对应的第一金属层和第二金属层可以显露在外面，形成阵列；或者除去对应于掩膜板通孔区域的保护层6形成一开口8，与掩膜板通孔区域对应的第二金属层可以显露在外面，形成阵列。在像素电极制程中，于所述彩色光阻层7上沉积一透明导电层9，并对透明导电层9进行曝光、显影与蚀刻，所述透明导电层9借由开口8耦接至第一金属层和第二金属层中的至少一个，以形成所述像素电极层。
上述实施例中，在彩色光阻层7的涂布、曝光以及显影后，不进行第二层绝缘层的成膜操作，也可以不进行光刻胶层的曝光、显影以及除去等操作，而是以已经成型的彩色光阻层作为屏蔽，进行蚀刻，以除去对应于掩膜板通孔区域的绝缘层2及保护层6，再继续后面的像素电极制程。本实施例的阵列基板制程通过简化阵列基板的结构以及生产流程，提高了生产线的效率与产能，可节省生产设备以及掩膜板费用，降低生产成本。
图3是本实施例提供的一种阵列基板的纵向截面图，如图3所示，本实施例提供一种阵列基板，阵列基板包括：基板100、薄膜晶体管的栅极1、绝缘层2、主动层3、欧姆接触层4、薄膜晶体管的源极5-1和漏极5-2、保护层6、彩色光阻层7以及像素电极层。
薄膜晶体管的栅极1，位于所述基板100上。
绝缘层2位于所述基板100及所述栅极1上。
主动层3，位于所述绝缘层2上。
欧姆接触层4位于所述主动层3上，其中，所述主动层和所述欧姆接触层上具有刻缝，作为所述薄膜晶体管的通道。
薄膜晶体管的源极5-1和漏极5-2，位于所述欧姆接触层上。
保护层6位于所述薄膜晶体管的源极5-1与漏极5-2及所述绝缘层2上。
彩色光阻层7位于所述保护层6上，彩色光阻层7包含多个滤光单元。
像素电极层直接形成于所述彩色光阻层上。
可选地，本实施例的阵列基板中，所述彩色光阻层7包括在同一平面内分布的多个红色滤光层、多个绿色滤光层及多个蓝色滤光层，所述多个红色滤光层、绿色滤光层及蓝色滤光层即为上述的滤光单元。
可选地，如果显示面板是搭配了四色技术的液晶面板，则彩色光阻层7为彩色滤光层以及透明滤光层(图中未示出)的组合。所述彩色光阻层可以包括在同一平面内分布的多个红色滤光层、多个绿色滤光层、多个蓝色滤光层及多个透明滤光层。
可选地，彩色光阻层7上具有一开口8，所述彩色光阻层7通过曝光、显影与蚀刻操作，并除去对应于掩膜板通孔区域的绝缘层2形成所述开口8，与掩膜板通孔区域对应的第一金属层和第二金属层可以显露在外面，形成阵列；或者所述彩色光阻层7通过曝光、显影与蚀刻操作，并除去对应于掩膜板通孔区域的保护层6形成所述开口8，与掩膜板通孔区域对应的第二金属层可以显露在外面，形成阵列。像素电极包括一透明导电层9，透明导电层9通过曝光、显影与蚀刻，借由开口8耦接至第一金属层和第二金属层中的至少一个，可以形成所述像素电极层。
本实施例提供了一种显示面板包括：背光模组、第一基板、第二基板和液晶层。
背光模组设置为提供照明光源。
第一基板包括：基板、薄膜晶体管的栅极、绝缘层、主动层、欧姆接触层、薄膜晶体管的源极和漏极、保护层、彩色光阻层、像素电极层、第一配向膜以及第一偏光板。
薄膜晶体管的栅极，位于所述基板第一侧表面上。
绝缘层，位于所述基板及所述栅极上。
主动层3，位于所述绝缘层上。
欧姆接触层，位于所述主动层上，其中，所述主动层和所述欧姆接触层上具有刻缝，作为所述薄膜晶体管的通道。
薄膜晶体管的源极和漏极，位于所述欧姆接触层上。
保护层，位于所述薄膜晶体管的源极与漏极及所述绝缘层上。
彩色光阻层，位于所述保护层上。
像素电极层，直接形成于所述彩色光阻层上。
第一配向膜，位于所述像素电极层上。以及，
第一偏光板，设置于所述基板第二侧。
第二基板与所述第一基板相扣合。
液晶层填充于第一基板与第二基板之间。
可选地，本实施例提供的显示面板还包括黑色矩阵层、第二配向膜以及第二偏光板。
黑色矩阵层，设置于所述第二基板内侧的。
第二配向膜，设在所述黑色矩阵层上。以及第二偏光板，设置于所述第二基板的外侧的。
可选地，本实施例提供的显示面板中，所述彩色光阻层可以包括在同一平面内分布的多个红色滤光层、多个绿色滤光层及多个蓝色滤光层，或所述彩色光阻层包括在同一平面内分布的多个红色滤光层、多个绿色滤光层、多个蓝色滤光层及多个透明滤光层。
本实施例的显示面板，在彩色光阻层的涂布、曝光以及显影后，可以不再进行第二层绝缘层的成膜操作，也可以不进行光刻胶层的曝光、显影以及除去等操作，而是以已经成型的彩色光阻层作为屏蔽，进行蚀刻以除去与所述通孔对应区域的绝缘层及保护层，并继续后面的像素电极制程。本实施例的显示面 板通过简化阵列基板的结构以及生产流程，提高了生产线的效率与产能，可节省生产设备以及掩膜板费用，降低生产成本。

Claims (20)

  1. 一种阵列基板的制程，包括：
    在一基板上形成一第一金属层，蚀刻所述第一金属层，以形成薄膜晶体管的栅极；
    沉积一绝缘层于所述基板及所述栅极上；
    于所述绝缘层上，依次沉积一主动层及一欧姆接触层；
    蚀刻所述主动层及所述欧姆接触层，以形成所述薄膜晶体管的通道；
    于所述欧姆接触层以及所述绝缘层上沉积一第二金属层，并蚀刻所述第二金属层以形成所述薄膜晶体管的源极与漏极；
    于所述第二金属层以及所述绝缘层上沉积一保护层；
    于所述保护层上沉积一彩色光阻层，并对所述彩色光阻层进行曝光及显影；
    于所述彩色光阻层上直接沉积一透明导电层，并蚀刻所述透明导电层，以形成像素电极层，其中所述彩色光阻层直接接触所述透明导电层。
  2. 如权利要求1所述的制程，其中，所述在一基板上形成一第一金属层，蚀刻所述第一金属层，以形成薄膜晶体管的栅极，包括：
    清洗基板，以去除所述基板上的异物；
    成膜，以在清洗后的所述基板表面，通过溅射沉积形成金属薄膜，所述金属薄膜为第一金属层；
    上光阻，以在已形成的所述第一金属层上面均匀涂覆一层光刻胶；
    曝光，以通过紫外线透过掩模板照射所述第一金属层表面的光刻胶，对所述光刻胶进行曝光操作；
    显影，以使得光刻胶曝光部分被显影液溶解，光刻胶剩余部分图案呈现所需形状；
    蚀刻，以把所述基板放入对应腐蚀液或腐蚀气体中，腐蚀掉无光刻胶覆盖的所述第一金属层；
    去光阻，以去除残余的光刻胶，留下所需形状的第一金属层，形成扫描线、薄膜晶体管的栅极以及共通电极。
  3. 如权利要求1所述的制程，其中，所述于所述欧姆接触层以及所述绝缘层上沉积一第二金属层，并蚀刻所述第二金属层以形成所述薄膜晶体管的源极与漏极，包括：
    成膜，以在所述欧姆接触层以及所述绝缘层表面，通过溅射沉积形成金属 薄膜，所述金属薄膜为第二金属层；
    上光阻，以在已形成的所述第二金属层上面均匀涂覆一层光刻胶；
    曝光，以将紫外线透过掩模板照射所述第二金属层表面的光刻胶，对光刻胶进行曝光操作；
    显影，以使得光刻胶曝光部分被显影液溶解，光刻胶留下部分图案呈现所需形状；
    蚀刻，以把所述基板放入对应腐蚀液或腐蚀气体中，腐蚀掉无光刻胶覆盖的所述第二金属层；
    去光阻，以去除残余的光刻胶，留下所需形状的第二金属层，形成数据线，并于所述欧姆接触层上定义出薄膜晶体管的源极及漏极。
  4. 如权利要求1所述的制程，其中，所述于所述保护层上沉积一彩色光阻层并对所述彩色光阻层进行曝光及显影，包括：
    在所述保护层上涂覆一层感光的第一有机感光层，通过掩模、曝光以及显影，形成与像素对应的第一滤光层；
    在所述保护层上涂覆一层感光的第二有机感光层，通过掩模、曝光以及显影，形成与像素对应的第二滤光层；以及
    在所述保护层上涂覆一层感光的第三有机感光层，通过掩模、曝光以及显影，形成与像素对应的第三滤光层；其中，
    所述彩色光阻层包括所述第一滤光层、所述第二滤光层和所述第三滤光层。
  5. 如权利要求4所述的制程，其中，所述于所述保护层上沉积一彩色光阻层并对所述彩色光阻层进行曝光及显影，还包括：
    在所述保护层上涂覆一层感光的透明有机感光层，通过掩模曝光、显影，形成与像素对应的透明滤光层；其中，
    所述彩色光阻层还包括所述透明滤光层。
  6. 如权利要求5所述的制程，其中，所述第一有机感光层为红色有机感光层、所述第二有机感光层为绿色有机感光层，以及所述第三有机感光层为蓝色有机感光层；
    所述第一滤光层为红色滤光层、所述第二滤光层为绿色滤光层，以及所述第三滤光层为蓝色滤光层。
  7. 如权利要求6所述的制程，其中，所述红色滤光层、所述绿色滤光层和 所述蓝色滤光层并排分布在同一平面内。
  8. 如权利要求5所述的制程，其中，所述第一滤光层、所述第二滤光层、所述第三滤光层和所述透明滤光层并排分布在同一平面内。
  9. 如权利要求8所述的制程，其中，所述第一有机感光层为红色有机感光层、所述第二有机感光层为绿色有机感光层，以及所述第三有机感光层为蓝色有机感光层；
    所述第一滤光层为红色滤光层、所述第二滤光层为绿色滤光层，以及所述第三滤光层为蓝色滤光层。
  10. 如权利要求1所述的制程，其中，所述于所述保护层上沉积一彩色光阻层并进行曝光及显影，包括：
    通过具有通孔的掩模板对所述彩色光阻层进行曝光、显影与蚀刻操作；
    除去对应于所述掩模板通孔区域的所述保护层形成一开口，以露出所述第二金属层。
  11. 如权利要求10所述的制程，其中，所述于所述彩色光阻层上沉积一透明导电层，并蚀刻所述透明导电层，以形成像素电极层，包括：
    于所述彩色光阻层上沉积一透明导电层，并对所述透明导电层进行曝光、显影与蚀刻操作；以及
    所述透明导电层通过所述开口耦接至所述第二金属层，以形成所述像素电极层。
  12. 一种阵列基板，包括：
    基板；
    薄膜晶体管的栅极，位于所述基板上；
    绝缘层，位于所述基板及所述栅极上；
    主动层，位于所述绝缘层上；
    欧姆接触层，位于所述主动层上，其中，所述主动层和所述欧姆接触层上具有刻缝，作为所述薄膜晶体管的通道；
    薄膜晶体管的源极与漏极，位于所述欧姆接触层上；
    保护层，位于所述薄膜晶体管的源极与漏极及所述绝缘层上；
    彩色光阻层，位于所述保护层上，所述彩色光阻层包含多个滤光层；以及
    像素电极层，直接形成于所述彩色光阻层上。
  13. 如权利要求12所述的阵列基板，还包括与所述栅极同层设置的扫描线和共通电极。
  14. 如权利要求12所述的阵列基板，还包括与所述源极和所述漏极同层设置的数据线。
  15. 如权利要求12所述的阵列基板，其中，所述像素电极层包括透明导电层，所述透明导电层与所述薄膜晶体管的栅极和所述薄膜晶体管的源极与漏极中的至少一个耦接。
  16. 如权利要求12所述的阵列基板，其中，所述滤光层包括红色滤光层、绿色滤光层及蓝色滤光层。
  17. 如权利要求16所述的阵列基板，其中，多个所述红色滤光层、多个所述绿色滤光层及多个所述蓝色滤光层并排分布在同一平面内。
  18. 如权利要求12所述的阵列基板，其中，所述滤光层包括红色滤光层、绿色滤光层、蓝色滤光层及透明滤光层。
  19. 如权利要求18所述的阵列基板，其中，多个所述红色滤光层、多个所述绿色滤光层、多个所述蓝色滤光层及多个所述透明滤光层并排分布在同一平面内。
  20. 一种阵列基板的制程，包括：
    在一基板上形成一第一金属层，蚀刻所述第一金属层，以形成薄膜晶体管的栅极；
    沉积一绝缘层于所述基板及所述栅极上；
    于所述绝缘层上，依次沉积一主动层及一欧姆接触层；
    蚀刻所述主动层及所述欧姆接触层，以形成所述薄膜晶体管的通道；
    于所述欧姆接触层以及所述绝缘层上沉积一第二金属层，并蚀刻所述第二金属层以形成所述薄膜晶体管的源极与漏极；
    于所述第二金属层以及所述绝缘层上沉积一保护层；
    于所述保护层上沉积一彩色光阻层并对所述彩色光阻层进行曝光及显影；
    于所述彩色光阻层上沉积一透明导电层，并蚀刻所述透明导电层，以形成像素电极层，其中所述彩色光阻层接触所述透明导电层；其中，
    所述于所述保护层上沉积一彩色光阻层并对所述彩色光阻层进行曝光及显影，包括：
    在所述保护层上涂覆一层感光的第一有机感光层，通过掩模、曝光以及显影，形成与像素对应的第一滤光层；
    在所述保护层上涂覆一层感光的第二有机感光层，通过掩模、曝光以及显影，形成与像素对应的第二滤光层；以及
    在所述保护层上涂覆一层感光的第三有机感光层，通过掩模、曝光以及显影，形成与像素对应的第三滤光层；其中，
    所述彩色光阻层包括所述第一滤光层、所述第二滤光层和所述第三滤光层；
    所述第一有机感光层为红色有机感光层、所述第二有机感光层为绿色有机感光层，以及所述第三有机感光层为蓝色有机感光层；
    所述第一滤光层为红色滤光层、所述第二滤光层为绿色滤光层，以及所述第三滤光层为蓝色滤光层；
    所述红色滤光层、所述绿色滤光层和所述蓝色滤光层并排分布在同一平面内。
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