WO2018180486A1 - 太陽電池セル及び太陽電池セルの製造方法 - Google Patents

太陽電池セル及び太陽電池セルの製造方法 Download PDF

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WO2018180486A1
WO2018180486A1 PCT/JP2018/009892 JP2018009892W WO2018180486A1 WO 2018180486 A1 WO2018180486 A1 WO 2018180486A1 JP 2018009892 W JP2018009892 W JP 2018009892W WO 2018180486 A1 WO2018180486 A1 WO 2018180486A1
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semiconductor layer
layer
region
main surface
amorphous semiconductor
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PCT/JP2018/009892
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English (en)
French (fr)
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歩 矢野
未奈都 瀬能
伸 難波
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パナソニック株式会社
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Priority to JP2019509221A priority Critical patent/JP6778816B2/ja
Priority to CN201880015651.4A priority patent/CN110383501B/zh
Publication of WO2018180486A1 publication Critical patent/WO2018180486A1/ja
Priority to US16/562,333 priority patent/US11430904B2/en

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    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
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    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer or HIT® solar cells; solar cells
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    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H—ELECTRICITY
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • H—ELECTRICITY
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
    • H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic System
    • H—ELECTRICITY
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H01L31/022458—Electrode arrangements specially adapted for back-contact solar cells for emitter wrap-through [EWT] type solar cells, e.g. interdigitated emitter-base back-contacts
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/546—Polycrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells

Definitions

  • the present invention relates to a solar battery cell and a method for manufacturing the solar battery cell.
  • a back junction type solar cell in which both an n-type semiconductor layer and a p-type semiconductor layer are formed on the back surface facing the light receiving surface on which light is incident.
  • an n-type amorphous semiconductor layer and a p-type amorphous semiconductor layer are provided over one main surface of a crystalline semiconductor substrate (see, for example, Patent Document 1).
  • the amorphous semiconductor layer is effective for passivation of the surface of the crystalline substrate, but contributes to increasing the series resistance of the solar cells. In order to improve the power generation efficiency, it is preferable that both passivation and low resistance can be achieved.
  • the present invention has been made in view of such circumstances, and an object thereof is to provide a solar battery cell with higher power generation efficiency.
  • a solar battery cell includes a first conductive crystalline semiconductor substrate, a first semiconductor layer provided on a first region of one principal surface of the substrate, a first region of one principal surface, A second semiconductor layer provided on a different second region; a first transparent electrode layer provided on the first semiconductor layer; and a second transparent electrode layer provided on the second semiconductor layer.
  • the first semiconductor layer includes a first amorphous semiconductor layer of a first conductivity type, and a first crystalline semiconductor portion extending from one main surface toward the first transparent electrode layer.
  • the second semiconductor layer includes a second amorphous semiconductor layer of a second conductivity type different from the first conductivity type.
  • a first semiconductor layer is formed in a first region on one main surface of a substrate of a first conductivity type crystalline semiconductor, and a second semiconductor layer is formed on a second region different from the first region on the one main surface. And forming a transparent electrode layer on the first semiconductor layer and the second semiconductor layer.
  • the first semiconductor layer includes a first amorphous semiconductor layer of a first conductivity type and a first crystalline semiconductor portion extending from one main surface toward the transparent electrode layer.
  • the second semiconductor layer includes a second amorphous semiconductor layer of a second conductivity type different from the first conductivity type. The first amorphous semiconductor layer and the first crystalline semiconductor portion are formed simultaneously.
  • the power generation efficiency of the solar battery cell can be improved.
  • FIG. 1 It is a top view which shows the structure of the photovoltaic cell which concerns on embodiment.
  • sectional drawing which shows the structure of the photovoltaic cell of FIG. It is a figure which shows typically the manufacturing process of a photovoltaic cell. It is a figure which shows typically the manufacturing process of a photovoltaic cell. It is a figure which shows typically the manufacturing process of a photovoltaic cell. It is a figure which shows typically the manufacturing process of a photovoltaic cell.
  • the present embodiment is a solar battery cell.
  • a solar battery cell includes a first conductive type crystalline semiconductor substrate, a first semiconductor layer provided on a first region of one principal surface of the substrate, and a second region different from the first region of the one principal surface.
  • a second semiconductor layer provided; a first transparent electrode layer provided on the first semiconductor layer; and a second transparent electrode layer provided on the second semiconductor layer.
  • the first semiconductor layer includes a first amorphous semiconductor layer of a first conductivity type, and a first crystalline semiconductor portion extending from one main surface toward the first transparent electrode layer.
  • the second semiconductor layer includes a second amorphous semiconductor layer of a second conductivity type different from the first conductivity type.
  • the passivation property by the amorphous semiconductor layer is improved, and the series resistance by the crystalline semiconductor portion is reduced. It is possible to achieve both reduction and increase the power generation efficiency of the solar battery cell.
  • FIG. 1 is a plan view showing a solar cell 10 according to the embodiment, and shows the structure of the back surface 13 of the solar cell 10.
  • the solar battery cell 10 includes a first electrode 14 and a second electrode 15 provided on the back surface 13.
  • the solar battery cell 10 is a so-called back contact type solar battery, in which no electrode is provided on the light receiving surface side, and the first electrode 14 and the second electrode 15 having different polarities on the back surface 13 opposite to the light receiving surface. Both are provided.
  • the first electrode 14 includes a first bus bar electrode 14a extending in the x direction and a plurality of first finger electrodes 14b extending in the y direction intersecting the first bus bar electrode 14a, and is formed in a comb shape.
  • the second electrode 15 includes a second bus bar electrode 15a extending in the x direction and a plurality of second finger electrodes 15b extending in the y direction intersecting the second bus bar electrode 15a, and is formed in a comb shape.
  • the first electrode 14 and the second electrode 15 are formed so that the respective comb teeth are engaged with each other and are inserted into each other.
  • Each of the first electrode 14 and the second electrode 15 may be a bus bar-less electrode that includes only a plurality of fingers and does not have a bus bar.
  • FIG. 2 is a cross-sectional view showing the structure of the solar battery cell 10 according to the embodiment, and shows a cross section taken along line AA of FIG.
  • the solar cell 10 includes a substrate 20, a first semiconductor layer 21, a second semiconductor layer 22, a first transparent electrode layer 23, a second transparent electrode layer 24, a first metal electrode layer 25, a second A metal electrode layer 26 and a light receiving surface protective layer 30 are provided.
  • the solar battery cell 10 is a back junction solar cell in which a heterojunction is formed on the back surface 13 side.
  • the solar battery cell 10 has a light receiving surface 12 and a back surface 13.
  • the light receiving surface 12 means a main surface on which light (sunlight) is mainly incident in the solar battery cell 10, and specifically, a surface on which most of the light incident on the solar battery cell 10 is incident. means.
  • the back surface 13 means the other main surface opposite to the light receiving surface 12.
  • the substrate 20 is made of a crystalline semiconductor having the first conductivity type.
  • the crystalline semiconductor substrate include a crystalline silicon (Si) wafer such as a single crystal silicon wafer and a polycrystalline silicon wafer.
  • the substrate 20 is an n-type single crystal silicon wafer, and the first conductivity type is n-type and the second conductivity type is p-type.
  • the substrate 20 includes a first conductivity type impurity, for example, phosphorus (P) as an n-type impurity doped in silicon.
  • the concentration of the n-type impurity of the substrate 20 is not particularly limited, but is, for example, about 1 ⁇ 10 15 / cm 3 to 1 ⁇ 10 16 / cm 3 .
  • the solar battery cell can be formed of a semiconductor substrate other than the crystalline semiconductor substrate as the semiconductor substrate.
  • a compound semiconductor wafer made of gallium arsenide (GaAs) or indium phosphorus (InP) may be used.
  • the first conductivity type may be p-type and the second conductivity type may be n-type.
  • the substrate 20 has a first main surface 20a on the light receiving surface 12 side and a second main surface 20b on the back surface 13 side.
  • the substrate 20 absorbs light incident on the first major surface 20a and generates electrons and holes as carriers.
  • the first main surface 20a is provided with a texture structure 40 for increasing the absorption efficiency of incident light.
  • the second main surface 20b is not provided with the same texture structure as the first main surface 20a, and the flatness of the second main surface 20b is higher than that of the first main surface 20a.
  • the texture structure on the second major surface 20b may be provided at least partially on the second major surface 20b. For example, a difference is provided in the texture structure on the second major surface 20b between the first region W1 and the second region W2 described later. May be.
  • the first semiconductor layer 21 and the second semiconductor layer 22 are provided on the second main surface 20b of the substrate 20.
  • the first semiconductor layer 21 is provided on the first region W1 of the second main surface 20b
  • the second semiconductor layer 22 is provided on a second region W2 different from the first region W1 of the second main surface 20b.
  • the first semiconductor layer 21 and the second semiconductor layer 22 are formed in a comb shape so as to correspond to the first electrode 14 and the second electrode 15, respectively, and are formed so as to be interleaved with each other. Accordingly, the first regions W1 and the second regions W2 are alternately arranged in the x direction on the second main surface 20b.
  • the first region W1 is on the first conductivity type side and collects carriers on the first conductivity type side among the carriers generated on the substrate 20. Since the substrate 20 is of the first conductivity type, the first region W1 can be said to be a region that collects majority carriers.
  • the second region W2 is on the second conductivity type side and collects carriers on the second conductivity type side which are minority carriers. When the first conductivity type is n-type and the second conductivity type is p-type, the first region W1 collects electrons and the second region W2 collects holes.
  • the second area S2 of the second region W2 on the minority carrier side is made larger than the first area S1 of the first region W1 on the majority carrier side.
  • the ratio S2 / S1 between the first area S1 and the second area S2 is set to be 1.5 or more and 5 or less, for example, 2 or more and 4 or less.
  • the first semiconductor layer 21 includes a first amorphous semiconductor layer 31, a third amorphous semiconductor layer 33, and a first crystalline semiconductor portion 35.
  • the third amorphous semiconductor layer 33 is provided on the second major surface 20 b, and the first amorphous semiconductor layer 31 is provided on the third amorphous semiconductor layer 33.
  • the first crystalline semiconductor portion 35 is provided in the first amorphous semiconductor layer 31 and the third amorphous semiconductor layer 33, and has a columnar shape from the second major surface 20b toward the first transparent electrode layer 23. It is provided to extend.
  • the first amorphous semiconductor layer 31 is a first conductive type amorphous semiconductor layer, and is made of, for example, n-type amorphous silicon (amorphous silicon) containing hydrogen (H).
  • the first amorphous semiconductor layer 31 has a thickness of about 2 nm to 50 nm, for example.
  • the first amorphous semiconductor layer 31 preferably contains, for example, phosphorus (P) as an impurity of the same first conductivity type as that of the substrate 20 and has a higher impurity concentration than the substrate 20.
  • the impurity concentration of the first amorphous semiconductor layer 31 is about 1 ⁇ 10 20 / cm 3 to 1 ⁇ 10 21 / cm 3 .
  • the third amorphous semiconductor layer 33 is a substantially intrinsic amorphous semiconductor, and is made of, for example, i-type amorphous silicon containing hydrogen.
  • a substantially intrinsic semiconductor is also referred to as an “i-type semiconductor”.
  • a substantially intrinsic semiconductor includes a semiconductor layer formed without positively using an element that becomes an n-type or p-type impurity, and is formed during chemical vapor deposition (CVD) or the like. , Including a semiconductor layer formed without supplying a dopant gas. Specifically, silicon obtained by supplying silane (SiH 4 ) diluted with hydrogen (H 2 ) without supplying a dopant gas such as diborane (B 2 H 6 ) or phosphine (PH 3 ). including.
  • the third amorphous semiconductor layer 33 is provided between the second major surface 20b and the first amorphous semiconductor layer 31, and has a thickness of about 2 nm to 25 nm, for example.
  • the third amorphous semiconductor layer 33 may not be provided, and the first amorphous semiconductor layer 31 may be provided immediately above the second major surface 20b of the first region W1.
  • the first crystalline semiconductor portion 35 is made of a crystalline semiconductor and includes, for example, at least one of single crystal silicon, polycrystalline silicon, and microcrystalline silicon.
  • the first crystalline semiconductor portion 35 is a portion having a different crystallinity from the first amorphous semiconductor layer 31 and the third amorphous semiconductor layer 33, and is a portion composed of a non-amorphous semiconductor. it can.
  • the first crystalline semiconductor portion 35 includes at least one of first conductivity type crystalline silicon and i-type crystalline silicon.
  • the first crystalline semiconductor portion 35 may have, for example, an i-type portion provided on the second major surface 20b and a first conductivity-type portion provided thereon.
  • the first crystalline semiconductor portion 35 is provided so as to penetrate the first amorphous semiconductor layer 31 and the third amorphous semiconductor layer 33 and reach the first transparent electrode layer 23. That is, the height h 1 of the first crystalline semiconductor portion 35 from the second major surface 20 b is approximately the same as the thickness of the first amorphous semiconductor layer 31 and the third amorphous semiconductor layer 33 stacked. .
  • the first crystalline semiconductor portion 35 may be provided so as to penetrate only the third amorphous semiconductor layer 33 and reach the middle of the first amorphous semiconductor layer 31.
  • the height of the first crystalline semiconductor portion 35 is smaller than the thickness in which the first amorphous semiconductor layer 31 and the third amorphous semiconductor layer 33 are stacked. Further, it may be provided so as to reach the middle of the third amorphous semiconductor layer 33 without penetrating the third amorphous semiconductor layer 33. In this case, the height of the first crystalline semiconductor portion 35 is smaller than the thickness of the third amorphous semiconductor layer 33. Further, the first crystalline semiconductor portions 35 may be provided so as to have different heights.
  • the first crystalline semiconductor portion 35 is partially provided on the first region W1 of the second main surface 20b, for example, discretely provided on the second main surface 20b.
  • the first crystalline semiconductor portion 35 is arranged in an island shape in a plan view of the second main surface 20b, and is provided so as to form a plurality of columnar portions.
  • the area ratio of the first crystalline semiconductor portion 35 on the first region W1 is preferably 0.05% or more and 20% or less, and more preferably 0.1% or more and 10% or less. Further, when observed in a cross section intersecting with the second major surface 20b as shown in FIG. 2, the first crystalline semiconductor portion in the first amorphous semiconductor layer 31 and the third amorphous semiconductor layer 33 is observed.
  • the area ratio occupied by 35 is preferably 0.02% or more and 10% or less, and more preferably 0.05% or more and 5% or less.
  • the second semiconductor layer 22 includes a second amorphous semiconductor layer 32, a fourth amorphous semiconductor layer 34, and a second crystalline semiconductor portion 36.
  • the fourth amorphous semiconductor layer 34 is provided on the second major surface 20b, and the second amorphous semiconductor layer 32 is provided on the fourth amorphous semiconductor layer 34.
  • the second crystalline semiconductor portion 36 is provided in the fourth amorphous semiconductor layer 34 on the second major surface 20b.
  • the second amorphous semiconductor layer 32 is an amorphous semiconductor layer of a second conductivity type different from the first conductivity type, and is made of, for example, p-type amorphous silicon containing hydrogen.
  • the second amorphous semiconductor layer 32 has a thickness of about 2 nm to 50 nm, for example.
  • the second amorphous semiconductor layer 32 includes, for example, boron (B) as a second conductivity type impurity.
  • the fourth amorphous semiconductor layer 34 is a substantially intrinsic amorphous semiconductor, and is made of, for example, i-type amorphous silicon containing hydrogen.
  • the fourth amorphous semiconductor layer 34 is provided between the second major surface 20b and the second amorphous semiconductor layer 32, and has a thickness of about 2 nm to 25 nm, for example.
  • the fourth amorphous semiconductor layer 34 preferably has a lower film density than the first amorphous semiconductor layer 31 and the third amorphous semiconductor layer 33.
  • the film density of the first amorphous semiconductor layer 31 and the third amorphous semiconductor layer 33 is 2.2 g / cm 3 or more and 2.4 g / cm 3 or less
  • the film density of 34 is preferably 2.0 g / cm 3 or more and 2.2 g / cm 3 or less.
  • the fourth amorphous semiconductor layer 34 is configured to have a low film density at least in a portion in contact with the second major surface 20b.
  • the portion of the fourth amorphous semiconductor layer 34 that is in contact with the second amorphous semiconductor layer 32 may have a higher film density than the portion that is in contact with the second major surface 20b. 31 and the third amorphous semiconductor layer 33 may have the same film density.
  • the fourth amorphous semiconductor layer 34 may not be provided, and the second amorphous semiconductor layer 32 may be provided immediately above the second major surface 20b of the second region W2. In this case, at least a portion of the second amorphous semiconductor layer 32 that is in contact with the second major surface 20b may have a lower film density than the first amorphous semiconductor layer 31 and the third amorphous semiconductor layer 33.
  • the film density may be 2.0 g / cm 3 or more and 2.2 g / cm 3 or less.
  • the second crystalline semiconductor portion 36 is made of a crystalline semiconductor, like the first crystalline semiconductor portion 35, and includes, for example, at least one of single crystal silicon, polycrystalline silicon, and microcrystalline silicon.
  • the second crystalline semiconductor portion 36 is a portion that is different in crystallinity from the second amorphous semiconductor layer 32 and the fourth amorphous semiconductor layer 34, and is a portion composed of a non-amorphous semiconductor.
  • the second crystalline semiconductor portion 36 includes at least one of second conductivity type crystalline silicon and i-type crystalline silicon.
  • the second crystalline semiconductor portion 36 is partially provided on the second region W2 of the second major surface 20b, like the first crystalline semiconductor portion 35.
  • the second crystalline semiconductor portion 36 is provided so that the amount per unit area is smaller than that of the first crystalline semiconductor portion 35.
  • the area occupied by the second crystalline semiconductor unit 36 per unit area on the second region W2 of the second major surface 20b is such that the first crystalline semiconductor unit 35 on the first region W1 of the second major surface 20b. It is smaller than the area occupied per unit volume. Note that the second crystalline semiconductor portion 36 may not be provided.
  • the height h 2 of the second crystalline semiconductor portion 36 from the second major surface 20 b is smaller than the height h 1 of the first crystalline semiconductor portion 35 from the second major surface 20 b.
  • the second crystalline semiconductor portion 36 is provided so as not to reach the second transparent electrode layer 24 and is provided so as not to penetrate the fourth amorphous semiconductor layer 34. Therefore, the height h 2 of the second crystalline semiconductor portion 36 may be smaller than the thickness of the fourth amorphous semiconductor layer 34.
  • the first transparent electrode layer 23 is provided on the first semiconductor layer 21, and the second transparent electrode layer 24 is provided on the second semiconductor layer 22.
  • the first transparent electrode layer 23 and the second transparent electrode layer 24 are made of, for example, tin oxide (SnO 2 ), zinc oxide (ZnO), indium tin oxide (ITO), etc., tin (Sn), antimony (Sb), fluorine (F), a transparent conductive oxide (TCO) doped with aluminum (Al) or the like.
  • the first transparent electrode layer 23 and the second transparent electrode layer 24 are formed of indium tin oxide.
  • the thickness of the first transparent electrode layer 23 and the second transparent electrode layer 24 can be, for example, about 50 nm to 100 nm.
  • the first metal electrode layer 25 is provided on the first transparent electrode layer 23, and the second metal electrode layer 26 is provided on the second transparent electrode layer 24.
  • the first metal electrode layer 25 and the second metal electrode layer 26 are conductive materials containing a metal such as copper (Cu), tin (Sn), gold (Au), silver (Ag), nickel (Ni), titanium (Ti). It is a functional material layer.
  • the first metal electrode layer 25 and the second metal electrode layer 26 may be composed of a single layer or a plurality of layers.
  • the first metal electrode layer 25 and the second metal electrode layer 26 include, for example, a seed layer of about 50 nm to 1100 nm, a first plating layer of about 11 ⁇ m to 50 ⁇ m, and a second plating layer of about 1 ⁇ m to 5 ⁇ m.
  • the seed layer and the first plating layer are made of copper (Cu)
  • the second plating layer is made of tin (Sn).
  • the first electrode 14 is composed of the first transparent electrode layer 23 and the first metal electrode layer 25, and the second electrode 15 is composed of the second transparent electrode layer 24 and the second metal electrode layer 26. Is done.
  • the first electrode 14 collects carriers on the first conductivity type side
  • the second electrode 15 collects carriers on the second conductivity type side.
  • a separation groove 16 is provided between the first electrode 14 and the second electrode 15, and the first electrode 14 and the second electrode 15 are electrically insulated.
  • An insulating material may be provided inside the isolation groove 16, and for example, an insulating material such as silicon oxide (SiO 2 ), silicon nitride (SiN), or silicon oxynitride (SiON) may be provided.
  • the light-receiving surface protective layer 30 is provided on the first main surface 20a.
  • the light-receiving surface protective layer 30 functions as a passivation layer for the first main surface 20a.
  • the passivation layer may include at least one of a substantially intrinsic amorphous semiconductor layer, a first conductive type amorphous semiconductor layer, and a second conductive type amorphous semiconductor layer.
  • the passivation layer can be formed of amorphous silicon containing hydrogen, silicon oxide, silicon nitride, silicon oxynitride, or the like.
  • the passivation layer has a thickness of about 2 nm to 50 nm, for example.
  • the light-receiving surface protective layer 30 may further have a function as an antireflection film or a protective film.
  • the antireflection film or the protective film insulating layer can be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like.
  • the thickness of the antireflection film or the protective film insulating layer is appropriately set according to, for example, the antireflection characteristics and is, for example, about 80 nm to 1100 nm.
  • the texture structure 40 is formed on the first main surface 20 a of the substrate 20.
  • the formation method of the texture structure 40 is not specifically limited, For example, it can form by anisotropic etching using an alkaline solution.
  • a texture structure is not formed on the second main surface 20b of the substrate 20.
  • the illustrated substrate 20 may be formed by removing the texture structure of the second main surface 20b by wet etching or dry etching.
  • a light-receiving surface protective layer 30 is formed on the first main surface 20a, and a third amorphous semiconductor layer 33 and a first amorphous semiconductor layer 31 are formed on the second main surface 20b. And the 1st crystalline semiconductor part 35 is formed.
  • the light-receiving surface protective layer 30, the first amorphous semiconductor layer 31, the third amorphous semiconductor layer 33, and the first crystalline semiconductor portion 35 can be formed by a chemical vapor deposition (CVD) method such as a plasma CVD method.
  • CVD chemical vapor deposition
  • the first conductive type first amorphous on the third amorphous semiconductor layer 33 is formed.
  • a quality semiconductor layer 31 is formed.
  • the first crystalline semiconductor portion 35 is formed at the same time. Since the second major surface 20b is at least partly composed of a (100) plane of crystalline silicon, crystalline silicon can be partly formed even under conditions for forming amorphous silicon. When crystalline silicon is partially formed on the second major surface 20b, the first crystalline semiconductor portion 35 grows starting from that location. As a result, a layer in which amorphous silicon and columnar crystalline silicon are mixed can be formed at a time.
  • the ratio of the amorphous semiconductor layers 31 and 33 and the crystalline semiconductor portion 35 formed on the second main surface 20b is controlled by controlling the surface state of the second main surface 20b and the film formation conditions of the semiconductor layer. Can be adjusted. Of the crystalline silicon surface, crystalline silicon is likely to grow on the (100) plane, and crystalline silicon is difficult to grow on the (111) plane, so that the (100) plane and the (111) plane on the second main surface 20b are By adjusting the occupying ratio, the ratio of the portion formed by the first crystalline semiconductor portion 35 can be controlled. For example, the ratio occupied by the first crystalline semiconductor portion 35 can be reduced by partially forming a texture structure on the second major surface 20b and increasing the ratio of the (111) plane.
  • the first crystallinity can also be adjusted by adjusting the film formation rates of the first amorphous semiconductor layer 31 and the third amorphous semiconductor layer 33.
  • the formation ratio of the semiconductor part 35 can be controlled.
  • the light-receiving surface protective layer 30 is formed on the first main surface 20a.
  • the light-receiving surface protection layer 30 is an amorphous silicon layer
  • the light-receiving surface protection is performed simultaneously with the steps of forming the first amorphous semiconductor layer 31, the third amorphous semiconductor layer 33, and the first crystalline semiconductor portion 35.
  • Layer 30 can also be formed.
  • the light-receiving surface protective layer 30 may substantially contain only amorphous silicon or may contain crystalline silicon.
  • the crystalline silicon of the light-receiving surface protective layer 30 may be more or less than the second main surface 20b.
  • the light-receiving surface protective layer 30 does not have to be formed simultaneously with the first amorphous semiconductor layer 31, the third amorphous semiconductor layer 33, and the first crystalline semiconductor portion 35, and is formed before these layers. It may be formed after these layers.
  • a mask 42 is partially formed on the first amorphous semiconductor layer 31 and the first crystalline semiconductor portion 35, and the first non-pattern in the region where the mask 42 is not formed.
  • the crystalline semiconductor layer 31, the third amorphous semiconductor layer 33, and the first crystalline semiconductor portion 35 are removed.
  • the mask 42 is provided at a position corresponding to the first region W1. Thereby, the first amorphous semiconductor layer 31, the third amorphous semiconductor layer 33, and the first crystalline semiconductor portion 35 remain only in the first region W1, and the first semiconductor layer 21 is completed. In the second region W2 different from the first region W1, the second main surface 20b is exposed.
  • the fourth amorphous semiconductor layer 34, the second amorphous semiconductor layer 32, and the second crystalline semiconductor portion 36 are formed on the second main surface 20b exposed in the second region W2.
  • the second conductive type second amorphous semiconductor layer 32 is formed on the fourth amorphous semiconductor layer 34. It is formed.
  • the second crystalline semiconductor portion 36 can be formed at the same time. Thereby, the second semiconductor layer 22 is completed.
  • the second amorphous semiconductor layer 32 and the fourth amorphous semiconductor layer 34 are formed under conditions where the growth of crystalline silicon is more hindered than in the first region W1.
  • at least one of the second amorphous semiconductor layer 32 and the fourth amorphous semiconductor layer 34 is formed at a higher deposition rate than the first amorphous semiconductor layer 31 and the third amorphous semiconductor layer 33.
  • at least one of the second amorphous semiconductor layer 32 and the fourth amorphous semiconductor layer 34 has a lower film density than the first amorphous semiconductor layer 31 and the third amorphous semiconductor layer 33.
  • a texture structure (not shown) may be formed in the second region W2 of the second main surface 20b by performing anisotropic etching on the second main surface 20b exposed in the second region W2.
  • the formation of the second crystalline semiconductor portion 36 may be inhibited by selectively forming a texture in the second region W2 of the second main surface 20b to increase the proportion of the (111) plane.
  • the ratio of the 2nd crystalline semiconductor part 36 contained in the 2nd semiconductor layer 22 can be made small.
  • the area ratio of the second crystalline semiconductor portion 36 occupying the second region W2 can be made smaller than the area ratio of the first crystalline semiconductor portion 35 occupying the first region W1.
  • the ratio of the first crystalline semiconductor portion 35 and the second crystalline semiconductor portion 36 is specified by a cross section intersecting the second major surface 20b, the first amorphous semiconductor layer 31 and the third amorphous semiconductor portion 31 are specified.
  • the second crystalline semiconductor portion 36 occupies in the second amorphous semiconductor layer 32 and the fourth amorphous semiconductor layer 34 rather than the area ratio of the first crystalline semiconductor portion 35 in the semiconductor layer 33. The area ratio can be reduced.
  • the first transparent electrode layer 23 and the first metal electrode layer 25 are formed on the first semiconductor layer 21, and the second transparent electrode layer 24 and the second metal electrode layer 26 are formed on the second semiconductor layer 22.
  • the first transparent electrode layer 23 and the second transparent electrode layer 24 are formed by a CVD method such as a plasma CVD method or a thin film formation method such as a sputtering method.
  • the first metal electrode layer 25 and the second metal electrode layer 26 are formed by a sputtering method, a plating method, or the like.
  • the solar battery cell 10 shown in FIG. 2 is completed.
  • the first semiconductor layer 21 is formed and the second semiconductor layer 22 is formed after removing a part of the first semiconductor layer 21.
  • the first semiconductor layer 21 and the second semiconductor layer 22 are formed.
  • the order may be reversed. That is, the first semiconductor layer 21 may be formed after the second semiconductor layer 22 is formed on the entire surface of the second major surface 20b and a part of the second semiconductor layer 22 is removed.
  • the first semiconductor layer 21 and the second semiconductor layer 22 may be formed only in the corresponding regions by providing a mask on the second main surface 20b.
  • the amorphous semiconductor layers 31 and 33 and the crystalline semiconductor portion 35 are mixed in the first region W1, so that the first region W1 can be prevented from being significantly deteriorated in passivation, and the first region W1.
  • the series resistance in the region W1 can be reduced.
  • H hydrogen
  • an amorphous semiconductor has lower conductivity than a crystalline semiconductor, and contributes to an increase in the series resistance of the solar battery cell 10.
  • the inventors of the present invention form both the amorphous semiconductor layers 31 and 33 and the crystalline semiconductor portion 35 in the first region W1, and mix them at an appropriate ratio, thereby generating power generation efficiency of the solar battery cell 10. It was found that further improvement is possible.
  • the area ratio occupied by the first crystalline semiconductor portion 35 on the first region W1 is 0.05% or more and 20% or less, preferably 0.1% or more and 10% or less. Compared with the case where the single crystalline semiconductor portion 35 is not provided, the power generation efficiency can be increased. Further, when the cross section intersecting the second main surface 20b is observed, the area ratio occupied by the first crystalline semiconductor portion 35 in the first amorphous semiconductor layer 31 and the third amorphous semiconductor layer 33 is set to 0.
  • the power generation efficiency can be increased by setting the ratio between 0.02% and 10%, preferably between 0.05% and 5%.
  • One reason for this is that since the vicinity of the first region W1 is a region having a low minority carrier density, even if the passivation property is reduced by providing the first crystalline semiconductor portion 35, the carrier recombination rate is reduced. It is thought that it does not lead to a significant increase.
  • the second crystalline semiconductor portion 36 is not substantially provided in the second region W2, and even if the second crystalline semiconductor portion 36 is provided, a proportion of the second crystalline semiconductor portion 36 formed is higher than that of the first region W1. Small is preferable. This is because the area of the second region W2 is larger than the area of the first region W1, so that the current density is lower than that of the first region W1, and the contribution to improving the power generation efficiency by reducing the series resistance is small.
  • the present embodiment it is possible to reduce the series resistance of the first region W1 while providing both the first region W1 and the second region W2 with a certain degree of passivation. Thereby, carriers can be efficiently collected from both the first region W1 and the second region W2, and the series resistance between the first electrode 14 and the second electrode 15 of the solar battery cell 10 can be reduced. As a result, the power generation efficiency of the solar battery cell 10 can be improved.
  • the first crystalline semiconductor portion 35 extends in a columnar shape from the second major surface 20b toward the first transparent electrode layer 23, thereby reducing the resistance by the first crystalline semiconductor portion 35. Can enhance the effect.
  • the first crystalline semiconductor part 35 is provided so as to reach the first transparent electrode layer 23, the substrate 20 and the second transparent electrode layer 24 are directly connected by the low-resistance first crystalline semiconductor part 35. Therefore, the series resistance of the first region W1 can be further reduced.
  • the effect of reducing the series resistance can be enhanced.
  • the solar battery cell (10) of an aspect is A first conductive type crystalline semiconductor substrate (20); A first semiconductor layer (21) provided on a first region (W1) of one main surface (second main surface 20b) of the substrate (20); A second semiconductor layer (22) provided on a second region (W2) different from the first region (W1) of one main surface (second main surface 20b); A first transparent electrode layer (23) provided on the first semiconductor layer (21); A second transparent electrode layer (24) provided on the second semiconductor layer (22).
  • the first semiconductor layer (21) has a first conductive type first amorphous semiconductor layer (31) and a columnar shape from one main surface (second main surface 20b) to the first transparent electrode layer (23). Extending first crystalline semiconductor portion (35),
  • the second semiconductor layer (22) includes a second amorphous semiconductor layer (32) of a second conductivity type different from the first conductivity type.
  • the first semiconductor layer (21) is a substantially intrinsic third amorphous semiconductor layer (33) provided between one main surface (second main surface 20b) and the first amorphous semiconductor layer (31). ) May further be included.
  • the first crystalline semiconductor part (35) may be provided so as to penetrate at least the third amorphous semiconductor layer (33) and reach the first amorphous semiconductor layer (31).
  • the second amorphous semiconductor layer (32) is in contact with one main surface (second main surface 20b) of the first semiconductor layer (21) with a film density of at least a portion in contact with one main surface (second main surface 20b). It may be lower than the portion.
  • the second semiconductor layer (22) is provided between one main surface (second main surface 20b) and the second amorphous semiconductor layer (32), and is substantially a fourth intrinsic amorphous semiconductor layer ( 34) may further be included.
  • the fourth amorphous semiconductor layer (34) is in contact with one main surface (second main surface 20b) of the first semiconductor layer (21) with a film density of at least a portion in contact with one main surface (second main surface 20b). It may be lower than the portion.
  • the portion in contact with one main surface (second main surface 20b) of the first semiconductor layer (21) is either the first amorphous semiconductor layer (31) or the third amorphous semiconductor layer (33). Also good.
  • the first crystalline semiconductor part (35) may reach the first transparent electrode layer (23).
  • the first crystalline semiconductor part (35) may be partially provided on the first region (W1).
  • the first amorphous semiconductor layer (31) may have a higher impurity concentration of the first conductivity type than the substrate (20).
  • the second semiconductor layer (22) may further include a second crystalline semiconductor portion (36) provided on one main surface (second main surface 20b).
  • the amount of the first crystalline semiconductor portion (35) provided per unit area of the first region (W1) is the amount of the second crystalline semiconductor portion (36) provided per unit area of the second region (W2). There may be more.
  • the height (h 1 ) from one main surface (second main surface 20b) of the first crystalline semiconductor portion (35) is one main surface (second main surface 20b) of the second crystalline semiconductor portion (36). It may be larger than the height (h 2 ).
  • the first area (W1) may be narrower than the second area (W2).
  • Another aspect of the present embodiment is a method for manufacturing a solar battery cell (10).
  • This method Forming a first semiconductor layer (21) in a first region W1 on one main surface (second main surface 20b) of a first conductive type crystalline semiconductor substrate (20); Forming a second semiconductor layer (22) on a second region (W2) different from the first region (W1) of one main surface (second main surface 20b); Transparent electrode layers (first transparent electrode layer 23 and second transparent electrode layer 24) are formed on the first semiconductor layer (21) and the second semiconductor layer (22).
  • the first semiconductor layer (21) is directed from the first conductive type first amorphous semiconductor layer (31) to the transparent electrode layer (first transparent electrode layer 23) from one main surface (second main surface 20b).
  • the second semiconductor layer (22) includes a second conductive semiconductor type second amorphous semiconductor layer (32) different from the first conductive type, The first amorphous semiconductor layer (31) and the first crystalline semiconductor portion (35) are formed simultaneously.
  • the first amorphous semiconductor layer (31) and the first crystalline semiconductor portion (35) are formed using a texture structure formed at least partially on one main surface (second main surface 20b) as a base. Also good.
  • FIG. 7 is a cross-sectional view showing the structure of a solar battery cell 110 according to a modification.
  • This modification is different from the above-described embodiment in that a high impurity concentration region 120c having a high first conductivity type impurity concentration is provided in the vicinity of the second main surface 20b of the first region W1.
  • the substrate 120 includes a bulk region 120d having a low first conductivity type impurity concentration and a high impurity concentration region 120c having a high first conductivity type impurity concentration.
  • the high impurity concentration region 120c is located immediately above the second main surface 20b of the first region W1 when the second main surface 20b is viewed from below. When the second main surface 20b is viewed from above with the top and bottom of FIG. 7 upside down, it can be said that the second main surface 20b is located directly below the second main surface 20b of the first region W1.
  • the high impurity concentration region 120c is provided in the first region W1, and is provided avoiding the second region W2.
  • the impurity concentration of 120c is about 1 ⁇ 10 17 / cm 3 to 1 ⁇ 10 20 / cm 3 , for example, about 1 ⁇ 10 18 / cm 3 to 2 ⁇ 10 19 / cm 3 .
  • the high impurity concentration region 120c includes, for example, phosphorus (P) as the first conductivity type impurity.
  • the impurity concentration of the high impurity concentration region 120 c may be higher than the impurity concentration of the first amorphous semiconductor layer 31.
  • the high impurity concentration region 120c is a depth h 3 from the second major surface 20b is formed so as to be 5 ⁇ m or less, for example 200nm or less, is formed so preferably is about 5 nm ⁇ 100 nm.
  • the high impurity concentration region 120c can be formed, for example, by diffusing impurities of the first conductivity type from the second major surface 20b in the first region W1.
  • the high impurity concentration region 120c may be formed by an ion implantation process.
  • the minority carriers in the vicinity of the first region W1 can be further reduced to improve the passivation property.
  • the deterioration of the passivation due to the provision of the first crystalline semiconductor part 35 is compensated, and both the passivation property and the low resistance can be more suitably achieved.
  • the substrate (120) is provided immediately below one main surface (second main surface 20b) in the first region (W1), and the other part (
  • a high impurity concentration region (120c) having a higher impurity concentration of the first conductivity type than the bulk region 120d) may be included.
  • FIG. 8 is a cross-sectional view showing a configuration of a solar battery cell 210 according to a modification.
  • This modification is different from the above-described embodiment in that a high impurity concentration layer 244 is further provided between the second main surface 20b of the first region W1 and the first semiconductor layer 21.
  • the high impurity concentration layer 244 is a portion having a high first conductivity type impurity concentration, and includes, for example, phosphorus (P) as the first conductivity type impurity, as in the above-described modification.
  • the high impurity concentration layer 244 is provided in the first region W1, and is provided avoiding the second region W2.
  • the high impurity concentration layer 244 can be formed by a CVD method or the like, similar to the first amorphous semiconductor layer 31, and is made of crystalline silicon, amorphous silicon, silicon oxide, silicon oxynitride, silicon nitride, or the like. be able to.
  • the high impurity concentration layer 244 may be selectively formed in the first region W1 by providing a mask in the second region W2, or the second region after being formed in both the first region W1 and the second region W2. A portion formed on the region W2 may be removed.
  • the impurity concentration of the high impurity concentration layer 244 is about 1 ⁇ 10 19 / cm 3 to 5 ⁇ 10 20 / cm 3 , for example, about 5 ⁇ 10 19 / cm 3 to 1 ⁇ 10 20 / cm 3. it can.
  • the impurity concentration of the high impurity concentration layer 244 is preferably lower than the impurity concentration of the first amorphous semiconductor layer 31.
  • High impurity concentration layer 244 is provided such that the second major surface 20b height h 4 from becomes 100nm or less, for example, about 0.1 nm ⁇ 50 nm.
  • the height h 4 of the high impurity concentration layer 244 is preferably about 0.1 nm to 3 nm, for example, 2 nm or less.
  • the minority carriers in the vicinity of the first region W1 can be further reduced and the passivation can be improved.
  • the decrease in passivation due to the provision of the first crystalline semiconductor portion 35 is compensated, and both the passivation property and the low resistance can be more suitably achieved.
  • the solar battery (210) of an aspect is provided between one main surface (second main surface 20b) and the first semiconductor layer (21), and has a higher impurity concentration of the first conductivity type than the substrate (20).
  • a high impurity concentration layer (244) may be further provided.
  • FIG. 9 is a cross-sectional view illustrating a configuration of a solar battery cell 310 according to a modification.
  • a first oxide layer 327 is provided between the second major surface 20b and the first semiconductor layer 21, and a second oxide layer 328 is disposed between the second major surface 20b and the second semiconductor layer 22. It differs from the above-described embodiment in that it is provided.
  • the first oxide layer 327 is provided on the first region W1 of the second main surface 20b, and the second oxide layer 328 is provided on the second region W2 of the second main surface 20b.
  • the first oxide layer 327 and the second oxide layer 328 are made of, for example, silicon oxide, silicon nitride, aluminum oxide, or the like.
  • the first oxide layer 327 and the second oxide layer 328 function as a passivation layer for the second major surface 20b. Further, the first oxide layer 327 functions as a base layer for controlling the generation amount of the first crystalline semiconductor part 35 included in the first semiconductor layer 21. Similarly, the second oxide layer 328 functions as a base layer for suppressing the generation of the second crystalline semiconductor portion in the layer of the second semiconductor layer 22. By forming the second oxide layer 328 thick, the second crystalline semiconductor portion can be substantially not formed on the second oxide layer 328.
  • the amount of the first crystalline semiconductor portion 35 formed on the second main surface 20b can be controlled by controlling the amount, thickness, formation range, and the like of the oxide layer on the second main surface 20b. .
  • the first oxide layer 327 is formed to have a relatively small thickness, and is a base layer in which the first crystalline semiconductor portion 35 is easily generated.
  • the first oxide layer 327 does not uniformly cover the entire second main surface 20b of the first region W1, but the second main surface 20b is partially exposed or partially the first region W1.
  • the oxide layer 327 is formed to have a small thickness. As a result, the generation of crystalline silicon is promoted at locations where the first oxide layer 327 is not provided or where the thickness of the first oxide layer 327 is small, and the first crystalline semiconductor portion 35 is partially formed. You can make it.
  • the second oxide layer 328 is formed so as to have a relatively large thickness, and serves as a base on which the second crystalline semiconductor portion is hardly generated.
  • the second oxide layer 328 is formed so as to uniformly cover the entire second main surface 20b of the second region W2. That is, the second oxide layer 328 is formed so that the second main surface 20b is not exposed without forming the second oxide layer 328 and the thickness of the second oxide layer 328 is not partially reduced. Is done. Thereby, the generation of crystalline silicon on the second oxide layer 328 can be inhibited, and the second crystalline semiconductor portion can be substantially not formed.
  • the first oxide layer 327 and the second oxide layer 328 can be formed by a CVD method, a chemical oxidation method, or the like.
  • the thickness and the range where the first oxide layer 327 and the second oxide layer 328 are formed can be changed by controlling the film formation conditions and the growth time of the oxide layer.
  • the first oxide layer 327 is formed before the formation of the first semiconductor layer 21, and the first semiconductor layer 21 is formed on the first oxide layer 327.
  • the second oxide layer 328 is formed before the second semiconductor layer 22 is formed, and the second semiconductor layer 22 is formed on the second oxide layer 328.
  • the first oxide layer 327 and the second oxide layer 328 are provided, so that the formation amounts of the first crystalline semiconductor portion 35 and the second crystalline semiconductor portion can be more suitably controlled.
  • the first oxide layer 327 and the second oxide layer 328 can function as a passivation layer, and the passivation property of the second main surface 20b can be improved. Therefore, according to this modification, it is possible to improve the power generation efficiency of the solar battery cell 310 by making the passivation property and the low resistance more suitable at the same time.
  • the solar cell (310) of an aspect includes a first oxide provided at least partially between the one main surface (second main surface 20b) and the first semiconductor layer 21 and on the first region (W1).
  • a layer (327) may further be provided.
  • the solar cell (310) of a certain aspect is provided between the one main surface (second main surface 20b) and the second semiconductor layer (22) and at least partially provided on the second region (W2).
  • An oxide layer (328) may further be provided.
  • the thickness of the second oxide layer (328) may be greater than the thickness of the first oxide layer (327).
  • the first amorphous semiconductor layer (31) and the first crystalline semiconductor part (35) are at least partially on one main surface (second main surface 20b).
  • the oxide layer (first oxide layer 327) formed may be formed as a base.
  • FIG. 10 is a cross-sectional view illustrating a configuration of a solar battery cell 410 according to a modification. This modification is different from the above-described embodiment in that the first crystalline semiconductor part 435 includes a base layer 435a and a plurality of columnar parts 435b extending from the base layer 435a toward the first transparent electrode layer 23.
  • the first semiconductor layer 421 includes a first amorphous semiconductor layer 31, a third amorphous semiconductor layer 33, and a first crystalline semiconductor portion 435.
  • the first crystalline semiconductor portion 435 includes a base layer 435a that is thinly formed on the first region W1 of the second main surface 20b, and a plurality of columnar portions 435b that extend from the base layer 435a toward the first transparent electrode layer 23. including.
  • the third amorphous semiconductor layer 33 is provided on the base layer 435 a, and the first amorphous semiconductor layer 31 is provided on the third amorphous semiconductor layer 33.
  • the base layer 435a is provided so as to occupy more than half the area of the first region W1, and is provided so as to occupy, for example, 80% or more or 90% or more of the first region W1.
  • the thickness of the base layer 435a is about 0.5 nm to 25 nm, for example, about 0.5 nm to 5 nm.
  • the base layer 435a may be formed thinner than the first amorphous semiconductor layer 31 and the third amorphous semiconductor layer 33.
  • Each of the plurality of columnar portions 435b extends from the base layer 435a toward the first transparent electrode layer 23 and is provided so as to penetrate the first amorphous semiconductor layer 31 and the third amorphous semiconductor layer 33.
  • the series resistance of the first region W1 can be further reduced by increasing the area of the base layer 435a formed of a highly conductive crystalline semiconductor.
  • the base layer 435a thin, the number of defects per unit area of the first region W1 can be reduced, and the influence of the deterioration in passivation due to lattice defects can be reduced. Therefore, according to this modification, the power generation efficiency of the solar battery cell 410 can be further increased.
  • the first crystalline semiconductor portion (435) includes a base layer (435a) provided so as to cover more than half of the first region (W1), and a base layer (435a). And a columnar part (435b) extending toward the first transparent electrode layer (23).
  • the present invention has been described with reference to the above-described embodiment.
  • the present invention is not limited to the above-described embodiment, and appropriate combinations or replacements of the configurations of the embodiment and the modification examples are made. Those are also included in the present invention.
  • the power generation efficiency of the solar battery cell can be improved.

Abstract

太陽電池セル１０は、第１導電型の結晶性半導体の基板２０と、基板２０の一主面の第１領域Ｗ１上に設けられる第１半導体層２１と、一主面の第１領域Ｗ１と異なる第２領域Ｗ２上に設けられる第２半導体層２２と、第１半導体層２１上に設けられる第１透明電極層２３と、第２半導体層２２上に設けられる第２透明電極層２４と、を備える。第１半導体層２１は、第１導電型の第１非晶質半導体層３１と、一主面から第１透明電極層２３に向けて延びる第１結晶性半導体部３５と、を含む。第２半導体層２２は、第１導電型と異なる第２導電型の第２非晶質半導体層３２を含む。

Description

太陽電池セル及び太陽電池セルの製造方法
　本発明は、太陽電池セル及び太陽電池セルの製造方法に関する。
　発電効率の高い太陽電池として、光が入射する受光面に対向する裏面にｎ型半導体層およびｐ型半導体層の双方が形成された裏面接合型の太陽電池がある。例えば、結晶性の半導体基板の一主面上にｎ型非晶質半導体層およびｐ型非晶質半導体層が設けられる（例えば、特許文献１参照）。
米国特許出願公開第２０１４／０２２４３０６号明細書
　非晶質半導体層は、結晶性基板表面のパッシベーションに有効であるが、太陽電池セルの直列抵抗を増加させる一因となる。発電効率の向上には、パッシベーション性と低抵抗性を両立できることが好ましい。
　本発明はこうした状況に鑑みてなされたものであり、その目的は、より発電効率の高い太陽電池セルを提供することにある。
　本発明のある態様の太陽電池セルは、第１導電型の結晶性半導体の基板と、基板の一主面の第１領域上に設けられる第１半導体層と、一主面の第１領域と異なる第２領域上に設けられる第２半導体層と、第１半導体層上に設けられる第１透明電極層と、第２半導体層上に設けられる第２透明電極層と、を備える。第１半導体層は、第１導電型の第１非晶質半導体層と、一主面から第１透明電極層に向けて延びる第１結晶性半導体部と、を含む。第２半導体層は、第１導電型と異なる第２導電型の第２非晶質半導体層を含む。
　本発明の別の態様は、太陽電池セルの製造方法である。この方法は、第１導電型の結晶性半導体の基板の一主面上の第１領域に第１半導体層を形成し、一主面の第１領域と異なる第２領域上に第２半導体層を形成し、第１半導体層上および第２半導体層上に透明電極層を形成する。第１半導体層は、第１導電型の第１非晶質半導体層と、一主面から透明電極層に向けて延びる第１結晶性半導体部と、を含む。第２半導体層は、第１導電型と異なる第２導電型の第２非晶質半導体層を含む。第１非晶質半導体層および第１結晶性半導体部は、同時に形成される。
　本発明によれば、太陽電池セルの発電効率を向上できる。
実施の形態に係る太陽電池セルの構造を示す平面図である。 図１の太陽電池セルの構造を示す断面図である。 太陽電池セルの製造工程を模式的に示す図である。 太陽電池セルの製造工程を模式的に示す図である。 太陽電池セルの製造工程を模式的に示す図である。 太陽電池セルの製造工程を模式的に示す図である。 変形例に係る太陽電池セルの構造を示す断面図である。 変形例に係る太陽電池セルの構造を示す断面図である。 変形例に係る太陽電池セルの構造を示す断面図である。 変形例に係る太陽電池セルの構造を示す断面図である。
　本発明を具体的に説明する前に、概要を述べる。本実施の形態は、太陽電池セルである。太陽電池セルは、第１導電型の結晶性半導体の基板と、基板の一主面の第１領域上に設けられる第１半導体層と、一主面の第１領域と異なる第２領域上に設けられる第２半導体層と、第１半導体層上に設けられる第１透明電極層と、第２半導体層上に設けられる第２透明電極層と、を備える。第１半導体層は、第１導電型の第１非晶質半導体層と、一主面から第１透明電極層に向けて延びる第１結晶性半導体部と、を含む。第２半導体層は、第１導電型と異なる第２導電型の第２非晶質半導体層を含む。本実施の形態によれば、第１領域上に非晶質半導体層と結晶性半導体部の双方を設けることにより、非晶質半導体層によるパッシベーション性の向上と、結晶性半導体部による直列抵抗の低減とを両立させ、太陽電池セルの発電効率を高めることができる。
　以下、図面を参照しながら、本発明を実施するための形態について詳細に説明する。図面の説明において同一の要素には同一の符号を付し、重複する説明を適宜省略する。
　図１は、実施の形態に係る太陽電池セル１０を示す平面図であり、太陽電池セル１０の裏面１３の構造を示す。太陽電池セル１０は、裏面１３に設けられる第１電極１４および第２電極１５を備える。太陽電池セル１０は、いわゆるバックコンタクト型の太陽電池であり、受光面側には電極が設けられず、受光面とは反対側の裏面１３に極性の異なる第１電極１４および第２電極１５の双方が設けられる。
　第１電極１４は、ｘ方向に延びる第１バスバー電極１４ａと、第１バスバー電極１４ａと交差するｙ方向に延びる複数の第１フィンガー電極１４ｂとを含み、櫛歯状に形成される。第２電極１５は、ｘ方向に延びる第２バスバー電極１５ａと、第２バスバー電極１５ａと交差するｙ方向に延びる複数の第２フィンガー電極１５ｂとを含み、櫛歯状に形成される。第１電極１４および第２電極１５は、それぞれの櫛歯が噛み合って互いに間挿し合うように形成される。第１電極１４及び第２電極１５のそれぞれは、複数のフィンガーのみにより構成され、バスバーを有さないバスバーレス型の電極であってもよい。
　図２は、実施の形態に係る太陽電池セル１０の構造を示す断面図であり、図１のＡ－Ａ線断面を示す。太陽電池セル１０は、基板２０と、第１半導体層２１と、第２半導体層２２と、第１透明電極層２３と、第２透明電極層２４と、第１金属電極層２５と、第２金属電極層２６と、受光面保護層３０とを備える。太陽電池セル１０は、裏面１３側にヘテロ接合が形成される裏面接合型の太陽電池である。
　太陽電池セル１０は、受光面１２および裏面１３を有する。受光面１２は、太陽電池セル１０において主に光（太陽光）が入射される主面を意味し、具体的には、太陽電池セル１０に入射される光の大部分が入射される面を意味する。一方、裏面１３は、受光面１２とは反対側の他方の主面を意味する。
　基板２０は、第１導電型を有する結晶性半導体により構成される。結晶性半導体基板の具体例としては、例えば、単結晶シリコンウェハ、多結晶シリコンウェハなどの結晶シリコン（Ｓｉ）ウェハが挙げられる。本実施の形態では、基板２０がｎ型の単結晶シリコンウェハである場合を示し、第１導電型がｎ型、第２導電型がｐ型である場合を示す。基板２０は、第１導電型の不純物を含み、例えばシリコンにドープされるｎ型の不純物としてリン（Ｐ）を含む。基板２０のｎ型不純物の濃度は特に限定されないが、例えば１×１０１５／ｃｍ３～１×１０１６／ｃｍ３程度である。
　なお太陽電池セルは、半導体基板として結晶性半導体基板以外の半導体基板により構成することができる。例えば、ガリウム砒素（ＧａＡｓ）やインジウム燐（ＩｎＰ）などからなる化合物半導体ウェハを用いてもよい。また、第１導電型がｐ型であり、第２導電型がｎ型であってもよい。
　基板２０は、受光面１２側の第１主面２０ａと、裏面１３側の第２主面２０ｂとを有する。基板２０は、第１主面２０ａに入射する光を吸収し、キャリアとして電子および正孔を生成する。第１主面２０ａには、入射する光の吸収効率を高めるためのテクスチャ構造４０が設けられる。一方、第２主面２０ｂには第１主面２０ａと同様のテクスチャ構造が設けられず、第１主面２０ａと比べて第２主面２０ｂの平坦性は高い。なお、第２主面２０ｂに少なくとも部分的にテクスチャ構造が設けられてもよく、例えば、後述する第１領域Ｗ１と第２領域Ｗ２の間で第２主面２０ｂ上のテクスチャ構造に差が設けられてもよい。
　基板２０の第２主面２０ｂの上には、第１半導体層２１および第２半導体層２２が設けられる。第１半導体層２１は第２主面２０ｂの第１領域Ｗ１上に設けられ、第２半導体層２２は第２主面２０ｂの第１領域Ｗ１と異なる第２領域Ｗ２上に設けられる。第１半導体層２１および第２半導体層２２は、それぞれが第１電極１４および第２電極１５に対応するように櫛歯状に形成され、互いに間挿し合うように形成される。したがって、第１領域Ｗ１と第２領域Ｗ２は、第２主面２０ｂ上においてｘ方向に交互に配列される。
　第１領域Ｗ１は第１導電型側であり、基板２０にて生成されたキャリアのうち第１導電型側のキャリアを収集する。基板２０が第１導電型であるため、第１領域Ｗ１は多数キャリアを収集する領域と言える。一方、第２領域Ｗ２は第２導電型側であり、少数キャリアである第２導電型側のキャリアを収集する。第１導電型がｎ型、第２導電型がｐ型の場合、第１領域Ｗ１が電子を収集し、第２領域Ｗ２が正孔を収集する。
　少数キャリアは多数キャリアに比べて収集効率が低い。そこで、セル全体の発電効率を高めるため、多数キャリア側である第１領域Ｗ１の第１面積Ｓ１よりも少数キャリア側である第２領域Ｗ２の第２面積Ｓ２を大きくしている。第１面積Ｓ１と第２面積Ｓ２の比Ｓ２／Ｓ１は、１．５以上５以下となるように設定され、例えば２以上４以下となるように設定される。
　第１半導体層２１は、第１非晶質半導体層３１と、第３非晶質半導体層３３と、第１結晶性半導体部３５とを含む。第３非晶質半導体層３３は第２主面２０ｂ上に設けられ、第１非晶質半導体層３１は第３非晶質半導体層３３上に設けられる。第１結晶性半導体部３５は、第１非晶質半導体層３１および第３非晶質半導体層３３の層内に設けられ、第２主面２０ｂから第１透明電極層２３に向けて柱状に延びるように設けられる。
　第１非晶質半導体層３１は、第１導電型の非晶質半導体層であり、例えば、水素（Ｈ）を含むｎ型非晶質シリコン（アモルファスシリコン）で構成される。第１非晶質半導体層３１は、例えば２ｎｍ～５０ｎｍ程度の厚さを有する。第１非晶質半導体層３１は、基板２０と同じ第１導電型の不純物として例えばリン（Ｐ）を含み、基板２０よりも不純物濃度が高いことが好ましい。第１非晶質半導体層３１の不純物濃度は、１×１０２０／ｃｍ３～１×１０２１／ｃｍ３程度である。
　第３非晶質半導体層３３は、実質的に真性な非晶質半導体であり、例えば、水素を含むｉ型の非晶質シリコンで構成される。本明細書において、実質的に真性な半導体を「ｉ型半導体」ともいう。また、実質的に真性な半導体とは、ｎ型またはｐ型の不純物となる元素を積極的に使用せずに成膜された半導体層を含み、化学気相成長法（ＣＶＤ）等による形成時に、ドーパントガスを供給せずに形成された半導体層を含む。具体的には、ジボラン（Ｂ２Ｈ６）やホスフィン（ＰＨ３）などのドーパントガスを供給せずに、水素（Ｈ２）で希釈したシラン（ＳｉＨ４）などを供給して得られたシリコンを含む。
　第３非晶質半導体層３３は、第２主面２０ｂと第１非晶質半導体層３１の間に設けられ、例えば２ｎｍ～２５ｎｍ程度の厚さを有する。なお、第３非晶質半導体層３３が設けられなくてもよく、第１領域Ｗ１の第２主面２０ｂの直上に第１非晶質半導体層３１が設けられてもよい。
　第１結晶性半導体部３５は、結晶質の半導体で構成され、例えば、単結晶シリコン、多結晶シリコンおよび微結晶シリコンの少なくとも一つを含む。第１結晶性半導体部３５は、第１非晶質半導体層３１および第３非晶質半導体層３３とは結晶性の異なる部分であり、非晶質ではない半導体で構成される部分ということができる。第１結晶性半導体部３５は、第１導電型の結晶質シリコンおよびｉ型の結晶質シリコンの少なくとも一方を含む。第１結晶性半導体部３５は、例えば、第２主面２０ｂ上に設けられるｉ型の部分と、その上に設けられる第１導電型の部分とを有してもよい。
　第１結晶性半導体部３５は、第１非晶質半導体層３１および第３非晶質半導体層３３を貫通して第１透明電極層２３に達するように設けられる。つまり、第１結晶性半導体部３５の第２主面２０ｂからの高さｈ１は、第１非晶質半導体層３１および第３非晶質半導体層３３を積層させた厚さと同程度である。
　なお、第１結晶性半導体部３５は、第３非晶質半導体層３３のみを貫通して第１非晶質半導体層３１の中途まで到達するように設けられてもよい。この場合、第１結晶性半導体部３５の高さは、第１非晶質半導体層３１および第３非晶質半導体層３３を積層させた厚さよりも小さい。また、第３非晶質半導体層３３を貫通せずに第３非晶質半導体層３３の中途まで到達するように設けられてもよい。この場合、第１結晶性半導体部３５の高さは、第３非晶質半導体層３３の厚さよりも小さい。また、第１結晶性半導体部３５はそれぞれが異なる高さを有するように設けられてもよい。
　第１結晶性半導体部３５は、第２主面２０ｂの第１領域Ｗ１上において部分的に設けられ、例えば第２主面２０ｂ上において離散的に設けられる。第１結晶性半導体部３５は、例えば、第２主面２０ｂの平面視において島状に配置され、複数の柱状部が形成されるように設けられる。第１領域Ｗ１上において第１結晶性半導体部３５が占める面積割合は、０．０５％以上２０％以下であることが好ましく、０．１％以上１０％以下であることがより好ましい。また、図２に示されるような第２主面２０ｂに交差する断面で観察した場合、第１非晶質半導体層３１および第３非晶質半導体層３３の層内で第１結晶性半導体部３５が占める面積割合は、０．０２％以上１０％以下であることが好ましく、０．０５％以上５％以下であることがより好ましい。このような数値範囲とすることにより、第１非晶質半導体層３１および第３非晶質半導体層３３によるパッシベーション性向上と、第１結晶性半導体部３５による直列抵抗低減とを好適に両立できる。
　第２半導体層２２は、第２非晶質半導体層３２と、第４非晶質半導体層３４と、第２結晶性半導体部３６とを含む。第４非晶質半導体層３４は第２主面２０ｂ上に設けられ、第２非晶質半導体層３２は第４非晶質半導体層３４上に設けられる。第２結晶性半導体部３６は、第２主面２０ｂ上の第４非晶質半導体層３４の層内に設けられる。
　第２非晶質半導体層３２は、第１導電型とは異なる第２導電型の非晶質半導体層であり、例えば、水素を含むｐ型の非晶質シリコンで構成される。第２非晶質半導体層３２は、例えば２ｎｍ～５０ｎｍ程度の厚さを有する。第２非晶質半導体層３２は、例えば、第２導電型の不純物としてボロン（Ｂ）を含む。
　第４非晶質半導体層３４は、実質的に真性な非晶質半導体であり、例えば、水素を含むｉ型の非晶質シリコンで構成される。第４非晶質半導体層３４は、第２主面２０ｂと第２非晶質半導体層３２の間に設けられ、例えば２ｎｍ～２５ｎｍ程度の厚さを有する。
　第４非晶質半導体層３４は、第１非晶質半導体層３１や第３非晶質半導体層３３よりも膜密度が低いことが好ましい。例えば、第１非晶質半導体層３１や第３非晶質半導体層３３の膜密度が２．２ｇ／ｃｍ３以上２．４ｇ／ｃｍ３以下であるのに対し、第４非晶質半導体層３４の膜密度は２．０ｇ／ｃｍ３以上２．２ｇ／ｃｍ３以下であることが好ましい。第４非晶質半導体層３４は、少なくとも第２主面２０ｂに接する部分において膜密度が低くなるように構成される。したがって、第４非晶質半導体層３４のうち第２非晶質半導体層３２の接する部分は、第２主面２０ｂに接する部分よりも膜密度が高くてもよく、第１非晶質半導体層３１や第３非晶質半導体層３３と同程度の膜密度を有してもよい。
　なお、第４非晶質半導体層３４が設けられなくてもよく、第２領域Ｗ２の第２主面２０ｂの直上に第２非晶質半導体層３２が設けられてもよい。この場合、第２非晶質半導体層３２の少なくとも第２主面２０ｂに接する部分は、第１非晶質半導体層３１や第３非晶質半導体層３３よりも膜密度が低くてもよく、例えば、２．０ｇ／ｃｍ３以上２．２ｇ／ｃｍ３以下の膜密度を有してもよい。
　第２結晶性半導体部３６は、第１結晶性半導体部３５と同様に結晶質の半導体で構成され、例えば、単結晶シリコン、多結晶シリコンおよび微結晶シリコンの少なくとも一つを含む。第２結晶性半導体部３６は、第２非晶質半導体層３２および第４非晶質半導体層３４とは結晶性の異なる部分であり、非晶質ではない半導体で構成される部分である。第２結晶性半導体部３６は、第２導電型の結晶質シリコンおよびｉ型の結晶質シリコンの少なくとも一方を含む。
　第２結晶性半導体部３６は、第１結晶性半導体部３５と同様、第２主面２０ｂの第２領域Ｗ２上において部分的に設けられる。一方で、第２結晶性半導体部３６は、第１結晶性半導体部３５よりも単位面積あたりの量が少なくなるように設けられる。例えば、第２主面２０ｂの第２領域Ｗ２上で第２結晶性半導体部３６が単位面積あたりに占める面積は、第２主面２０ｂの第１領域Ｗ１上で第１結晶性半導体部３５が単位体積あたりに占める面積よりも小さい。なお、第２結晶性半導体部３６は、設けられなくてもよい。
　また、第２結晶性半導体部３６の第２主面２０ｂからの高さｈ２は、第１結晶性半導体部３５の第２主面２０ｂからの高さｈ１よりも小さい。例えば、第２結晶性半導体部３６は、第２透明電極層２４に到達しないように設けられ、第４非晶質半導体層３４を貫通しないように設けられる。したがって、第２結晶性半導体部３６の高さｈ２は、第４非晶質半導体層３４の厚さより小さくてもよい。
　第１透明電極層２３は、第１半導体層２１の上に設けられ、第２透明電極層２４は、第２半導体層２２の上に設けられる。第１透明電極層２３および第２透明電極層２４は、例えば、酸化錫（ＳｎＯ２）、酸化亜鉛（ＺｎＯ）、インジウム錫酸化物（ＩＴＯ）等に錫（Ｓｎ）、アンチモン（Ｓｂ）、フッ素（Ｆ）、アルミニウム（Ａｌ）等をドープした透明導電性酸化物（ＴＣＯ）により形成される。本実施の形態において、第１透明電極層２３および第２透明電極層２４は、インジウム錫酸化物により形成される。第１透明電極層２３および第２透明電極層２４の厚みは、例えば、５０ｎｍ～１００ｎｍ程度とすることができる。
　第１金属電極層２５は、第１透明電極層２３の上に設けられ、第２金属電極層２６は、第２透明電極層２４の上に設けられる。第１金属電極層２５および第２金属電極層２６は、銅（Ｃｕ）、錫（Ｓｎ）、金（Ａｕ）、銀（Ａｇ）、ニッケル（Ｎｉ）、チタン（Ｔｉ）などの金属を含む導電性材料層である。第１金属電極層２５および第２金属電極層２６は、単層で構成されてもよいし、複数層で構成されてもよい。第１金属電極層２５および第２金属電極層２６は、例えば、５０ｎｍ～１１００ｎｍ程度のシード層と、１１μｍ～５０μｍ程度の第１めっき層と、１μｍ～５μｍ程度の第２めっき層とを有する。例えば、シード層および第１めっき層が銅（Ｃｕ）で構成され、第２めっき層が錫（Ｓｎ）で構成される。
　本実施の形態において、第１電極１４は、第１透明電極層２３および第１金属電極層２５により構成され、第２電極１５は、第２透明電極層２４および第２金属電極層２６により構成される。第１電極１４は第１導電型側のキャリアを収集し、第２電極１５は第２導電型側のキャリアを収集する。第１電極１４と第２電極１５の間には分離溝１６が設けられ、第１電極１４と第２電極１５の間が電気的に絶縁される。分離溝１６の内側には絶縁材料が設けられてもよく、例えば、酸化シリコン（ＳｉＯ２）、窒化シリコン（ＳｉＮ）、酸窒化シリコン（ＳｉＯＮ）などの絶縁性材料が設けられてもよい。
　受光面保護層３０は、第１主面２０ａ上に設けられる。受光面保護層３０は、第１主面２０ａのパッシベーション層として機能する。このパッシベーション層は、実質的に真性な非晶質半導体層、第１導電型の非晶質半導体層、第２導電型の非晶質半導体層の少なくとも一つを含んでもよい。パッシベーション層は、水素を含む非晶質シリコン、酸化シリコン、窒化シリコン、酸窒化シリコンなどで構成することができる。パッシベーション層は、例えば、２ｎｍ～５０ｎｍ程度の厚さを有する。
　受光面保護層３０は、反射防止膜や保護膜としての機能をさらに有してもよい。反射防止膜ないし保護膜絶縁層は、酸化シリコン、窒化シリコン、酸窒化シリコンなどにより構成することができる。反射防止膜ないし保護膜絶縁層の厚さは、例えば反射防止特性などに応じて適宜設定され、例えば８０ｎｍ～１１００ｎｍ程度である。
　つづいて、太陽電池セル１０の製造方法を説明する。まず、図３に示すように、基板２０の第１主面２０ａにテクスチャ構造４０を形成する。テクスチャ構造４０の形成方法は特に限定されないが、例えば、アルカリ溶液を用いた異方性エッチングにより形成できる。一方、基板２０の第２主面２０ｂにはテクスチャ構造は形成されないようにする。なお、基板２０の両面２０ａ，２０ｂにテクスチャ構造を形成した後、第２主面２０ｂのテクスチャ構造をウェットエッチングやドライエッチングにより除去することで図示される基板２０を形成してもよい。
　次に、図４に示すように、第１主面２０ａ上に受光面保護層３０を形成し、第２主面２０ｂ上に第３非晶質半導体層３３、第１非晶質半導体層３１および第１結晶性半導体部３５を形成する。受光面保護層３０、第１非晶質半導体層３１、第３非晶質半導体層３３および第１結晶性半導体部３５は、プラズマＣＶＤ法等の化学気相成長（ＣＶＤ）法により形成できる。
　第２主面２０ｂでは、第２主面２０ｂ上にｉ型の第３非晶質半導体層３３を形成した後、第３非晶質半導体層３３の上に第１導電型の第１非晶質半導体層３１が形成される。第１非晶質半導体層３１および第３非晶質半導体層３３の形成時には、同時に第１結晶性半導体部３５が形成される。第２主面２０ｂは、少なくとも部分的に結晶性シリコンの（１００）面で構成されるため、非晶質シリコンを成膜する条件下であっても部分的に結晶質シリコンが形成されうる。第２主面２０ｂ上で部分的に結晶質シリコンが形成されると、その場所を起点として第１結晶性半導体部３５が成長していく。その結果、非晶質シリコンと柱状の結晶質シリコンとが混在した層を一度に形成できる。
　第２主面２０ｂ上に形成される非晶質半導体層３１，３３および結晶性半導体部３５の割合は、第２主面２０ｂの表面の状態や、半導体層の成膜条件を制御することにより調整できる。結晶性シリコン表面のうち（１００）面では結晶性シリコンが成長しやすく、（１１１）面では結晶性シリコンが成長しにくいことから、第２主面２０ｂにおける（１００）面および（１１１）面が占める割合を調整することで、第１結晶性半導体部３５が形成する部分の割合を制御できる。例えば、第２主面２０ｂ上に部分的にテクスチャ構造を形成して（１１１）面の割合を増やすことにより、第１結晶性半導体部３５が占める割合を小さくできる。また、成膜速度を速くすると結晶質シリコンが生成されにくくなることから、第１非晶質半導体層３１および第３非晶質半導体層３３の成膜速度を調整することによっても第１結晶性半導体部３５の形成割合を制御することができる。
　一方、第１主面２０ａには受光面保護層３０が形成される。受光面保護層３０を非晶質シリコン層とする場合には、第１非晶質半導体層３１、第３非晶質半導体層３３および第１結晶性半導体部３５の形成工程と同時に受光面保護層３０を形成することもできる。受光面保護層３０は、実質的に非晶質シリコンのみを含んでもよいし、結晶性シリコンを含んでもよい。受光面保護層３０の結晶性シリコンは、第２主面２０ｂより多くてもよいし、少なくてもよい。なお、受光面保護層３０は、第１非晶質半導体層３１、第３非晶質半導体層３３および第１結晶性半導体部３５と同時形成されなくてもよく、これらの層の前に形成されてもよいし、これらの層の後に形成されてもよい。
　つづいて、図５に示すように、第１非晶質半導体層３１および第１結晶性半導体部３５の上に部分的にマスク４２を形成し、マスク４２が形成されていない領域の第１非晶質半導体層３１、第３非晶質半導体層３３および第１結晶性半導体部３５を除去する。マスク４２は、第１領域Ｗ１に対応する位置に設けられる。これにより、第１領域Ｗ１のみに第１非晶質半導体層３１、第３非晶質半導体層３３および第１結晶性半導体部３５が残り、第１半導体層２１ができあがる。第１領域Ｗ１とは異なる第２領域Ｗ２では、第２主面２０ｂが露出する。
　つづいて、図６に示すように、第２領域Ｗ２に露出する第２主面２０ｂの上に第４非晶質半導体層３４、第２非晶質半導体層３２および第２結晶性半導体部３６を形成する。まず、第２主面２０ｂ上にｉ型の第４非晶質半導体層３４を形成した後、第４非晶質半導体層３４の上に第２導電型の第２非晶質半導体層３２が形成される。第２非晶質半導体層３２および第４非晶質半導体層３４の形成時には、同時に第２結晶性半導体部３６が形成されうる。これにより第２半導体層２２ができあがる。
　第２領域Ｗ２では、第１領域Ｗ１に比べて結晶質シリコンの成長が阻害されやすい条件下で第２非晶質半導体層３２および第４非晶質半導体層３４が成膜される。例えば、第２非晶質半導体層３２および第４非晶質半導体層３４の少なくとも一方は、第１非晶質半導体層３１や第３非晶質半導体層３３よりも速い成膜速度で形成される。その結果、第２非晶質半導体層３２および第４非晶質半導体層３４の少なくとも一方は、第１非晶質半導体層３１や第３非晶質半導体層３３よりも膜密度が小さくなる。
　なお、第２領域Ｗ２に露出する第２主面２０ｂに異方性エッチングを施すことにより、第２主面２０ｂのうち第２領域Ｗ２にテクスチャ構造（不図示）を形成してもよい。第２主面２０ｂの第２領域Ｗ２に選択的にテクスチャを形成して（１１１）面が占める割合を増やすことにより、第２結晶性半導体部３６の形成が阻害されるようにしてもよい。これにより、第２半導体層２２に含まれる第２結晶性半導体部３６の割合を小さくすることができる。例えば、第１領域Ｗ１に占める第１結晶性半導体部３５の面積割合よりも第２領域Ｗ２に占める第２結晶性半導体部３６の面積割合を小さくできる。例えば、第１結晶性半導体部３５および第２結晶性半導体部３６の割合を第２主面２０ｂに交差する断面で特定する場合には、第１非晶質半導体層３１および第３非晶質半導体層３３の層内に占める第１結晶性半導体部３５の面積割合よりも、第２非晶質半導体層３２および第４非晶質半導体層３４の層内に占める第２結晶性半導体部３６の面積割合を小さくできる。
　つづいて、第１半導体層２１の上に第１透明電極層２３および第１金属電極層２５を形成し、第２半導体層２２の上に第２透明電極層２４および第２金属電極層２６を形成する。第１透明電極層２３および第２透明電極層２４は、プラズマＣＶＤ法等のＣＶＤ法や、スパッタリング法などの薄膜形成法により形成される。第１金属電極層２５および第２金属電極層２６は、スパッタリング法やめっき法などにより形成される。
　以上により、図２に示す太陽電池セル１０ができあがる。上述の製造方法では、第１半導体層２１を形成し、第１半導体層２１の一部を除去した後に第２半導体層２２を形成したが、第１半導体層２１と第２半導体層２２の形成順序を逆にしてもよい。つまり、第２半導体層２２を第２主面２０ｂの全面に形成し、第２半導体層２２の一部を除去した後に第１半導体層２１を形成してもよい。その他、第２主面２０ｂ上にマスクを設けることで、第１半導体層２１および第２半導体層２２が対応する領域にのみ形成されるようにしてもよい。
　本実施の形態によれば、第１領域Ｗ１に非晶質半導体層３１，３３および結晶性半導体部３５を混在させることで、第１領域Ｗ１におけるパッシベーション性の顕著な低下を抑えつつ、第１領域Ｗ１における直列抵抗を低減できる。第１領域Ｗ１のパッシベーション性を高めるためには、基板２０の第２主面２０ｂのダングリングボンドを水素（Ｈ）で終端化することが好ましく、第２主面２０ｂの全面を水素を含む非晶質半導体で被覆することが好ましい。非晶質ではなく微結晶や多結晶の半導体には格子欠陥が含まれ、格子欠陥に起因したパッシベーション性の低下につながるからである。その一方で、非晶質半導体は、結晶質半導体と比べると導電性が低く、太陽電池セル１０の直列抵抗の増加の一因となる。
　本発明者らは、第１領域Ｗ１に非晶質半導体層３１，３３および結晶性半導体部３５の双方を形成するとともに、これらを適切な割合で混在させることにより、太陽電池セル１０の発電効率のさらなる向上が可能なことを見出した。ある実施例によれば、第１領域Ｗ１上において第１結晶性半導体部３５が占める面積割合を０．０５％以上２０％以下、好ましくは０．１％以上１０％以下にすることで、第１結晶性半導体部３５を設けない場合と比べて発電効率を高めることができる。また、第２主面２０ｂに交差する断面で観察する場合、第１非晶質半導体層３１および第３非晶質半導体層３３の層内で第１結晶性半導体部３５が占める面積割合を０．０２％以上１０％以下、好ましくは０．０５％以上５％以下にすることで発電効率を高めることができる。この理由の一つとして、第１領域Ｗ１の近傍は少数キャリア密度の低い領域であるため、第１結晶性半導体部３５を設けることによるパッシベーション性の低下が生じたとしても、キャリア再結合速度の顕著な増加につながらないことが考えられる。
　その一方で、第２領域Ｗ２には第２結晶性半導体部３６が実質的に設けられないことが好ましく、第２結晶性半導体部３６を設けるとしても第１領域Ｗ１よりも形成される割合が小さいことが好ましい。第２領域Ｗ２の面積は第１領域Ｗ１の面積よりも大きいため、第１領域Ｗ１と比べて電流密度が低く、直列抵抗低減による発電効率向上への寄与が小さいためである。
　以上の考察から、本実施の形態によれば、第１領域Ｗ１および第２領域Ｗ２の双方に一定以上のパッシベーション性を持たせつつ、第１領域Ｗ１の直列抵抗を下げることができる。これにより、第１領域Ｗ１および第２領域Ｗ２の双方からキャリアを効率的に収集し、かつ、太陽電池セル１０の第１電極１４と第２電極１５の間の直列抵抗を下げることができる。その結果、太陽電池セル１０の発電効率を向上させることができる。
　本実施の形態によれば、第１結晶性半導体部３５が第２主面２０ｂから第１透明電極層２３に向けて柱状に延在することにより、第１結晶性半導体部３５による抵抗性低減の効果を高めることができる。第１結晶性半導体部３５が第１透明電極層２３に達するように設けられる場合、基板２０と第２透明電極層２４の間が低抵抗の第１結晶性半導体部３５により直接的に接続されるため、第１領域Ｗ１の直列抵抗をより小さくできる。特に導電性の低いｉ型の第３非晶質半導体層３３を少なくとも貫通するように第１結晶性半導体部３５を設けることで、直列抵抗低減の効果を高めることができる。
　本実施の形態の一態様は次の通りである。ある態様の太陽電池セル（１０）は、
　第１導電型の結晶性半導体の基板（２０）と、
　基板（２０）の一主面（第２主面２０ｂ）の第１領域（Ｗ１）上に設けられる第１半導体層（２１）と、
　一主面（第２主面２０ｂ）の第１領域（Ｗ１）と異なる第２領域（Ｗ２）上に設けられる第２半導体層（２２）と、
　第１半導体層（２１）上に設けられる第１透明電極層（２３）と、
　第２半導体層（２２）上に設けられる第２透明電極層（２４）と、を備える。
　第１半導体層（２１）は、第１導電型の第１非晶質半導体層（３１）と、一主面（第２主面２０ｂ）から第１透明電極層（２３）に向けて柱状に延びる第１結晶性半導体部（３５）と、を含み、
　第２半導体層（２２）は、第１導電型と異なる第２導電型の第２非晶質半導体層（３２）を含む。
　第１半導体層（２１）は、一主面（第２主面２０ｂ）と第１非晶質半導体層（３１）との間に設けられる実質的に真性な第３非晶質半導体層（３３）をさらに含んでもよい。
　第１結晶性半導体部（３５）は、少なくとも第３非晶質半導体層（３３）を貫通して第１非晶質半導体層（３１）に達するように設けられてもよい。
　第２非晶質半導体層（３２）は、少なくとも一主面（第２主面２０ｂ）と接する部分の膜密度が第１半導体層（２１）の一主面（第２主面２０ｂ）と接する部分より低くてもよい。
　第２半導体層（２２）は、一主面（第２主面２０ｂ）と第２非晶質半導体層（３２）との間に設けられ、実質的に真性な第４非晶質半導体層（３４）をさらに含んでもよい。
　第４非晶質半導体層（３４）は、少なくとも一主面（第２主面２０ｂ）と接する部分の膜密度が第１半導体層（２１）の一主面（第２主面２０ｂ）と接する部分より低くてもよい。
　第１半導体層（２１）の一主面（第２主面２０ｂ）と接する部分は、第１非晶質半導体層（３１）または第３非晶質半導体層（３３）のいずれかであってもよい。
　第１結晶性半導体部（３５）は、第１透明電極層（２３）に達してもよい。
　第１結晶性半導体部（３５）は、第１領域（Ｗ１）上に部分的に設けられてもよい。
　第１非晶質半導体層（３１）は、基板（２０）よりも第１導電型の不純物濃度が高くてもよい。
　第２半導体層（２２）は、一主面（第２主面２０ｂ）上に設けられる第２結晶性半導体部（３６）をさらに含んでもよい。
　第１領域（Ｗ１）の単位面積あたりに設けられる第１結晶性半導体部（３５）の量は、第２領域（Ｗ２）の単位面積あたりに設けられる第２結晶性半導体部（３６）の量より多くてもよい。
　第１結晶性半導体部（３５）の一主面（第２主面２０ｂ）からの高さ（ｈ１）は、第２結晶性半導体部（３６）の一主面（第２主面２０ｂ）からの高さ（ｈ２）より大きくてもよい。
　第１領域（Ｗ１）は、第２領域（Ｗ２）より狭くてもよい。
　本実施の形態の別の態様は、太陽電池セル（１０）の製造方法である。この方法は、
　第１導電型の結晶性半導体の基板（２０）の一主面（第２主面２０ｂ）上の第１領域Ｗ１に第１半導体層（２１）を形成し、
　一主面（第２主面２０ｂ）の第１領域（Ｗ１）と異なる第２領域（Ｗ２）上に第２半導体層（２２）を形成し、
　第１半導体層（２１）上および第２半導体層（２２）上に透明電極層（第１透明電極層２３，第２透明電極層２４）を形成する。
　第１半導体層（２１）は、第１導電型の第１非晶質半導体層（３１）と、一主面（第２主面２０ｂ）から透明電極層（第１透明電極層２３）に向けて柱状に延びる第１結晶性半導体部（３５）と、を含み、
　第２半導体層（２２）は、第１導電型と異なる第２導電型の第２非晶質半導体層（３２）を含み、
　第１非晶質半導体層（３１）および第１結晶性半導体部（３５）は、同時に形成される。
　第１非晶質半導体層（３１）および第１結晶性半導体部（３５）は、一主面（第２主面２０ｂ）上に少なくとも部分的に形成されるテクスチャ構造を下地にして形成されてもよい。
（変形例１）
　図７は、変形例に係る太陽電池セル１１０の構造を示す断面図である。本変形例では、第１領域Ｗ１の第２主面２０ｂの近傍に第１導電型の不純物濃度が高い高不純物濃度領域１２０ｃが設けられる点で上述の実施の形態と相違する。基板１２０は、第１導電型の不純物濃度が低いバルク領域１２０ｄと、第１導電型の不純物濃度が高い高不純物濃度領域１２０ｃと、を含む。高不純物濃度領域１２０ｃは、図７に示されるように、第２主面２０ｂを下から見た場合には第１領域Ｗ１の第２主面２０ｂの直上に位置する。図７の上下を反対にして、第２主面２０ｂを上から見た場合には第１領域Ｗ１の第２主面２０ｂの直下に位置すると言える。
　高不純物濃度領域１２０ｃは、第１領域Ｗ１に設けられ、第２領域Ｗ２を避けて設けられる。１２０ｃの不純物濃度は、１×１０１７／ｃｍ３～１×１０２０／ｃｍ３程度であり、例えば１×１０１８／ｃｍ３～２×１０１９／ｃｍ３程度とすることができる。高不純物濃度領域１２０ｃは、例えば第１導電型の不純物としてリン（Ｐ）を含む。高不純物濃度領域１２０ｃの不純物濃度は、第１非晶質半導体層３１の不純物濃度より高くてもよい。
　高不純物濃度領域１２０ｃは、第２主面２０ｂからの深さｈ３が５μｍ以下となるように形成され、例えば２００ｎｍ以下、好ましくは５ｎｍ～１００ｎｍ程度となるように形成される。高不純物濃度領域１２０ｃは、例えば、第１領域Ｗ１において第２主面２０ｂから第１導電型の不純物を拡散させることにより形成することができる。高不純物濃度領域１２０ｃは、イオン注入処理により形成されてもよい。
　本変形例によれば、高不純物濃度領域１２０ｃを設けることにより、第１領域Ｗ１の近傍の少数キャリアをさらに減少させてパッシベーション性を向上させることができる。これにより、第１結晶性半導体部３５を設けることによるパッシベーションの低下を補償し、パッシベーション性と低抵抗性をより好適に両立できる。
　ある態様の太陽電池セル（１１０）において、基板（１２０）は、第１領域（Ｗ１）内の一主面（第２主面２０ｂ）の直下に設けられ、基板（１２０）の他の部分（バルク領域１２０ｄ）よりも第１導電型の不純物濃度が高い高不純物濃度領域（１２０ｃ）を有してもよい。
（変形例２）
　図８は、変形例に係る太陽電池セル２１０の構成を示す断面図である。本変形例では、第１領域Ｗ１の第２主面２０ｂと第１半導体層２１の間に高不純物濃度層２４４がさらに設けられる点で上述の実施の形態と相違する。高不純物濃度層２４４は、上述の変形例と同様、第１導電型の不純物濃度が高い部分であり、例えば第１導電型の不純物としてリン（Ｐ）を含む。
　高不純物濃度層２４４は、第１領域Ｗ１に設けられ、第２領域Ｗ２を避けて設けられる。高不純物濃度層２４４は、第１非晶質半導体層３１と同様にＣＶＤ法などで形成することができ、結晶質シリコン、非晶質シリコン、酸化シリコン、酸窒化シリコン、窒化シリコンなどで構成することができる。高不純物濃度層２４４は、第２領域Ｗ２にマスクを設けることで第１領域Ｗ１に選択的に形成されてもよいし、第１領域Ｗ１および第２領域Ｗ２の双方に形成された後に第２領域Ｗ２上に形成された部分が除去されてもよい。
　高不純物濃度層２４４の不純物濃度は、１×１０１９／ｃｍ３～５×１０２０／ｃｍ３程度であり、例えば５×１０１９／ｃｍ３～１×１０２０／ｃｍ３程度とすることができる。高不純物濃度層２４４の不純物濃度は、第１非晶質半導体層３１の不純物濃度より低いことが好ましい。高不純物濃度層２４４は、第２主面２０ｂからの高さｈ４が１００ｎｍ以下となるように設けられ、例えば０．１ｎｍ～５０ｎｍ程度である。高不純物濃度層２４４の高さｈ４は、０．１ｎｍ～３ｎｍ程度、例えば２ｎｍ以下であることが好ましい。
　本変形例においても、高不純物濃度層２４４を設けることにより、第１領域Ｗ１の近傍の少数キャリアをさらに減少させてパッシベーション性を向上させることができる。これにより、第１結晶性半導体部３５を設けることによるパッシベーションの低下を補償し、パッシベーション性と低抵抗性とをより好適に両立できる。
　ある態様の太陽電池セル（２１０）は、一主面（第２主面２０ｂ）と第１半導体層（２１）の間に設けられ、基板（２０）よりも第１導電型の不純物濃度が高い高不純物濃度層（２４４）をさらに備えてもよい。
（変形例３）
　図９は、変形例に係る太陽電池セル３１０の構成を示す断面図である。本変形例では、第２主面２０ｂと第１半導体層２１の間に第１酸化物層３２７が設けられ、第２主面２０ｂと第２半導体層２２の間に第２酸化物層３２８が設けられる点で上述の実施の形態と相違する。
　第１酸化物層３２７は、第２主面２０ｂの第１領域Ｗ１上に設けられ、第２酸化物層３２８は、第２主面２０ｂの第２領域Ｗ２上に設けられる。第１酸化物層３２７および第２酸化物層３２８は、例えば酸化シリコン、窒化シリコンまたはアルミニウム酸化物等で構成される。
　第１酸化物層３２７および第２酸化物層３２８は、第２主面２０ｂのパッシベーション層として機能する。また、第１酸化物層３２７は、第１半導体層２１に含まれる第１結晶性半導体部３５の生成量を制御するための下地層として機能する。同様に、第２酸化物層３２８は、第２半導体層２２の層内に第２結晶性半導体部が生成されるのを抑制するための下地層として機能する。第２酸化物層３２８を厚く形成することにより、第２酸化物層３２８の上に実質的に第２結晶性半導体部が形成されないようにできる。
　結晶性シリコンの基板２０上に酸化物層を設けた場合、酸化物層が設けられない場合と比べて結晶性シリコンの生成が阻害される一方、非晶質シリコンが生成されやすくなる。したがって、第２主面２０ｂ上の酸化物層の量、厚さ、形成範囲などを制御することにより、第２主面２０ｂ上に形成される第１結晶性半導体部３５の生成量を制御できる。
　第１領域Ｗ１では、第１酸化物層３２７の厚さが相対的に小さくなるように形成され、第１結晶性半導体部３５が生成されやすい下地層とする。また、第１酸化物層３２７は、第１領域Ｗ１の第２主面２０ｂ上の全体を均一に被覆するのではなく、部分的に第２主面２０ｂが露出したり、部分的に第１酸化物層３２７の厚さが小さくなったりするように形成される。これにより、第１酸化物層３２７が設けられない箇所や第１酸化物層３２７の厚さが小さい箇所において結晶性シリコンの生成が促進され、部分的に第１結晶性半導体部３５が形成されるようにできる。
　一方、第２領域Ｗ２では、第２酸化物層３２８の厚さが相対的に大きくなるように形成され、第２結晶性半導体部が生成されにくい下地とする。また、第２酸化物層３２８が第２領域Ｗ２の第２主面２０ｂ上の全体を均一に被覆するように形成される。つまり、第２酸化物層３２８が形成されずに第２主面２０ｂが露出したり、第２酸化物層３２８の厚さが部分的に小さくなったりしないように第２酸化物層３２８が形成される。これにより、第２酸化物層３２８上での結晶性シリコンの生成を阻害し、第２結晶性半導体部が実質的に形成されないようにできる。
　第１酸化物層３２７および第２酸化物層３２８は、ＣＶＤ法や薬液酸化法などにより形成することができる。第１酸化物層３２７および第２酸化物層３２８の厚さや形成される範囲は、酸化物層の成膜条件や成長時間を制御することにより変化させることができる。第１酸化物層３２７は第１半導体層２１の形成前に形成され、第１半導体層２１は第１酸化物層３２７の上に形成される。第２酸化物層３２８は第２半導体層２２の形成前に形成され、第２半導体層２２は第２酸化物層３２８の上に形成される。
　本変形例によれば、第１酸化物層３２７および第２酸化物層３２８を設けることで、第１結晶性半導体部３５および第２結晶性半導体部の形成量をより好適に制御できる。また、第１酸化物層３２７および第２酸化物層３２８をパッシベーション層として機能させ、第２主面２０ｂのパッシベーション性を高めることができる。したがって、本変形例によれば、パッシベーション性と低抵抗性をより好適に両立させて太陽電池セル３１０の発電効率を高めることができる。
　ある態様の太陽電池セル（３１０）は、一主面（第２主面２０ｂ）と第１半導体層２１の間であって第１領域（Ｗ１）上に少なくとも部分的に設けられる第１酸化物層（３２７）をさらに備えてもよい。
　ある態様の太陽電池セル（３１０）は、一主面（第２主面２０ｂ）と第２半導体層（２２）の間であって第２領域（Ｗ２）上に少なくとも部分的に設けられる第２酸化物層（３２８）をさらに備えてもよい。第２酸化物層（３２８）の厚さは、第１酸化物層（３２７）の厚さより大きくてもよい。
　ある態様の太陽電池セル（３１０）の製造方法において、第１非晶質半導体層（３１）および第１結晶性半導体部（３５）は、一主面上（第２主面２０ｂ）に少なくとも部分的に形成される酸化物層（第１酸化物層３２７）を下地にして形成されてもよい。
（変形例４）
　図１０は、変形例に係る太陽電池セル４１０の構成を示す断面図である。本変形例では、第１結晶性半導体部４３５がベース層４３５ａと、ベース層４３５ａから第１透明電極層２３に向けて延びる複数の柱状部４３５ｂとを含む点で上述の実施の形態と異なる。
　第１半導体層４２１は、第１非晶質半導体層３１、第３非晶質半導体層３３および第１結晶性半導体部４３５を含む。第１結晶性半導体部４３５は、第２主面２０ｂの第１領域Ｗ１上に薄く形成されるベース層４３５ａと、ベース層４３５ａから第１透明電極層２３に向けて延びる複数の柱状部４３５ｂとを含む。第３非晶質半導体層３３はベース層４３５ａの上に設けられ、第１非晶質半導体層３１は第３非晶質半導体層３３の上に設けられる。
　ベース層４３５ａは、第１領域Ｗ１の半分以上の面積を占めるように設けられ、例えば、第１領域Ｗ１の８０％以上または９０％以上の面積を占めるように設けられる。ベース層４３５ａの厚さは、０．５ｎｍ～２５ｎｍ程度であり、例えば０．５ｎｍ～５ｎｍ程度である。ベース層４３５ａは、第１非晶質半導体層３１や第３非晶質半導体層３３より薄く形成されてもよい。複数の柱状部４３５ｂのそれぞれは、ベース層４３５ａから第１透明電極層２３に向けて延び、第１非晶質半導体層３１および第３非晶質半導体層３３を貫通するように設けられる。
　本変形例によれば、導電性の高い結晶質半導体で形成されるベース層４３５ａの面積を大きくすることで、第１領域Ｗ１の直列抵抗をさらに低減できる。また、ベース層４３５ａを薄く形成することで、第１領域Ｗ１の単位面積あたりの欠陥数を減らし、格子欠陥によるパッシベーション性低下の影響を小さくできる。したがって、本変形例によれば、太陽電池セル４１０の発電効率をより高めることができる。
　ある態様の太陽電池セル（４１０）において、第１結晶性半導体部（４３５）は、第１領域（Ｗ１）の半分以上を被覆するように設けられるベース層（４３５ａ）と、ベース層（４３５ａ）から第１透明電極層（２３）に向けて延びる柱状部（４３５ｂ）とを有してもよい。
　以上、本発明を上述の実施の形態を参照して説明したが、本発明は上述の実施の形態に限定されるものではなく、実施の形態および変形例の構成を適宜組み合わせたものや置換したものについても本発明に含まれるものである。
　１０…太陽電池セル、２０…基板、２１…第１半導体層、２２…第２半導体層、２３…第１透明電極層、２４…第２透明電極層、３１…第１非晶質半導体層、３２…第２非晶質半導体層、３３…第３非晶質半導体層、３４…第４非晶質半導体層、３５…第１結晶性半導体部、３６…第２結晶性半導体部、Ｗ１…第１領域、Ｗ２…第２領域。
　本発明によれば、太陽電池セルの発電効率を向上できる。

Claims (18)

  1. 　第１導電型の結晶性半導体の基板と、
    　前記基板の一主面の第１領域上に設けられる第１半導体層と、
    　前記一主面の前記第１領域と異なる第２領域上に設けられる第２半導体層と、
    　前記第１半導体層上に設けられる第１透明電極層と、
    　前記第２半導体層上に設けられる第２透明電極層と、を備え、
    　前記第１半導体層は、前記第１導電型の第１非晶質半導体層と、前記一主面から前記第１透明電極層に向けて延びる第１結晶性半導体部と、を含み、
    　前記第２半導体層は、前記第１導電型と異なる第２導電型の第２非晶質半導体層を含む、太陽電池セル。
  2. 　前記第１半導体層は、前記一主面と前記第１非晶質半導体層との間に設けられ、実質的に真性な第３非晶質半導体層をさらに含む、請求項１に記載の太陽電池セル。
  3. 　前記第１結晶性半導体部は、少なくとも前記第３非晶質半導体層を貫通して前記第１非晶質半導体層に達するように設けられる、請求項２に記載の太陽電池セル。
  4. 　前記第２非晶質半導体層は、少なくとも前記一主面と接する部分の膜密度が前記第１半導体層の前記一主面と接する部分よりも低い、請求項１から３のいずれか一項に記載の太陽電池セル。
  5. 　前記第２半導体層は、前記一主面と前記第２非晶質半導体層との間に設けられ、実質的に真性な第４非晶質半導体層をさらに含む、請求項１から４のいずれか一項に記載の太陽電池セル。
  6. 　前記第４非晶質半導体層は、少なくとも前記一主面と接する部分の膜密度が前記第１半導体層の前記一主面と接する部分よりも低い、請求項５に記載の太陽電池セル。
  7. 　前記第１結晶性半導体部は、前記第１透明電極層に達する、請求項１から６のいずれか一項に記載の太陽電池セル。
  8. 　前記第１結晶性半導体部は、前記第１領域上に部分的に設けられる、請求項１から７のいずれか一項に記載の太陽電池セル。
  9. 　前記第１結晶性半導体部は、前記第１領域の半分以上を被覆するように設けられるベース層と、前記ベース層から前記第１透明電極層に向けて延びる柱状部とを有する、請求項１から８のいずれか一項に記載の太陽電池セル。
  10. 　前記第１非晶質半導体層は、前記基板よりも前記第１導電型の不純物濃度が高い、請求項１から９のいずれか一項に記載の太陽電池セル。
  11. 　前記第２半導体層は、前記一主面上に設けられる第２結晶性半導体部をさらに含み、
    　前記第１領域の単位面積あたりに設けられる第１結晶性半導体部の量は、前記第２領域の単位面積あたりに設けられる第２結晶性半導体部の量よりも多い、請求項１から１０のいずれか一項に記載の太陽電池セル。
  12. 　前記第１結晶性半導体部の前記一主面からの高さは、前記第２結晶性半導体部の前記一主面からの高さよりも大きい、請求項１１に記載の太陽電池セル。
  13. 　前記第１領域は、前記第２領域よりも狭い、請求項１から１２のいずれか一項に記載の太陽電池セル。
  14. 　前記基板は、前記第１領域内の前記一主面の直下に設けられ、前記基板の他の部分よりも前記第１導電型の不純物濃度が高い高不純物濃度領域を有する、請求項１から１３のいずれか一項に記載の太陽電池セル。
  15. 　前記一主面と前記第１半導体層の間に設けられ、前記基板よりも前記第１導電型の不純物濃度が高い高不純物濃度層をさらに備える、請求項１から１４のいずれか一項に記載の太陽電池セル。
  16. 　前記一主面と前記第１半導体層の間であって前記第１領域上に少なくとも部分的に設けられる第１酸化物層をさらに備える、請求項１から１５のいずれか一項に記載の太陽電池セル。
  17. 　前記一主面と前記第２半導体層の間であって前記第２領域上に少なくとも部分的に設けられる第２酸化物層をさらに備え、前記第２酸化物層の厚さは、前記第１酸化物層の厚さより大きい、請求項１６に記載の太陽電池セル。
  18. 　第１導電型の結晶性半導体の基板の一主面上の第１領域に第１半導体層を形成し、
    　前記一主面の前記第１領域と異なる第２領域上に第２半導体層を形成し、
    　前記第１半導体層上および前記第２半導体層上に透明電極層を形成する太陽電池セルの製造方法であって、
    　前記第１半導体層は、前記第１導電型の第１非晶質半導体層と、前記一主面から前記透明電極層に向けて延びる第１結晶性半導体部と、を含み、
    　前記第２半導体層は、前記第１導電型と異なる第２導電型の第２非晶質半導体層を含み、
    　前記第１非晶質半導体層および前記第１結晶性半導体部を同時に形成する、太陽電池セルの製造方法。
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