WO2018176880A1 - 一种阵列基板的制作方法 - Google Patents

一种阵列基板的制作方法 Download PDF

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WO2018176880A1
WO2018176880A1 PCT/CN2017/113328 CN2017113328W WO2018176880A1 WO 2018176880 A1 WO2018176880 A1 WO 2018176880A1 CN 2017113328 W CN2017113328 W CN 2017113328W WO 2018176880 A1 WO2018176880 A1 WO 2018176880A1
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Prior art keywords
layer
metal
drain
gate
metal layer
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French (fr)
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姜春生
武岳
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Publication of WO2018176880A1 publication Critical patent/WO2018176880A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/286—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials
    • H10P50/287—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/269—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only pre- or post-treatments, e.g. anti-corrosion processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to a method for fabricating an array substrate.
  • Liquid crystal display has many advantages such as thin body, power saving, and no radiation, and has been widely used.
  • a liquid crystal display panel includes a CF (Color Filter) substrate, a TFT (Thin Film Transistor) array substrate, and a liquid crystal (Liquid Crystal) provided between the CF substrate and the TFT array substrate.
  • the liquid crystal molecules are controlled to change direction by powering the TFT array substrate, and the light of the backlight module is projected onto the CF substrate to generate a picture.
  • the performance characteristics and operational characteristics of the TFT array substrate are largely dependent on the materials forming the various elements of the TFT array substrate.
  • a metal wire is disposed on the TFT array substrate, and the metal wire in the TFT array substrate is formed by etching a metal layer physically vapor-deposited on the TFT array substrate, and the etching process can be divided into dry etching and wet etching.
  • the metal wires conventionally applied to the TFT array substrate are aluminum wires.
  • the high electrical resistivity of the aluminum wire makes the pixel electrode layer of the TFT array substrate not fully charged, which is more obvious with the wide application of high frequency addressing (greater than 120 Hz) liquid crystal display.
  • the copper wire has a lower electrical resistivity and good electromigration resistance with respect to the aluminum wire, and thus is applied to the TPT array substrate to solve the problem caused by the above aluminum wire.
  • Copper and glass have poor adhesion, and need to be transitioned with the underlying metal layer, and copper is easily reacted with silicon by interdiffusion at 200 ° C or lower to form a copper silicide (CuSi3) compound, that is, a copper and TPT semiconductor layer reacts. It produces a high contact resistance, so other underlying metal layers are also required for the transition.
  • a refractory metal as a transitional bonding layer and a barrier layer, such as molybdenum (Mo), titanium (Ti), and alloys of corresponding elements.
  • Mo molybdenum
  • Ti titanium
  • alloys of corresponding elements.
  • different barrier metals and alloys have different appearances after etching.
  • FIG. 4 is a cross-sectional view showing the overall structure of the gate insulating layer 15 overlying the gate layer 13 and the first metal layer 12 in the method for fabricating an array substrate of the prior art.
  • a crack 14 exists in the contact edge of the gate layer 13 and the first metal layer 12 on the substrate substrate 11 of the prior art.
  • An object of the present invention is to provide a method for fabricating an array substrate, which solves the problem that in the prior art, when the photoresist is stripped by using a stripping solution, a hollowing phenomenon occurs at the edge of the contact between the gate layer and the first metal layer. A crack is formed, which in turn causes a problem in that the source layer, the drain layer, and the gate layer are short-circuited.
  • a method for fabricating an array substrate comprising:
  • first metal layer Forming a first metal layer, a gate layer, a gate insulating layer, a semiconductor layer, a second metal layer on the substrate, and forming a source layer and a drain layer on the second metal layer;
  • forming the gate layer on the first metal layer comprises:
  • the first metal cation having a chemical corrosion potential less than or equal to a chemical corrosion potential of the first metal layer is added to the first stripping solution.
  • the forming the source layer and the drain layer on the second metal layer comprises:
  • the second stripping solution is added with a second metal cation having a chemical corrosion potential less than or equal to a chemical corrosion potential of the second metal layer.
  • the method further includes:
  • a pixel electrode layer is formed on the flat layer, and the pixel electrode layer is connected to the drain layer through the via hole.
  • a chemical etching potential of the gate layer is higher than a chemical etching potential of the first metal layer, and a chemical etching potential of the source layer and the drain layer is higher than that of the second metal layer Chemical corrosion potential.
  • the thickness of the first metal layer is smaller than the thickness of the gate layer, and the thickness of the second metal layer is smaller than the thickness of the source layer and the drain layer.
  • the thickness of the gate insulating layer is smaller than the thickness of the gate layer, and the thickness of the gate insulating layer is one third of the thickness of the gate layer.
  • the first metal layer and the second metal layer are made of a molybdenum metal material or a metal material having a chemical corrosion potential lower than a chemical corrosion potential of the molybdenum metal.
  • the first stripping liquid and the second stripping liquid are provided by a stripping device provided with a chemical corrosion potential less than or equal to a chemical corrosion potential of the first metal layer and the second metal layer a metal mesh for passing the first metal cation or the second metal cation.
  • the first metal cation and the second metal cation are both molybdenum metal cations.
  • the gate layer, the source layer and the drain layer are made of a copper metal material.
  • a method for fabricating an array substrate comprising:
  • first metal layer Forming a first metal layer, a gate layer, a gate insulating layer, a semiconductor layer, a second metal layer on the substrate, and forming a source layer and a drain layer on the second metal layer;
  • forming the gate layer on the first metal layer comprises:
  • the first stripping solution is added with a chemical corrosion potential less than or equal to a first metal cation of a chemical corrosion potential of the first metal layer;
  • the forming the source layer and the drain layer on the second metal layer includes:
  • the second stripping solution is added with a second metal cation having a chemical corrosion potential less than or equal to a chemical corrosion potential of the second metal layer;
  • the method further includes:
  • a pixel electrode layer is formed on the flat layer, and the pixel electrode layer is connected to the drain layer through the via hole.
  • a chemical etching potential of the gate layer is higher than a chemical etching potential of the first metal layer, and a chemical etching potential of the source layer and the drain layer
  • the thickness of the first metal layer is smaller than the thickness of the gate layer
  • the thickness of the second metal layer is smaller than the thickness of the source layer and the drain layer
  • the thickness of the gate insulating layer is smaller than the thickness of the gate layer, and the thickness of the gate insulating layer is one third of the thickness of the gate layer.
  • the material of the first metal layer and the second metal layer is a molybdenum metal material, or a metal material having a chemical corrosion potential lower than a chemical corrosion potential of the molybdenum metal.
  • first stripping liquid and the second stripping liquid are provided by a stripping apparatus provided with a chemical corrosion potential less than or equal to a chemical corrosion potential of the first metal layer and the second metal layer a metal mesh for passing the first metal cation or the second metal cation.
  • first metal cation and the second metal cation are both molybdenum metal cations.
  • the material for forming the gate layer, the source layer and the drain layer is a copper metal material.
  • the invention discloses a method for fabricating an array substrate, which solves the problem that in the prior art, when the photoresist is deprived by using a stripping solution, the gate layer and the first gold are The edge of the contact of the genus layer is hollowed out to form a crack, which causes a problem of short circuit between the source layer, the drain layer and the gate layer.
  • FIG. 1 is a flow chart showing an implementation step of forming the gate layer on a first metal layer in a method for fabricating an array substrate according to an embodiment of the invention
  • FIG. 2 is a flow chart showing a step of forming a source layer and a drain layer on a second metal layer in a method for fabricating an array substrate according to an embodiment of the invention
  • FIG. 3 is a schematic cross-sectional view showing an overall structure of an array substrate in a method of fabricating an array substrate according to an embodiment of the invention
  • FIG. 4 is a cross-sectional view showing an overall structure in which a gate insulating layer covers a gate layer and a first metal layer in a method of fabricating an array substrate in the prior art.
  • FIG. 1 is a fabrication of an array substrate according to an embodiment of the present invention.
  • a flow chart of the implementation steps of forming the gate layer 3 on the first metal layer 2 is performed.
  • FIG. 2 is a flow chart showing the steps of forming the source layer 7 and the drain layer 8 on the second metal layer 6 in the method for fabricating the array substrate of the embodiment.
  • FIG 3 is a cross-sectional view showing the overall structure of an array substrate in a method of fabricating an array substrate according to an embodiment of the invention.
  • the first metal layer 2 is formed on the base substrate 1, wherein the base substrate 1 is preferably a glass substrate.
  • a gate layer 3 is formed on the first metal layer 2.
  • a gate insulating layer 4 is formed on the gate layer 3.
  • a semiconductor layer 5 is formed on the gate insulating layer 4.
  • a second metal layer 6 is formed on the semiconductor layer 5.
  • a source layer 7 and a drain layer 8 are formed on the second metal layer 6.
  • the gate layer 3 is formed on the first metal layer 2, including:
  • Step S101 depositing a gate metal layer of the gate layer 3 on the first metal layer 2.
  • Step S102 coating a photoresist layer on the gate metal layer, performing exposure development on the gate metal layer, and performing wet etching on the gate metal layer until the drain The first metal layer 2 is formed.
  • Step S103 removing the photoresist layer on the gate metal layer using a first stripping solution to form the gate layer 3.
  • the first metal cation having a chemical corrosion potential less than or equal to the chemical corrosion potential of the first metal layer 2 is added to the first stripping solution.
  • the first stripping solution comprises an anion, and the anion is a chelating agent.
  • the source layer 7 and the drain layer 8 are formed on the second metal layer 6, including:
  • Step S201 depositing a source/drain metal layer for forming the source layer 7 and the drain layer 8 on the second metal layer 6.
  • Step S202 coating a photoresist layer on the source/drain metal layer, performing exposure development on the source/drain metal layer, and performing wet etching on the source/drain metal layer until the second metal is leaked out Layer 6 up to now.
  • Step S203 removing the photoresist layer on the source/drain metal layer using a second stripping solution to form the source layer 7 and the drain layer 8.
  • the second stripping solution comprises an anion
  • the anion is a chelating agent.
  • the second metal cation having a chemical corrosion potential less than or equal to the chemical corrosion potential of the second metal layer 6 is added to the second stripping solution.
  • the method further includes:
  • a flat layer 9 is formed on the source layer 7 and the drain layer 8.
  • a via hole is formed on the corresponding flat layer 9 above the drain layer 8, and the via hole communicates with the drain layer 8.
  • a pixel electrode layer 10 is formed on the flat layer 9, and the pixel electrode layer 10 is connected to the drain layer 8 through the via holes.
  • the chemical corrosion potential of the gate layer 3 is higher than the chemical corrosion potential of the first metal layer 2, and the chemical corrosion potential of the source layer 7 and the drain layer 8 is higher than The chemical corrosion potential of the second metal layer 6.
  • the thickness of the first metal layer 2 is smaller than the thickness of the gate layer 3, and the thickness of the second metal layer 6 is smaller than that of the source layer 7 and the drain layer 8. thickness.
  • the thickness of the gate insulating layer 4 is smaller than the thickness of the gate layer 3, and the thickness of the gate insulating layer 4 is three-thirds of the thickness of the gate layer 3.
  • the thickness of the gate insulating layer 4 is smaller than the thickness of the gate layer 3, and the thickness of the gate insulating layer 4 is three-thirds of the thickness of the gate layer 3.
  • the first metal layer 2 and the second metal layer 6 are made of a molybdenum metal material, or a metal material having a chemical corrosion potential lower than that of the molybdenum metal.
  • the first stripping liquid and the second stripping liquid are provided by a stripping device provided with a chemical corrosion potential less than or equal to the first metal layer 2 and the second metal layer 6
  • Metal grid of chemical corrosion potential, the metal A grid is used to pass the first metal cation or the second metal cation.
  • the metal mesh of the present invention ensures that the active metal is continuously added to the first stripping liquid and the second stripping liquid, effectively suppressing chemical corrosion of the gate metal layer and the source/drain metal layer.
  • the first metal cation and the second metal cation are both molybdenum metal cations.
  • the gate layer 3, the source layer 7 and the drain layer 8 are made of a copper metal material.
  • the following table is a graph showing the corrosion test results of copper metal, molybdenum metal and copper-molybdenum mixed metal under a certain range of concentration conditions, namely corrosion Tafel curve.
  • the abscissa indicates the potential applied to the corroded metal, and the applied potential is increased, the corrosion is intensified, and the applied potential is lowered, and the corrosion is slowed down.
  • the ordinate represents the logarithm of the current that occurs at a certain potential. Copper metal and molybdenum metal have no dissolution The same corrosion potential (due to the different degree of active copper/molybdenum metal), galvanic corrosion begins when exposed to a conductive solution (eg, etchant, etched water wash). It can be seen from the above table that the lower the chemical corrosion potential of the different metals in the conductive liquid, the more easily the metal is corroded and the first to be corroded.
  • the first metal cation when the photoresist layer on the gate metal layer is stripped using the first stripping solution, the first metal cation can effectively suppress the first metal layer 2 from being chemically corroded, thereby causing cracks and further causing short circuit of the array substrate. problem.
  • the second metal cation when the photoresist layer on the source/drain metal layer is stripped using the second stripping solution, the second metal cation can effectively suppress the second metal layer 6 from being chemically etched, thereby causing cracks and further causing short circuit of the array substrate. .
  • the invention discloses a method for fabricating an array substrate, which solves the problem that in the prior art, when the photoresist is stripped by using a stripping solution, a hollowing phenomenon occurs at the edge of the contact between the gate layer 3 and the first metal layer 2. A crack is formed, which in turn causes a problem in that the source layer 7, the drain layer 8, and the gate layer 3 are short-circuited.

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  • Thin Film Transistor (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
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  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)

Abstract

提供一种阵列基板的制作方法，包括：在衬底基板（1）上依次形成第一金属层（2）、栅极层（3）、栅极绝缘层（4）、半导体层（5）、第二金属层（6）、源极层（7）与漏极层（8）；其中，在第一金属层上形成栅极层，包括：沉积栅极金属层并进行曝光显影和湿蚀刻；去除光阻层；剥离液中添加有化学腐蚀电位小于或等于第一金属层的化学腐蚀电位的金属阳离子。避免了短路的问题。

Description

一种阵列基板的制作方法 【技术领域】
本发明涉及液晶显示领域，特别涉及一种阵列基板的制作方法。
【背景技术】
液晶显示装置(LCD，Liquid Crystal Display)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。通常液晶显示面板包括CF(Color Filter)基板、TFT(Thin Film Transistor)阵列基板、及设于CF基板与TFT阵列基板之间的液晶(Liquid Crystal)。通过给TFT阵列基板供电与否来控制液晶分子改变方向，将背光模组的光线投射到CF基板产生画面。TFT阵列基板的性能特征和运行特性部分很大程度上取决于形成TFT阵列基板各元件的材料。在TFT阵列基板上布有金属导线，TFT阵列基板中的金属导线是将物理气相沉积在TFT阵列基板上的金属层通过蚀刻工艺制成，该蚀刻工艺可分为干式蚀刻和湿式蚀刻。
常规应用于TFT阵列基板中的金属导线为铝导线。随着电视等液晶显示终端的大尺寸化、高解析度以及驱动频率高速化的发展趋势及要求，液晶显示领域技术人员不得不面对TFT阵列基板中电阻及所造成的电阻/电容时间延迟问题。而铝导线具有较高的电阻率使得TFT阵列基板的像素电极层不能够充分充电，随着高频寻址(大于120Hz)液晶显示的广泛应用，这一现象更加明显。 铜导线相对于铝导线具有较低的电阻率及良好的抗电迁移能力，因而被应用到TPT阵列基板上来解决上述铝导线产生的问题。
铜与玻璃具有差的粘附性，需要用下层金属层进行过渡，并且铜在200℃以下通过互扩散易与硅反应生成具有硅化铜(CuSi3)化合物，即铜会和TPT的半导体层产生反应，产生很高的接触电阻，因此也需要采用其它下层金属层进行过渡。目前较为常用的是采用难熔金属作为过渡的粘结层和阻挡层，例如钼(Mo)，钛(Ti)以及相应元素的合金等。但是不同的阻挡层金属及合金在蚀刻后形成的外型不同，在对光阻进行剥夺的时候，会在铜和钼接触的边缘发生掏空现象，形成裂缝。此种掏空的现象会导致源、漏电极与栅电极的短路，显著的影响显示终端的良率。
图4为现有技术的一种阵列基板的制作方法中，栅极绝缘层15覆盖在栅极层13和第一金属层12上的整体结构的剖面示意图，从图4中可以看到，现有技术的衬底基板11上的栅极层13和第一金属层12的接触边缘存在裂缝14。
【发明内容】
本发明的目的在于提供一种阵列基板的制作方法，以解决现有技术中，在使用剥离液对光阻进行剥夺的时候，会在栅极层和第一金属层接触的边缘发生掏空现象，形成裂缝，进而导致源极层、漏极层与栅极层短路的问题。
本发明的技术方案如下：
一种阵列基板的制作方法，其包括：
在衬底基板上依次形成第一金属层、栅极层、栅极绝缘层、半导体层、第二金属层，及在所述第二金属层上形成源极层与漏极层；
其中，在所述第一金属层上形成所述栅极层，包括：
在所述第一金属层上沉积制作所述栅极层的栅极金属层；
在所述栅极金属层上涂布光阻层，对所述栅极金属层进行曝光显影，并对所述栅极金属层进行湿蚀刻，直至漏出所述第一金属层为止；
使用第一剥离液去除所述栅极金属层上的所述光阻层，以形成所述栅极层；
其中，所述第一剥离液中添加有化学腐蚀电位小于或等于所述第一金属层的化学腐蚀电位的第一金属阳离子。
优选地，其中，在所述第二金属层上形成所述源极层与所述漏极层，包括：
在所述第二金属层上沉积制作所述源极层与所述漏极层的源漏极金属层；
在所述源漏极金属层上涂布光阻层，对所述源漏极金属层进行曝光显影，并对所述源漏极金属层进行湿蚀刻，直至漏出所述第二金属层为止；
使用第二剥离液去除所述源漏极金属层上的所述光阻层，以形成所述源极层与漏极层；
其中，所述第二剥离液中添加有化学腐蚀电位小于或等于所述第二金属层的化学腐蚀电位的第二金属阳离子。
优选地，形成所述源极层与所述漏极层后，还包括：
在所述源极层与所述漏极层上形成平坦层；
在所述漏极层上方对应的所述平坦层上形成过孔，所述过孔与所述漏极层相通；
在所述平坦层上形成像素电极层，所述像素电极层通过所述过孔与所述漏极层连接。
优选地，所述栅极层的化学腐蚀电位高于所述第一金属层的化学腐蚀电位，且所述源极层与所述漏极层的化学腐蚀电位高于所述第二金属层的化学腐蚀电位。
优选地，所述第一金属层的厚度小于所述栅极层的厚度，且所述第二金属层的厚度小于所述源极层与所述漏极层的厚度。
优选地，所述栅极绝缘层的厚度小于所述栅极层的厚度，且所述栅极绝缘层的厚度为所述所述栅极层的厚度的三分之一。
优选地，所述第一金属层与所述第二金属层的制作材料均为钼金属材料，或均为化学腐蚀电位低于钼金属的化学腐蚀电位的金属材料。
优选地，所述第一剥离液与所述第二剥离液由剥离设备提供，该剥离设备设有化学腐蚀电位小于或等于所述第一金属层和所述第二金属层的化学腐蚀电位的金属网格，所述金属网格用于通过所述第一金属阳离子或所述第二金属阳离子。
优选地，所述第一金属阳离子与所述第二金属阳离子均为钼金属阳离子。
优选地，所述栅极层、所述源极层与所述漏极层的制作材料为铜金属材料。
一种阵列基板的制作方法，其包括：
在衬底基板上依次形成第一金属层、栅极层、栅极绝缘层、半导体层、第二金属层，及在所述第二金属层上形成源极层与漏极层；
其中，在所述第一金属层上形成所述栅极层，包括：
在所述第一金属层上沉积制作所述栅极层的栅极金属层；
在所述栅极金属层上涂布光阻层，对所述栅极金属层进行曝光显影，并对所述栅极金属层进行湿蚀刻，直至漏出所述第一金属层为止；
使用第一剥离液去除所述栅极金属层上的所述光阻层，以形成所述栅极层；
其中，所述第一剥离液中添加有化学腐蚀电位小于或等于所 述第一金属层的化学腐蚀电位的第一金属阳离子；
其中，在所述第二金属层上形成所述源极层与所述漏极层，包括：
在所述第二金属层上沉积制作所述源极层与所述漏极层的源漏极金属层；
在所述源漏极金属层上涂布光阻层，对所述源漏极金属层进行曝光显影，并对所述源漏极金属层进行湿蚀刻，直至漏出所述第二金属层为止；
使用第二剥离液去除所述源漏极金属层上的所述光阻层，以形成所述源极层与漏极层；
其中，所述第二剥离液中添加有化学腐蚀电位小于或等于所述第二金属层的化学腐蚀电位的第二金属阳离子；
其中，形成所述源极层与所述漏极层后，还包括：
在所述源极层与所述漏极层上形成平坦层；
在所述漏极层上方对应的所述平坦层上形成过孔，所述过孔与所述漏极层相通；
在所述平坦层上形成像素电极层，所述像素电极层通过所述过孔与所述漏极层连接。
优选地，其中所述栅极层的化学腐蚀电位高于所述第一金属层的化学腐蚀电位，且所述源极层与所述漏极层的化学腐蚀电位
高于所述第二金属层的化学腐蚀电位。
优选地，其中所述第一金属层的厚度小于所述栅极层的厚度，且所述第二金属层的厚度小于所述源极层与所述漏极层的厚度。
优选地，其中所述栅极绝缘层的厚度小于所述栅极层的厚度，且所述栅极绝缘层的厚度为所述所述栅极层的厚度的三分之一。
优选地，其中所述第一金属层与所述第二金属层的制作材料均为钼金属材料，或均为化学腐蚀电位低于钼金属的化学腐蚀电位的金属材料。
优选地，其中所述第一剥离液与所述第二剥离液由剥离设备提供，该剥离设备设有化学腐蚀电位小于或等于所述第一金属层和所述第二金属层的化学腐蚀电位的金属网格，所述金属网格用于通过所述第一金属阳离子或所述第二金属阳离子。
优选地，其中所述第一金属阳离子与所述第二金属阳离子均为钼金属阳离子。
优选地，其中所述栅极层、所述源极层与所述漏极层的制作材料为铜金属材料。
本发明的有益效果：
本发明公开了一种阵列基板的制作方法，解决了现有技术中，在使用剥离液对光阻进行剥夺的时候，会在栅极层和第一金 属层接触的边缘发生掏空现象，形成裂缝，进而导致源极层、漏极层与栅极层短路的问题。
【附图说明】
图1为本发明实施例的一种阵列基板的制作方法中，在第一金属层上形成所述栅极层的实施步骤流程图；
图2为本发明实施例的一种阵列基板的制作方法中，在第二金属层上形成源极层与漏极层实施步骤流程图；
图3为发明实施例的一种阵列基板的制作方法中，阵列基板的整体结构的剖面示意图；
图4为现有技术的一种阵列基板的制作方法中，栅极绝缘层覆盖在栅极层和第一金属层上的整体结构的剖面示意图。
【具体实施方式】
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
实施例一
请参考图1至图3，图1为本实施例的一种阵列基板的制作 方法中，在第一金属层2上形成所述栅极层3的实施步骤流程图。
图2为本实施例的一种阵列基板的制作方法中，在第二金属层6上形成源极层7与漏极层8实施步骤流程图。
图3为发明实施例的一种阵列基板的制作方法中，阵列基板的整体结构的剖面示意图。
本实施例的阵列基板的制作方法，包括以下步骤：
第一，在衬底基板1上形成第一金属层2，其中衬底基板1优选为玻璃基板。
第二，在所述第一金属层2上形成栅极层3。
第三，在所述栅极层3上形成栅极绝缘层4。
第四，在所述栅极绝缘层4上形成半导体层5。
第五，在所述半导体层5上形成第二金属层6。
第六，在所述第二金属层6上形成源极层7与漏极层8。
在本实施例中，如图1所示，其中在所述第一金属层2上形成所述栅极层3，包括：
步骤S101：在所述第一金属层2上沉积制作所述栅极层3的栅极金属层。
步骤S102：在所述栅极金属层上涂布光阻层，对所述栅极金属层进行曝光显影，并对所述栅极金属层进行湿蚀刻，直至漏 出所述第一金属层2为止。
步骤S103：使用第一剥离液去除所述栅极金属层上的所述光阻层，以形成所述栅极层3。其中，所述第一剥离液中添加有化学腐蚀电位小于或等于所述第一金属层2的化学腐蚀电位的第一金属阳离子。其中，所述第一剥离液包括阴离子，所述阴离子为螯合剂。
在本实施例中，如图2所示，其中在所述第二金属层6上形成所述源极层7与所述漏极层8，包括：
步骤S201：在所述第二金属层6上沉积制作所述源极层7与所述漏极层8的源漏极金属层。
步骤S202：在所述源漏极金属层上涂布光阻层，对所述源漏极金属层进行曝光显影，并对所述源漏极金属层进行湿蚀刻，直至漏出所述第二金属层6为止。
步骤S203：使用第二剥离液去除所述源漏极金属层上的所述光阻层，以形成所述源极层7与漏极层8。其中，所述第二剥离液包括阴离子，所述阴离子为螯合剂。
其中，所述第二剥离液中添加有化学腐蚀电位小于或等于所述第二金属层6的化学腐蚀电位的第二金属阳离子。
在本实施例中，形成所述源极层7与所述漏极层8后，还包括：
在所述源极层7与所述漏极层8上形成平坦层9。
在所述漏极层8上方对应的所述平坦层9上形成过孔，所述过孔与所述漏极层8相通。
在所述平坦层9上形成像素电极层10，所述像素电极层10通过所述过孔与所述漏极层8连接。
在本实施例中，所述栅极层3的化学腐蚀电位高于所述第一金属层2的化学腐蚀电位，且所述源极层7与所述漏极层8的化学腐蚀电位高于所述第二金属层6的化学腐蚀电位。
在本实施例中，所述第一金属层2的厚度小于所述栅极层3的厚度，且所述第二金属层6的厚度小于所述源极层7与所述漏极层8的厚度。
在本实施例中，所述栅极绝缘层4的厚度小于所述栅极层3的厚度，且所述栅极绝缘层4的厚度为所述所述栅极层3的厚度的三分之一。
在本实施例中，所述第一金属层2与所述第二金属层6的制作材料均为钼金属材料，或均为化学腐蚀电位低于钼金属的化学腐蚀电位的金属材料。
在本实施例中，所述第一剥离液与所述第二剥离液由剥离设备提供，该剥离设备设有化学腐蚀电位小于或等于所述第一金属层2和所述第二金属层6的化学腐蚀电位的金属网格，所述金属 网格用于通过所述第一金属阳离子或所述第二金属阳离子。本发明的金属网格保证了活性金属持续地添加到所述第一剥离液与所述第二剥离液中，有效地抑制了上述栅极金属层和源漏极金属层的化学腐蚀。
在本实施例中，所述第一金属阳离子与所述第二金属阳离子均为钼金属阳离子。
在本实施例中，所述栅极层3、所述源极层7与所述漏极层8的制作材料为铜金属材料。
本发明所依据的原理如下所述：
下表为铜金属、钼金属和铜钼混合金属在一定范围的浓度条件下的腐蚀测试结果的曲线图表，即腐蚀塔菲尔曲线。
Figure PCTCN2017113328-appb-000001
其中，横坐标表示外加在被腐蚀金属上的电位，外加电位提高，则腐蚀加剧，外加电位降低，则腐蚀减慢。纵坐标表示在某种电位下发生的电流的对数值。铜金属和钼金属在溶解中具有不 同的腐蚀电位(由于铜/钼金属活泼程度不同)，在接触到导电溶液的时候(如蚀刻液，蚀刻后的水洗液)，电偶腐蚀开始。由上表可见，处于导电液体中的不同金属，化学腐蚀电位越低的金属越容易被腐蚀，也是最先被腐蚀的。
根据以上原理，在使用第一剥离液剥离栅极金属层上的光阻层时，第一金属阳离子可以有效地抑制第一金属层2不被化学腐蚀掉，以致造成裂缝进而造成阵列基板短路的问题。同样，在使用第二剥离液剥离源漏极金属层上的光阻层时，第二金属阳离子可以有效地抑制第二金属层6不被化学腐蚀掉，以致造成裂缝进而造成阵列基板短路的问题。
本发明公开了一种阵列基板的制作方法，解决了现有技术中，在使用剥离液对光阻进行剥夺的时候，会在栅极层3和第一金属层2接触的边缘发生掏空现象，形成裂缝，进而导致源极层7、漏极层8与栅极层3短路的问题。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (18)

  1. 一种阵列基板的制作方法，其包括：
    在衬底基板上依次形成第一金属层、栅极层、栅极绝缘层、半导体层、第二金属层，及在所述第二金属层上形成源极层与漏极层；
    其中，在所述第一金属层上形成所述栅极层，包括：
    在所述第一金属层上沉积制作所述栅极层的栅极金属层；
    在所述栅极金属层上涂布光阻层，对所述栅极金属层进行曝光显影，并对所述栅极金属层进行湿蚀刻，直至漏出所述第一金属层为止；
    使用第一剥离液去除所述栅极金属层上的所述光阻层，以形成所述栅极层；
    其中，所述第一剥离液中添加有化学腐蚀电位小于或等于所述第一金属层的化学腐蚀电位的第一金属阳离子。
  2. 根据权利要求1所述的制作方法，其中在所述第二金属层上形成所述源极层与所述漏极层，包括：
    在所述第二金属层上沉积制作所述源极层与所述漏极层的源漏极金属层；
    在所述源漏极金属层上涂布光阻层，对所述源漏极金属层进行曝光显影，并对所述源漏极金属层进行湿蚀刻，直至漏出所述第二金属层为止；
    使用第二剥离液去除所述源漏极金属层上的所述光阻层，以形成所述源极层与漏极层；
    其中，所述第二剥离液中添加有化学腐蚀电位小于或等于所述第二金属层的化学腐蚀电位的第二金属阳离子。
  3. 根据权利要求1所述的制作方法，其中形成所述源极层与所述漏极层后，还包括：
    在所述源极层与所述漏极层上形成平坦层；
    在所述漏极层上方对应的所述平坦层上形成过孔，所述过孔与所述漏极层相通；
    在所述平坦层上形成像素电极层，所述像素电极层通过所述过孔与所述漏极层连接。
  4. 根据权利要求1所述的制作方法，其中所述栅极层的化学腐蚀电位高于所述第一金属层的化学腐蚀电位，且所述源极层 与所述漏极层的化学腐蚀电位高于所述第二金属层的化学腐蚀电位。
  5. 根据权利要求1所述的制作方法，其中所述第一金属层的厚度小于所述栅极层的厚度，且所述第二金属层的厚度小于所述源极层与所述漏极层的厚度。
  6. 根据权利要求1所述的制作方法，其中所述栅极绝缘层的厚度小于所述栅极层的厚度，且所述栅极绝缘层的厚度为所述所述栅极层的厚度的三分之一。
  7. 根据权利要求1所述的制作方法，其中所述第一金属层与所述第二金属层的制作材料均为钼金属材料，或均为化学腐蚀电位低于钼金属的化学腐蚀电位的金属材料。
  8. 根据权利要求2所述的制作方法，其中所述第一剥离液与所述第二剥离液由剥离设备提供，该剥离设备设有化学腐蚀电位小于或等于所述第一金属层和所述第二金属层的化学腐蚀电位的金属网格，所述金属网格用于通过所述第一金属阳离子或所述第二金属阳离子。
  9. 根据权利要求2所述的制作方法，其中所述第一金属阳离子与所述第二金属阳离子均为钼金属阳离子。
  10. 根据权利要求1所述的制作方法，其中所述栅极层、所述源极层与所述漏极层的制作材料为铜金属材料。
  11. 一种阵列基板的制作方法，其包括：
    在衬底基板上依次形成第一金属层、栅极层、栅极绝缘层、半导体层、第二金属层，及在所述第二金属层上形成源极层与漏极层；
    其中，在所述第一金属层上形成所述栅极层，包括：
    在所述第一金属层上沉积制作所述栅极层的栅极金属层；
    在所述栅极金属层上涂布光阻层，对所述栅极金属层进行曝光显影，并对所述栅极金属层进行湿蚀刻，直至漏出所述第一金属层为止；
    使用第一剥离液去除所述栅极金属层上的所述光阻层，以形成所述栅极层；
    其中，所述第一剥离液中添加有化学腐蚀电位小于或等于所述第一金属层的化学腐蚀电位的第一金属阳离子；
    其中，在所述第二金属层上形成所述源极层与所述漏极层，包括：
    在所述第二金属层上沉积制作所述源极层与所述漏极层的源漏极金属层；
    在所述源漏极金属层上涂布光阻层，对所述源漏极金属层进行曝光显影，并对所述源漏极金属层进行湿蚀刻，直至漏出所述第二金属层为止；
    使用第二剥离液去除所述源漏极金属层上的所述光阻层，以形成所述源极层与漏极层；
    其中，所述第二剥离液中添加有化学腐蚀电位小于或等于所述第二金属层的化学腐蚀电位的第二金属阳离子；
    其中，形成所述源极层与所述漏极层后，还包括：
    在所述源极层与所述漏极层上形成平坦层；
    在所述漏极层上方对应的所述平坦层上形成过孔，所述过孔与所述漏极层相通；
    在所述平坦层上形成像素电极层，所述像素电极层通过所述过孔与所述漏极层连接。
  12. 根据权利要求11所述的制作方法，其中所述栅极层的化学腐蚀电位高于所述第一金属层的化学腐蚀电位，且所述源极层与所述漏极层的化学腐蚀电位高于所述第二金属层的化学腐蚀电位。
  13. 根据权利要求11所述的制作方法，其中所述第一金属层的厚度小于所述栅极层的厚度，且所述第二金属层的厚度小于所述源极层与所述漏极层的厚度。
  14. 根据权利要求11所述的制作方法，其中所述栅极绝缘层的厚度小于所述栅极层的厚度，且所述栅极绝缘层的厚度为所述所述栅极层的厚度的三分之一。
  15. 根据权利要求11所述的制作方法，其中所述第一金属 层与所述第二金属层的制作材料均为钼金属材料，或均为化学腐蚀电位低于钼金属的化学腐蚀电位的金属材料。
  16. 根据权利要求11所述的制作方法，其中所述第一剥离液与所述第二剥离液由剥离设备提供，该剥离设备设有化学腐蚀电位小于或等于所述第一金属层和所述第二金属层的化学腐蚀电位的金属网格，所述金属网格用于通过所述第一金属阳离子或所述第二金属阳离子。
  17. 根据权利要求11所述的制作方法，其中所述第一金属阳离子与所述第二金属阳离子均为钼金属阳离子。
  18. 根据权利要求11所述的制作方法，其中所述栅极层、所述源极层与所述漏极层的制作材料为铜金属材料。
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