CN107026120B - 一种阵列基板的制作方法 - Google Patents

一种阵列基板的制作方法 Download PDF

Info

Publication number
CN107026120B
CN107026120B CN201710202255.XA CN201710202255A CN107026120B CN 107026120 B CN107026120 B CN 107026120B CN 201710202255 A CN201710202255 A CN 201710202255A CN 107026120 B CN107026120 B CN 107026120B
Authority
CN
China
Prior art keywords
layer
metal
metal layer
drain electrode
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710202255.XA
Other languages
English (en)
Other versions
CN107026120A (zh
Inventor
姜春生
武岳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to CN201710202255.XA priority Critical patent/CN107026120B/zh
Publication of CN107026120A publication Critical patent/CN107026120A/zh
Priority to US15/578,979 priority patent/US10453874B2/en
Priority to PCT/CN2017/113328 priority patent/WO2018176880A1/zh
Application granted granted Critical
Publication of CN107026120B publication Critical patent/CN107026120B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32138—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only pre- or post-treatments, e.g. anti-corrosion processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本发明提供一种阵列基板的制作方法，其包括：在衬底基板上依次形成第一金属层、栅极层、栅极绝缘层、半导体层、第二金属层，及在第二金属层上形成源极层与漏极层；其中，在第一金属层上形成栅极层，包括：在第一金属层上沉积栅极金属层；在栅极金属层上涂布光阻层，对栅极金属层进行曝光显影，并对栅极金属层进行湿蚀刻；使用第一剥离液去除栅极金属层上的光阻层，以形成栅极层；其中，第一剥离液中添加有化学腐蚀电位小于或等于第一金属层的化学腐蚀电位的第一金属阳离子。本发明解决了现有技术中，在使用剥离液对光阻进行剥夺的时候，会在栅极层和第一金属层接触的边缘发生掏空现象，形成裂缝，进而导致源极层、漏极层与栅极层短路的问题。

Description

一种阵列基板的制作方法
【技术领域】
本发明涉及液晶显示领域，特别涉及一种阵列基板的制作方法。
【背景技术】
液晶显示装置(LCD,Liquid Crystal Display)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。通常液晶显示面板包括CF(Color Filter)基板、TFT(Thin FilmTransistor)阵列基板、及设于CF基板与TFT阵列基板之间的液晶(Liquid Crystal)。通过给TFT阵列基板供电与否来控制液晶分子改变方向，将背光模组的光线投射到CF基板产生画面。TFT阵列基板的性能特征和运行特性部分很大程度上取决于形成TFT阵列基板各元件的材料。在TFT阵列基板上布有金属导线，TFT阵列基板中的金属导线是将物理气相沉积在TFT阵列基板上的金属层通过蚀刻工艺制成，该蚀刻工艺可分为干式蚀刻和湿式蚀刻。
常规应用于TFT阵列基板中的金属导线为铝导线。随着电视等液晶显示终端的大尺寸化、高解析度以及驱动频率高速化的发展趋势及要求，液晶显示领域技术人员不得不面对TFT阵列基板中电阻及所造成的电阻/电容时间延迟问题。而铝导线具有较高的电阻率使得TFT阵列基板的像素电极层不能够充分充电，随着高频寻址(大于120Hz)液晶显示的广泛应用，这一现象更加明显。铜导线相对于铝导线具有较低的电阻率及良好的抗电迁移能力，因而被应用到TFT阵列基板上来解决上述铝导线产生的问题。
铜与玻璃具有差的粘附性，需要用下层金属层进行过渡，并且铜在200℃以下通过互扩散易与硅反应生成具有硅化铜(CuSi3)化合物，即铜会和TFT的半导体层产生反应，产生很高的接触电阻，因此也需要采用其它下层金属层进行过渡。目前较为常用的是采用难熔金属作为过渡的粘结层和阻挡层，例如钼(Mo)，钛(Ti)以及相应元素的合金等。但是不同的阻挡层金属及合金在蚀刻后形成的外型不同，在对光阻进行剥夺的时候，会在铜和钼接触的边缘发生掏空现象，形成裂缝。此种掏空的现象会导致源、漏电极与栅电极的短路，显著的影响显示终端的良率。
图4为现有技术的一种阵列基板的制作方法中，栅极绝缘层15覆盖在栅极层13和第一金属层12上的整体结构的剖面示意图，从图4中可以看到，现有技术的衬底基板11上的栅极层13和第一金属层12的接触边缘存在裂缝14。
【发明内容】
本发明的目的在于提供一种阵列基板的制作方法，以解决现有技术中，在使用剥离液对光阻进行剥夺的时候，会在栅极层和第一金属层接触的边缘发生掏空现象，形成裂缝，进而导致源极层、漏极层与栅极层短路的问题。
本发明的技术方案如下：
一种阵列基板的制作方法，其包括：
在衬底基板上依次形成第一金属层、栅极层、栅极绝缘层、半导体层、第二金属层，及在所述第二金属层上形成源极层与漏极层；
其中，在所述第一金属层上形成所述栅极层，包括：
在所述第一金属层上沉积制作所述栅极层的栅极金属层；
在所述栅极金属层上涂布光阻层，对所述栅极金属层进行曝光显影，并对所述栅极金属层进行湿蚀刻，直至漏出所述第一金属层为止；
使用第一剥离液去除所述栅极金属层上的所述光阻层，以形成所述栅极层；
其中，所述第一剥离液中添加有化学腐蚀电位小于或等于所述第一金属层的化学腐蚀电位的第一金属阳离子。
优选地，其中，在所述第二金属层上形成所述源极层与所述漏极层，包括：
在所述第二金属层上沉积制作所述源极层与所述漏极层的源漏极金属层；
在所述源漏极金属层上涂布光阻层，对所述源漏极金属层进行曝光显影，并对所述源漏极金属层进行湿蚀刻，直至漏出所述第二金属层为止；
使用第二剥离液去除所述源漏极金属层上的所述光阻层，以形成所述源极层与漏极层；
其中，所述第二剥离液中添加有化学腐蚀电位小于或等于所述第二金属层的化学腐蚀电位的第二金属阳离子。
优选地，形成所述源极层与所述漏极层后，还包括：
在所述源极层与所述漏极层上形成平坦层；
在所述漏极层上方对应的所述平坦层上形成过孔，所述过孔与所述漏极层相通；
在所述平坦层上形成像素电极层，所述像素电极层通过所述过孔与所述漏极层连接。
优选地，所述栅极层的化学腐蚀电位高于所述第一金属层的化学腐蚀电位，且所述源极层与所述漏极层的化学腐蚀电位高于所述第二金属层的化学腐蚀电位。
优选地，所述第一金属层的厚度小于所述栅极层的厚度，且所述第二金属层的厚度小于所述源极层与所述漏极层的厚度。
优选地，所述栅极绝缘层的厚度小于所述栅极层的厚度，且所述栅极绝缘层的厚度为所述所述栅极层的厚度的三分之一。
优选地，所述第一金属层与所述第二金属层的制作材料均为钼金属材料，或均为化学腐蚀电位低于钼金属的化学腐蚀电位的金属材料。
优选地，所述第一剥离液与所述第二剥离液由剥离设备提供，该剥离设备设有化学腐蚀电位小于或等于所述第一金属层和所述第二金属层的化学腐蚀电位的金属网格，所述金属网格用于通过所述第一金属阳离子或所述第二金属阳离子。
优选地，所述第一金属阳离子与所述第二金属阳离子均为钼金属阳离子。
优选地，所述栅极层、所述源极层与所述漏极层的制作材料为铜金属材料。
本发明的有益效果：
本发明公开了一种阵列基板的制作方法，解决了现有技术中，在使用剥离液对光阻进行剥夺的时候，会在栅极层和第一金属层接触的边缘发生掏空现象，形成裂缝，进而导致源极层、漏极层与栅极层短路的问题。
【附图说明】
图1为本发明实施例的一种阵列基板的制作方法中，在第一金属层上形成所述栅极层的实施步骤流程图；
图2为本发明实施例的一种阵列基板的制作方法中，在第二金属层上形成源极层与漏极层实施步骤流程图；
图3为发明实施例的一种阵列基板的制作方法中，阵列基板的整体结构的剖面示意图；
图4为现有技术的一种阵列基板的制作方法中，栅极绝缘层覆盖在栅极层和第一金属层上的整体结构的剖面示意图。
【具体实施方式】
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
实施例一
请参考图1至图3，图1为本实施例的一种阵列基板的制作方法中，在第一金属层2上形成所述栅极层3的实施步骤流程图。
图2为本实施例的一种阵列基板的制作方法中，在第二金属层6上形成源极层7与漏极层8实施步骤流程图。
图3为发明实施例的一种阵列基板的制作方法中，阵列基板的整体结构的剖面示意图。
本实施例的阵列基板的制作方法，包括以下步骤：
第一，在衬底基板1上形成第一金属层2，其中衬底基板1优选为玻璃基板。
第二，在所述第一金属层2上形成栅极层3。
第三，在所述栅极层3上形成栅极绝缘层4。
第四，在所述栅极绝缘层4上形成半导体层5。
第五，在所述半导体层5上形成第二金属层6。
第六，在所述第二金属层6上形成源极层7与漏极层8。
在本实施例中，如图1所示，其中在所述第一金属层2上形成所述栅极层3，包括：
步骤S101：在所述第一金属层2上沉积制作所述栅极层3的栅极金属层。
步骤S102：在所述栅极金属层上涂布光阻层，对所述栅极金属层进行曝光显影，并对所述栅极金属层进行湿蚀刻，直至漏出所述第一金属层2为止。
步骤S103：使用第一剥离液去除所述栅极金属层上的所述光阻层，以形成所述栅极层3。其中，所述第一剥离液中添加有化学腐蚀电位小于或等于所述第一金属层2的化学腐蚀电位的第一金属阳离子。其中，所述第一剥离液包括阴离子，所述阴离子为螯合剂。
在本实施例中，如图2所示，其中在所述第二金属层6上形成所述源极层7与所述漏极层8，包括：
步骤S201：在所述第二金属层6上沉积制作所述源极层7与所述漏极层8的源漏极金属层。
步骤S202：在所述源漏极金属层上涂布光阻层，对所述源漏极金属层进行曝光显影，并对所述源漏极金属层进行湿蚀刻，直至漏出所述第二金属层6为止。
步骤S203：使用第二剥离液去除所述源漏极金属层上的所述光阻层，以形成所述源极层7与漏极层8。其中，所述第二剥离液包括阴离子，所述阴离子为螯合剂。
其中，所述第二剥离液中添加有化学腐蚀电位小于或等于所述第二金属层6的化学腐蚀电位的第二金属阳离子。
在本实施例中，形成所述源极层7与所述漏极层8后，还包括：
在所述源极层7与所述漏极层8上形成平坦层9。
在所述漏极层8上方对应的所述平坦层9上形成过孔，所述过孔与所述漏极层8相通。
在所述平坦层9上形成像素电极层10，所述像素电极层10通过所述过孔与所述漏极层8连接。
在本实施例中，所述栅极层3的化学腐蚀电位高于所述第一金属层2的化学腐蚀电位，且所述源极层7与所述漏极层8的化学腐蚀电位高于所述第二金属层6的化学腐蚀电位。
在本实施例中，所述第一金属层2的厚度小于所述栅极层3的厚度，且所述第二金属层6的厚度小于所述源极层7与所述漏极层8的厚度。
在本实施例中，所述栅极绝缘层4的厚度小于所述栅极层3的厚度，且所述栅极绝缘层4的厚度为所述所述栅极层3的厚度的三分之一。
在本实施例中，所述第一金属层2与所述第二金属层6的制作材料均为钼金属材料，或均为化学腐蚀电位低于钼金属的化学腐蚀电位的金属材料。
在本实施例中，所述第一剥离液与所述第二剥离液由剥离设备提供，该剥离设备设有化学腐蚀电位小于或等于所述第一金属层2和所述第二金属层6的化学腐蚀电位的金属网格，所述金属网格用于通过所述第一金属阳离子或所述第二金属阳离子。本发明的金属网格保证了活性金属持续地添加到所述第一剥离液与所述第二剥离液中，有效地抑制了上述栅极金属层和源漏极金属层的化学腐蚀。
在本实施例中，所述第一金属阳离子与所述第二金属阳离子均为钼金属阳离子。
在本实施例中，所述栅极层3、所述源极层7与所述漏极层8的制作材料为铜金属材料。
本发明所依据的原理如下所述：
下表为铜金属、钼金属和铜钼混合金属在一定范围的浓度条件下的腐蚀测试结果的曲线表，即腐蚀塔菲尔曲线。
其中，横坐标表示外加在被腐蚀金属上的电位，外加电位提高，则腐蚀加剧，外加电位降低，则腐蚀减慢。纵坐标表示在某种电位下发生的电流的对数值。铜金属和钼金属在溶解中具有不同的腐蚀电位(由于铜/钼金属活泼程度不同)，在接触到导电溶液的时候(如蚀刻液，蚀刻后的水洗液)，电偶腐蚀开始。由上表可见，处于导电液体中的不同金属，化学腐蚀电位越低的金属越容易被腐蚀，也是最先被腐蚀的。
根据以上原理，在使用第一剥离液剥离栅极金属层上的光阻层时，第一金属阳离子可以有效地抑制第一金属层2不被化学腐蚀掉，以致造成裂缝进而造成阵列基板短路的问题。同样，在使用第二剥离液剥离源漏极金属层上的光阻层时，第二金属阳离子可以有效地抑制第二金属层6不被化学腐蚀掉，以致造成裂缝进而造成阵列基板短路的问题。
本发明公开了一种阵列基板的制作方法，解决了现有技术中，在使用剥离液对光阻进行剥夺的时候，会在栅极层3和第一金属层2接触的边缘发生掏空现象，形成裂缝，进而导致源极层7、漏极层8与栅极层3短路的问题。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (8)

1.一种阵列基板的制作方法，其特征在于，其包括：
在衬底基板上依次形成第一金属层、栅极层、栅极绝缘层、半导体层、第二金属层，及在所述第二金属层上形成源极层与漏极层；
其中，在所述第一金属层上形成所述栅极层，包括：
在所述第一金属层上沉积制作所述栅极层的栅极金属层；
在所述栅极金属层上涂布光阻层，对所述栅极金属层进行曝光显影，并对所述栅极金属层进行湿蚀刻，直至露 出所述第一金属层为止；
使用第一剥离液去除所述栅极金属层上的所述光阻层，以形成所述栅极层；
其中，所述第一剥离液中添加有化学腐蚀电位小于或等于所述第一金属层的化学腐蚀电位的第一金属阳离子；
在所述第二金属层上形成所述源极层与所述漏极层，包括：
在所述第二金属层上沉积制作所述源极层与所述漏极层的源漏极金属层；
在所述源漏极金属层上涂布光阻层，对所述源漏极金属层进行曝光显影，并对所述源漏极金属层进行湿蚀刻，直至露 出所述第二金属层为止；
使用第二剥离液去除所述源漏极金属层上的所述光阻层，以形成所述源极层与漏极层；
其中，所述第二剥离液中添加有化学腐蚀电位小于或等于所述第二金属层的化学腐蚀电位的第二金属阳离子；
所述第一剥离液与所述第二剥离液由剥离设备提供，该剥离设备设有化学腐蚀电位小于或等于所述第一金属层和所述第二金属层的化学腐蚀电位的金属网格，所述金属网格用于通过所述第一金属阳离子或所述第二金属阳离子。
2.根据权利要求1所述的制作方法，其特征在于，形成所述源极层与所述漏极层后，还包括：
在所述源极层与所述漏极层上形成平坦层；
在所述漏极层上方对应的所述平坦层上形成过孔，所述过孔与所述漏极层相通；
在所述平坦层上形成像素电极层，所述像素电极层通过所述过孔与所述漏极层连接。
3.根据权利要求1所述的制作方法，其特征在于，所述栅极层的化学腐蚀电位高于所述第一金属层的化学腐蚀电位，且所述源极层与所述漏极层的化学腐蚀电位高于所述第二金属层的化学腐蚀电位。
4.根据权利要求1所述的制作方法，其特征在于，所述第一金属层的厚度小于所述栅极层的厚度，且所述第二金属层的厚度小于所述源极层与所述漏极层的厚度。
5.根据权利要求1所述的制作方法，其特征在于，所述栅极绝缘层的厚度小于所述栅极层的厚度，且所述栅极绝缘层的厚度为所述栅极层的厚度的三分之一。
6.根据权利要求1所述的制作方法，其特征在于，所述第一金属层与所述第二金属层的制作材料均为钼金属材料，或均为化学腐蚀电位低于钼金属的化学腐蚀电位的金属材料。
7.根据权利要求1所述的制作方法，其特征在于，所述第一金属阳离子与所述第二金属阳离子均为钼金属阳离子。
8.根据权利要求1所述的制作方法，其特征在于，所述栅极层、所述源极层与所述漏极层的制作材料为铜金属材料。
CN201710202255.XA 2017-03-30 2017-03-30 一种阵列基板的制作方法 Active CN107026120B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201710202255.XA CN107026120B (zh) 2017-03-30 2017-03-30 一种阵列基板的制作方法
US15/578,979 US10453874B2 (en) 2017-03-30 2017-11-28 Manufacturing method for array substrate
PCT/CN2017/113328 WO2018176880A1 (zh) 2017-03-30 2017-11-28 一种阵列基板的制作方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710202255.XA CN107026120B (zh) 2017-03-30 2017-03-30 一种阵列基板的制作方法

Publications (2)

Publication Number Publication Date
CN107026120A CN107026120A (zh) 2017-08-08
CN107026120B true CN107026120B (zh) 2019-07-23

Family

ID=59527482

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710202255.XA Active CN107026120B (zh) 2017-03-30 2017-03-30 一种阵列基板的制作方法

Country Status (3)

Country Link
US (1) US10453874B2 (zh)
CN (1) CN107026120B (zh)
WO (1) WO2018176880A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107026120B (zh) * 2017-03-30 2019-07-23 深圳市华星光电半导体显示技术有限公司 一种阵列基板的制作方法
CN108281431B (zh) * 2018-01-04 2021-01-05 Tcl华星光电技术有限公司 一种用于薄膜晶体管阵列基板的湿制程的方法
CN112259558B (zh) * 2020-10-15 2022-12-06 Tcl华星光电技术有限公司 阵列基板及其制备方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BR9408176A (pt) * 1993-11-29 1997-05-27 Henkel Corp Composiçao líquida ácida aquosa processo de tratar uma superfície de metal e artigo de manufatura
US6599370B2 (en) * 2000-10-16 2003-07-29 Mallinckrodt Inc. Stabilized alkaline compositions for cleaning microelectronic substrates
JP4300400B2 (ja) * 2003-01-07 2009-07-22 三菱瓦斯化学株式会社 レジスト剥離液組成物
KR100905052B1 (ko) * 2003-02-26 2009-06-30 엘지디스플레이 주식회사 몰리브덴/구리 배선의 제조 방법
WO2005043245A2 (en) 2003-10-29 2005-05-12 Mallinckrodt Baker Inc. Alkaline, post plasma etch/ash residue removers and photoresist stripping compositions containing metal-halide corrosion inhibitors
CN104952932A (zh) * 2015-05-29 2015-09-30 合肥鑫晟光电科技有限公司 薄膜晶体管、阵列基板及其制作方法、显示装置
US10266799B2 (en) * 2016-05-23 2019-04-23 Fujifilm Electronic Materials U.S.A., Inc. Stripping compositions for removing photoresists from semiconductor substrates
CN107026120B (zh) * 2017-03-30 2019-07-23 深圳市华星光电半导体显示技术有限公司 一种阵列基板的制作方法

Also Published As

Publication number Publication date
CN107026120A (zh) 2017-08-08
US10453874B2 (en) 2019-10-22
WO2018176880A1 (zh) 2018-10-04
US20180301478A1 (en) 2018-10-18

Similar Documents

Publication Publication Date Title
CN102769040B (zh) 薄膜晶体管、阵列基板及其制作方法、显示装置
CN103295970B (zh) 阵列基板、其制造方法及显示装置
CN101957529A (zh) Ffs型tft-lcd阵列基板及其制造方法
CN107026120B (zh) 一种阵列基板的制作方法
KR101348474B1 (ko) 은 박막의 식각액 조성물 및 이를 이용한 금속 패턴형성방법
CN103227148B (zh) 一种阵列基板制备方法及阵列基板和显示装置
CN103911616B (zh) 刻蚀剂组合物、金属图案的形成方法和阵列基板的制法
EP3151279B1 (en) Array substrate and manufacturing method therefor, and display device
CN103236419A (zh) 阵列基板的制备方法、阵列基板以及显示装置
KR20140063283A (ko) 은 박막의 식각액 조성물 및 이를 이용한 금속 패턴의 형성방법
CN103700628A (zh) 阵列基板制作方法、阵列基板及显示装置
CN104900656A (zh) 一种阵列基板及其制备方法、显示面板和显示装置
CN103545252B (zh) 阵列基板及其制备方法、液晶显示装置
CN101963726B (zh) Ffs型tft-lcd阵列基板及其制造方法
CN101840117A (zh) Tft-lcd阵列基板及其制造方法
EP2863435A1 (en) Array substrate, manufacturing method of same, and display device
CN103820784A (zh) 刻蚀剂组合物、金属图案的形成方法和阵列基板的制法
CN102610564B (zh) Tft阵列基板的制作方法
CN107978608B (zh) Ips型薄膜晶体管阵列基板及其制作方法
CN107275343B (zh) 底栅型tft基板的制作方法
CN103117284A (zh) 一种阵列基板及其制作方法、显示装置
CN203312295U (zh) 一种裸眼3d功能面板的信号基板及显示设备
US9171939B2 (en) Method for manufacturing thin-film transistor and thin-film transistor manufactured with same
CN111383998B (zh) 阵列基板及其制作方法
CN105590895B (zh) 显示面板的制备方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right

Effective date of registration: 20171103

Address after: 518132 No. 9-2 Ming Avenue, Gongming street, Guangming District, Guangdong, Shenzhen

Applicant after: Shenzhen Huaxing photoelectric semiconductor display technology Co., Ltd.

Address before: 518132 9-2, Guangming Road, Guangming New District, Guangdong, Shenzhen

Applicant before: Shenzhen Huaxing Optoelectronic Technology Co., Ltd.

TA01 Transfer of patent application right
GR01 Patent grant
GR01 Patent grant