WO2018176833A1 - Display substrate, manufacturing method thereof, and display panel - Google Patents

Display substrate, manufacturing method thereof, and display panel Download PDF

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Publication number
WO2018176833A1
WO2018176833A1 PCT/CN2017/108566 CN2017108566W WO2018176833A1 WO 2018176833 A1 WO2018176833 A1 WO 2018176833A1 CN 2017108566 W CN2017108566 W CN 2017108566W WO 2018176833 A1 WO2018176833 A1 WO 2018176833A1
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WO
WIPO (PCT)
Prior art keywords
substrate
layer
substantially same
display substrate
conductive adhesive
Prior art date
Application number
PCT/CN2017/108566
Other languages
English (en)
French (fr)
Inventor
Yang Wang
Tingliang LIU
Weiyun Huang
Shan Gao
Yuanjie XU
Pengcheng Zang
Zhonglin CAO
Original Assignee
Boe Technology Group Co., Ltd.
Chengdu Boe Optoelectronics Technology Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Boe Technology Group Co., Ltd., Chengdu Boe Optoelectronics Technology Co., Ltd. filed Critical Boe Technology Group Co., Ltd.
Priority to US15/772,812 priority Critical patent/US20200257151A1/en
Priority to EP17868493.2A priority patent/EP3411753B1/de
Publication of WO2018176833A1 publication Critical patent/WO2018176833A1/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/16—Materials and properties conductive
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/28—Adhesive materials or arrangements

Definitions

  • the present disclosure relates generally to the field of display technologies, and specifically to a display substrate, its manufacturing method, and a display panel.
  • TFT-LCDs thin-film transistor liquid crystal displays
  • the liquid crystal display panel typically includes a display substrate (also known as thin-film transistor panel) , and an encasing substrate (sometimes known as the color filter substrate) .
  • the display substrate is provided with one or more conductive adhesive coating portions configured to provide regions for coating a conductive adhesive (e.g., a silver paste) thereupon, and the encasing substrate is equipped with a coupling portion, which may include an anti-static sub-portion configured to collect and guide out the static electricity that is accumulated in the encasing substrate.
  • the present disclosure provides a display substrate, its manufacturing method, and a display panel including the display substrate.
  • a display substrate in a first aspect, includes a substrate, a first portion, a second portion, and a protruding portion. The first portion, the second portion, and the protruding portion are disposed over an upper surface of the substrate.
  • the first portion is configured to coat a conductive adhesive thereon for attachment, and for electric coupling, of the display substrate with an encasing substrate.
  • the second portion includes at least one wiring.
  • the protruding portion is disposed between the first portion and the second portion, and is configured to prevent the conductive adhesive coated on the first portion from spreading to the second portion.
  • an upper surface of the protruding portion has a larger distance to the upper surface of the substrate than an upper surface of the first portion. According to some other embodiments, an upper surface of the protruding portion has a distance to the upper surface of the substrate smaller than, or equal to, an upper surface of the first portion.
  • one or more first depressions can be arranged between the first portion and the protruding portion.
  • the one or more first depressions are configured such that a bottom surface thereof has a shorter distance to the upper surface of the substrate than the upper surface of the first portion.
  • the one or more first depressions can take a shape of strips, extending in a direction substantially parallel to one of the at least one wiring in the second portion that is closest to the first portion, and can take other shapes as well.
  • the bottom surface of the one or more first depressions is on a substantially same plane as the upper surface of the substrate.
  • the display substrate can further include a display area having a plurality of layers, and the protruding portion can include at least one patterned layer, configured to be at a substantially same layer as one or more of the plurality of layers in the display area of the display substrate.
  • the one or more of the at least one patterned layer of the protruding portion can be further configured to have a substantially same composition as one or more of the plurality of layers in the display area of the display substrate.
  • the display area can include at least one thin-film transistor and at least one pixel electrode, which are disposed over the upper surface of the substrate.
  • the one or more of the at least one patterned layer in the protruding portion is configured to be at a substantially same layer, and have a substantially same composition, as at least one of a gate electrode, an active layer, or a source electrode and a drain electrode, of the at least one thin-film transistor, or the at least one pixel electrode.
  • the protruding portion includes a first patterned layer, a second patterned layer, a third patterned layer, and a fourth patterned layer. It is configured such that the first patterned layer is at a substantially same layer, and has a substantially same composition, as the gate electrode; the second patterned layer is at a substantially same layer, and has a substantially same composition, as the active layer; the third patterned layer is at a substantially same layer, and has a substantially same composition, as the source electrode and the drain electrode; and the fourth patterned layer is at a substantially same layer, and has a substantially same composition, as the pixel electrode.
  • the display area comprises at least one thin-film transistor, at least one pixel electrode, at least one common electrode, and a passivation layer, disposed over the upper surface of the substrate.
  • the one or more of the at least one patterned layer in the protruding portion can be configured to be at a substantially same layer, and have a substantially same composition, as at least one of a gate electrode, an active layer, or a source electrode and a drain electrode, of the at least one thin-film transistor, the at least one pixel electrode, the at least one common electrode, or the passivation layer.
  • the protruding portion comprises a first patterned layer, a second patterned layer, a third patterned layer, a fourth patterned layer, and a fifth patterned layer. It is configured such that the first patterned layer is at a substantially same layer, and has a substantially same composition, as the gate electrode; the second patterned layer is at a substantially same layer, and has a substantially same composition, as the active layer; the third patterned layer is at a substantially same layer, and has a substantially same composition, as the source electrode and the drain electrode; the fourth patterned layer is at a substantially same layer, and has a substantially same composition, as the pixel electrode; and the fifth patterned layer is at a substantially same layer, and has a substantially same composition, as the at least one common electrode.
  • an upper surface of the first portion is provided with one or more second depressions, which are configured such that a bottom surface thereof has a shorter distance to the upper surface of the substrate than the upper surface of the first portion.
  • the one or more second depressions can take a shape of strips, extending in a direction substantially parallel to one of the at least one wiring in the second portion that is closest to the first portion, and can take other shapes as well.
  • the first portion includes a metal patterned layer, an insulating layer, and a transparent conductive patterned layer, which are sequentially disposed over the upper surface of the substrate.
  • the metal patterned layer can be provided with at least one first opening, which is configured such that an orthographic projection of the at least one first opening on the substrate is overlapped with an orthographic projection of the one or more second depressions on the substrate.
  • the insulating layer can be provided with at least one second opening, which is configured such that an orthographic projection of the at least one second opening on the substrate is overlapped with an orthographic projection of the one or more second depressions on the substrate.
  • the metal patterned layer can be configured to be at a substantially same layer, and have a substantially same composition, as either or both of a source electrode and a drain electrode, or a gate electrode of at least one thin-film transistor in the display substrate, and the transparent conductive patterned layer is configured to be at a substantially same layer, and have a substantially same composition, as either or both of at least one pixel electrode or at least one common electrode in the display substrate.
  • the disclosure further provides a display panel.
  • the display panel comprises an encasing substrate and a display substrate according to any one embodiment of the display substrate as mentioned above.
  • the encasing substrate is assembled with the display substrate, and is electrically coupled with the display substrate via the conductive adhesive coated onto the first portion of the display substrate.
  • the first portion on the display substrate can include two conductive adhesive coating sub-portions, and the two conductive adhesive coating sub-portions can be disposed respectively at two ends of a diagonal line on the display substrate.
  • the encasing substrate can be provided with a coupling portion, which is configured to be electrically coupled with the first portion on the display substrate via the conductive adhesive.
  • the coupling portion can include an anti-static sub-portion, which comprises a transparent conductive film, disposed on a side of the encasing substrate far away from the display substrate.
  • the conductive adhesive can be a silver paste.
  • the disclosure further provides a method for manufacturing a display panel.
  • the method includes a step of forming a first portion, a second portion, and a protruding portion over an upper surface of a substrate.
  • the first portion is configured to coat a conductive adhesive thereon for attachment, and for electric coupling, of the display substrate with an encasing substrate.
  • the second portion comprises at least one wiring.
  • the protruding portion is disposed between the first portion and the second portion, and is configured to prevent the conductive adhesive coated on the first portion from spreading to the second portion.
  • FIG. 1 illustrates a structural diagram of a non-display area having a conductive adhesive coating portion and a wiring region in a conventional display substrate;
  • FIG. 2A is a schematic diagram of a non-display area of a display substrate according to a first embodiment of the present disclosure
  • FIG. 2B illustrates the display substrate as shown in FIG. 2A, where the conductive adhesive is applied onto the conductive adhesive coating portion and there are ruptures and perforations in the passivation layer;
  • FIG. 3A is a schematic diagram of a non-display area of a display substrate according to a second embodiment of the present disclosure
  • FIG. 3B illustrates the display substrate as shown in FIG. 3A, where the conductive adhesive is applied onto the conductive adhesive coating portion and there are ruptures and perforations in the passivation layer;
  • FIG. 4A is a schematic diagram of a display area of a display substrate according to a third embodiment of the present disclosure.
  • FIG. 4B is a schematic diagram of a non-display area of the display substrate as mentioned in FIG. 4A;
  • FIG. 5A is a schematic diagram of a display area of a display substrate according to a fourth embodiment of the present disclosure.
  • FIG. 5B is a schematic diagram of a non-display area of the display substrate as mentioned in FIG. 5A;
  • FIG. 6A is a schematic diagram of a non-display area of a display substrate according to a fifth embodiment of the present disclosure.
  • FIG. 6B is a schematic diagram of a non-display area of a display substrate according to a sixth embodiment of the present disclosure.
  • FIG. 7A is a schematic diagram of a non-display area of a display substrate according to a seventh embodiment of the present disclosure.
  • FIG. 7B illustrates the display substrate as shown in FIG. 7A, where the conductive adhesive is applied onto the conductive adhesive coating portion and there are ruptures and perforations in the passivation layer;
  • FIG. 8 is a top view of the metal patterned layer of the conductive adhesive coating portion in the display substrate as shown in FIG. 7A;
  • FIG. 9 is a schematic diagram of a non-display area of a display substrate according to an eighth embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a non-display area of a display substrate according to a ninth embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of a non-display area of a display substrate according to a tenth embodiment of the present disclosure.
  • FIG. 12 is a top view of a display panel according to some embodiments of the present disclosure.
  • FIG. 1 illustrates one conventional conductive adhesive coating portion according to an existing technology.
  • the conductive adhesive coating portion 10 comprises a metal patterned layer 101 and a transparent conductive patterned layer 102.
  • the transparent conductive patterned layer 102 is disposed on an outer surface (i.e. an upper surface as shown in FIG. 1) of the display substrate, and is electrically connected with the metal patterned layer 101 through vias 103 arranged on a passivation layer 20 that is sandwiched between the metal patterned layer 101 and the transparent conductive patterned layer 102.
  • a conductive adhesive coating process also known as a silver dotting process if a silver paste is used as a conductive adhesive 30
  • the conductive adhesive 30 is applied on a top surface of the conductive adhesive coating portion 10 to thereby allow the attachment of the display substrate and the encasing substrate, while at the same time to realize an electrical connection between the coupling portion (e.g. anti-static sub-portion) of the encasing substrate and a common electrode of the display substrate through the conductive adhesive 30 and the conductive adhesive coating portions 10.
  • the conductive adhesive coating portion is electrically connected to a grounding wire (such as a common electrode? ) , the static electricity accumulated in the encasing substrate can be guided out by means of the electrical connection through the conductive adhesive and the conductive adhesive coating portion. As such the reliability of the vehicle-mounted display can be effectively increased.
  • the conductive adhesive 30 employed for coating the conductive adhesive coating portion 10 usually has a certain level of fluidity, the conductive adhesive 30 can occasionally spread to a wiring region (i.e. a region of the display substrate having wirings 40 disposed therein, as illustrated in FIG. 1) in the proximity of the conductive adhesive coating portion 10.
  • the present disclosure provides a display substrate.
  • the display substrate comprises a substrate, a first portion, a second portion, and a protruding portion.
  • the first portion, the second portion, and the protruding portion are disposed over an upper surface of the substrate.
  • the first portion is configured to coat a conductive adhesive thereon for attachment, and for electric coupling, of the display substrate with an encasing substrate.
  • the second portion includes at least one wiring.
  • the protruding portion is disposed between the first portion and the second portion, and is configured to prevent the conductive adhesive coated on the first portion from spreading to the second portion.
  • any of the first portion, the second portion, and the protruding portion can be disposed directly on an upper surface of the substrate, but can also be disposed to have a distance to the upper surface of the substrate.
  • upper surface and lower surface are relative terms that are respectively referred to as one and another of the two opposing surfaces of an object, and are relative to the viewing angle of the object that is illustrated in the drawings, but do not impose any special or positional limitations.
  • FIG. 2A shows a non-display area of a display substrate according to a first embodiment of the present disclosure.
  • this first embodiment of the display substrate 01 includes a conductive adhesive coating portion 10, and at least one wiring 40.
  • the conductive adhesive coating portion 10 is configured to provide a coating region for a conductive adhesive to allow a subsequent attachment of the display substrate with an encasing substrate.
  • the at least one wiring 40 is located in a wiring region (i.e. the region in the display substrate 01 that has the at least one wiring 40 disposed therein) .
  • the display substrate 01 further includes a protruding portion 60, which is disposed between the conductive adhesive coating portion 10 and one of the at least one wiring 40 that is closest to the conductive adhesive coating portion 10.
  • the protruding portion 50 is configured to have a larger height from a reference surface than the conductive adhesive coating portion 10.
  • the reference surface is referred to an upper surface of the substrate 50
  • the upper surface of the substrate 50 is referred to as a surface of the substrate 50 on which the conductive adhesive coating portion 10 and at least one wiring 40 are disposed.
  • the height of the protruding portion 50/conductive adhesive coating portion 10 is defined as a distance between an upper surface of the protruding portion 50/conductive adhesive coating portion 10 from the reference surface.
  • An upper surface of the protruding portion 50/conductive adhesive coating portion 10 is referred to as a surface thereof that is farthest away from the upper surface of the substrate 50.
  • the protruding portion 60 is configured to separate the conductive adhesive coating portion 10 with the at least one wiring 40 to thereby block the conductive adhesive 30 from spreading to the wiring region during a conductive adhesive coating process (the display substrate 01 having the conductive adhesive coating portion 10 coated with the conductive adhesive 30 is illustrated in FIG. 2B) .
  • the conductive adhesive coating process is performed only when it is needed for the display substrate and the encasing substrate to align together for encasing (or attachment) , when the conductive adhesive 30 is coated onto a top surface of the conductive adhesive coating portion 10 of the display substrate.
  • the conductive adhesive coating portion 10 is further configured to be electrically connected to a grounding wiring on the display substrate 01.
  • more than one conductive adhesive coating portions 10 can be employed.
  • the number of the conductive adhesive coating portion 10 can be chosen based on a size of the display panel having the display substrate 01.
  • two conductive adhesive coating portions 10 can be employed to allow a sufficient grounding for the anti-static sub-portion on the encasing substrate.
  • two conductive adhesive coating portions 10 can be configured on the display substrate of a vehicle-mounted display panel.
  • all the conductive adhesive coating portions 10 and the at least one wiring 40 shall be arranged in a non-display area of the substrate 50.
  • the protruding portion 60 can have any shape or structure as long as it can block the spreading of the conductive adhesive 30 during the conductive adhesive coating process.
  • the conductive adhesive coating portion 10 includes a metal patterned layer 101, a transparent conductive patterned layer 102, and a passivation layer 20.
  • the metal patterned layer 101 and the transparent conductive patterned layer 102 are disposed consecutively over the upper surface of the substrate 50, and the passivation layer 20 is sandwiched between, and configured to insulate, the metal patterned layer 10 and the transparent conductive patterned layer 102.
  • the passivation layer 20 is provided with at least one via 103, and the metal patterned layer 101 and the transparent conductive patterned layer 102 are electrically connected to each other through the at least one via in the passivation layer 20.
  • the display substrate 01 as shown in FIG. 2A and FIG. 2B serve only as one illustrating embodiment and does not impose a limitation to the scope of the disclosure. There are other embodiments based on practical needs.
  • an insulating layer other than the passivation layer 20 in the embodiment as illustrated in FIG. 2A and FIG. 2B can be arranged between the transparent conductive patterned layer 102 and the metal patterned layer 101.
  • the insulating layer can be an interlayer insulating layer or a gate insulating layer.
  • the transparent conductive patterned layer 102 and the metal patterned layer 101 in these embodiments can be electrically connected through at least one via that is arranged in the insulating layer.
  • a gate insulating layer is arranged between the transparent conductive patterned layer 102 and the metal patterned layer 101, and the transparent conductive patterned layer 102 and the metal patterned layer 101 are electrically connected through at least one via arranged in the gate insulating layer.
  • an interlayer insulating layer is arranged between the transparent conductive patterned layer 102 and the metal patterned layer 101, and the transparent conductive patterned layer 102 and the metal patterned layer 101 are electrically connected through at least one via arranged in the interlayer insulating layer.
  • each of the more than one insulating layers can be selected from a passivation layer 20, a gate insulating layer, and an interlayer insulating layer.
  • each of the passivation layer 20, the gate insulating layer, and the interlayer insulating layer is essentially an insulating layer which is formed by coating over the substrate 50.
  • the at least one via that runs through one or more insulating layers to thereby provide a means for electrically connecting the transparent conductive patterned layer 102 and the metal patterned layer 101 in the display substrate can be formed through one or more patterning processes over each of the one or more insulating layers.
  • any of the embodiments of the display substrate 01 as described above by configuring a protruding portion 60 between a conductive adhesive coating portion 10 and one wiring 40 that is closest thereto (i.e. the wiring 40 that is closest to the conductive adhesive coating portion 10) , because of the block by the protruding portion 60, it is difficult for the conductive adhesive 30 to spread to the wiring region (i.e., a region on the display substrate having the at least one wire 40) in the proximity of the conductive adhesive coating portion 10 when the conductive adhesive 30 is applied onto the conductive adhesive coating portion 10 in a conductive adhesive coating process.
  • the wiring region i.e., a region on the display substrate having the at least one wire 40
  • FIG. 3A illustrates a non-display area of a display substrate according to a second embodiment of the present disclosure.
  • the non-display area of this second embodiment of the display substrate is further provided with a depression 70, which is arranged between each conductive adhesive coating portion 10 and a protruding portion 60 corresponding thereto (i.e. the protruding portion 60 closest to the each conductive adhesive coating portion 10) .
  • the depression 70 is configured such that a bottom surface thereof has a shorter distance to the upper surface of the substrate 50 than an upper surface of the each conductive adhesive coating portion 10.
  • the bottom surface of the depression 70 is referred to as a surface thereof that is closest to the upper surface of the substrate 50, which can also be considered as a bottom surface of the depression 70, and the upper surface of the substrate 50 has been defined above whose description is skipped.
  • the depression 70 can be a groove structure formed on a surface of the display substrate, or can be substantially a gap between two portions, such as between the each conductive adhesive coating portion 10 and a protruding portion 60 that are formed on the upper surface of the substrate 50.
  • each conductive adhesive coating portion 10 includes a metal patterned layer 101 and a transparent conductive patterned layer 102, and the metal patterned layer 101 and the transparent conductive patterned layer 102 are electrically connected through the vias in the passivation layer 20, serve only as an illustrating embodiment and does not impose a limitation to the scope of the disclosure. Other embodiments that are based on practical needs are also possible.
  • a depression 70 and a protruding portion 60 are arranged between each conductive adhesive coating portion 10 and one wiring 40 that is closest to the each conductive adhesive coating portion 10, with the depression 70 arranged between the each conductive adhesive coating portion 10 and the protruding portion 60.
  • it is substantially configured such that a depression 70 and a protrusion are arranged between the each conductive adhesive coating portion 10 and the one wiring 40 that is closest to the each conductive adhesive coating portion 10.
  • FIG. 4A is a schematic diagram of a display area of a display substrate according to a third embodiments of the present disclosure.
  • this third embodiment of the display substrate 01 can further comprise a thin-film transistor 80 and a pixel electrode 90, disposed over the substrate 50 and in a display area of the display substrate 01.
  • the thin-film transistor 80 comprises a gate electrode 801, a gate insulating layer 802, an active layer 803, a source electrode 804, and a drain electrode 805.
  • the protruding portion 60 can comprise more than one patterned layers according to some embodiments of the present disclosure.
  • one or more of the patterned layers in the protruding portion 60 can be configured to be at a substantially same layer as the gate electrode 801, and/or the active layer 803, and/or the source electrode 804 and a drain electrode 805, and/or the pixel electrode 90.
  • one or more of the patterned layers in the protruding portion 60 and one or more patterned layers in the thin-film transistor 80 and the pixel electrode 90 are at substantially same layer (s)
  • at least the one or more of the patterned layers in the protruding portion 60 can be formed at the same time when the one or more patterned layers in the thin-film transistor 80 and the pixel electrode 90 that are at the same layer (s) are fabricated. Therefore, it leads to a simplified manufacturing process for the display substrate and the display panel containing the display substrate as disclosed herein.
  • one or more of the patterned layers in the protruding portion 60 and one or more patterned layers in the thin-film transistor 80 and the pixel electrode 90 that are at substantially same layer (s) can have a substantially same composition, which can lead to an even more simplified manufacturing process.
  • the gate insulating layer 802 is formed by coating over the substrate 50, thus the gate insulating layer 802 can be retained in the protruding portion 60. As such, the gate insulating layer 802 can constitute one patterned layer in the protruding portion 60.
  • the protruding portion 60 can further include a first patterned layer that is at a substantially same layer as the gate electrode 801, and/or a second patterned layer that is at a substantially same layer as the active layer 803, and/or a third patterned layer that is at a substantially same layer as the source electrode 804 and the drain electrode 805, and/or a fourth patterned layer that is at a substantially same layer as the pixel electrode 90.
  • an interlayer insulating layer can be formed by coating over the substrate 50 during the formation of the thin-film transistor 80 and the pixel electrode 90, thus the protruding portion 60 can further include an interlayer insulating layer.
  • the position of the interlayer insulating layer which can be arranged between any two electrodes to be insulated based on practical needs.
  • the display substrate 01 further comprises a thin-film transistor 80 and a pixel electrode 90, which are consecutively disposed in a display area over the substrate 50.
  • the thin-film transistor 80 comprises a gate electrode 801, a gate insulating layer 802, an active layer 803, a source electrode 804 and a drain electrode 805, which are consecutively disposed over the substrate 50.
  • the drain electrode 805 is electrically connected with a pixel electrode 90 through vias in an interlayer insulating layer 100.
  • the gate insulating layer 802 and the interlayer insulating layer 100 are both configured to coat over the substrate 50.
  • the protruding portion 60 further comprises, in addition to the gate insulating layer 802 and the interlayer insulating layer 100, a first patterned layer 601 that is at a substantially same layer as the gate electrode 801, a second patterned layer 602 that is at a substantially same layer as the active layer 803, a third patterned layer 603 that is at a substantially same layer as the source electrode 804 and the drain electrode 805, and a fourth patterned layer 604 that is at a substantially same layer as the pixel electrode 90, as illustrated in FIG. 4B.
  • the conductive adhesive coating portion 10 includes a metal patterned layer 101 and a transparent conductive patterned layer 102, wherein the metal patterned layer 101 is at a substantially same layer as the source electrode 804 and the drain electrode 805, as well as the third patterned layer 603 in the protruding portion 60.
  • the transparent conductive patterned layer 102 is at a substantially same layer as the pixel electrode 90, as well as the fourth patterned layer 604 in the protruding portion 60.
  • a wiring 40 is at a substantially same layer as the source electrode 804 and the drain electrode 805, as the third patterned layer 603 in the protruding portion 60, and as the transparent conductive patterned layer 102 in the conductive adhesive coating portion 10.
  • the type of the thin-film transistor 80 which can be an amorphous silicon thin-film transistor, a metal oxide thin-film transistor, a polycrystalline silicon thin-film transistor, or an organic thin-film transistor, etc.
  • the film transistor 80 which can be of a bottom-gate type or can be of a top-gate type. Only a bottom-gate thin-film transistor is shown in FIG. 4A as an illustrated example.
  • FIG. 5A is a schematic diagram of a display area of a display substrate according to a fourth embodiment of the present disclosure. As illustrated in FIG. 5A, in addition to a thin-film transistor 80 and a pixel electrode 90, this fourth embodiment of the display substrate 01 can further include at least one common electrode 110 and a passivation layer 20.
  • the protruding portion 60 can include a plurality of patterned layers, wherein one or more of the plurality of patterned layers are configured to be at a substantially same layer as the gate electrode 801, the active layer 803, the source electrode 804 and the drain electrode 805, the pixel electrode 90, or the at least one common electrode 110.
  • one or more of the plurality of patterned layers in the protruding portion 60 can be formed at the same time by least one one-time patterning process.
  • the gate insulating layer 802 of the thin-film transistor and the passivation layer 20 are formed by coating over the substrate 50, the gate insulating layer 802 and the passivation layer 20 can be retained in the protruding portion 60. As such, the gate insulating layer 802 and the passivation layer 20 can constitute two patterned layers in the protruding portion 60.
  • the protruding portion 60 can further include at least one of a first patterned layer 601 that is at a substantially same layer as the gate electrode 801, a second patterned layer 602 that is at a substantially same layer as the active layer 803, a third patterned layer 603 that is at a substantially same layer as the source electrode 804 and the drain electrode 805, a fourth patterned layer 604 that is at a substantially same layer as the pixel electrode 90, or a fifth patterned layer 605 that is at a substantially same layer as the at least one common electrode 110.
  • the display substrate 01 comprises a thin-film transistor 80, a pixel electrode 90, a passivation layer 20, and at least one common electrode 110, which are consecutively disposed over the substrate 50 in a display area.
  • the thin-film transistor 80 comprises a gate electrode 801, a gate insulating layer 802, an active layer 803, a source electrode 804 and a drain electrode 805, which are consecutively disposed over the substrate 50.
  • the pixel electrode 90 is disposed at a lateral side of the drain electrode 805 that is close to the substrate 50, and the pixel electrode 90 is directly in contact with the drain electrode 805.
  • the passivation layer 20 and the common electrodes 110 are disposed over a top surface of the source electrode 804 and the drain electrode 805 that is far away from the substrate 50.
  • the gate insulating layer 802 and the passivation layer 20 are disposed to coat over the whole substrate 50.
  • the protruding portion 60 further includes a first patterned layer 601 that is at a substantially same layer as the gate electrode 801, a second patterned layer 602 that is at a substantially same layer as the active layer 803, a third patterned layer 603 that is at a substantially same layer as the source electrode 804 and the drain electrode 805, a fourth patterned layer 604 that is at a substantially same layer as the pixel electrode 90, and a fifth patterned layer 605 that is at a substantially same layer as the common electrode 110.
  • a conductive adhesive coating portion 10 includes a metal patterned layer 101 and a transparent conductive patterned layer 102, wherein the metal patterned layer 101 is at a substantially same layer as the source electrode 804 and the drain electrode 805, and as well as the third patterned layer 603 in the protruding portion 60.
  • the transparent conductive patterned layer 102 is at a substantially same layer as the common electrode 110 and the fifth patterned layer 605 in the protruding portion 60.
  • a wiring 40 is at a substantially same layer as the source electrode 804 and the drain electrode 805 in the thin-film transistor 80, as the third patterned layer 603 in the protruding portion 60, and as the metal patterned layer 101 in the conductive adhesive coating portion 10.
  • the protruding portion 60 having one of the above mentioned configurations can have a height difference of more than 1.9 ⁇ m between the protruding portion 60 and the conductive adhesive coating portions 10.
  • the height difference between the protruding portion 60 and the conductive adhesive coating portions 10 is referred to as a distance between an upper surface of the protruding portion 60 and an upper surface of the conductive adhesive coating portion 10.
  • the metal patterned layer 101 can be configured to be at a substantially same layer as the source electrode 804 and the drain electrode 805, or configured to be at a substantially same layer as the gate electrode 801.
  • the metal patterned layer 101 can include two sub-layers, with a first sub-layer at a substantially same layer as the source electrode 804 and the drain electrode 805, and with a second sub-layer at a substantially same layer as the gate electrode 801.
  • the transparent conductive patterned layer 102 in the conductive adhesive coating portion 10 can be configured to be at a substantially same layer as the common electrode 110, or can be configured to be at a substantially same layer as the pixel electrode 90.
  • the transparent conductive patterned layer 102 can include two sub-layers, with one sub-layer at a substantially same layer as the common electrode 110, and with another sub-layer at a substantially same layer as the pixel electrode 90.
  • each wiring 40 can be configured to be at a substantially same layer as the source electrode 804 and the drain electrode 805, or configured to be at a substantially same layer as the gate electrode 801.
  • each wiring 40 can include two layers, with one layer at a substantially same layer as the source electrode 804 and the drain electrode 805, and with another layer at a substantially same layer as the gate electrode 801.
  • FIG. 6A and FIG. 6B illustrated a non-display area of a fifth embodiment and a sixth embodiment of the display substrate, respectively.
  • the depression 70 can be configured such that a bottom surface (i.e., a bottom surface) thereof is at a substantially same plane as an upper surface of the gate insulating layer 802.
  • the depression 70 can be configured such that a bottom surface (i.e., a bottom surface) thereof is at a substantially same plane as an upper surface of the substrate 50.
  • the display substrate 01 it is substantially configured such that the upper surface of the gate insulating layer 802 (shown in FIG. 6A) or the substrate 50 (shown in FIG. 6B) can be exposed at the site for the depression 70 to thereby form the depression 70.
  • the depression 70 is configured to have the upper surface of the substrate 50 exposed (as illustrated in FIG. 6B), and such a configuration can realize a distance of about 0.8 ⁇ m between the bottom surface of the depression 70 and the upper surface of the conductive adhesive coating portions 10.
  • Such a configuration substantially further increases the distance between the upper surface of the protruding portion 60 and the bottom surface of the depression 70, which in turn can result in a better effect in blocking the conductive adhesive 30 from spreading to the wiring region (i.e., the region having the at least one wirings 40) after the conductive adhesive coating process.
  • the present disclosure further provides a display substrate 01 according to a seventh embodiment.
  • this seventh embodiment of the display substrate 01 includes a substrate 50, at least one conductive adhesive coating portion 10, and at least one wiring 40.
  • the at least one conductive adhesive coating portion 10 and the at least one wiring 40 are disposed over the substrate 50.
  • Each of the at least one conductive adhesive coating portion 10 comprises a metal patterned layer 101 and a transparent conductive patterned layer 102, wherein the transparent conductive patterned layer 102 is disposed over a side of the metal patterned layer 101 that is farther away from the substrate 50 (i.e., the metal patterned layer 101 is between the substrate 50 and the transparent conductive patterned layer 102) .
  • the metal patterned layer 101 is configured to include a at least one first opening 1011.
  • the at least one first opening 1011 take a shape of strips and are spaced apart from one another, and are configured such that each opening 1011 can have an extending direction substantially in parallel to one of the at least one wiring 40 that is closest thereto.
  • the plurality of the first openings take a shape of straight stripes and are evenly spaced apart from one another. It is noted that at least one first opening 1011 may not be spaced apart but may be connected with each other according to some embodiments.
  • the at least one first opening 1011 can allow the conductive adhesive 30 to flow along the extending direction of the at least one first opening 1011, it increases the level of difficulty for the conductive adhesive 30 to spread to the region having the at least one wirings 40 (i.e. the wiring region) to cause electrical connection with the at least one wiring 40 through the ruptures and/or the perforations in the passivation layer 20.
  • the at least one first opening 1011 can take various different shapes, such as straight stripes (as shown in FIG. 8) , or curved stripes, etc., and that the at least one first opening 1011 do not necessarily need to be spaced apart, and can be connected to one another at any places, as long as the presence of the at least one first opening 1011 allow the conductive adhesive 30 to flow along the extending direction of the at least one first opening 1011 during the conductive adhesive coating process.
  • the conductive adhesive coating process is performed only when the display substrate and the encasing substrate are aligned together for encasing, when the conductive adhesive 30 is applied onto, and to thereby contact with, the at least one conductive adhesive coating portion 10. It is further noted that the at least one conductive adhesive coating portion 10 is electrically coupled to a grounding wiring on the display substrate 01.
  • the number of the at least one conductive adhesive coating portion 10 can be configured based on a size of the display panel to which the display substrate 01 is applied. If the display panel is small, one conductive adhesive coating portion 10 can be configured; and if the display panel is relatively big, two or more conductive adhesive coating portions 10 can be configured to allow a sufficient grounding for the anti-static sub-portion on the encasing substrate.
  • all of the conductive adhesive coating portions 10 are disposed in a non-display area of the substrate 50. All of the at least one wiring 40 as mentioned above are also disposed in the non-display area of the substrate 50.
  • the size, number, and shape of the at least one first opening 1011 in the conductive adhesive coating portions 10 which can be configured based on practical needs as long as the configuration allows the conductive adhesive 30 to flow along the extending direction of the at least one first opening 1011 to thereby prevent the conductive adhesive 30 from spreading to the wiring region in the proximity of the conductive adhesive coating portion 10.
  • each conductive adhesive coating portion 10 includes a metal patterned layer 101 and a transparent conductive patterned layer 102, which are electrically connected to each other through the vias in the passivation layer 20, the display substrate 01 serves only as illustrating embodiments and do not impose a limitation to the scope of the disclosure. There are other embodiments based on practical needs.
  • At least one insulating layer (such as an interlayer insulating layer or a gate insulating layer) can be arranged between the transparent conductive patterned layer 102 and the metal patterned layer 101.
  • the transparent conductive patterned layer 102 and the metal patterned layer 101 can be electrically connected through vias that are configured in both the passivation layer 20 and the at least one insulating layer.
  • a gate insulating layer is arranged between the transparent conductive patterned layer 102 and the metal patterned layer 101.
  • the transparent conductive patterned layer 102 and the metal patterned layer 101 can be electrically connected through vias that are configured in the gate insulating layer.
  • an interlayer insulating layer is arranged between the transparent conductive patterned layer 102 and the metal patterned layer 101.
  • the transparent conductive patterned layer 102 and the metal patterned layer 101 can be electrically connected through vias that are configured in the interlayer insulating layer.
  • each of the passivation layer 20, the gate insulating layer, and the interlayer insulating layer is essentially and substantially an insulating layer which is formed by coating over the substrate 50.
  • the metal patterned layer 101 is provided with at least one first opening 1011 that are spaced apart from one another, which substantially provide a plurality of depression 70s having an extending direction along the at least one first opening 1011 for the conductive adhesive 30 during the conductive adhesive coating process to coat the conductive adhesive 30 onto the conductive adhesive coating portion 10 of the display substrate 01 and to attach the encasing substrate with the display substrate 01 through the conductive adhesive coating portion 01 and the conductive adhesive 30.
  • the conductive adhesive 30 can flow along the extending direction of the plurality of depression 70s (i.e. the at least one first opening 1011) .
  • the at least one first opening 1011 is further configured to have the extending direction in parallel to the wirings 40 that are close thereto, which can effectively prevent the conductive adhesive 30 from spreading to the nearby wiring region. Due to these above features, the issue of short circuiting between the conductive adhesive 30 and the wirings 40 that are close thereto can be effectively avoided.
  • FIG. 9 is a schematic diagram of a non-display area of a display substrate according to an eighth embodiment of the present disclosure.
  • an insulating layer 120 is sandwiched between the metal patterned layer 101 and the transparent conductive patterned layer 102, and the insulating layer 120 is provided with at least one second opening 1201, which are spaced apart and can take a shape of strips. Similar to the at least one first opening 1101, the at least one second opening may not be spaced apart and may be connected to each other.
  • the at least one second opening 1201 correspond to the at least one first opening 1101 in a one-to-one relationship, and are configured such that an orthographic projection of the at least one second opening 1201 on the substrate 50 overlaps with an orthographic projection of the at least one first opening 1101 on the substrate 50.
  • the transparent conductive patterned layer 102 can be electrically connected to the metal patterned layer 101 through the overlapped second openings 1201 and first openings 1101.
  • the insulating layer 120 can be a passivation layer, a gate insulating layer, or an interlayer insulating layer, depending on the specific design and actual manufacturing process.
  • At least one second opening 1201 are further configured in the insulating layer 120 at sites of each conductive adhesive coating portion 10.
  • the at least one second opening 1201 correspond to the at least one first opening 1101 in the metal patterned layer 101 in a one-to-one relationship, and are further configured to have their orthographic projection on the substrate 50 overlap with the orthographic projection of the at least one first opening 1101 on the substrate 50.
  • the depression 70s formed by both the second openings 1201 in the insulating layer 120 and the first openings 1101 in the metal patterned layer 101 can be relatively deep, which further ensures that the conductive adhesive 30 can only flow along the extending direction of the depression 70s (i.e. substantially the extending direction of the first openings 1101 and the second openings 1201) , thereby effectively preventing the conductive adhesive 30 from spreading to the nearby wiring regions (i.e., regions having the wirings 40) .
  • a protruding portion 60 is disposed between each conductive adhesive coating portion 10 and one of the at least one wiring 40 that is closest to the each conductive adhesive coating portion 10.
  • the protruding portion 60 is configured to have a larger height than the each conductive adhesive coating portion 10 (i.e. a distance from the upper surface of the protruding portion 60 to the upper surface of the substrate 50 is configured to be larger than a distance from the upper surface of the each conductive adhesive coating portion 10 to the upper surface of the substrate 50) .
  • the protruding portion 60 is configured to block the conductive adhesive 30 from spreading to a region having wiring 40.
  • the display substrate is further provided with a depression 70 (i.e. a depressing structure) , which is arranged between each conductive adhesive coating portion 10 and its corresponding protruding portion 60.
  • the depression 70 is configured such that a bottom surface thereof has a shorter distance to the upper surface of the substrate 50 than an upper surface of each conductive adhesive coating portion 10.
  • the bottom surface of the depression 70 and the upper surface of the substrate 50 are at a substantially same plane.
  • a depression 70 and a protruding portion 60 are arranged between each conductive adhesive coating portion 10 and one wiring 40 that is closest to the each conductive adhesive coating portion 10, configured such that the depression 70 is between the each conductive adhesive coating portion 10 and the protruding portion 60.
  • This is substantially equivalent to the configuration of a depression 70 and a bulge between the each conductive adhesive coating portion 10 and the one wiring 40 that is closest to the each conductive adhesive coating portion 10.
  • the insulating layer 120 can also be a gate insulating layer, or an interlayer insulating layer, depending on the specific design and actual manufacturing process.
  • the metal patterned layer 101 it can be at a substantially same layer as at least one of the gate electrode 801, or the source electrode 804 and the drain electrode 805.
  • the transparent conductive patterned layer 102 it can be at a substantially same layer as at least one of the common electrode 110, or the pixel electrode 90.
  • the at least one wiring 40 each can be at a substantially same layer as at least one of the gate electrode 801, or the source electrode 804 and the drain electrode 805.
  • the metal patterned layer 101 in the conductive adhesive coating portion 10 can be configured to be at a substantially same layer as the source electrode 804 and the drain electrode 805, or configured to be at a substantially same layer as the gate electrode 801.
  • the metal patterned layer 101 can include two layers, with one layer at a substantially same layer as the source electrode 804 and the drain electrode 805 and another layer at a substantially same layer as the gate electrode 801.
  • the transparent conductive patterned layer 102 in the conductive adhesive coating portion 10 can be configured to be at a substantially same layer as the common electrode 110, or can be configured to be at a substantially same layer as the pixel electrode 90.
  • the transparent conductive patterned layer 102 can include two layers, with one layer at a substantially same layer as the common electrode 110 and another layer at a substantially same layer as the pixel electrode 90.
  • the at least one wiring 40 can be configured to be at a substantially same layer as the source electrode 804 and the drain electrode 805, or configured to be at a substantially same layer as the gate electrode 801.
  • each wiring 40 can include two layers, with one layer at a substantially same layer as the source electrode 804 and the drain electrode 805 and another layer at a substantially same layer as the gate electrode 801.
  • the disclosure further provides a display panel.
  • the display panel includes a display substrate 01 as described above, and an encasing substrate 02.
  • the encasing substrate 02 is provided with a coupling portion (not shown in the drawings) , which is electrically connected with at least one conductive adhesive coating portion 10 arranged on the display substrate 01 via the conductive adhesive 30.
  • the coupling portion can include an anti-static sub-portion, which configured to collect and guide out the static electricity that is accumulated in the encasing substrate, but can also include another sub-portion having another functionality.
  • the environment where the vehicle-mounted display panel is used can easily cause the insulating layer 120 (e.g. the passivation layer 20) that is sandwiched between the metal patterned layer 101 and the transparent conductive patterned layer 102 to subject to ruptures and perforations.
  • the display panel can be a vehicle-mounted display panel.
  • the display panel as described above has substantially same advantages or favored features as the aforementioned display substrate, which have been detailed above and will not be repeated herein.
  • configuration of two conductive adhesive coating portions 10 can guarantee a relatively high anti-static efficiency, whereas the difficulty in arranging the wirings in the display substrate 01 is not increased, compared with a configuration of more than two conductive adhesive coating portions 10.
  • one conductive adhesive coating portion 10 cannot exert its anti-static function due to some issues, the other conductive adhesive coating portion 10 can still work to exert its anti-static function, thereby resulting in an increased reliability for the display panel.
  • the coupling portion in the encasing substrate 02 can be a transparent conductive film, which is disposed on a side of the encasing substrate 02 that is relatively farther away from the display substrate 01.
  • the present disclosure provides a method for manufacturing a display substrate.
  • the method includes the steps of:
  • each protruding portion 60 is configured such that a distance of an upper surface of the one protruding portion 60 to an upper surface of the substrate 50 is larger than a distance of an upper surface of the each conductive adhesive coating portion 10 to the upper surface of the substrate 50.
  • Each of the at least one protruding portion 60 is configured to block a conductive adhesive 30 from spreading to a region containing the at least one wiring 40.
  • a thin-film transistor 80 comprises a gate electrode 801, a gate insulating layer 802, an active layer 803, a source electrode 804 and a drain electrode 805, which are consecutively disposed over the substrate 50.
  • the drain electrode 805 is electrically connected with a pixel electrode 90 through at least one via arranged in an interlayer insulating layer 100.
  • the gate insulating layer 802 and the interlayer insulating layer 100 are configured to be coated onto the whole upper surface of the substrate 50.
  • Each protruding portion 60 can include a plurality of patterned layers, and one or more of the plurality of patterned layers in each protruding portion 60 can be configured to be formed through a one-time patterning process with one or more of the gate electrode 801, the active layer 803, the source electrode 804 and the drain electrode 805, or the pixel electrode 90 in the thin-film transistor 80.
  • the protruding portion 60 can further include a first patterned layer 601 that is formed by a substantially same patterning process as the gate electrode 801, a second patterned layer 602 that is formed by a substantially same patterning process as the active layer 803, a third patterned layer 603 that is formed by a substantially same patterning process as the source electrode 804 and the drain electrode 805, a fourth patterned layer 604 that is formed by a substantially same patterning process as the pixel electrode 90.
  • each of the at least one conductive adhesive coating portion 10 includes a metal patterned layer 101 and a transparent conductive patterned layer 102. Therefore, according to some embodiments of the method, the metal patterned layer 101 is formed by a substantially same patterning process as the source electrode 804 and the drain electrode 805; the transparent conductive patterned layer 102 is formed by a substantially same patterning process as the pixel electrode 90; and each of the at least one wiring 40 is formed by a substantially same patterning process as the source electrode 804 and the drain electrode 805 of each thin-film transistor 80.
  • the metal patterned layer 101 in the conductive adhesive coating portion 10 can be configured to be at a substantially same layer as the source electrode 804 and the drain electrode 805, or can be configured to be at a substantially same layer as the gate electrode 801, or alternatively can include two sub-layers, with a first sub-layer at a substantially same layer as the source electrode 804 and the drain electrode 805 and as a second sub-layer at a substantially same layer as the gate electrode 801.
  • the metal patterned layer 101 can be formed by a substantially same patterning process as the source electrode 804 and the drain electrode 805, or as the gate electrode 801, or alternatively, by forming the first sub-layer via a substantially same patterning process as the source electrode 804 and the drain electrode 805, and forming the second sub-layer via a substantially same patterning process as the gate electrode 801.
  • the transparent conductive patterned layer 102 in the conductive adhesive coating portion 10 can be configured to be at a substantially same layer as the common electrode 110, or can be configured to be at a substantially same layer as the pixel electrode 90, or alternatively can include two sub-layers, with one sub-layer at a substantially same layer as the common electrode 110, and with another sub-layer at a substantially same layer as the pixel electrode 90.
  • the transparent conductive patterned layer 102 can be formed by a substantially same patterning process as the common electrode 110, or as the pixel electrode 90, or alternatively, by forming the one sub-layer via a substantially same patterning process as the common electrode 110, and forming the another sub-layer via a substantially same patterning process as the pixel electrode 90.
  • each of the at least one wiring 40 can be configured to be at a substantially same layer as the source electrode 804 and the drain electrode 805, or can be configured to be at a substantially same layer as the gate electrode 801, or alternatively can include two sub-layers, with one sub-layer at a substantially same layer as the source electrode 804 and the drain electrode 805, and with another sub-layer at a substantially same layer as the gate electrode 801.
  • the metal patterned layer 101 can be formed by a substantially same patterning process as the source electrode 804 and the drain electrode 805, or as the gate electrode 801, or alternatively, by forming the one sub-layer via a substantially same patterning process as the source electrode 804 and the drain electrode 805, and forming the another sub-layer via a substantially same patterning process as the gate electrode 801.
  • the method for manufacturing a display substrate further includes:
  • the protruding portion 60 can include a plurality of patterned layers, and it is configured such that one or more of the plurality of patterned layers in the protruding portion 60 are configured to be formed by a substantially same patterning process as the gate electrode 801, the active layer 803, the source electrode 804 and the drain electrode 805, the pixel electrode 90, or the at least one common electrode 110.
  • the protruding portion 60 can further include the gate insulating layer 802 and the passivation layer 20.
  • one or more of the plurality of patterned layers in the protruding portion 60 can also be formed at the same time.
  • the protruding portion 60 includes a first patterned layer 601, a second patterned layer 602, a third patterned layer 603, a fourth patterned layer 604, and a fifth patterned layer 605.
  • the first patterned layer 601 can be formed by a substantially same patterning process as the gate electrode 801
  • the second patterned layer 602 can be formed by a substantially same patterning process as the active layer 803
  • the third patterned layer 603 can be formed by a substantially same patterning process as the source electrode 804 and the drain electrode 805
  • the fourth patterned layer 604 can be formed by a substantially same patterning process as the pixel electrode 90
  • the fifth patterned layer 605 can be formed by a substantially same patterning process as the at least one common electrode 110.
  • the protruding portion 60 having the above mentioned configuration can have a height difference of more than 1.9 ⁇ m between the protruding portion 60 and the conductive adhesive coating portions 10) .
  • the method can further include:
  • the depression 70 can be configured such that a bottom surface thereof is at a substantially same plane as an upper surface of the gate insulating layer 802, as shown in FIG. 6A, or that the bottom surface thereof is at a substantially same plane as an upper surface of the substrate 50, as illustrated in FIG. 6B.
  • the upper surface of the gate insulating layer 802 (shown in FIG. 6A) or the substrate 50 (shown in FIG. 6B) can be exposed at the site for the depression 70 to thereby form the depression 70.
  • the depression 70 is configured to have the upper surface of the substrate 50 exposed (as illustrated in FIG. 6B) , and such a configuration can realize a distance of about 0.8 ⁇ m between the bottom surface of the depression 70 and the upper surface of the conductive adhesive coating portions 10.
  • Such a configuration substantially further increases the distance between the upper surface of the protruding portion 60 and the bottom surface of the depression 70, which in turn can result in a better effect in blocking the conductive adhesive 30 from spreading to the wiring region after the conductive adhesive coating process.
  • the type of the thin-film transistor 80 which can be an amorphous silicon thin-film transistor, a metal oxide thin-film transistor, a polycrystalline silicon thin-film transistor, or an organic thin-film transistor, etc.
  • the configuration of the film transistor 80 which can be of a bottom-gate type or can be of a top-gate type. Only a bottom-gate thin-film transistor is shown in FIG. 4A as an illustrated example.
  • the protruding portions 60 can be formed at the same time when each thin-film transistor 80 and each pixel electrode 90 are fabricated, the number of patterning processes for the whole manufacturing process of the display substrate do not need to be increased.

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