WO2018176540A1 - Ips型阵列基板及液晶显示面板 - Google Patents

Ips型阵列基板及液晶显示面板 Download PDF

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Publication number
WO2018176540A1
WO2018176540A1 PCT/CN2017/081833 CN2017081833W WO2018176540A1 WO 2018176540 A1 WO2018176540 A1 WO 2018176540A1 CN 2017081833 W CN2017081833 W CN 2017081833W WO 2018176540 A1 WO2018176540 A1 WO 2018176540A1
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Prior art keywords
common
array substrate
transparent electrode
substrate
layer
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PCT/CN2017/081833
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English (en)
French (fr)
Inventor
任维
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深圳市华星光电技术有限公司
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Priority to US15/576,141 priority Critical patent/US10488719B2/en
Publication of WO2018176540A1 publication Critical patent/WO2018176540A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an IPS type array substrate and a liquid crystal display panel.
  • TFT-LCD Active Thin Film Transistor-Liquid Crystal Display
  • IPS In-Plane
  • TFT-LCD Switching, flat panel conversion displays are widely used in TVs and public display devices with touch capabilities.
  • IPS display Two electrodes that control liquid crystal molecules in the IPS display - pixel electrode and common electrode (common Electrode) are fabricated on the same substrate, unlike traditional TN (twisted The two poles of the nematic, TN) liquid crystal display are respectively arranged on the upper and lower substrates, and the liquid crystal molecules are vertically arranged under the electric field.
  • IPS display usually uses ITO (Indium tin Oxide, indium tin oxide)
  • the transparent electrode is a common electrode and a pixel electrode, and the entire surface of the ITO is used at the common electrode, resulting in an excessive impedance.
  • An object of the present invention is to provide an IPS type array substrate and a liquid crystal display panel, which can reduce impedance.
  • An embodiment of the present invention provides an IPS type array substrate, including: a substrate, a common line, a data line, a plurality of pixel electrodes, and a plurality of common electrodes;
  • the common line is disposed on the substrate
  • the data line is disposed on the substrate
  • the pixel electrode is disposed on the substrate and electrically connected to the data line;
  • the common electrode and the pixel electrode are alternately arranged on the substrate and electrically connected to the common line, and the common electrode is used to generate a horizontally oriented electric field with the pixel electrode;
  • the pixel electrode and the common electrode each include a first transparent electrode layer, a second transparent electrode layer, and a metal layer between the first transparent electrode layer and the second transparent electrode layer.
  • the array substrate further includes: a plurality of passivation layers
  • the passivation layer is disposed between the substrate and the pixel electrode, and a trench is formed between adjacent passivation layers;
  • the common electrode is disposed within the trench. as well as
  • the first transparent electrode layer and the second transparent electrode layer each include indium tin oxide.
  • the first transparent electrode layer has a thickness of 10-12 nm.
  • the second transparent electrode layer has a thickness of 10-12 nm.
  • the material of the metal layer is copper or aluminum.
  • the metal layer has a thickness of 1-4 nm.
  • the pixel electrode and the common electrode are etched by oxalic acid at a temperature of 45-60 degrees Celsius for 110-130 seconds to form a pixel electrode pattern and a common electrode pattern, respectively.
  • the pixel electrode and the common electrode are formed in the same mask process.
  • An embodiment of the present invention further provides an IPS type array substrate, including: a substrate, a common line, a data line, a plurality of pixel electrodes, and a plurality of common electrodes;
  • the common line is disposed on the substrate
  • the data line is disposed on the substrate
  • the pixel electrode is disposed on the substrate and electrically connected to the data line;
  • the common electrode and the pixel electrode are alternately arranged on the substrate and electrically connected to the common line, and the common electrode is used to generate a horizontally oriented electric field with the pixel electrode;
  • the pixel electrode and the common electrode each include a first transparent electrode layer, a second transparent electrode layer, and a metal layer between the first transparent electrode layer and the second transparent electrode layer.
  • the array substrate further includes: a plurality of passivation layers;
  • the passivation layer is disposed between the substrate and the pixel electrode, and a trench is formed between adjacent passivation layers;
  • the common electrode is disposed within the trench.
  • the first transparent electrode layer and the second transparent electrode layer each include indium tin oxide.
  • the first transparent electrode layer has a thickness of 10-12 nm.
  • the second transparent electrode layer has a thickness of 10-12 nm.
  • the material of the metal layer is copper or aluminum.
  • the metal layer has a thickness of 1-4 nm.
  • the pixel electrode and the common electrode are etched by oxalic acid at a temperature of 45-60 degrees Celsius for 110-130 seconds to form a pixel electrode pattern and a common electrode pattern, respectively.
  • the pixel electrode and the common electrode are formed in the same mask process.
  • the present invention also provides a liquid crystal display panel comprising an IPS type array substrate
  • the IPS type array substrate includes: a substrate, a common line, a data line, a plurality of pixel electrodes, and a plurality of common electrodes;
  • the common line is disposed on the substrate
  • the data line is disposed on the substrate
  • the pixel electrode is disposed on the substrate and electrically connected to the data line;
  • the common electrode and the pixel electrode are alternately arranged on the substrate and electrically connected to the common line, and the common electrode is used to generate a horizontally oriented electric field with the pixel electrode;
  • the pixel electrode and the common electrode each include a first transparent electrode layer, a second transparent electrode layer, and a metal layer between the first transparent electrode layer and the second transparent electrode layer.
  • the array substrate further includes: a plurality of passivation layers;
  • the passivation layer is disposed between the substrate and the pixel electrode, and a trench is formed between adjacent passivation layers;
  • the common electrode is disposed within the trench.
  • the first transparent electrode layer and the second transparent electrode layer each include indium tin oxide.
  • the first transparent electrode layer has a thickness of 10 to 12 nm.
  • the IPS type array substrate and the liquid crystal display panel of the present invention have a structure in which the pixel electrode and the common electrode are arranged in a two-layer transparent electrode layer sandwiching the metal layer, thereby reducing the impedance. .
  • FIG. 1 is a schematic structural diagram of an IPS type array substrate according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of another IPS type array substrate according to an embodiment of the present invention.
  • FIG. 1 is a schematic structural view of a first preferred embodiment of an IPS type array substrate according to the present invention.
  • the IPS type array substrate 100 of the preferred embodiment includes a substrate 10, a common line (not shown), a data line (not shown), a plurality of pixel electrodes 20, and a plurality of common electrodes 30.
  • the common line and the data line are both disposed on the substrate 10.
  • the common line is used to transmit a common signal
  • the data line is used to transmit a data signal.
  • the pixel electrode is disposed on the substrate 10 and electrically connected to the data line to receive a data signal transmitted by the data line.
  • the common electrode 30 is electrically connected to the common line to receive a common signal transmitted by the common line.
  • the common electrode 30 and the pixel electrode 20 are alternately arranged on the substrate 10, and a horizontally oriented electric field is generated with the pixel electrode 20.
  • the pixel electrode 20 is a strip electrode, and includes a first transparent electrode layer 21, a second transparent electrode layer 22, and a metal layer 22 between the first transparent electrode layer 20 and the second transparent electrode layer 21.
  • the common electrode 30 is a strip electrode, and includes a first transparent electrode layer 31, a second transparent electrode layer 32, and a metal layer 33 between the first transparent electrode layer 31 and the second transparent electrode layer 32.
  • the first transparent electrode layer and the second transparent electrode layer included in the pixel electrode 20 or the common electrode 30 each include a transparent metal such as ITO, indium zinc oxide, aluminum oxide tin, or aluminum zinc oxide. Oxide material. In some embodiments, the first transparent electrode layer and the second transparent electrode layer each include indium tin oxide.
  • the first transparent electrode layer of the pixel electrode 20 or the common electrode 30 has a thickness of 10-12 nm
  • the second transparent electrode layer has a thickness of 10-12 nm
  • the material of the metal layer included in the pixel electrode 20 or the common electrode 30 is copper or aluminum.
  • the metal layer has a thickness of 1-4 nm.
  • the substrate 10 is first provided, and in some embodiments the substrate 10 is a glass substrate.
  • the substrate 10 is then cleaned to remove dust, grease, contaminants, and natural oxides from the surface of the substrate 10.
  • PVD Physical
  • Vapor Deposition, physical vapor deposition is performed to form a first transparent electrode layer 21, a metal layer 22, and a second transparent electrode layer 23.
  • the substrate 10 may be subjected to ITO sputtering, using a dissociation of high-energy electrons to ionize the sputtering gas to form a plasma, and the gas plasma bombards the target under the acceleration of the electric field to make the target atom Sputtering is transferred to the surface of the substrate 10 to form the first transparent electrode layer 21, and the thickness is controlled to 10-12 nm.
  • the substrate 10 may be sputtered with a transparent metal oxide such as indium zinc oxide, aluminum oxide oxide or aluminum zinc oxide to form a first transparent electrode layer 21 having a thickness of 10-12 nm.
  • a 1-4 nm thick metal layer 22 is sputtered on the first transparent electrode layer 21, wherein the metal layer 22 material may be copper or aluminum. Since the impedance of a metal such as copper or aluminum is smaller than the impedance of a transparent metal oxide such as ITO, the impedance of the pixel electrode 20 can also be lowered.
  • a transparent metal oxide such as ITO, indium zinc oxide, aluminum oxide tin or aluminum zinc oxide is sputtered on the metal layer 22 to form a second transparent electrode layer having a thickness of 10 to 12 nm.
  • the coating process of the first transparent electrode layer 21, the metal layer 22 and the second transparent electrode layer can be completed by different coating chambers of one machine equipment, without adding additional equipment and redundant processes. Process.
  • the method of forming the common electrode 30 is similar to the method of forming the pixel electrode 20, it will not be described in detail in this embodiment. After the pixel electrode 20 and the common electrode 30 are formed, they are subjected to photoresist coating, exposure, inspection development, size measurement, wet etching, and stripping of the photoresist to form a pixel electrode pattern and a common electrode pattern.
  • the strong acid liquid is generally used for patterning in wet etching.
  • the etching time of the chemical solution will affect the line width and etching residue of the pattern, and the line width and etching residue are the most important performance parameters of the pixel electrode wet etching, so it is necessary to control the etching. Eclipse time.
  • the temperature of the chemical solution affects the chemical reaction and the reaction rate, and has an effect on the etching rate and uniformity.
  • the temperature change of the pharmaceutical industry also affects the wettability between the photoresist and the film, and has a very large etching shape. influences. Therefore, the temperature of the chemical solution should be strictly controlled during etching.
  • both the first transparent electrode layer and the second transparent electrode layer are ITO materials
  • oxalic acid etching at a temperature of 45-60 degrees Celsius may be used for 110-130 seconds to form a pixel electrode pattern and a common electrode pattern.
  • the etching amount is insufficient, etching residues are likely to occur, which may cause point defects and short circuits. If the etching amount is too large, it may cause a misalignment with the contact hole to cause a point defect, or cause poor control of liquid crystal molecules outside the light shielding region, resulting in light leakage. In order to place the etching amount too large or too small, some auxiliary wiring can be used.
  • the photoresist is stripped by the chemical reaction of the stripping solution and the photoresist to expand, soften and dissolve the photoresist.
  • the pixel electrode and the common electrode are formed in the same mask process, thereby effectively reducing the process difficulty and reducing the cost.
  • FIG. 2 is another schematic structural diagram of the IPS type array substrate 100 of the present invention.
  • the IPS type array substrate 100 further includes a plurality of passivation layers 40.
  • the passivation layer 40 is trapezoidal in shape.
  • the passivation layer 40 is disposed between the substrate 10 and the pixel electrode 20, and a trench is formed between the adjacent passivation layers 40 such that the common electrode 30 is disposed in the trench.
  • the IPS type array substrate of the present invention reduces the impedance by providing the pixel electrode and the common electrode in a structure in which the two transparent electrode layers sandwich the metal layer.
  • the present invention also provides a liquid crystal display panel comprising an IPS type array substrate, a liquid crystal layer and a color filter substrate, the liquid crystal layer being disposed between the IPS type array substrate and the color filter substrate.
  • the IPS type array substrate includes: a substrate, a common line, a data line, a plurality of pixel electrodes, and a plurality of common electrodes;
  • the common line is disposed on the substrate
  • the data line is disposed on the substrate
  • the pixel electrode is disposed on the substrate and electrically connected to the data line;
  • the common electrode and the pixel electrode are alternately arranged on the substrate and electrically connected to the common line, and the common electrode is used to generate a horizontally oriented electric field with the pixel electrode;
  • the pixel electrode and the common electrode each include a first transparent electrode layer, a second transparent electrode layer, and a metal layer between the first transparent electrode layer and the second transparent electrode layer.
  • the array substrate further includes: a plurality of passivation layers;
  • the passivation layer is disposed between the substrate and the pixel electrode, and a trench is formed between adjacent passivation layers;
  • the common electrode is disposed within the trench.
  • the first transparent electrode layer and the second transparent electrode layer each include indium tin oxide.
  • the first transparent electrode layer has a thickness of 10-12 nm.
  • the second transparent electrode layer has a thickness of 10-12 nm.
  • the material of the metal layer is copper or aluminum.
  • the metal layer has a thickness of 1-4 nm.
  • the pixel electrode and the common electrode are etched by oxalic acid at a temperature of 45-60 degrees Celsius for 110-130 seconds to form a pixel electrode pattern and a common electrode pattern, respectively.
  • the pixel electrode and the common electrode are formed in the same mask process.
  • the working principle of the liquid crystal display panel of the preferred embodiment is the same as that of the IPS type array substrate of the preferred embodiment.
  • the liquid crystal display panel of the present invention reduces the impedance by providing the pixel electrode and the common electrode in a structure in which the two transparent electrode layers sandwich the metal layer.

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Abstract

一种IPS型阵列基板（100）及液晶显示面板，其中阵列基板（100）包括：基板（10）、公共线、数据线、多个像素电极（20）和多个公共电极（30）；像素电极（20）、公共电极（30）均包括第一透明电极层（21、31）、第二透明电极层（22、32）以及位于第一透明电极层（21、31）和第二透明电极层（22、32）之间的金属层（23、33）。

Description

IPS型阵列基板及液晶显示面板 技术领域
本发明涉及显示技术领域，特别是涉及一种IPS型阵列基板及液晶显示面板。
 背景技术
主动式薄膜晶体管液晶显示屏（Thin Film Transistor-Liquid Crystal Display,TFT-LCD）近年来得到飞速发展。其中TFT-LCD中的IPS（In-Plane Switching，平面转换）显示屏被广泛应用与具有触摸功能的电视和公共显示设备中。
IPS显示屏中控制液晶分子的两个电极--像素电极（pixel electrode）和公共电极（common electrode）都制作在同一块基板上，而不像传统的TN（twisted nematic,TN）型液晶显示器的两极分别在上下两块基板上，在电场作用下液晶分子垂直基板排列。IPS显示屏通常会使用ITO（Indium tin oxide,氧化铟锡）透明电极当公共电极和像素电极,且在公共电极使用整面的ITO，导致阻抗过大。
 技术问题
本发明的目的在于提供一种IPS型阵列基板及液晶显示面板，可以降低阻抗。
 技术解决方案
本发明实施例提供一种IPS型阵列基板，其包括：基板、公共线、数据线、多个像素电极和多个公共电极；
所述公共线设置在所述基板上；
所述数据线设置在所述基板上；
所述像素电极设置在所述基板上，并与所述数据线电连接；
所述公共电极与所述像素电极交替排布在所述基板上，并与所述公共线电连接，所述公共电极用于与所述像素电极产生水平取向的电场；
所述像素电极、所述公共电极均包括第一透明电极层、第二透明电极层以及位于所述第一透明电极层和所述第二透明电极层之间的金属层。
其中，所述阵列基板还包括：多个钝化层；
所述钝化层设置在所述基板和所述像素电极之间，相邻所述钝化层之间形成沟槽；
所述公共电极设置在所述沟槽内。以及
其中，所述第一透明电极层和所述第二透明电极层均包括氧化铟锡。
在本发明所述的IPS型阵列基板中，所述第一透明电极层厚度为10-12纳米。
在本发明所述的IPS型阵列基板中，所述第二透明电极层厚度为10-12纳米。
在本发明所述的IPS型阵列基板中，所述金属层的材料为铜或铝。
在本发明所述的IPS型阵列基板中，所述金属层厚度为1-4纳米。
在本发明所述的IPS型阵列基板中，所述像素电极和所述公共电极经温度为45-60摄氏度的草酸蚀刻110-130秒分别形成像素电极图形和公共电极图形。
在本发明所述的IPS型阵列基板中，所述像素电极和所述公共电极在同一道光罩制程中形成。
本发明实施例还提供一种IPS型阵列基板，其包括：基板、公共线、数据线、多个像素电极和多个公共电极；
所述公共线设置在所述基板上；
所述数据线设置在所述基板上；
所述像素电极设置在所述基板上，并与所述数据线电连接；
所述公共电极与所述像素电极交替排布在所述基板上，并与所述公共线电连接，所述公共电极用于与所述像素电极产生水平取向的电场；
所述像素电极、所述公共电极均包括第一透明电极层、第二透明电极层以及位于所述第一透明电极层和所述第二透明电极层之间的金属层。
在本发明所述的IPS型阵列基板中，所述阵列基板还包括：多个钝化层；
所述钝化层设置在所述基板和所述像素电极之间，相邻所述钝化层之间形成沟槽；
所述公共电极设置在所述沟槽内。
在本发明所述的IPS型阵列基板中，所述第一透明电极层和所述第二透明电极层均包括氧化铟锡。
在本发明所述的IPS型阵列基板中，所述第一透明电极层厚度为10-12纳米。
在本发明所述的IPS型阵列基板中，所述第二透明电极层厚度为10-12纳米。
在本发明所述的IPS型阵列基板中，所述金属层的材料为铜或铝。
在本发明所述的IPS型阵列基板中，所述金属层厚度为1-4纳米。
在本发明所述的IPS型阵列基板中，所述像素电极和所述公共电极经温度为45-60摄氏度的草酸蚀刻110-130秒分别形成像素电极图形和公共电极图形。
在本发明所述的IPS型阵列基板中，所述像素电极和所述公共电极在同一道光罩制程中形成。
本发明还提供一种液晶显示面板，其包括IPS型阵列基板；
所述IPS型阵列基板包括：基板、公共线、数据线、多个像素电极和多个公共电极；
所述公共线设置在所述基板上；
所述数据线设置在所述基板上；
所述像素电极设置在所述基板上，并与所述数据线电连接；
所述公共电极与所述像素电极交替排布在所述基板上，并与所述公共线电连接，所述公共电极用于与所述像素电极产生水平取向的电场；以及
所述像素电极、所述公共电极均包括第一透明电极层、第二透明电极层以及位于所述第一透明电极层和所述第二透明电极层之间的金属层。
在本发明所述的液晶显示面板中，所述阵列基板还包括：多个钝化层；
所述钝化层设置在所述基板和所述像素电极之间，相邻所述钝化层之间形成沟槽；
所述公共电极设置在所述沟槽内。
在本发明所述的液晶显示面板中，所述第一透明电极层和所述第二透明电极层均包括氧化铟锡。
在本发明所述的液晶显示面板中，所述第一透明电极层厚度为10-12纳米。
 有益效果
相较于现有的IPS型阵列基板及液晶显示面板，本发明的IPS型阵列基板及液晶显示面板通过将像素电极和公共电极设置成两层透明电极层夹着金属层的结构，降低了阻抗。
 附图说明
为让本发明的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下：
图1为本发明实施例提供的IPS型阵列基板的结构示意图；
图2为本发明实施例提供的另一IPS型阵列基板的结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的单元是以相同标号表示。
请参照图1，图1为本发明的IPS型阵列基板的第一优选实施例的结构示意图。本优选实施例的IPS型阵列基板100包括：基板10、公共线（图未示出）、数据线（图未示出）、多个像素电极20和多个公共电极30。
所述公共线和所述数据线均设置在所述基板10上。其中该公共线用于传输公共信号，该数据线用于传输数据信号。
所述像素电极设置在所述基板10上，并与所述数据线电连接，以接收该数据线传输的数据信号。
所述公共电极30与所述公共线电连接，以接收该公共线传输的公共信号。所述公共电极30与所述像素电极20交替排布在所述基板10上，与所述像素电极20产生水平取向的电场。
所述像素电极20为条状电极，包括第一透明电极层21、第二透明电极层22以及位于所述第一透明电极层20和所述第二透明电极层21之间的金属层22。
所述公共电极30为条状电极，包括第一透明电极层31、第二透明电极层32以及位于所述第一透明电极层31和所述第二透明电极层32之间的金属层33。
在一些实施例中，所述像素电极20或公共电极30包含的所述第一透明电极层和所述第二透明电极层均包括ITO、氧化铟锌、氧化铝锡、氧化铝锌等透明金属氧化物材料。在一些实施例中，所述第一透明电极层和所述第二透明电极层均包括氧化铟锡。
在一些实施例中，所述像素电极20或公共电极30包含的所述第一透明电极层厚度为10-12纳米，第二透明电极层厚度为10-12纳米。
在一些实施例中，所述像素电极20或公共电极30包含的金属层的材料为铜或铝。所述金属层厚度为1-4纳米。
接下来详细介绍像素电极20的形成过程。首先提供基板10，在一些实施例中基板10为玻璃基板。接着对基板10进行清洗，去除基板10表面的灰尘、油渍、污染物及自然氧化物。然后对清洗后的基板10进行PVD(Physical Vapor Deposition，物理气相沉积)镀膜操作，以形成包含第一透明电极层21、金属层22和第二透明电极层23。
在一些实施例中，可以对基板10进行ITO溅射，利用高能量电子的解离作用，使溅射气体离化形成等离子体，气体等离子体在电场的加速下轰击靶材，使靶材原子溅射转移到基板10表面形成第一透明电极层21，并将厚度控制在10-12纳米。在一些实施例中，还可以对基板10进行氧化铟锌、氧化铝锡、氧化铝锌等透明金属氧化物溅射，形成厚度为10-12纳米的第一透明电极层21。
接着在第一透明电极层21上溅射1-4纳米厚的金属层22，其中，该金属层22材料可以为铜或铝。由于铜或铝等金属的阻抗小于ITO等透明金属氧化物的阻抗，因此也可以降低像素电极20的阻抗。
最后再在金属层22上溅射ITO、氧化铟锌、氧化铝锡或氧化铝锌等透明金属氧化物，以形成厚度为10-12纳米的第二透明电极层。
在一些实施例中，可以通过一台机台设备的不同镀膜室完成该第一透明电极层21、金属层22及第二透明电极层的镀膜工艺，无需增加额外的机台设备及多余的工艺流程。
由于公共电极30的形成方法与像素电极20的形成方法类似，本实施例中不再赘述。在形成像素电极20和公共电极30后，再经过涂光刻胶，曝光，检查显影，测定尺寸，湿刻，剥离光刻胶，形成像素电极图形和公共电极图形。
其中，在湿刻中一般采用强酸药液实现图形化。对透明金属氧化物刻蚀时，药液刻蚀时间会影响图形的线宽及刻蚀残余，而线宽及刻蚀残余即为像素电极湿刻最重要的性能参数，因此有必要控制好刻蚀时间。同时，药液温度影响化学反应及反应速度，对刻蚀速率及均一性都有影响，此外药业温度的变化还影响光刻胶和膜之间的浸润性，对刻蚀形状有非常大的影响。因此在蚀刻时要严格控制药液温度。在一些实施例中，如果第一透明电极层和第二透明电极层均为ITO材料，则可采用温度为45-60摄氏度的草酸蚀刻110-130秒，以形成像素电极图形和公共电极图形。
又对像素电极20进行刻蚀时，如果刻蚀量不足，易产生刻蚀残余，将导致点缺陷和短路。如果刻蚀量过大，则可能会造成与接触孔的错位而引起点缺陷，或引起遮光区域外的液晶分子控制不良，导致漏光。为了放置刻蚀量过大或过小，可以使用一些辅助配线。
其中，光刻胶剥离通过剥离液和光刻胶的化学反应，使光刻胶膨胀、软化并溶解。
在一些实施例中，所述像素电极和所述公共电极在同一道光罩制程中形成，从而有效的降低了工艺难度，降低了成本。
请参照图2，图2为本发明的IPS型阵列基板100的另一结构示意图。所述IPS型阵列基板100还包括多个钝化层40。在一些实施例中，该钝化层40为梯形形状。
所述钝化层40设置在所述基板10和所述像素电极20之间，相邻所述钝化层40之间形成沟槽，以使所述公共电极30设置在所述沟槽内。
本发明的IPS型阵列基板通过将像素电极和公共电极设置成两层透明电极层夹着金属层的结构，降低了阻抗。
本发明还提供一种液晶显示面板，其包括IPS型阵列基板、液晶层及彩膜基板，所述液晶层设置在所述IPS型阵列基板和所述彩膜基板之间。所述IPS型阵列基板包括：基板、公共线、数据线、多个像素电极和多个公共电极；
所述公共线设置在所述基板上；
所述数据线设置在所述基板上；
所述像素电极设置在所述基板上，并与所述数据线电连接；
所述公共电极与所述像素电极交替排布在所述基板上，并与所述公共线电连接，所述公共电极用于与所述像素电极产生水平取向的电场；
所述像素电极、所述公共电极均包括第一透明电极层、第二透明电极层以及位于所述第一透明电极层和所述第二透明电极层之间的金属层。
优选的，所述阵列基板还包括：多个钝化层；
所述钝化层设置在所述基板和所述像素电极之间，相邻所述钝化层之间形成沟槽；
所述公共电极设置在所述沟槽内。
优选的，所述第一透明电极层和所述第二透明电极层均包括氧化铟锡。
优选的，所述第一透明电极层厚度为10-12纳米。
优选的，所述第二透明电极层厚度为10-12纳米。
优选的，所述金属层的材料为铜或铝。
优选的，所述金属层厚度为1-4纳米。
优选的，所述像素电极和所述公共电极经温度为45-60摄氏度的草酸蚀刻110-130秒分别形成像素电极图形和公共电极图形。
优选的，所述像素电极和所述公共电极在同一道光罩制程中形成。
本优选实施例的液晶显示面板的工作原理跟上述优选实施例的IPS型阵列基板的工作原理一致，具体可以参考上述优选实施例的IPS型阵列基板的工作原理，在此不再赘述。
本发明的液晶显示面板通过将像素电极和公共电极设置成两层透明电极层夹着金属层的结构，降低了阻抗。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种IPS型阵列基板，其包括：基板、公共线、数据线、多个像素电极和多个公共电极；
    所述公共线设置在所述基板上；
    所述数据线设置在所述基板上；
    所述像素电极设置在所述基板上，并与所述数据线电连接；
    所述公共电极与所述像素电极交替排布在所述基板上，并与所述公共线电连接，所述公共电极用于与所述像素电极产生水平取向的电场；
    所述像素电极、所述公共电极均包括第一透明电极层、第二透明电极层以及位于所述第一透明电极层和所述第二透明电极层之间的金属层。
    其中，所述阵列基板还包括：多个钝化层；
    所述钝化层设置在所述基板和所述像素电极之间，相邻所述钝化层之间形成沟槽；
    所述公共电极设置在所述沟槽内。以及
    其中，所述第一透明电极层和所述第二透明电极层均包括氧化铟锡。
  2. 根据权利要求1所述的IPS型阵列基板，其中所述第一透明电极层厚度为10-12纳米。
  3. 根据权利要求1所述的IPS型阵列基板，其中所述第二透明电极层厚度为10-12纳米。
  4. 根据权利要求1所述的IPS型阵列基板，其中所述金属层的材料为铜或铝。
  5. 根据权利要求1所述的IPS型阵列基板，其中所述金属层厚度为1-4纳米。
  6. 根据权利要求1所述的IPS型阵列基板，其中所述像素电极和所述公共电极经温度为45-60摄氏度的草酸蚀刻110-130秒分别形成像素电极图形和公共电极图形。
  7. 根据权利要求1所述的IPS型阵列基板，其中所述像素电极和所述公共电极在同一道光罩制程中形成。
  8. 一种IPS型阵列基板，其包括：基板、公共线、数据线、多个像素电极和多个公共电极；
    所述公共线设置在所述基板上；
    所述数据线设置在所述基板上；
    所述像素电极设置在所述基板上，并与所述数据线电连接；
    所述公共电极与所述像素电极交替排布在所述基板上，并与所述公共线电连接，所述公共电极用于与所述像素电极产生水平取向的电场；以及
    所述像素电极、所述公共电极均包括第一透明电极层、第二透明电极层以及位于所述第一透明电极层和所述第二透明电极层之间的金属层。
  9. 根据权利要求8所述的IPS型阵列基板，其中所述阵列基板还包括：多个钝化层；
    所述钝化层设置在所述基板和所述像素电极之间，相邻所述钝化层之间形成沟槽；
    所述公共电极设置在所述沟槽内。
  10. 根据权利要求8所述的IPS型阵列基板，其中所述第一透明电极层和所述第二透明电极层均包括氧化铟锡。
  11. 根据权利要求10所述的IPS型阵列基板，其中所述第一透明电极层厚度为10-12纳米。
  12. 根据权利要求10所述的IPS型阵列基板，其中所述第二透明电极层厚度为10-12纳米。
  13. 根据权利要求8所述的IPS型阵列基板，其中所述金属层的材料为铜或铝。
  14. 根据权利要求8所述的IPS型阵列基板，其中所述金属层厚度为1-4纳米。
  15. 根据权利要求8所述的IPS型阵列基板，其中所述像素电极和所述公共电极经温度为45-60摄氏度的草酸蚀刻110-130秒分别形成像素电极图形和公共电极图形。
  16. 根据权利要求8所述的IPS型阵列基板，其中所述像素电极和所述公共电极在同一道光罩制程中形成。
  17. 一种液晶显示面板，其包括IPS型阵列基板；
    所述IPS型阵列基板包括：基板、公共线、数据线、多个像素电极和多个公共电极；
    所述公共线设置在所述基板上；
    所述数据线设置在所述基板上；
    所述像素电极设置在所述基板上，并与所述数据线电连接；
    所述公共电极与所述像素电极交替排布在所述基板上，并与所述公共线电连接，所述公共电极用于与所述像素电极产生水平取向的电场；以及
    所述像素电极、所述公共电极均包括第一透明电极层、第二透明电极层以及位于所述第一透明电极层和所述第二透明电极层之间的金属层。
  18. 根据权利要求17所述的液晶显示面板，其中所述阵列基板还包括：多个钝化层；
    所述钝化层设置在所述基板和所述像素电极之间，相邻所述钝化层之间形成沟槽；
    所述公共电极设置在所述沟槽内。
  19. 根据权利要求17所述的液晶显示面板，其中所述第一透明电极层和所述第二透明电极层均包括氧化铟锡。
  20. 根据权利要求19所述的液晶显示面板，其中所述第一透明电极层厚度为10-12纳米。
PCT/CN2017/081833 2017-04-01 2017-04-25 Ips型阵列基板及液晶显示面板 WO2018176540A1 (zh)

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