WO2018173105A1 - プログラマブルロジックコントローラ、メモリモジュールおよびプログラム - Google Patents

プログラマブルロジックコントローラ、メモリモジュールおよびプログラム Download PDF

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Publication number
WO2018173105A1
WO2018173105A1 PCT/JP2017/011133 JP2017011133W WO2018173105A1 WO 2018173105 A1 WO2018173105 A1 WO 2018173105A1 JP 2017011133 W JP2017011133 W JP 2017011133W WO 2018173105 A1 WO2018173105 A1 WO 2018173105A1
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WO
WIPO (PCT)
Prior art keywords
memory
unit
control
storage device
data
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PCT/JP2017/011133
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English (en)
French (fr)
Japanese (ja)
Inventor
勝裕 大西
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三菱電機株式会社
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Priority to PCT/JP2017/011133 priority Critical patent/WO2018173105A1/ja
Priority to CN201780032240.1A priority patent/CN109313425B/zh
Priority to JP2017561993A priority patent/JP6351882B1/ja
Publication of WO2018173105A1 publication Critical patent/WO2018173105A1/ja

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  • the present invention relates to a programmable logic controller (PLC), a memory module, and a program.
  • PLC programmable logic controller
  • a programmable logic controller used as a control device for industrial machines or the like includes a base unit and various units arranged on the base unit. Specifically, signals from power supply units that supply power to other units, CPU (Central Processing Unit) units that control controlled devices connected to the PLC, sensors installed in production equipment and equipment, etc.
  • Various units such as an input unit that inputs a control signal, an output unit that outputs a control output to an actuator, and a network unit for connecting to a communication network, are attached to the base unit to constitute a PLC.
  • the CPU unit appropriately updates device values and parameter values (hereinafter collectively referred to as data) used in device control, which are held in the memory.
  • the device value is a physical quantity indicating the state of the control target device.
  • Conventional PLCs are volatile that allows high-speed memory access to data updated during control operations based on the relationship between the memory access speed, that is, the data write speed to the memory and the data read speed from the memory.
  • a general configuration is provided with a backup battery that is held in a memory and prevents data loss due to a sudden power interruption.
  • a nonvolatile memory having a slower memory access speed than a volatile memory is generally used for backup of data held in the volatile memory (for example, Patent Document 1).
  • a non-volatile memory that can be used in the CPU unit that is, a non-volatile memory that satisfies the specifications required for the memory of the CPU unit
  • the batteryless unit itself is expensive, and there are many users who use a unit that is not batteryless in terms of cost.
  • the price of parts will become cheaper as it is distributed in the market, so it is expected that currently expensive non-volatile memory will become cheaper in the future, and a CPU unit with a battery-less configuration can be realized at a lower price. Is done. That is, in the future, it is expected that the cost of the nonvolatile memory that can be used in the CPU unit will be lower than the cost in the case of using a combination of a volatile memory and a data backup battery.
  • the present invention has been made in view of the above, and an object thereof is to obtain a programmable logic controller that can be changed to a battery-less configuration in the future.
  • the present invention determines whether or not a nonvolatile storage device is connected, and if a nonvolatile storage device is connected, the nonvolatile storage device The control of the control target device is started using the data stored in the apparatus as the device value or parameter value.
  • the programmable logic controller according to the present invention is advantageous in that it can be changed from a configuration including a battery for data backup to a configuration without a battery.
  • FIG. 1 is a diagram illustrating a configuration example of a CPU unit according to a first embodiment.
  • 3 is a flowchart showing an operation example of the CPU unit according to the first embodiment.
  • 6 is a flowchart showing an operation example when a volatile memory and a nonvolatile memory are mounted on the CPU unit according to the first embodiment.
  • FIG. 1 is a diagram illustrating a configuration example of a CPU unit according to a first embodiment.
  • 3 is a flowchart showing an operation example of the CPU unit according to the first embodiment.
  • 6 is a flowchart showing an operation example when a volatile memory and a nonvolatile memory are mounted on the CPU unit according to the first embodiment.
  • FIG. 2 The figure which shows the structural example of the CPU unit concerning Embodiment 2.
  • FIG. 1 is a diagram illustrating a configuration example of a PLC including a unit according to the first embodiment of the present invention.
  • the PLC 1 includes a base unit 10 that electrically connects various units for realizing functions required in production facilities, and a power supply unit 11, a CPU unit 12, and an input unit 13 that are various units connected to the base unit 10.
  • the output unit 14 and the network unit 15 are provided. There may be a case where a plurality of units of the same type are connected to one base unit.
  • the various units shown in FIG. 1 are examples.
  • FIG. 2 is a diagram illustrating a configuration example of the CPU unit 12 according to the first embodiment.
  • the CPU unit 12 is also referred to as a control unit, and includes a memory connection unit 120, a control unit 121 that controls a control target device such as an actuator connected to the output unit 14, and a control unit 121 during a control operation of the control target device.
  • a memory 122 that holds data to be updated and a battery connection unit 123 are provided.
  • the CPU unit 12 is a unit according to the present invention.
  • the data held in the memory 122 is a device value and a parameter value.
  • the memory connection unit 120 is provided for mounting a memory different from the memory 122 in the CPU unit 12.
  • An example of the memory connection unit 120 is a land provided on a substrate.
  • the control unit 121 is realized by an information processing apparatus, which is a processor having a small-capacity internal memory, executing a PLC sequence program.
  • the memory 122 is a volatile memory, and holds data used by the control unit 121 in the control operation of the control target device. However, in the future, it is assumed that the nonvolatile memory connected to the memory connection unit 120 holds data such as device values and parameters held in the memory 122.
  • a non-volatile memory connected to the control unit 121 via the memory connection unit 120 holds data such as device values and parameters so that a battery for backup of the memory 122 is not required. Is assumed.
  • the CPU 122 may be configured such that the memory 122 is removed in addition to the backup battery of the memory 122.
  • the volatile memory is a volatile storage device
  • the nonvolatile memory is a nonvolatile storage device.
  • the battery connection unit 123 is a mechanism for connecting a backup battery for data stored in the memory 122, and includes a connector or the like.
  • the memory 122 may be configured to be detachable from the CPU unit 12 in the same manner as the data backup battery. That is, the control unit 121 and the memory 122 may be mounted on different substrates, and the control unit 121 and the memory 122 may be connected via a connection mechanism such as a connector.
  • the control unit 121 includes a connection determination unit 124 that determines the type of the connected memory, that is, the type of the memory mounted on the CPU unit 12.
  • the connection determination unit 124 determines whether or not the memory 122 that is a volatile memory is connected, and whether or not the nonvolatile memory is connected via the memory connection unit 120.
  • FIG. 3 is a flowchart showing an operation example of the CPU unit 12 according to the first embodiment, and specifically shows an operation example of the operation executed when the control unit 121 starts sequence control of the control target device. ing.
  • the control operation refers to an operation of controlling a control target device by sequence control.
  • the control unit 121 of the CPU unit 12 executes the processing shown in FIG. 3 when an operator instructs the start of the control operation by performing an operation of an operation switch or the like not shown in FIG.
  • Step S11 When the control unit 121 detects the start instruction of the control operation, the control unit 121 confirms the connection of the memory to the memory connection unit 120 (step S11), and when the nonvolatile memory is connected and the volatile memory is not connected (step S11).
  • step S17 sequence control using data held in the nonvolatile memory is started (Step S17).
  • the case where the nonvolatile memory is connected refers to the case where the nonvolatile memory is connected to the memory connection unit 120.
  • the state where the volatile memory is connected refers to a state where the memory 122 is mounted.
  • Step S12 Yes, Step S15: Yes
  • the control unit 121 clears the data held in the volatile memory. Is executed (step S16). Specifically, the control unit 121 discards the stored data by clearing the memory 122, which is a volatile memory, to zero. When the discard of the data held in the volatile memory is completed, the control unit 121 starts sequence control using the data held in the nonvolatile memory (step S17).
  • the control unit 121 uses the data held in the non-volatile memory at the start of sequence control. Is stored in both a volatile memory and a nonvolatile memory. That is, when starting the sequence control, the control unit 121 first reads data such as device values and parameter values used for device control from the nonvolatile memory, and writes the read data to the volatile memory. Next, the control unit 121 performs sequence control using data held in the volatile memory, and appropriately updates the data held in the volatile memory. The operation of the control unit 121 when both the volatile memory and the nonvolatile memory are connected will be described separately.
  • step S12 When the non-volatile memory is not connected and the volatile memory is connected (step S12: No, step S13: Yes), the control unit 121 displays the data or initial value held in the volatile memory.
  • the used sequence control is started (step S14).
  • a case where the initial value is used may be a case where data is not held in the volatile memory.
  • the initial values of the device value and parameter value are described in the operation program of the control unit 121, for example.
  • Step S12 No
  • Step S13 No
  • the control unit 121 ends the operation without starting the sequence control.
  • the connection determination unit 124 executes the processes of steps S11 to S13 and S15.
  • a method for the connection determination unit 124 to determine the type of the connected memory a method of determining from the voltage applied to the memory can be considered.
  • the operating voltages of the nonvolatile memory and the volatile memory are different, it is possible to determine the type of the memory based on the voltage.
  • a pull-up resistor or a pull-down resistor is added to the conventional circuit, and the voltage value is changed by resistance division so that the type of memory can be determined.
  • Another possible method is to write information indicating the type in a specific area of the memory and read the information.
  • the operation shown in FIG. 3 may be performed after the CPU unit 12 is started, that is, at the start of the first sequence control after the power of the PLC 1 is turned on and the power supply to the CPU unit 12 is started.
  • this is not limited to the time when the first sequence control is started after the CPU unit 12 is activated, and may be always performed when starting the sequence control.
  • 3 is performed only when the first sequence control after the CPU unit 12 is started, the control unit 121 performs the first sequence control after the CPU unit 12 is started.
  • steps S11 to S13, S15, and S16 may be executed in advance to check the memory connection state. That is, the control unit 121 may automatically execute steps S11 to S13, S15, and S16 when the CPU unit 12 is activated.
  • MRAM Magneticoresistive Random Access Memory
  • DRAM Dynamic Random Access Memory
  • SRAM Static Random Access Memory
  • MRAM or a non-volatile memory having equivalent performance is connected to the memory connection unit 120 and the memory 122 is left as it is, that is, both the MRAM and the memory 122 are mounted. Even if it becomes, the battery for data backup of the memory 122 becomes unnecessary. That is, when MRAM or a non-volatile memory having equivalent performance is connected to the memory connection unit 120, the control unit 121 writes data used for control of the control target device to the non-volatile memory. The battery can be removed from the CPU unit 12 to form a battery-less configuration.
  • nonvolatile memory having a memory access performance equivalent to that of MRAM
  • a resistance change type memory Resistive Random Access Memory
  • FeRAM Ferroelectric Random Access Memory
  • a “non-volatile memory with a small capacity” may be mounted in addition to the volatile memory 122. That is, in step S17 of FIG. 3, control is started using both the data held in the “nonvolatile memory with a small capacity” and the data held in the attached nonvolatile memory as parameters or device values. May be.
  • FIG. 4 is a flowchart showing an operation example of the CPU unit 12 according to the first embodiment. Specifically, when both the volatile memory and the nonvolatile memory are mounted on the CPU unit 12, that is, FIG. The example of operation
  • the control unit 121 uses the data held in the non-volatile memory when starting the sequence control, and after starting the sequence control. Stores data in volatile memory. The data stored in the volatile memory is updated each time the control unit 121 controls the control target device.
  • the operation shown in FIG. 4 is executed for the purpose of updating the data in the non-volatile memory used at the start of sequence control to the latest state and using the latest data at the start of sequence control. It is an operation to do.
  • the control unit 121 of the CPU unit 12 executes the operation shown in FIG. 3 to determine that both the volatile memory and the nonvolatile memory are connected, and starts the control operation, that is, the sequence control. It is confirmed whether or not it is the update timing of the data held in (step S21).
  • the control unit 121 determines whether or not it is a data update timing by analyzing the sequence program. That is, the control unit 121 checks whether or not a command for instructing the update of data in the nonvolatile memory is described in the sequence program being executed, and updates the data if a data update command is detected. Judgment is timing.
  • step S21 When it is determined that the update timing of the data in the nonvolatile memory is reached (step S21: Yes), the control unit 121 updates the data in the nonvolatile memory (step S24). Specifically, the control unit 121 reads data held in the volatile memory and writes the read data to the nonvolatile memory. Similarly, in the subsequent update of data in the nonvolatile memory, the control unit 121 reads the data held in the volatile memory and writes the read data to the nonvolatile memory. After performing the process of step S24, it returns to step S21 and continues the process. In addition, when an instruction is given to update the data in the nonvolatile memory before or after the start of sequence control, the data is updated according to the instruction.
  • step S21 determines that it is not the update timing of the data in the nonvolatile memory (step S21: No), whether or not the control operation has been stopped, that is, the operator uses a switch or the like. It is confirmed whether or not an operation for stopping the sequence control has been performed (step S22).
  • the control unit 121 confirms whether or not the corresponding operation has been performed by analyzing the input signal received from the input unit 13.
  • step S22: Yes the control unit 121 updates the data in the nonvolatile memory (step S25) and stops the control operation (step S26).
  • step S25 and S26 process performs step S25 and S26 process. That is, the control unit 121 updates data in the nonvolatile memory and performs an emergency stop of the control operation.
  • the control unit 121 determines whether or not a control operation start operation has been performed, that is, whether the operator has performed an operation to start sequence control using a switch or the like. It is confirmed whether or not (step S27).
  • step S27 the control unit 121 starts the sequence control and returns to step S21 to continue the process.
  • the control unit 121 may start the sequence control after confirming the connection state of the memory by executing the operation shown in FIG.
  • step S27: No the control unit 121 determines whether or not the power shut-off operation has been performed, that is, the operator uses a switch or the like from the power supply unit 11 to perform another operation. It is confirmed whether or not an operation for stopping power supply to the unit has been performed (step S28).
  • step S28: No the control unit 121 returns to step S27 and continues the process.
  • step S28: Yes the control unit 121 shuts off the power and ends the process (step S30).
  • step S22 the control unit 121 confirms whether or not the power shut-off operation is performed (step S23).
  • step S23 the control unit 121 returns to step S21 and continues the process.
  • step S29 the control unit 121 updates the data in the nonvolatile memory (step S29), shuts off the power, and ends the process (step S30).
  • the control unit 121 when it is time to update data in the nonvolatile memory, when an operation to instruct the stop of the control operation is performed, When an operation for shutting off the power is performed, the data in the nonvolatile memory is updated.
  • both the volatile memory and the nonvolatile memory can hold the latest data, and the control unit 121 starts the control operation using the latest data held in the nonvolatile memory. can do. Therefore, a battery for backing up data held in the volatile memory becomes unnecessary.
  • the control unit 121 of the CPU unit 12 includes the connection determination unit 124 that determines whether or not the nonvolatile memory is connected, and when the nonvolatile memory is connected. Decided to use the data held in the non-volatile memory to perform the control operation.
  • the control unit 121 uses the data held in the nonvolatile memory at the start of the control operation, and after starting the control operation, The data in the nonvolatile memory is updated so that the data held in the nonvolatile memory is the same as the data held in the nonvolatile memory.
  • the control unit 121 updates the data in the nonvolatile memory even when the control operation is stopped and the power is shut off.
  • control unit 121 can perform sequence control using the latest data stored in the non-volatile memory, and even if a volatile memory is provided, it is not necessary to mount a data backup battery. Therefore, it is possible to realize a PLC having a configuration in which the battery for data backup is reduced.
  • the type of memory to be used can be changed in accordance with memory cost fluctuations.
  • the cost of using a non-volatile memory with high-speed memory access at a certain point in time is higher than the cost of using a volatile memory and a data backup battery. Even if it is large, it is conceivable that the costs of both are reversed over time.
  • the CPU unit 12 is realized by combining the volatile memory and the battery, and then the volatile memory and the battery are replaced with the nonvolatile memory when the price of the nonvolatile memory is reduced. Is possible.
  • the PLC 1 having the configuration in which the CPU unit 12 includes the memory connection unit 120 and the connection determination unit 124 has been described. However, one or both of the memory connection unit 120 and the connection determination unit 124 are used. It may be provided outside the CPU unit 12.
  • the “outside of the CPU unit” corresponds to a unit other than the CPU unit 12 and the base unit 10 constituting the PLC 1.
  • Embodiment 2 the configuration in which the control unit 121 of the CPU unit 12 has the connection determination unit 124 in advance has been described, but the CPU unit 12 is not limited to this configuration. In a state before the nonvolatile memory is connected to the memory connection unit 120, the control unit 121 may not have the connection determination unit 124.
  • the control unit 121 is realized by a processor executing a PLC sequence program. Therefore, in the initial state, when it becomes necessary to connect the non-volatile memory to the memory connection unit 120 by causing the processor to execute a sequence program that does not include a program for operating as the connection determination unit 124.
  • the sequence program may be updated. That is, when a non-volatile memory is connected to the memory connection unit 120 to realize the battery-less CPU unit 12, a sequence program executed by a processor (not shown) of the CPU unit 12 operates as the connection determination unit 124.
  • the program may be rewritten to a sequence program including the above program.
  • the sequence program for realizing the control unit 121 is rewritten at a necessary timing, that is, at a timing for realizing a battery-less connection by connecting a non-volatile memory to the memory connection unit 120, and a control having the connection determination unit 124
  • the unit 121 may be realized.
  • FIG. 5 is a diagram illustrating a configuration example of a CPU unit according to the third embodiment.
  • the CPU unit 12 described in the first and second embodiments has a memory connection unit 120 and is configured to be battery-less by mounting a nonvolatile memory in the CPU unit 12.
  • the CPU unit 12a according to the present embodiment has a configuration in which a memory module in which a nonvolatile memory is mounted can be connected.
  • the CPU unit 12 a includes a control unit 121, a memory 122, a battery connection unit 123, and a memory module connection unit 125.
  • the control unit 121, the memory 122, and the battery connection unit 123 are the same as the control unit 121, the memory 122, and the battery connection unit 123 of the CPU unit 12 according to the first embodiment. That is, the CPU unit 12a is obtained by replacing the memory connection unit 120 of the CPU unit 12 according to the first embodiment with the memory module connection unit 125.
  • the memory module 20 is connected to the memory module connection unit 125.
  • the memory module 20 includes a CPU unit connection unit 126 for connecting the CPU unit 12a and a memory 127 which is a nonvolatile memory.
  • the memory module connection unit 125 of the CPU unit 12 a and the CPU unit connection unit 126 of the memory module 20 electrically connect the control unit 121 mounted on the CPU unit 12 a and the memory 127 mounted on the memory module 20. It is a connector for.
  • the CPU unit 12a can realize a battery-less operation by connecting the memory module 20. Also.
  • the memory 127 which is a non-volatile memory for realizing the battery-less CPU unit 12a, can be easily attached and the workability is improved.
  • Embodiment 4 FIG.
  • the configuration in which the control unit 121 of the CPU unit 12a has the connection determination unit 124 in advance has been described.
  • the CPU unit 12a is not limited to this configuration.
  • the control unit 121 may not have the connection determination unit 124.
  • the processor executes a sequence program having a configuration that does not include a program for operating as the connection determination unit 124, and the memory module connection unit 125 includes the memory module.
  • the sequence program may be updated when it becomes necessary to connect 20.
  • a sequence program executed by a processor (not shown) of the CPU unit 12a operates as the connection determination unit 124. May be rewritten to a sequence program having a configuration including a program for performing the above.
  • the sequence program for realizing the control unit 121 is rewritten at a necessary timing, that is, at a timing for realizing a battery-less connection by connecting a non-volatile memory to the memory connection unit 120, and a control having the connection determination unit 124
  • the unit 121 may be realized.
  • the control unit 121 of the CPU units 12 and 12a determines the type of memory connected to the CPU unit 12 or 12a.
  • the constituent elements determine the type of memory connected to the control unit 121. May be provided separately.
  • a component for determining the type of memory connected to the control unit 121 may be provided in a unit other than the CPU units 12 and 12a.
  • the configuration described in the above embodiment shows an example of the contents of the present invention, and can be combined with another known technique, and can be combined with other configurations without departing from the gist of the present invention. It is also possible to omit or change the part.
  • PLC programmable logic controller
  • 10 base unit 11 power supply unit, 12, 12a CPU unit, 13 input unit, 14 output unit, 15 network unit, 20 memory module, 120 memory connection unit, 121 control unit, 122, 127 Memory, 123 battery connection unit, 124 connection determination unit, 125 memory module connection unit, 126 CPU unit connection unit.
  • PLC programmable logic controller

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PCT/JP2017/011133 2017-03-21 2017-03-21 プログラマブルロジックコントローラ、メモリモジュールおよびプログラム WO2018173105A1 (ja)

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PCT/JP2017/011133 WO2018173105A1 (ja) 2017-03-21 2017-03-21 プログラマブルロジックコントローラ、メモリモジュールおよびプログラム
CN201780032240.1A CN109313425B (zh) 2017-03-21 2017-03-21 可编程逻辑控制器
JP2017561993A JP6351882B1 (ja) 2017-03-21 2017-03-21 プログラマブルロジックコントローラおよびプログラム

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JP6735938B1 (ja) * 2019-07-01 2020-08-05 三菱電機株式会社 データ処理装置、データ処理システム、データ退避方法およびプログラム

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JPH08124668A (ja) * 1994-10-26 1996-05-17 Sanyo Electric Co Ltd 加熱装置及び加熱手順設定方法
JP2014081700A (ja) * 2012-10-15 2014-05-08 Fuji Electric Co Ltd プログラマブルコントローラ、プログラマブルコントローラのデータバックアップ方法、プログラマブルコントローラの起動方法
JP2015005062A (ja) * 2013-06-19 2015-01-08 三菱電機株式会社 製造実行システム及びプログラマブルロジックコントローラ

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CN104699413B (zh) * 2013-12-09 2019-02-22 群联电子股份有限公司 数据管理方法、存储器存储装置及存储器控制电路单元
KR102174818B1 (ko) * 2014-04-07 2020-11-06 에스케이하이닉스 주식회사 휘발성 메모리, 이를 포함하는 메모리 모듈 및 메모리 모듈의 동작 방법
CN104077246A (zh) * 2014-07-02 2014-10-01 浪潮(北京)电子信息产业有限公司 一种实现易失性存储器备份的装置

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JPH08124668A (ja) * 1994-10-26 1996-05-17 Sanyo Electric Co Ltd 加熱装置及び加熱手順設定方法
JP2014081700A (ja) * 2012-10-15 2014-05-08 Fuji Electric Co Ltd プログラマブルコントローラ、プログラマブルコントローラのデータバックアップ方法、プログラマブルコントローラの起動方法
JP2015005062A (ja) * 2013-06-19 2015-01-08 三菱電機株式会社 製造実行システム及びプログラマブルロジックコントローラ

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