WO2018153336A1 - 像素驱动电路及其驱动方法和晶体管的版图结构 - Google Patents

像素驱动电路及其驱动方法和晶体管的版图结构 Download PDF

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Publication number
WO2018153336A1
WO2018153336A1 PCT/CN2018/076788 CN2018076788W WO2018153336A1 WO 2018153336 A1 WO2018153336 A1 WO 2018153336A1 CN 2018076788 W CN2018076788 W CN 2018076788W WO 2018153336 A1 WO2018153336 A1 WO 2018153336A1
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Prior art keywords
transistor
active layer
switching transistor
driving
gate
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PCT/CN2018/076788
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English (en)
French (fr)
Inventor
张露
文国哲
韩珍珍
朱修剑
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昆山国显光电有限公司
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Priority claimed from CN201710095713.4A external-priority patent/CN108461504B/zh
Priority claimed from CN201710098993.4A external-priority patent/CN108470544B/zh
Application filed by 昆山国显光电有限公司 filed Critical 昆山国显光电有限公司
Priority to JP2019537159A priority Critical patent/JP7198206B2/ja
Priority to KR1020197019778A priority patent/KR102209416B1/ko
Priority to EP18757819.0A priority patent/EP3588480B1/en
Priority to US16/324,549 priority patent/US10692432B2/en
Publication of WO2018153336A1 publication Critical patent/WO2018153336A1/zh

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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    • H10K59/10—OLED displays
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Definitions

  • the present invention relates to the field of display technologies, and in particular, to a pixel driving circuit, a driving method thereof, and a layout structure of a transistor.
  • AMOLED Active Matrix Organic Light Emitting Diode
  • OLED Organic Light Emitting Diode
  • the brightness of a pixel is determined by the amount of current flowing through the organic light emitting diode, and the magnitude of the current is controlled by a driving thin film transistor in the pixel driving circuit.
  • the current required by each pixel will become smaller and smaller, which requires driving the thin film transistor in the pixel driving circuit.
  • the width to length ratio (W/L) of the channel is reduced.
  • the width of the channel of the driving thin film transistor is limited by the manufacturing process, and the width-to-length ratio (W/L) of the channel of the driving thin film transistor is usually reduced by increasing the channel length, thereby reducing the current of the organic light emitting diode. .
  • W/L width-to-length ratio
  • high PPI, high resolution and high refresh rate are a trend in AMOLED display products. High resolution and high refresh rate will reduce the charging time of each row of pixels, which will affect the charging rate of the gate of the pixel driving thin film transistor. In order to increase the charging rate, it is necessary to make the width of the channel of the driving thin film transistor larger than that designed.
  • the width-to-length ratio of the channel of the pixel-driven thin film transistor is difficult to meet the requirements of reducing the current of the organic light-emitting diode and increasing the charging rate of the gate of the pixel-driven thin film transistor.
  • the main purpose of the present invention is to provide a pixel driving circuit and a driving method thereof, which aim to solve the aspect ratio design of a channel of a pixel driving thin film transistor in the prior art, and it is difficult to simultaneously reduce the current of the organic light emitting diode and increase the pixel.
  • the problem of the charge rate requirement of the drive transistor gate is to provide a pixel driving circuit and a driving method thereof, which aim to solve the aspect ratio design of a channel of a pixel driving thin film transistor in the prior art, and it is difficult to simultaneously reduce the current of the organic light emitting diode and increase the pixel.
  • the main purpose of the present invention is to provide a layout structure of a transistor, which aims to solve the problem that the number of driving thin film transistors in the pixel driving circuit in the prior art is large, and the occupied area or space is large in the layout design, which affects the high pixel density. Design issues.
  • a first aspect of the embodiments of the present invention provides a pixel driving circuit, where the pixel driving circuit includes:
  • a storage capacitor having a first end connected to the first voltage source and a second end;
  • a first switching transistor having a first end connected to a second end of the storage capacitor, a second end for receiving a reference voltage, and a control end for receiving the first control signal
  • a second switching transistor having a first end for receiving a data signal input, a second end, and a control end for receiving the second control signal
  • a third switching transistor having a first end, a second end connected to the first end of the first switching transistor, and a control end for receiving the second control signal
  • a fourth switching transistor having a first end connected to the second end of the second switching transistor, a second end, and a control end connected to the second end of the storage capacitor;
  • a fifth switching transistor having a first end connected to an anode end of the organic light emitting diode, a second end for receiving a reference voltage, and a control end for receiving a third control signal
  • a sixth switching transistor having a first end connected to the first voltage source, a second end, and a control end for receiving the driving signal
  • the first driving transistor has a first end connected to the second end of the sixth switching transistor, a second end connected to the second end of the fourth switching transistor, and a control end connected to the second end of the storage capacitor;
  • a second driving transistor having a first end connected to the second end of the fourth switching transistor, a second end connected to the first end of the third switching transistor, and a control end connected to the second end of the storage capacitor;
  • a seventh switching transistor having a first end connected to the second end of the second driving transistor, a second end connected to the anode end of the organic light emitting diode, and a control end for receiving the driving signal;
  • the organic light emitting diode has an anode end connected to a second voltage source.
  • the aspect ratio W1/L1 of the first driving transistor, the aspect ratio W2/L2 of the second driving transistor, and the width to length ratio W3/L3 of the fourth switching transistor satisfy the following relationship :
  • L1/L2 1 or L1/L2>1 or L1/L2 ⁇ 1, L3 ⁇ L2; or
  • the reference voltage and the potential of the voltage provided by the second voltage source are equal.
  • the reference voltage is an independent voltage source.
  • the first to seventh switching transistors, and the first and second driving transistors all have the same channel type.
  • a second aspect of the embodiments of the present invention provides a driving method of a pixel driving circuit, where the driving method includes:
  • control end of the first switching transistor receives the first control signal and is turned on, and initializes the control ends of the fourth switching transistor, the first driving transistor, and the second driving transistor to be reference voltages;
  • control ends of the second switching transistor and the third switching transistor receive the second control signal and are turned on, and the data signal V data input by the data signal is supplied to the second end of the storage capacitor;
  • control end of the fifth switching transistor receives the third control signal and is turned on, and the anode end of the organic light emitting diode is reversely initialized to a reference voltage;
  • control terminals of the sixth switching transistor and the seventh switching transistor receive a driving signal and are turned on, and the organic light emitting diode starts to emit light.
  • the voltages of the control terminals of the fourth switching transistor, the first driving transistor, and the second driving transistor reach V data -
  • a third aspect of the embodiments of the present invention provides an array substrate including the above pixel driving circuit.
  • a fourth aspect of the embodiments of the present invention provides a display device including the above array substrate.
  • a fifth aspect of the embodiments of the present invention provides a layout structure of a transistor, the layout structure including a circuit node and an active layer connected to the circuit node; the active layer includes a first active layer, and a second active a layer and a third active layer;
  • a first source connected to the first active layer, a drain connected to the second active layer, and a second source connected to the third active layer;
  • a gate pattern composed of a third gate is located above the circuit node and the active layer.
  • the first active layer and the third active layer constitute an inverted "U” type structure; and the second active layer constitutes an inverted "L” type structure.
  • the first active layer and the second active layer constitute The type of structure; the third active layer constitutes an inverted "L" type structure.
  • the first active layer and the second active layer constitute an "n" type structure; and the third active layer constitutes an inverted “L” type structure.
  • the gate patterns composed of the first gate, the second gate, and the third gate are square or polygonal.
  • the pixel driving circuit and the driving method thereof are provided by the first driving transistor and the second driving transistor connected in series; when the pixel is charged, the pixel driving circuit can compensate the second driving transistor and the series connected in series
  • the threshold voltage of the four-switching transistor can simultaneously satisfy the requirement of reducing the current of the organic light emitting diode and increasing the charging rate of the gate of the pixel driving transistor.
  • the gates of the three transistors form the same pattern, and the circuit nodes formed by the drains of the two transistors and the sources of the third transistor are located under the gate pattern.
  • This design can reduce the layout area of the three transistors, reduce the difficulty of layout design, and improve the application range.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present invention.
  • FIG. 2 is a schematic flow chart of a driving method of a pixel driving circuit according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram showing a signal timing state of a pixel driving circuit according to an embodiment of the present invention.
  • FIG. 4 to FIG. 7 are schematic diagrams showing a current flow structure of a pixel driving circuit according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram showing a layout structure of a transistor according to an embodiment of the present invention.
  • FIG. 9 is another schematic diagram of a layout structure of a transistor according to an embodiment of the present invention.
  • FIG. 10 is still another schematic diagram of a layout structure of a transistor according to an embodiment of the present invention.
  • the switching transistor and the driving transistor used in all the embodiments of the present invention may be a thin film transistor or a field effect transistor or other devices having the same characteristics. Since the source and the drain of the switching transistor used herein are symmetrical, the source thereof, The drains are interchangeable. In the embodiment of the present invention, in order to distinguish the two poles of the transistor except the gate, one of the poles is referred to as a source and the other pole is referred to as a drain. According to the form in the drawing, the control terminal of the transistor is a gate, the first terminal is a source, and the second terminal is a drain.
  • the switching transistor used in the embodiment of the present invention includes two types of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low level, and is turned off when the gate is at a high level, and the N-type switching transistor is turned off. It is turned on when the gate is high and turned off when the gate is low.
  • the switching transistor and the driving transistor of the pixel driving circuit in the drawing are all P-channel transistors, and those skilled in the art can easily find that the pixel driving circuit provided by the present invention can be easily changed into an N-channel.
  • an embodiment of the present invention provides a pixel driving circuit, where the pixel driving circuit includes:
  • a storage capacitor Cst having a first end connected to the first voltage source ELVDD and a second end;
  • the first switching transistor T1 has a first end connected to the second end of the storage capacitor Cst, the second end is for receiving the reference voltage Vref, and the control end is for receiving the first control signal S1;
  • the second switching transistor T2 has a first end for receiving a data signal input data signal V data , a second end, and a control end for receiving the second control signal S2;
  • the third switching transistor T3 has a first end, the second end is connected to the first end of the first switching transistor T1, and the control end is used to receive the second control signal S2;
  • the fourth switching transistor T4 has a first end connected to the second end of the second switching transistor T2, a second end, and a control end connected to the second end of the storage capacitor Cst;
  • the fifth switching transistor T5 has a first end connected to the anode end of the organic light emitting diode L1, a second end for receiving the reference voltage Vref, and a control end for receiving the third control signal S3;
  • the sixth switching transistor T6 has a first end connected to the first voltage source ELVDD, a second end, and a control end for receiving the driving signal EM;
  • the first driving transistor D1 has a first end connected to the second end of the sixth switching transistor T6, a second end connected to the second end of the fourth switching transistor T4, and a control end connected to the second end of the storage capacitor Cst;
  • the second driving transistor D2 has a first end connected to the second end of the fourth switching transistor T4, a second end connected to the first end of the third switching transistor T3, and a control end connected to the second end of the storage capacitor Cst;
  • the seventh switching transistor T7 has a first end connected to the second end of the second driving transistor D2, a second end connected to the anode end of the organic light emitting diode L1, and a control end for receiving the driving signal EM;
  • the organic light emitting diode L1 has an anode terminal connected to a second voltage source ELVSS.
  • the aspect ratio W1/L1 of the first driving transistor D1, the width-to-length ratio W2/L2 of the second driving transistor D2, and the width-to-length ratio W3/L3 of the fourth switching transistor T4 satisfy the following relationship:
  • L1/L2 1 or L1/L2>1 or L1/L2 ⁇ 1, L3 ⁇ L2; or
  • the design of the aspect ratio W1/L1 of the first driving transistor D1, the aspect ratio W2/L2 of the second driving transistor D2, and the width to length ratio W3/L3 of the fourth switching transistor T4 are not limited thereto.
  • the D1, D2, and T4 aspect ratio designs designed by the pixel driving circuit according to the embodiment of the present invention are all within the scope of this patent.
  • the first to seventh switching transistors T1 to T7, and the first and second driving transistors D1 and D2 all have the same channel type.
  • the reference voltage Vref and the potential of the voltage provided by the second voltage source ELVSS are equal.
  • the reference voltage Vref can be an independent voltage source.
  • the pixel driving circuit drives the organic light emitting diode through the first driving transistor and the second driving transistor connected in series; when the pixel is charged, the pixel driving circuit can compensate the second driving transistor and the fourth switching transistor connected in series Threshold voltage; can simultaneously meet the requirements of reducing the current of the organic light emitting diode and increasing the charging rate of the gate of the pixel driving transistor.
  • an embodiment of the present invention further provides a driving method of a pixel driving circuit, where the driving method includes:
  • the control terminal of the first switching transistor T1 receives the first control signal S1 and is turned on, and initializes the control terminals of the fourth switching transistor T4, the first driving transistor D1 and the second driving transistor D2 as a reference voltage Vref;
  • control ends of the second switching transistor T2 and the third switching transistor T3 receive the second control signal S2 and are turned on, and the data signal V data input by the data signal is supplied to the second end of the storage capacitor Cst;
  • the voltages of the control terminals of the fourth switching transistor T4, the first driving transistor D1, and the second driving transistor D2 may reach V data -
  • control terminal of the fifth switching transistor T5 receives the third control signal S3 and is turned on, and the anode end of the organic light emitting diode L1 is reversely initialized to the reference voltage Vref;
  • control terminals of the sixth switching transistor T6 and the seventh switching transistor T7 receive the driving signal and are turned on, and the organic light emitting diode L1 starts to emit light.
  • the first control signal S1 is at a low level
  • the second control signal S2, the third control signal S3, and the driving signal EM are at a high level; at this time, the control end of the first switching transistor T1 receives the first control signal.
  • the low level of S1 is turned on, and the control terminals of the fourth switching transistor T4, the first driving transistor D1, and the second driving transistor D2 are initialized to be the reference voltage Vref.
  • the current flow direction can be shown by the dotted line in FIG.
  • the second control signal S2 is at a low level, and the first control signal S1, the third control signal S3, and the driving signal EM are at a high level; at this time, the control of the second switching transistor T2 and the third switching transistor T3
  • the terminal receives the low level of the second control signal S2 and is turned on, and the data signal V data input by the data signal is supplied to the second end of the storage capacitor Cst.
  • the current flow direction can be shown by the dotted line in FIG.
  • the second driving transistor D2 and the fourth switching transistor T4 can be regarded as a transistor having a width-to-length ratio of W/(L2+L3).
  • the P-point voltage can be Faster is written as V data -
  • the third control signal S3 is at a low level, and the first control signal S1, the second control signal S2, and the driving signal EM are at a high level; at this time, the control terminal of the fifth switching transistor T5 receives the third control signal.
  • the low level of S3 is turned on, and the anode end of the organic light emitting diode L1 is reversely initialized to the reference voltage Vref.
  • the current flow direction can be shown by the dotted line in FIG.
  • the driving signal EM is at a low level, and the first control signal S1, the second control signal S2, and the third control signal S3 are at a high level; at this time, the control of the sixth switching transistor T6 and the seventh switching transistor T7
  • the terminal receives the low level of the driving signal and conducts, and the organic light emitting diode L1 starts to emit light.
  • the current flow direction can be shown by the dotted line in FIG.
  • the driving method of the pixel driving circuit drives the organic light emitting diode through the first driving transistor and the second driving transistor connected in series; when the pixel is charged, the pixel driving circuit can compensate the second driving transistor and the fourth connected in series
  • the threshold voltage of the switching transistor can simultaneously satisfy the requirement of reducing the current of the organic light emitting diode and increasing the charging rate of the gate of the pixel driving transistor.
  • An embodiment of the present invention further provides an array substrate, including:
  • control signal lines and driving signal lines arranged along the row;
  • the pixel includes the pixel driving circuit described above.
  • the array substrate provided by the embodiment of the invention drives the organic light emitting diode through the first driving transistor and the second driving transistor connected in series; when the pixel is charged, the pixel driving circuit can compensate the thresholds of the second driving transistor and the fourth switching transistor connected in series
  • the voltage can meet the requirements of reducing the current of the organic light emitting diode and increasing the charging rate of the gate of the pixel driving transistor.
  • the embodiment of the invention further provides a display device comprising: the above array substrate.
  • the display device can also be a display device such as an electronic paper, a mobile phone, a television, or a digital photo frame.
  • the display device drives the organic light emitting diode through the first driving transistor and the second driving transistor connected in series; when the pixel is charged, the pixel driving circuit can compensate the thresholds of the second driving transistor and the fourth switching transistor connected in series
  • the voltage can meet the requirements of reducing the current of the organic light emitting diode and increasing the charging rate of the gate of the pixel driving transistor.
  • an embodiment of the present invention further provides a layout structure of a transistor, the layout structure including a circuit node 10 and an active layer connected to the circuit node 10.
  • the active layer includes a first active layer 21, a second active layer 22, and a third active layer 23.
  • the first active layer 21 and the third active layer 23 form an inverted “U”-type structure; the second active layer 22 forms an inverted “L”-type structure. .
  • the first active layer 21 and the second active layer 22 are configured.
  • the type structure; the third active layer 23 constitutes an inverted "L" type structure.
  • the first active layer 21 and the second active layer 22 constitute an "n"-type structure; and the third active layer 23 constitutes an inverted "L"-type structure. .
  • the second active layer 22 is connected to a drain 32, and the third active layer 23 is connected to a second source 33.
  • the layout structure further includes first, second, and third gates corresponding to the first active layer 21, the second active layer 22, and the third active layer 23, respectively; the first gate, the first A gate pattern 40 composed of a second gate and a third gate is located above the circuit node 10 and the active layer.
  • the gate pattern 40 has a substantially square shape, such as a square or a rectangle; the gate pattern may also be a polygon, that is, four or more line segments are connected end to end. Flat graphics.
  • the active layer covered by the gate pattern 40 is a channel region, and the active layer 211 (the dotted frame in the figure) of the first active layer 21 covered by the gate pattern 40 is the first.
  • the active layer 221 (the dotted line frame in the figure) in which the second active layer 22 is covered by the gate pattern 40 is the second channel, and the active layer 231 in which the third active layer 23 is covered by the gate pattern 40 ( The dashed box in the figure is the third channel.
  • the first source 31, the first active layer 21 and the circuit node 10 can form a current flowing channel; the second source 33, the third active layer 23 and the circuit node 10 can form a current flowing channel; 10.
  • the second active layer 22 and the drain 32 form a current flowing channel. Therefore, the layout structure is equivalent to a layout composed of three transistors, that is, a circuit node in which the drains of the two transistors and the sources of the third transistor are connected together, and the gates of the three transistors are connected together.
  • the layout structure of the transistor provided by the embodiment of the present invention is applicable not only to the transistor of the bottom gate structure but also to the transistor of the top gate structure.
  • the manufacturing process of the top gate structure and the bottom gate structure of the transistor are different.
  • the manufacturing process of the top gate structure is as follows:
  • S1 buffer layer, active layer deposition, and active layer patterning
  • S3 transistor source and drain P+ doping.
  • the manufacturing process of the bottom gate structure is as follows:
  • the gate barrier layer is peeled off.
  • the layout structure of the transistor is equivalent to the same pattern of the gates of the three transistors, and the circuit nodes formed by the drains of the two transistors and the source of the third transistor are located. Under the gate pattern, this design can reduce the layout area of the three transistors, reduce the difficulty of layout design, and improve the application range.
  • the embodiment of the present invention further provides a pixel driving circuit, the pixel driving circuit includes a first driving transistor, a second driving transistor, and a switching transistor.
  • the layout structure of the first driving transistor, the second driving transistor, and the switching transistor is The above layout structure.
  • the aspect ratio W1/L1 of the first driving transistor, the aspect ratio W2/L2 of the second driving transistor, and the width to length ratio W3/L3 of the switching transistor satisfy the following relationship:
  • L1/L2 1 or L1/L2>1 or L1/L2 ⁇ 1, L3 ⁇ L2; or
  • the aspect ratio W1/L1 of the first driving transistor, the width to length ratio W2/L2 of the second driving transistor, and the width to length ratio of the switching transistor W3/L3 are not limited to the cases listed above.
  • the aspect ratio design of the pixel driving circuit according to the embodiment of the present invention should be within the scope of the patent protection.
  • the pixel driving circuit of FIG. 1 includes a first driving transistor D1, a second driving transistor D2, and a fourth switching transistor T4 (shown by a broken line in the figure).
  • a second end (drain) of the first driving transistor D1, a second end (drain) of the fourth switching transistor T4, and a first end (source) of the second driving transistor D2 are connected together to form a circuit node;
  • the gate of the driving transistor D1, the gate of the second driving transistor D2, and the gate of the fourth switching transistor T4 are connected together, and the layout structure thereof is as described above.
  • the gates of the three transistors form the same pattern, and the circuit nodes formed by connecting the drains of the two transistors and the sources of the third transistor are located under the gate pattern.
  • This design can reduce the layout area of the three transistors, reduce the difficulty of layout design, and improve the application range.
  • the invention further provides an array substrate comprising:
  • control signal lines and driving signal lines arranged along the row;
  • the pixel includes the pixel driving circuit described above.
  • the gates of the three transistors form the same pattern, and the circuit nodes formed by the drains of the two transistors and the sources of the third transistor are located under the gate pattern.
  • the design can reduce the layout area of the three transistors, reduce the difficulty of layout design, and improve the application range.
  • the present invention further provides a display device comprising: the above array substrate.
  • the display device can also be a display device such as an electronic paper, a mobile phone, a television, a digital photo frame, or the like.
  • the gates of the three transistors form the same pattern, and the circuit nodes formed by the drains of the two transistors and the sources of the third transistor are located under the gate pattern.
  • the design can reduce the layout area of the three transistors, reduce the difficulty of layout design, and improve the application range.
  • the pixel driving circuit and the driving method thereof are provided by the first driving transistor and the second driving transistor connected in series; when the pixel is charged, the pixel driving circuit can compensate the second driving transistor and the series connected in series
  • the threshold voltage of the four-switching transistor can simultaneously satisfy the requirement of reducing the current of the organic light emitting diode and increasing the charging rate of the gate of the pixel driving transistor.
  • the gates of the three transistors form the same pattern, and the circuit nodes formed by the drains of the two transistors and the sources of the third transistor are located under the gate pattern.
  • This design can reduce the layout area of the three transistors, reduce the difficulty of layout design, and improve the application range.

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Abstract

一种像素驱动电路及其驱动方法和晶体管的版图结构。像素驱动电路包括储存电容（Cst）、第一开关晶体管（T1）、第二开关晶体管（T2）、第三开关晶体管（T3）、第四开关晶体管（T4）、第五开关晶体管（T5）、第六开关晶体管（T6）、第七开关晶体管（T7）、第一驱动晶体管（D1）、第二驱动晶体管（D2）和有机发光二极管（L1）。晶体管的版图结构包括电路节点（10）以及与电路节点连接的有源层；有源层包括第一有源层（21）、第二有源层（22）以及第三有源层（23）；与第一有源层（21）相连的第一源极（31），与第二有源层（22）相连的漏极（32），与第三有源层（23）相连的第二源极（33）；分别与第一有源层（21）、第二有源层（22）和第三有源层（23）对应的第一栅极、第二栅极和第三栅极；第一栅极、第二栅极以及第三栅极组成的栅极图案（40）位于电路节点（10）和有源层的上方。

Description

像素驱动电路及其驱动方法和晶体管的版图结构 技术领域
本发明涉及显示技术领域，尤其涉及一种像素驱动电路及其驱动方法和晶体管的版图结构。
背景技术
有源矩阵有机发光二极管(Active Matrix Organic Light Emitting Diode，AMOLED)显示器是当前显示器研究领域的热点之一。与液晶显示器相比，有机发光二极管(Organic Light Emitting Diode，OLED)具有低能耗、生产成本低、自发光、宽视角及响应速度快等优点。
对于AMOLED显示产品，像素的亮暗程度由流经有机发光二极管的电流大小决定，而电流大小受像素驱动电路中的驱动薄膜晶体管控制。在显示屏亮度相同的情况下，随着显示屏像素密度(Pixels Per Inch，PPI)的增大，每个像素所需要的电流会越来越小，这就要求像素驱动电路中驱动薄膜晶体管的沟道的宽长比(W/L)缩小。驱动薄膜晶体管的沟道的宽度受到制造工艺的限制，设计时通常是通过增加沟道长度来实现驱动薄膜晶体管的沟道的宽长比(W/L)的缩小，从而降低有机发光二极管的电流。然而，高PPI、高分辨率和高刷新率是AMOLED显示产品的一个发展趋势，高分辨率和高刷新率会降低每一行像素的充电时间，从而会影响像素驱动薄膜晶体管栅极的充电率，为了提高充电率需要将驱动薄膜晶体管的沟道的宽长比设计的更大。
技术问题
随着AMOLED显示技术的发展，像素驱动薄膜晶体管的沟道的宽长比设计，很难同时满足降低有机发光二极管的电流和提高像素驱动薄膜晶体管栅极的充电率的要求。
另外，对于AMOLED显示产品，像素驱动电路中的驱动薄膜晶体管数量多，在版图设计中占用面积或空间比较大，影响高像素密度(Pixels Per Inch，PPI)的产品设计。
技术解决方案
本发明的主要目的在于提出一种像素驱动电路及其驱动方法，旨在解决现有技术中像素驱动薄膜晶体管的沟道的宽长比设计，很难同时满足降低有机发光二极管的电流和提高像素驱动晶体管栅极的充电率要求的问题。
本发明的主要目的还在于提出一种晶体管的版图结构，旨在解决现有技术中像素驱动电路中的驱动薄膜晶体管数量多，在版图设计中占用面积或空间比较大，影响高像素密度的产品设计的问题。
本发明实施例第一方面提供一种像素驱动电路，所述像素驱动电路包括：
储存电容，具有第一端连接第一电压源，以及第二端；
第一开关晶体管，具有第一端连接于储存电容的第二端，第二端用来接收参考电压，以及控制端用来接收第一控制信号；
第二开关晶体管，具有第一端用于接收数据信号输入，第二端，以及控制端用来接收第二控制信号；
第三开关晶体管，具有第一端，第二端连接于第一开关晶体管的第一端，以及控制端用来接收第二控制信号；
第四开关晶体管，具有第一端连接于第二开关晶体管的第二端，第二端，以及控制端连接于储存电容的第二端；
第五开关晶体管，具有第一端连接于有机发光二极管的阳极端，第二端用来接收参考电压，以及控制端用来接收第三控制信号；
第六开关晶体管，具有第一端连接第一电压源，第二端，以及控制端用来接收驱动信号；
第一驱动晶体管，具有第一端连接于第六开关晶体管的第二端，第二端连接于第四开关晶体管的第二端，以及控制端连接于储存电容的第二端；
第二驱动晶体管，具有第一端连接于第四开关晶体管的第二端，第二端连接于第三开关晶体管的第一端，以及控制端连接于储存电容的第二端；
第七开关晶体管，具有第一端连接于第二驱动晶体管的第二端，第二端连接于有机发光二极管的阳极端，以及控制端用来接收驱动信号；
有机发光二极管，具有阳极端，阴极端连接于一第二电压源。
在一实施例中，所述第一驱动晶体管的宽长比W1/L1、所述第二驱动晶体管的宽长比W2/L2、所述第四开关晶体管的宽长比W3/L3满足以下关系：
W1＝W2＝W3，L1/L2＝1，L3<L2；或
W1＝W2＝W3，L1/L2>1，L3<L2；或
W1＝W2＝W3，L1/L2<1，L3<L2；或
W1＝W2<W3，L1/L2＝1或L1/L2>1或L1/L2<1，L3<L2；或
W1＝W2>W3，L1/L2＝1或L1/L2>1或L1/L2<1，L3<L2。
在一实施例中，所述参考电压以及所述第二电压源所提供的电压的电位相等。
在一实施例中，所述参考电压为一独立电压源。
在一实施例中，所述第一开关晶体管至第七开关晶体管、以及第一驱动晶体管、第二驱动晶体管全部具有相同的沟道类型。
本发明实施例第二方面提供一种像素驱动电路的驱动方法，所述驱动方法包括：
第一阶段，第一开关晶体管的控制端接收第一控制信号并导通，初始化第四开关晶体管、第一驱动晶体管和第二驱动晶体管的控制端为参考电压；
第二阶段，第二开关晶体管和第三开关晶体管的控制端接收第二控制信号并导通，数据信号输入的数据信号V data提供至储存电容的第二端；
第三阶段，第五开关晶体管的控制端接收第三控制信号并导通，有机发光二极管的阳极端被反向初始化为参考电压；
第四阶段，第六开关晶体管和第七开关晶体管的控制端接收驱动信号并导通，所述有机发光二极管开始发光。
在一实施例中，在所述第二阶段，所述第四开关晶体管、所述第一驱动晶体管和所述第二驱动晶体管的控制端的电压达到V data-|V th2|，其中V th2为第二驱动晶体管的阈值电压。
在一实施例中，在所述第四阶段，流经所述有机发光二极管的电流为：I＝1/2×U×C ox×[W/(L1+L2)]×(V data-VDD) 2，其中，U为所述第一驱动晶体管和所述第二驱动晶体管的迁移率，C ox为所述第一驱动晶体管和所述第二驱动晶体管的栅极绝缘层单位面积的电容。
本发明实施例第三方面提供一种阵列基板，包括上述的像素驱动电路。
本发明实施例第四方面提供一种显示装置，包括上述的阵列基板。
本发明实施例第五方面提供一种晶体管的版图结构，所述版图结构包括电路 节点以及与所述电路节点连接的有源层；所述有源层包括第一有源层、第二有源层以及第三有源层；
与所述第一有源层相连的第一源极，与所述第二有源层相连的漏极，与所述第三有源层相连的第二源极；
分别与所述第一有源层、第二有源层和第三有源层对应的第一栅极、第二栅极和第三栅极；所述第一栅极、第二栅极以及第三栅极组成的栅极图案位于所述电路节点和所述有源层的上方。
在一实施例中，所述第一有源层和第三有源层构成倒“U”型结构；所述第二有源层构成倒“L”型结构。
在一实施例中，所述第一有源层和第二有源层构成
Figure PCTCN2018076788-appb-000001
型结构；所述第三有源层构成倒“L”型结构。
在一实施例中，所述第一有源层和第二有源层构成“n”型结构；所述第三有源层构成倒“L”型结构。
在一实施例中，所述第一栅极、第二栅极以及第三栅极组成的栅极图案为方形状或者多边形。
有益效果
本发明实施例提供的像素驱动电路及其驱动方法，通过串联连接的第一驱动晶体管和第二驱动晶体管驱动有机发光二极管；像素充电时，像素驱动电路可补偿串联连接的第二驱动晶体管和第四开关晶体管的阈值电压；可同时满足降低有机发光二极管的电流和提高像素驱动晶体管栅极的充电率的要求。
本发明实施例提供的晶体管的版图结构，三个晶体管的栅极组成同一个图形，两个晶体管的漏极和第三个晶体管的源极连接在一起形成的电路节点位于栅极图形之下，通过这种设计可以缩小三个晶体管的版图面积，降低版图设计难度，提高应用范围。
附图说明
图1为本发明实施例的像素驱动电路的结构示意图；
图2为本发明实施例的像素驱动电路的驱动方法流程示意图；
图3为本发明实施例的像素驱动电路的信号时序状态示意图；
图4至图7为本发明实施例的像素驱动电路的电流流向结构示意图；
图8为本发明实施例的晶体管的版图结构其中一示意图；
图9为本发明实施例的晶体管的版图结构另一示意图；
图10为本发明实施例的晶体管的版图结构又一示意图。
本发明的实施方式
为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效，以下结合附图及较佳实施例，对本发明的具体实施方式、结构、特征及其功效，详细说明如后。
现在将参考附图描述实现本发明的各个实施例，在后续的描述中，使用用于表示元件的诸如“模块”、“部件”或“单元”的后缀仅为了有利于本发明的说明，其本身并没有特定的意义。
本发明所有实施例中采用的开关晶体管和驱动晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件，由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本发明实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定晶体管的控制端为栅极、第一端为源极、第二端为漏极。此外本发明实施例所采用的开关晶体管包括P型开关晶体管和N型开关晶体管两种，其中，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型开关晶体管为在栅极为高电平时导通，在栅极为低电平时截止。
需要说明的是，附图中像素驱动电路的开关晶体管和驱动晶体管全部为P沟道型晶体管，本领域所属技术人员很容易得出本发明所提供的像素驱动电路可以轻易改成全为N沟道型晶体管的像素驱动电路。
如图1所示，本发明实施例提出一种像素驱动电路，该像素驱动电路包括：
储存电容Cst，具有第一端连接第一电压源ELVDD，以及第二端；
第一开关晶体管T1，具有第一端连接于储存电容Cst的第二端，第二端用来接收参考电压Vref，以及控制端用来接收第一控制信号S1；
第二开关晶体管T2，具有第一端用于接收数据信号输入的数据信号V data，第二端，以及控制端用来接收第二控制信号S2；
第三开关晶体管T3，具有第一端，第二端连接于第一开关晶体管T1的第一 端，以及控制端用来接收第二控制信号S2；
第四开关晶体管T4，具有第一端连接于第二开关晶体管T2的第二端，第二端，以及控制端连接于储存电容Cst的第二端；
第五开关晶体管T5，具有第一端连接于有机发光二极管L1的阳极端，第二端用来接收参考电压Vref，以及控制端用来接收第三控制信号S3；
第六开关晶体管T6，具有第一端连接第一电压源ELVDD，第二端，以及控制端用来接收驱动信号EM；
第一驱动晶体管D1，具有第一端连接于第六开关晶体管T6的第二端，第二端连接于第四开关晶体管T4的第二端，以及控制端连接于储存电容Cst的第二端；
第二驱动晶体管D2，具有第一端连接于第四开关晶体管T4的第二端，第二端连接于第三开关晶体管T3的第一端，以及控制端连接于储存电容Cst的第二端；
第七开关晶体管T7，具有第一端连接于第二驱动晶体管D2的第二端，第二端连接于有机发光二极管L1的阳极端，以及控制端用来接收驱动信号EM；
有机发光二极管L1，具有阳极端，阴极端连接于一第二电压源ELVSS。
在本实施例中，第一驱动晶体管D1的宽长比W1/L1、第二驱动晶体管D2的宽长比W2/L2、第四开关晶体管T4的宽长比W3/L3满足以下关系：
W1＝W2＝W3，L1/L2＝1，L3<L2；或
W1＝W2＝W3，L1/L2>1，L3<L2；或
W1＝W2＝W3，L1/L2<1，L3<L2；或
W1＝W2<W3，L1/L2＝1或L1/L2>1或L1/L2<1，L3<L2；或
W1＝W2>W3，L1/L2＝1或L1/L2>1或L1/L2<1，L3<L2。
需要说明的是，第一驱动晶体管D1的宽长比W1/L1、第二驱动晶体管D2的宽长比W2/L2、第四开关晶体管T4的宽长比W3/L3的设计，并不限定于上面所列出的情形，按照本发明实施例的像素驱动电路所设计的D1、D2、T4宽长比设计都应在本专利保护范围内。
在本实施例中，第一开关晶体管T1至第七开关晶体管T7、以及第一驱动晶体管D1、第二驱动晶体管D2全部具有相同的沟道类型。
在一种可能的实施方式中，参考电压Vref以及第二电压源ELVSS所提供的 电压的电位相等。
在另一种可能的实施方式中，参考电压Vref可为一独立电压源。
本发明实施例提供的像素驱动电路，通过串联连接的第一驱动晶体管和第二驱动晶体管驱动有机发光二极管；像素充电时，像素驱动电路可补偿串联连接的第二驱动晶体管和第四开关晶体管的阈值电压；可同时满足降低有机发光二极管的电流和提高像素驱动晶体管栅极的充电率的要求。
如图2所示，本发明实施例进一步提供一种像素驱动电路的驱动方法，该驱动方法包括：
第一阶段，第一开关晶体管T1的控制端接收第一控制信号S1并导通，初始化第四开关晶体管T4、第一驱动晶体管D1和第二驱动晶体管D2的控制端为参考电压Vref；
第二阶段，第二开关晶体管T2和第三开关晶体管T3的控制端接收第二控制信号S2并导通，数据信号输入的数据信号V data提供至储存电容Cst的第二端；
在本实施例中，第四开关晶体管T4、第一驱动晶体管D1和第二驱动晶体管D2的控制端的电压可达到V data-|V th2|，其中V th2为第二驱动晶体管D2的阈值电压。
第三阶段，第五开关晶体管T5的控制端接收第三控制信号S3并导通，有机发光二极管L1的阳极端被反向初始化为参考电压Vref；
第四阶段，第六开关晶体管T6和第七开关晶体管T7的控制端接收驱动信号并导通，有机发光二极管L1开始发光。
在本实施例中，流经有机发光二极管的电流为：I＝1/2×U×C ox×[W/(L1+L2)]×(V data-VDD) 2，其中，U为第一驱动晶体管D1和第二驱动晶体管D2的迁移率，C ox为第一驱动晶体管D1和第二驱动晶体管D2的栅极绝缘层单位面积的电容。
作为示例地，以下结合图3至图7进行进一步地说明：
在t1阶段，第一控制信号S1为低电平，第二控制信号S2、第三控制信号S3以及驱动信号EM为高电平；此时，第一开关晶体管T1的控制端接收第一控制信号S1的低电平并导通，初始化第四开关晶体管T4、第一驱动晶体管D1和第二驱动晶体管D2的控制端为参考电压Vref。其电流流向可参图4中虚线所示。
在t2阶段，第二控制信号S2为低电平，第一控制信号S1、第三控制信号S3以及驱动信号EM为高电平；此时，第二开关晶体管T2和第三开关晶体管T3的控制端接收第二控制信号S2的低电平并导通，数据信号输入的数据信号V data提供至储存电容Cst的第二端。其电流流向可参图5中虚线所示。需要说明的是，此时第二驱动晶体管D2和第四开关晶体管T4可以看成是一个宽长比为W/(L2+L3)的晶体管，在较短的充电时间t2内，P点电压可以比较快速的被写入为V data-|V th2|，其中V th2为第二驱动晶体管D2的阈值电压，在这种情况下，第二驱动晶体管D2和第四开关晶体管T4组成的晶体管的阈值电压主要受第二驱动晶体管D2决定。
在t3阶段，第三控制信号S3为低电平，第一控制信号S1、第二控制信号S2以及驱动信号EM为高电平；此时，第五开关晶体管T5的控制端接收第三控制信号S3的低电平并导通，有机发光二极管L1的阳极端被反向初始化为参考电压Vref。其电流流向可参图6中虚线所示。
在t4阶段，驱动信号EM为低电平，第一控制信号S1、第二控制信号S2以及第三控制信号S3为高电平；此时，第六开关晶体管T6和第七开关晶体管T7的控制端接收驱动信号的低电平并导通，有机发光二极管L1开始发光。其电流流向可参图7中虚线所示。需要说明的是，此时由于第一驱动晶体管D1和第二驱动晶体管D2串联在一起，并且栅极连接在一起，可以认为是一个宽长比为W/(L1+L2)的晶体管，这个晶体管工作在饱和区，V th主要由第二驱动晶体管D2的V th2决定，所以根据饱和区电流计算公式，流经有机发光二极管的电流为：I＝1/2×U×C ox×[W/(L1+L2)]×(V data-VDD) 2，其中，U为第一驱动晶体管D1和第二驱动晶体管D2的迁移率，C ox为第一驱动晶体管D1和第二驱动晶体管D2的栅极绝缘层单位面积的电容。
本发明实施例提供的像素驱动电路的驱动方法，通过串联连接的第一驱动晶体管和第二驱动晶体管驱动有机发光二极管；像素充电时，像素驱动电路可补偿串联连接的第二驱动晶体管和第四开关晶体管的阈值电压；可同时满足降低有机发光二极管的电流和提高像素驱动晶体管栅极的充电率的要求。
本发明实施例进一步提供一种阵列基板，包括：
沿列延伸排列的多条数据信号线；
沿行延伸排列的多条控制信号线和驱动信号线；
以矩阵形式布置在数据信号线和控制信号线交叉位置处的多个像素；
像素包括上述的像素驱动电路。
本发明实施例提供的阵列基板，通过串联连接的第一驱动晶体管和第二驱动晶体管驱动有机发光二极管；像素充电时，像素驱动电路可补偿串联连接的第二驱动晶体管和第四开关晶体管的阈值电压；可同时满足降低有机发光二极管的电流和提高像素驱动晶体管栅极的充电率的要求。
本发明实施例进一步提供一种显示装置，包括：上述的阵列基板。另外，显示装置还可以为电子纸、手机、电视、数码相框等显示设备。
本发明实施例提供的显示装置，通过串联连接的第一驱动晶体管和第二驱动晶体管驱动有机发光二极管；像素充电时，像素驱动电路可补偿串联连接的第二驱动晶体管和第四开关晶体管的阈值电压；可同时满足降低有机发光二极管的电流和提高像素驱动晶体管栅极的充电率的要求。
如图8至图10所示，本发明实施例进一步提出一种晶体管的版图结构，该版图结构包括电路节点10以及与电路节点10连接的有源层。
在本实施例中，有源层包括第一有源层21、第二有源层22以及第三有源层23。
请参图8所示，在一种可能的实施方式中，第一有源层21和第三有源层23构成倒“U”型结构；第二有源层22构成倒“L”型结构。
请参图9所示，在另一种可能的实施方式中，第一有源层21和第二有源层22构成
Figure PCTCN2018076788-appb-000002
型结构；第三有源层23构成倒“L”型结构。
请参图10所示，在另一种可能的实施方式中，第一有源层21和第二有源层22构成“n”型结构；第三有源层23构成倒“L”型结构。
与第一有源层21相连的为第一源极31，与第二有源层22相连的为漏极32，与第三有源层23相连的为第二源极33。
该版图结构还包括分别与第一有源层21、第二有源层22和第三有源层23对应的第一栅极、第二栅极和第三栅极；第一栅极、第二栅极以及第三栅极组成的栅极图案40位于电路节点10和有源层的上方。
请参图8至图10所示，在本实施例中，栅极图案40大致呈方形状，如正方形或者长方形；栅极图案也可以为多边形，即四条以上的线段首尾顺次连接所组 成的平面图形。
请再参图8所示，被栅极图案40覆盖的有源层即为沟道区，第一有源层21被栅极图案40覆盖的有源层211(图中虚线框)为第一沟道，第二有源层22被栅极图案40覆盖的有源层221(图中虚线框)为第二沟道，第三有源层23被栅极图案40覆盖的有源层231(图中虚线框)为第三沟道。
第一源极31、第一有源层21和电路节点10可形成一电流流动的通道；第二源极33、第三有源层23和电路节点10可形成一电流流动的通道；电路节点10、第二有源层22和漏极32可形成一电流流动的通道。因此，该版图结构相当于三个晶体管组成的版图，即：其中两个晶体管的漏极和第三个晶体管的源极连接在一起形成的电路节点，以及三个晶体管的栅极连接在一起。
需要说明的是，本发明实施例提供的晶体管的版图结构，不但适用于底栅结构的晶体管，还适用于顶栅结构的晶体管。
顶栅结构和底栅结构的晶体管，制造工艺存在不同。顶栅结构制造工艺流程如下：
S1：缓冲层、有源层沉积和有源层图形化；
S2：栅极绝缘层、栅极金属层沉积和栅极金属层图形化；
S3：晶体管源漏极P+掺杂。
底栅结构制造工艺流程如下：
S10、缓冲层、栅极金属层沉积和栅极金属层图形化；
S11、栅极绝缘层、有源层沉积和有源层图形化；
S12、掺杂阻挡层涂布、图形化，TFT源漏极P+掺杂；
S13、栅极阻挡层剥离。
本发明实施例提供的晶体管的版图结构，晶体管的版图结构相当于三个晶体管的栅极组成同一个图形，两个晶体管的漏极和第三个晶体管的源极连接在一起形成的电路节点位于栅极图形之下，通过这种设计可以缩小三个晶体管的版图面积，降低版图设计难度，提高应用范围。
本发明实施例还提出一种像素驱动电路，该像素驱动电路包括第一驱动晶体管、第二驱动晶体管和一个开关晶体管；其中，第一驱动晶体管、第二驱动晶体管和开关晶体管构成的版图结构为上述的版图结构。
在本实施例中，第一驱动晶体管的宽长比W1/L1、第二驱动晶体管的宽长比 W2/L2、开关晶体管的宽长比W3/L3满足以下关系：
W1＝W2＝W3，L1/L2＝1，L3<L2；或
W1＝W2＝W3，L1/L2>1，L3<L2；或
W1＝W2＝W3，L1/L2<1，L3<L2；或
W1＝W2<W3，L1/L2＝1或L1/L2>1或L1/L2<1，L3<L2；或
W1＝W2>W3，L1/L2＝1或L1/L2>1或L1/L2<1，L3<L2。
需要说明的是，第一驱动晶体管的宽长比W1/L1、第二驱动晶体管的宽长比W2/L2、开关晶体管的宽长比W3/L3设计，并不限定于上面所列出的情形，按照本发明实施例的像素驱动电路所设计的宽长比设计都应在本专利保护范围内。
作为示例地，请参图1所示，图1的像素驱动电路包括第一驱动晶体管D1、第二驱动晶体管D2和第四开关晶体管T4(图中虚线框所示)。第一驱动晶体管D1的第二端(漏极)、第四开关晶体管T4的第二端(漏极)和第二驱动晶体管D2的第一端(源极)连接在一起形成电路节点；第一驱动晶体管D1的栅极、第二驱动晶体管D2的栅极和第四开关晶体管T4的栅极连接在一起，其版图结构设计如上所述。
本发明实施例提供的像素驱动电路，三个晶体管的栅极组成同一个图形，两个晶体管的漏极和第三个晶体管的源极连接在一起形成的电路节点位于栅极图形之下，通过这种设计可以缩小三个晶体管的版图面积，降低版图设计难度，提高应用范围。
本发明进一步提供一种阵列基板，包括：
沿列延伸排列的数据信号线；
沿行延伸排列的多条控制信号线和驱动信号线；
以矩阵形式布置在数据信号线和控制信号线交叉位置处的多个像素；
像素包括上述的像素驱动电路。
本发明实施例提供的阵列基板，三个晶体管的栅极组成同一个图形，两个晶体管的漏极和第三个晶体管的源极连接在一起形成的电路节点位于栅极图形之下，通过这种设计可以缩小三个晶体管的版图面积，降低版图设计难度，提高应用范围。
本发明进一步提供一种显示装置，包括：上述的阵列基板。另外，显示装置还可以为电子纸、手机、电视、数码相框等等显示设备。
本发明实施例提供的显示装置，三个晶体管的栅极组成同一个图形，两个晶体管的漏极和第三个晶体管的源极连接在一起形成的电路节点位于栅极图形之下，通过这种设计可以缩小三个晶体管的版图面积，降低版图设计难度，提高应用范围。
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。
工业实用性
本发明实施例提供的像素驱动电路及其驱动方法，通过串联连接的第一驱动晶体管和第二驱动晶体管驱动有机发光二极管；像素充电时，像素驱动电路可补偿串联连接的第二驱动晶体管和第四开关晶体管的阈值电压；可同时满足降低有机发光二极管的电流和提高像素驱动晶体管栅极的充电率的要求。
本发明实施例提供的晶体管的版图结构，三个晶体管的栅极组成同一个图形，两个晶体管的漏极和第三个晶体管的源极连接在一起形成的电路节点位于栅极图形之下，通过这种设计可以缩小三个晶体管的版图面积，降低版图设计难度，提高应用范围。

Claims (15)

  1. 一种像素驱动电路，其特征在于，所述像素驱动电路包括：
    储存电容，具有第一端连接第一电压源，以及第二端；
    第一开关晶体管，具有第一端连接于储存电容的第二端，第二端用来接收参考电压，以及控制端用来接收第一控制信号；
    第二开关晶体管，具有第一端用于接收数据信号输入，第二端，以及控制端用来接收第二控制信号；
    第三开关晶体管，具有第一端，第二端连接于第一开关晶体管的第一端，以及控制端用来接收第二控制信号；
    第四开关晶体管，具有第一端连接于第二开关晶体管的第二端，第二端，以及控制端连接于储存电容的第二端；
    第五开关晶体管，具有第一端连接于有机发光二极管的阳极端，第二端用来接收参考电压，以及控制端用来接收第三控制信号；
    第六开关晶体管，具有第一端连接第一电压源，第二端，以及控制端用来接收驱动信号；
    第一驱动晶体管，具有第一端连接于第六开关晶体管的第二端，第二端连接于第四开关晶体管的第二端，以及控制端连接于储存电容的第二端；
    第二驱动晶体管，具有第一端连接于第四开关晶体管的第二端，第二端连接于第三开关晶体管的第一端，以及控制端连接于储存电容的第二端；
    第七开关晶体管，具有第一端连接于第二驱动晶体管的第二端，第二端连接于有机发光二极管的阳极端，以及控制端用来接收驱动信号；
    有机发光二极管，具有阳极端，阴极端连接于第二电压源。
  2. 根据权利要求1所述的像素驱动电路，其特征在于，所述第一驱动晶体管的宽长比W1/L1、所述第二驱动晶体管的宽长比W2/L2、所述第四开关晶体管的宽长比W3/L3满足以下关系：
    W1＝W2＝W3，L1/L2＝1，L3<L2；或
    W1＝W2＝W3，L1/L2>1，L3<L2；或
    W1＝W2＝W3，L1/L2<1，L3<L2；或
    W1＝W2<W3，L1/L2＝1或L1/L2>1或L1/L2<1，L3<L2；或
    W1＝W2>W3，L1/L2＝1或L1/L2>1或L1/L2<1，L3<L2。
  3. 根据权利要求1所述的像素驱动电路，其特征在于，所述参考电压以及所述第二电压源所提供的电压的电位相等。
  4. 根据权利要求1所述的像素驱动电路，其特征在于，所述参考电压为一独立电压源。
  5. 根据权利要求1所述的像素驱动电路，其特征在于，所述第一开关晶体管至第七开关晶体管、以及第一驱动晶体管、第二驱动晶体管全部具有相同的沟道类型。
  6. 一种像素驱动电路的驱动方法，其特征在于，所述驱动方法包括：
    第一阶段，第一开关晶体管的控制端接收第一控制信号并导通，初始化第四开关晶体管、第一驱动晶体管和第二驱动晶体管的控制端为参考电压；
    第二阶段，第二开关晶体管和第三开关晶体管的控制端接收第二控制信号并导通，数据信号输入的数据信号V data提供至储存电容的第二端；
    第三阶段，第五开关晶体管的控制端接收第三控制信号并导通，有机发光二极管的阳极端被反向初始化为参考电压；
    第四阶段，第六开关晶体管和第七开关晶体管的控制端接收驱动信号并导通，所述有机发光二极管开始发光。
  7. 根据权利要求6所述的像素驱动电路的驱动方法，其特征在于，在所述第二阶段，所述第四开关晶体管、所述第一驱动晶体管和所述第二驱动晶体管的控制端的电压达到V data-|V th2|，其中V th2为第二驱动晶体管的阈值电压。
  8. 根据权利要求6所述的像素驱动电路的驱动方法，其特征在于，在所述第四阶段，流经所述有机发光二极管的电流为：I＝1/2×U×C ox×[W/(L1+L2)]×(V data-VDD) 2，其中，U为所述第一驱动晶体管和所述第二驱动晶体管的迁移率，C ox为所述第一驱动晶体管和所述第二驱动晶体管的栅极绝缘层单位面积的电容。
  9. 一种阵列基板，其特征在于，包括权利要求1-5任一项所述的像素驱动电路。
  10. 一种显示装置，其特征在于，包括权利要求9所述的阵列基板。
  11. 一种晶体管的版图结构，其特征在于，所述版图结构包括电路节点以及 与所述电路节点连接的有源层；所述有源层包括第一有源层、第二有源层以及第三有源层；
    与所述第一有源层相连的第一源极，与所述第二有源层相连的漏极，与所述第三有源层相连的第二源极；
    分别与所述第一有源层、第二有源层和第三有源层对应的第一栅极、第二栅极和第三栅极；所述第一栅极、第二栅极以及第三栅极组成的栅极图案位于所述电路节点和所述有源层的上方。
  12. 根据权利要求11所述的晶体管的版图结构，其特征在于，所述第一有源层和第三有源层构成倒“U”型结构；所述第二有源层构成倒“L”型结构。
  13. 根据权利要求11所述的晶体管的版图结构，其特征在于，所述第一有源层和第二有源层构成
    Figure PCTCN2018076788-appb-100001
    型结构；所述第三有源层构成倒“L”型结构。
  14. 根据权利要求11所述的晶体管的版图结构，其特征在于，所述第一有源层和第二有源层构成“n”型结构；所述第三有源层构成倒“L”型结构。
  15. 根据权利要求11所述的晶体管的版图结构，其特征在于，所述第一栅极、第二栅极以及第三栅极组成的栅极图案为方形状或者多边形。
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