WO2018143073A1 - Couche mince semi-conductrice d'oxyde cristalline, procédé de fabrication de stratifié, transistor à couches minces, procédé de fabrication de transistor à couches minces, dispositif électronique et dispositif d'affichage embarqué - Google Patents

Couche mince semi-conductrice d'oxyde cristalline, procédé de fabrication de stratifié, transistor à couches minces, procédé de fabrication de transistor à couches minces, dispositif électronique et dispositif d'affichage embarqué Download PDF

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WO2018143073A1
WO2018143073A1 PCT/JP2018/002432 JP2018002432W WO2018143073A1 WO 2018143073 A1 WO2018143073 A1 WO 2018143073A1 JP 2018002432 W JP2018002432 W JP 2018002432W WO 2018143073 A1 WO2018143073 A1 WO 2018143073A1
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thin film
oxide semiconductor
semiconductor thin
transistor
semiconductor layer
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PCT/JP2018/002432
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English (en)
Japanese (ja)
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井上　一吉
雅敏 柴田
勇輝 霍間
絵美 川嶋
基浩 竹嶋
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出光興産株式会社
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Priority to JP2018565502A priority Critical patent/JP7187322B2/ja
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    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B35/00—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products
    • C04B35/01—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxide ceramics
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/08—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present invention relates to a crystalline oxide semiconductor thin film, a method for manufacturing a laminated body, a thin film transistor, a method for manufacturing a thin film transistor, an electronic device, and an in-vehicle display device.
  • Amorphous (amorphous) oxide semiconductors used for thin film transistors (TFTs) have higher carrier mobility than general-purpose amorphous silicon (a-Si), a large optical band gap, and can be formed at low temperatures. It is expected to be applied to next-generation displays that require large size, high resolution, and high-speed driving, and resin substrates with low heat resistance.
  • a sputtering method is preferably used in which a sputtering target made of the same material as the film is sputtered.
  • the sputtering target is usually formed by mixing and sintering oxide powder and machining.
  • Patent Documents 1 to 4 The most advanced development of the composition of an oxide semiconductor used for a display device is an In-containing In—Ga—Zn—O amorphous oxide semiconductor (see, for example, Patent Documents 1 to 4). Furthermore, recently, for the purpose of improving high mobility and reliability of TFTs, attempts have been made to change the type and concentration of additive elements containing In as a main component (for example, see Patent Document 5). Patent Documents 6 to 8 report In—Al-based sputtering targets. Patent Document 9 discloses a technique related to a thin film transistor using a sputtering target or a semiconductor film containing indium oxide, gallium oxide, and samarium oxide.
  • An oxide semiconductor can be classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor.
  • the carrier of the amorphous oxide semiconductor is composed of electrons generated by oxygen vacancies. It has been reported that a crystalline oxide semiconductor can obtain a high mobility TFT by making it a crystalline thin film.
  • the carrier density of the crystalline thin film fluctuates due to various heat loads, oxidation loads, reduction loads, etc. in each TFT manufacturing process. That is, the crystalline oxide semiconductor thin film still has a problem that the carrier density fluctuates, and the fluctuation of TFT characteristics cannot be suppressed.
  • Patent Document 8 Water is decomposed in plasma and becomes OH radicals that exhibit a very strong oxidizing power, which has the effect of reducing trapping of oxide semiconductors.
  • the process of introducing water has problems that oxygen and nitrogen dissolved in the water need to be sufficiently deaerated beforehand, and that new countermeasures such as a pipe corrosion countermeasure are required.
  • An object of the present invention is to provide a crystalline oxide semiconductor thin film having a stable carrier density and a thin film transistor having high saturation mobility using the same.
  • an oxide semiconductor thin film containing indium oxide as a main component is formed without introducing impurities such as water or in a reduced state, and a protective film is formed without heat treatment in an oxidizing atmosphere.
  • an oxide semiconductor film with a high carrier density is formed, and the band gap is increased by the Burstein-Moss effect.
  • heat treatment is performed to obtain a crystalline oxide semiconductor thin film including surface crystal grains having a single crystal orientation, a high band gap, and a high saturation mobility.
  • a crystalline oxide semiconductor thin film has surface crystal grains having a single crystal orientation, so that the crystal is stabilized, and since the band gap is high, the light stability is excellent. Variation in the carrier density of the thin film, and hence variation in TFT characteristics, can be reduced, and a TFT having ultrahigh mobility can be manufactured.
  • the action mechanism of a TFT having ultra-high mobility can be considered as follows. That is, the heat treatment after forming the protective film on the oxide semiconductor thin film causes a reaction with oxygen on the surface of the oxide semiconductor thin film (the surface on the protective film side), so that oxygen deficiency is reduced and carrier density is also reduced. To do.
  • the carrier density of the oxide semiconductor thin film before the formation of the protective film is made sufficiently high by forming the protective film without the heat treatment in the oxidizing atmosphere after the formation of the oxide semiconductor thin film.
  • the carrier density on the front surface side of the oxide semiconductor thin film is kept low by the subsequent heat treatment, and the carrier density in the vicinity of the back surface (the surface on the gate insulating film side) can be kept high, and the stable Vth ( A TFT having a threshold voltage) and an ultrafast mobility can be achieved.
  • the following crystalline oxide semiconductor thin film and the like are provided.
  • the crystalline oxide semiconductor thin film according to [1] wherein crystal particles whose surface crystal state is faceted are observed when observed by an electron beam backscattering analysis method.
  • An oxide semiconductor thin film is formed by sputtering using a sputtering target containing indium oxide as a main component and using as a sputtering gas one or more gases selected from the group consisting of argon and oxygen that are substantially free of impurity gas.
  • Forming a film A step of forming a protective film on the oxide semiconductor thin film without subjecting the oxide semiconductor thin film to heat treatment in an oxidizing atmosphere; and heating the stacked body including the oxide semiconductor thin film and the protective film.
  • the manufacturing method of the laminated body as described in any one of [8] to [10] whose heat processing temperature of the process which performs the said heat processing is 250 degreeC or more and 500 degrees C or less.
  • a thin film transistor comprising: [15].
  • a graph of the transfer characteristic Id-Vg is created from the current Id between the source and drain electrodes and the gate voltage Vg when 0.1 V is applied to the drain voltage, and the field effect mobility ⁇ obtained from the Id-Vg graph is calculated as Vg.
  • the thin film transistor according to [14] or [15] which is 50% or more of a maximum field-effect mobility between them.
  • An oxide semiconductor layer is formed by sputtering using a sputtering target containing indium oxide as a main component, using one or more gases selected from the group consisting of argon and oxygen, which are substantially free of impurity gas, as a sputtering gas.
  • Forming a film A step of forming a protective insulating film on the oxide semiconductor layer without performing heat treatment in an oxidizing atmosphere on the oxide semiconductor layer; and a stacked body including the oxide semiconductor layer and the protective insulating film.
  • the present invention it is possible to provide a crystalline oxide semiconductor thin film having a stable carrier density and a thin film transistor having high saturation mobility using the crystalline oxide semiconductor thin film.
  • FIG. 10 is a vertical cross-sectional view illustrating a thin film transistor according to one embodiment of the present invention.
  • FIG. 10 is a vertical cross-sectional view illustrating a thin film transistor according to one embodiment of the present invention.
  • FIG. 1 is a longitudinal cross-sectional view illustrating a quantum tunnel field effect transistor according to one embodiment of the present invention.
  • the longitudinal cross-sectional view which shows the other example of a quantum tunnel field effect transistor.
  • FIG. 5 is a TEM (transmission electron microscope) photograph of a portion where a silicon oxide layer is formed between a p-type semiconductor layer and an n-type semiconductor layer.
  • the longitudinal cross-sectional view for demonstrating the manufacturing procedure of a quantum tunnel field effect transistor The longitudinal cross-sectional view for demonstrating the manufacturing procedure of a quantum tunnel field effect transistor.
  • FIG. 11 is a top view illustrating a display device including a thin film transistor according to one embodiment of the present invention.
  • FIG. 6 is a diagram showing a circuit of a pixel portion that can be applied to a pixel of a VA liquid crystal display device. The figure which shows the circuit of the pixel part of the display apparatus using an organic EL element
  • FIG. 6 illustrates a circuit of a pixel portion of a solid-state imaging element using a thin film transistor according to one embodiment of the present invention.
  • the longitudinal cross-sectional view which shows the state which formed the oxide semiconductor thin film on the glass substrate. It is a diagram showing a state of forming a SiO 2 film on the oxide semiconductor thin film of FIG 11A.
  • a crystalline oxide semiconductor thin film according to one embodiment of the present invention includes surface crystal grains mainly composed of indium oxide and having a single crystal orientation, and has a band gap of 3.90 eV or more.
  • a crystalline oxide semiconductor thin film including surface crystal grains having a single crystal orientation is stable in crystal and has carrier density due to various loads (for example, thermal load, oxidation load, reduction load, etc.) in the TFT manufacturing process. Variations can be reduced.
  • a thin film transistor using such a crystalline oxide semiconductor thin film as a channel layer can achieve high saturation mobility.
  • the band gap of the crystalline oxide semiconductor thin film is preferably 3.90 eV or more, more preferably 3.95 eV or more, and further preferably 4.00 eV or more.
  • the optical band gap can be measured using, for example, a self-recording spectrophotometer “UV-3100PC” manufactured by Shimadzu Corporation. When the band gap is 3.90 eV or more, malfunction due to light from a light emitter such as external light or organic EL can be reduced.
  • “Mainly containing indium oxide” means that 50% by mass or more of the oxide constituting the crystalline oxide semiconductor thin film is indium oxide, and the ratio is preferably 70% by mass or more, more Preferably it is 80 mass% or more, More preferably, it is 90 mass% or more.
  • indium oxide 50% by mass or more of the oxide constituting the crystalline oxide semiconductor thin film, a sufficiently high saturation mobility can be exhibited when it is employed in a TFT.
  • “Including surface crystal grains having a single crystal orientation” means a state in which the crystal orientation is controlled. For example, normally, when a crystal particle having a facet-like crystal state on the surface of a crystalline oxide semiconductor thin film is observed when observed by EBSD (electron beam backscattering analysis), “single crystal orientation” It includes surface crystal grains having FIG. 1 shows an azimuth reference by EBSD measurement as a crystal analysis method for the surface of indium oxide (In 2 O 3 ) thin film.
  • FIG. 2 shows a typical EBSD image when the surface crystal shows a faceted crystal state.
  • the average crystal grain size in the faceted crystal state is usually 0.5 ⁇ m or more, preferably 1 ⁇ m or more, more preferably 2 ⁇ m or more. Moreover, the upper limit of the average crystal grain size is usually 10 ⁇ m or less. Each facet-like crystal grain has a single crystal orientation. If the average crystal grain size is 0.5 ⁇ m or more, the possibility of becoming a microcrystal is small, and if it is 10 ⁇ m or less, the internal crystal transition can be suppressed and the faceted state can be maintained without problems.
  • the particle size of the crystal particles is obtained by confirming the surface form by EBSD and measuring the ferret diameter (the short side of the rectangle circumscribing the crystal).
  • the average crystal grain size is calculated by calculating the average value of the facet-like crystal grains observed within the frame centered on the central part (intersection of diagonal lines) of the crystalline oxide semiconductor thin film. It is a thing.
  • the size of the frame is usually 5 ⁇ m ⁇ 5 ⁇ m, but is appropriately adjusted depending on the size of the crystalline oxide semiconductor thin film and the size of the particle size.
  • the number of faceted crystals in the frame is 5 or more. If the number is less than 5, the size of the frame is enlarged and observation is performed.
  • the crystal particle usually has a particle size of about 1 ⁇ m or more and 20 ⁇ m or less. Particularly, a crystal exceeding 10 ⁇ m does not show a single crystal orientation within the particle size, and the center The crystal has a crystal orientation that changes radially from the portion or the end of the crystal.
  • the area occupied by crystal grains whose surface crystal state is faceted is preferably 50% or more, more preferably 80%, and still more preferably 90% or more.
  • the proportion is 50% or more, a stable carrier density can be achieved.
  • crystal forms that are not faceted include amorphous crystals and fine crystals in addition to radial crystals.
  • a portion other than the portion occupied by facet-like crystal particles is usually occupied by particles of these forms.
  • the crystalline oxide semiconductor thin film in one embodiment of the present invention preferably contains one or more elements selected from the group consisting of positive trivalent metal elements other than indium elements.
  • positive trivalent metal elements other than indium elements include gallium and lanthanoid elements, and preferably one or more selected from the group consisting of gallium and lanthanoid elements. It is particularly preferable to include it.
  • Gallium is preferable because it has the effect of reducing the lattice constant of crystallized indium oxide and the effect of improving the mobility of the TFT.
  • lanthanoid element lanthanum, neodymium, samarium, europium, gadolinium, terbium, dyspronium, holnium, erbium, thulium, ytterbium and lutetium are preferable, and neodymium, samarium, ytterbium and europium are more preferable.
  • the lanthanoid element has a large binding force with oxygen, and has an effect of suppressing carrier generation due to oxygen deficiency. Oxygen vacancies may occur due to various loads in the TFT manufacturing process and reduction loads in chemical vapor deposition (CVD), resulting in an increase in carrier density. Heat treatment can reduce the carrier density, which is preferable. Further, it is preferable because it has an effect of increasing the band gap.
  • the crystalline oxide semiconductor thin film contains one or more elements selected from gallium and lanthanoid elements, facet-like crystallization is easily performed.
  • the content of positive trivalent metal elements other than indium elements is preferably more than 5 atomic% and not more than 20 atomic%, more than 7 atomic% and not more than 15 atomic%, based on the total metal content in the crystalline oxide semiconductor thin film. It is more preferable that The content of positive trivalent metal elements other than indium element means the total amount of positive trivalent metal elements other than indium element contained in the crystalline oxide semiconductor thin film.
  • the crystalline oxide semiconductor thin film according to one embodiment of the present invention for example, 70 mass% or more, 80 mass% or more, 90 mass% or more, 98 mass% or more, 99 mass% or more, 99.9 mass% or more is indium. It may be a positive trivalent metal element other than the element and the indium element.
  • the crystalline oxide semiconductor thin film according to one embodiment of the present invention may consist essentially of an indium element and a positive trivalent metal element other than the indium element. In this case, inevitable impurities may be included. The inevitable impurities are elements that are not intentionally added and are elements mixed in the raw material or the manufacturing process. The same applies to the following description.
  • Examples of inevitable impurities include alkali metals and alkaline earth metals (Li, Na, K, Rb, Mg, Ca, Sr, Ba, etc.), 10 ppm or less, preferably 1 ppm or less, more preferably 100 ppb. The following is good.
  • the impurity concentration can be measured by ICP or SIMS.
  • hydrogen, nitrogen, and halogen atoms may be included. In this case, it is 5 ppm or less, preferably 1 ppm or less, more preferably 100 ppb or less as measured by SIMS.
  • the crystalline oxide semiconductor thin film according to one embodiment of the present invention may include only an indium element and a positive trivalent metal element other than the indium element.
  • the crystalline oxide semiconductor thin film according to one embodiment of the present invention may further contain one or more elements selected from the group consisting of positive tetravalent metal elements.
  • positive tetravalent metal element examples include tin, zirconium, and cerium. Tin and cerium are preferable.
  • the content of the positive tetravalent metal element can be contained within a range that does not affect the crystalline oxide semiconductor thin film, and is 0.01 atomic% or more and 0% relative to the total metal content in the crystalline oxide semiconductor thin film. It is preferably 1 atomic% or less, more preferably 0.03 atomic% or more and 0.07 atomic% or less.
  • the content of the positive tetravalent metal element means the total amount of the positive tetravalent metal element contained in the crystalline oxide semiconductor thin film.
  • tin element in a sputtering target used for forming a crystalline oxide semiconductor thin film because the resistance value of the sputtering target can be reduced, abnormal discharge can be reduced, and stable sputtering can be performed.
  • carriers are generated by crystallization of the oxide semiconductor thin film, and a decrease in carrier density due to disappearance of oxygen vacancies due to various thermal loads and oxidation loads in the TFT manufacturing process can be suppressed.
  • the crystalline oxide semiconductor thin film according to one embodiment of the present invention preferably has a carrier density of 5 ⁇ 10 17 cm ⁇ 3 or more, more preferably 5.5 ⁇ 10 17 cm ⁇ 3 or more. Further, it may be 7.0 ⁇ 10 17 cm -3 or more, or 9.0 ⁇ 10 17 cm -3 or more.
  • the crystalline oxide semiconductor thin film according to one embodiment of the present invention preferably has a mobility of 50 cm 2 / V ⁇ sec or more, more preferably 60 cm 2 / V ⁇ sec or more.
  • the crystalline oxide semiconductor thin film according to one embodiment of the present invention includes surface crystal grains having a single crystal orientation as described above, and further, since the carrier density and mobility are high, the carrier density of the oxide semiconductor thin film is high.
  • a TFT that is stable, can reduce fluctuations in TFT characteristics, and has extremely high mobility can be manufactured.
  • the crystalline oxide semiconductor thin film according to one embodiment of the present invention is useful for TFTs used for display devices such as liquid crystal displays and organic EL displays.
  • a crystalline oxide semiconductor thin film according to the present invention can be produced, for example, as a part of a laminate including a crystalline oxide semiconductor thin film and a protective film.
  • a sputtering target mainly composed of indium oxide is used, and one or more gases selected from the group consisting of argon and oxygen that do not substantially contain an impurity gas are used as a sputtering gas.
  • a step of forming an oxide semiconductor thin film by sputtering, a step of forming a protective film on the oxide semiconductor thin film without subjecting the oxide semiconductor thin film to heat treatment in an oxidizing atmosphere, and the oxidation The manufacturing method including the process of heat-processing the laminated body containing a physical-semiconductor thin film and the said protective film is mentioned.
  • the semiconductor thin film is an amorphous (amorphous) oxide semiconductor thin film.
  • the oxide semiconductor thin film is heated and crystallized after forming the protective film, thereby obtaining a crystalline oxide semiconductor thin film having a single crystal orientation, preferably a faceted crystal state. be able to.
  • each step will be described.
  • a sputtering target containing indium oxide as a main component is used, and one or more gases selected from the group consisting of argon and oxygen that do not substantially contain an impurity gas are used as a sputtering gas.
  • a semiconductor thin film is formed (see, for example, FIG. 11A).
  • the sputtering gas “substantially free of impurity gas” means that other than argon and oxygen, except for adsorbed water brought in by gas insertion, and gas that cannot be excluded such as chamber leakage and adsorbed gas (inevitable impurity gas) This means that no impurity gas is actively introduced.
  • a commercially available mixed gas of high purity argon and high purity oxygen can be used. Impurities should be eliminated if possible.
  • the ratio of the impurity gas in the sputtering gas is preferably 0.1% by volume or less, and more preferably 0.05% by volume or less. When the ratio of the impurity gas is 0.1% by volume or less, crystallization of the oxide semiconductor thin film proceeds without any problem, and a desired faceted crystal can be obtained.
  • the purity of high purity argon or high purity oxygen is preferably 99% by volume or more, more preferably 99.9% by volume or more, and still more preferably 99.99% by volume or more.
  • the oxygen partial pressure in the mixed gas of argon and oxygen is preferably more than 0 volume% and 10 volume% or less, and more preferably more than 0 volume% and 5 volume% or less.
  • the oxygen partial pressure is in the above range, it is easily crystallized and becomes a semiconductor upon heating.
  • the degree of oxidation of the oxide semiconductor thin film that is, the degree of crystallization can be adjusted. What is necessary is just to select an oxygen partial pressure suitably as needed.
  • the sputtering target mainly composed of indium oxide preferably contains one or more elements selected from the group consisting of gallium and lanthanoid elements.
  • Gallium and lanthanoid elements are as described above.
  • the ion radius of the gallium atom is 0.62 ⁇ 10 ⁇ 10 m, and as an example of the lanthanoid element, the atomic radius of samarium is 0.96 ⁇ 10 ⁇ 10 m, and the ion radius of the In atom is 0.80 ⁇ 10 ⁇ Since it is different from 10 m, crystallization can be inhibited during the formation of the oxide semiconductor thin film.
  • the sputtering target contains a gallium element and a lanthanoid element (for example, samarium element)
  • a lanthanoid element for example, samarium element
  • an amorphous oxide semiconductor thin film can be obtained during film formation without introducing impurities such as water. Faceted crystals can be grown.
  • gallium element can be dissolved in indium oxide, and the lattice constant of indium oxide can be reduced. This is thought to improve the mobility of the final product TFT.
  • a gallium element having a small ionic radius cannot be dissolved in indium oxide.
  • an element having a large ion radius for example, a lanthanoid element (eg, samarium element)
  • the distortion of the crystal caused by gallium ions can be eliminated, and a stable indium oxide crystal can be obtained. TFT characteristics can be realized.
  • the effect of reducing the lattice defects of the crystal inside the facet-like crystal by simultaneously presenting a gallium element having a small ion radius and a lanthanide element having a large ion radius (for example, samarium element) to the indium element It can be expected to relieve misalignment.
  • a protective film is formed over the oxide semiconductor thin film without performing heat treatment in an oxidizing atmosphere on the obtained oxide semiconductor thin film (see, for example, FIG. 11B).
  • “Without heat treatment in an oxidizing atmosphere” means independent heat treatment in an atmosphere (for example, air atmosphere) in which oxygen molecules exist between the formation of the oxide semiconductor thin film and the formation of the protective film. It means that a process (heat-treatment temperature is 250-350 degreeC, for example) is not included.
  • the heat treatment in an atmosphere substantially free of oxygen molecules causes substantially no oxidation reaction. Therefore, it does not fall under “heat treatment in an oxidizing atmosphere”.
  • the substrate heating performed when the protective film is formed by chemical vapor deposition (CVD) is performed in an atmosphere substantially free of oxygen molecules, and thus does not correspond to the “heat treatment in an oxidizing atmosphere”.
  • CVD chemical vapor deposition
  • the carrier concentration of the oxide semiconductor thin film is increased as compared with the case where the heat treatment is performed.
  • the band gap increases due to the Burstein-Moss effect, and can be increased to 3.90 eV or more.
  • Examples of the material for the protective film include SiO 2 , SiN x , SiON x , Al 2 O 3 , and Ga 2 O 3 .
  • the thickness of the protective film is usually 50 nm or more and 500 nm or less.
  • Examples of the method for forming the protective film include CVD, sputtering, and coating.
  • heat treatment process heat treatment is performed on the stacked body in which the protective film is formed over the oxide semiconductor thin film.
  • the temperature of the heat treatment is preferably 250 ° C. or higher and 500 ° C. or lower, more preferably 280 ° C. or higher and 470 ° C. or lower, and further preferably 300 ° C. or higher and 450 ° C. or lower. If it is 250 ° C. or higher, there is no crystallization or generation of microcrystals, and the oxide semiconductor thin film crystallizes in a faceted form without any problem. If it is 500 degrees C or less, a problem will not arise in the heat resistance of a board
  • the heating time is preferably from 0.1 hours to 5 hours, more preferably from 0.3 hours to 3 hours, and even more preferably from 0.5 hours to 2 hours. If it is 0.1 hour or longer, the oxide semiconductor thin film is crystallized in a facet form without any problem without crystallizing or becoming a radial crystal. If it is 5 hours or less, it is excellent in economical efficiency. “Heating time” refers to the time from reaching 250 ° C. to less than 250 ° C.
  • the crystallization rate In order to easily generate faceted crystals, it is preferable to lower the crystallization rate than the oxygen diffusion rate.
  • oxygen concentration in the oxide semiconductor thin film after film formation is high, oxygen is not insufficient at the time of crystallization, and facet-like crystals can be obtained even when crystallization is performed at a high crystallization rate.
  • the crystallization speed is increased in the state of oxygen deficiency, oxygen vacancies are generated during crystallization, and crystal transition occurs starting from the vacancies, and it may be easy to generate radial crystals instead of facets.
  • the crystallization rate may be set lower than the oxygen diffusion rate. That is, the rate of temperature increase between 150 ° C. and 250 ° C. at which crystallization begins to proceed is preferably 20 ° C./min or less, more preferably 15 ° C./min or less, more preferably 10 ° C./min or less. The temperature rising rate is more preferable. Thereby, since the crystallization speed can be made slower than the oxygen diffusion speed, faceted crystals can be easily obtained.
  • the lower limit of the rate of temperature rise is preferably 2 ° C./min or more, more preferably 3 ° C./min or more. If it is less than 1 ° C./minute, it takes too much heating time and is not economical. It is preferable not to directly put the substrate into a furnace having a temperature of 250 ° C. or higher, but to put the substrate into a furnace having a temperature of 150 ° C. or lower and raise the temperature to 250 ° C. at the above temperature rising rate. A more preferable facet-like crystal can be obtained by setting the temperature rising rate of 150 ° C. or more and 250 ° C. or less within the above range.
  • Said manufacturing method can be implemented as follows, for example. That is, (1) without introducing or reducing impurities such as water, the oxide semiconductor thin film containing indium oxide as a main component is in a low oxygen state (for example, an oxygen concentration of more than 0% by volume and 10% by volume or less). ) (Oxide semiconductor thin film forming step). (2) The oxide semiconductor thin film is reduced under reduced pressure (for example, 1 ⁇ 10 ⁇ 4 Pa or more and 1 ⁇ 10 ⁇ 2 Pa or less) as part of the step of forming the protective film without performing the heat treatment in the oxidizing atmosphere.
  • reduced pressure for example, 1 ⁇ 10 ⁇ 4 Pa or more and 1 ⁇ 10 ⁇ 2 Pa or less
  • the rate of temperature increase is, for example, 5 ° C./min or more and 50 ° C./min or less
  • the carrier density in the oxide semiconductor thin film is increased and the temperature is increased to a predetermined temperature (for example, 250 ° C. or more and 350 ° C. or less).
  • a protective film is formed by CVD, whereby an oxide semiconductor film with a high carrier density is formed (protective film forming step).
  • Heat treatment is performed (heat treatment step).
  • a thin film transistor (TFT) in one embodiment of the present invention includes a source electrode and a drain electrode, a gate electrode, a gate insulating film, a protective insulating film, and an oxide semiconductor layer.
  • the oxide semiconductor layer is located between the gate insulating film and the protective insulating film, and includes the above-described crystalline oxide semiconductor thin film according to one embodiment of the present invention.
  • a conventionally known TFT structure can be employed in one embodiment of the present invention.
  • the TFT in one embodiment of the present invention can be manufactured by employing the method for manufacturing a stacked body in one embodiment of the present invention. That is, an oxide semiconductor layer is formed by sputtering using a sputtering target containing indium oxide as a main component and using one or more gases selected from the group consisting of argon and oxygen substantially free of impurity gas as a sputtering gas. Forming a protective insulating film on the oxide semiconductor layer without performing heat treatment in an oxidizing atmosphere on the oxide semiconductor layer, and forming the oxide semiconductor layer and the protective insulating film. It is a manufacturing method including the process of heat-processing to the laminated body containing.
  • the “oxide semiconductor thin film” according to the method for manufacturing a stacked body in one embodiment of the present invention corresponds to the “oxide semiconductor layer”, and the “protective layer” corresponds to the “protective insulating film”.
  • the source / drain electrodes, gate electrode, and gate insulating film can be formed by known materials and formation methods.
  • the crystalline oxide semiconductor thin film according to one embodiment of the present invention includes surface crystal grains having a single crystal orientation, and preferably a crystal whose surface crystal state is facet-like when observed by EBSD. Particles are observed. Further, the crystalline oxide semiconductor thin film according to one embodiment of the present invention has high carrier density and mobility. That is, the crystalline oxide semiconductor thin film has a high carrier density and mobility in the first place, and can stably suppress fluctuations in carrier density due to various loads (thermal load, oxidation load, reduction load, etc.) in the TFT manufacturing process. It is a highly functional oxide semiconductor thin film. By using such a crystalline oxide semiconductor thin film for an oxide semiconductor layer (channel layer) of a TFT, a TFT having high saturation mobility can be obtained.
  • the saturation mobility is preferably 100 cm 2 / V ⁇ sec or more, more preferably 150 cm 2 / V ⁇ sec or more, and further preferably 200 cm 2 / V ⁇ sec or more.
  • the saturation mobility is obtained from transfer characteristics when a drain voltage of 20 V is applied. Specifically, it can be calculated by creating a transfer characteristic Id-Vg graph, calculating the transconductance (Gm) of each Vg, and obtaining the saturation mobility by the equation of the saturation region.
  • a current Id is a current between the source and drain electrodes
  • Vg is a gate voltage when a voltage Vd is applied between the source and drain electrodes.
  • the crystalline oxide semiconductor thin film according to one embodiment of the present invention has an ohmic electrode such as indium metal, ITO, or IZO disposed on one surface, and a metal or carbide such as molybdenum or titanium on the other surface.
  • ohmic electrode such as indium metal, ITO, or IZO
  • a metal or carbide such as molybdenum or titanium on the other surface.
  • a Schottky barrier diode can also be configured by disposing Schottky electrodes such as silicide.
  • the TFT in one embodiment of the present invention is preferably a high-speed response type.
  • An evaluation method for determining whether or not the TFT is a high-speed response type TFT will be described in Examples.
  • the shape of the thin film transistor of one embodiment of the present invention is not particularly limited, but a back channel etch transistor, an etch stopper transistor, a top gate transistor, and the like are preferable.
  • the thin film transistor 100 includes a silicon wafer 20, a gate insulating film 30, an oxide semiconductor thin film 40, a source electrode 50, a drain electrode 60, and interlayer insulating films 70 and 70A.
  • the silicon wafer 20 is a gate electrode, and is provided on the gate insulating film 30 so as to face the oxide semiconductor thin film 40 with the gate insulating film 30 interposed therebetween.
  • the gate insulating film 30 is an insulating film that blocks conduction between the gate electrode and the oxide semiconductor thin film 40, and is provided on the silicon wafer 20 and provided on one surface of the oxide semiconductor thin film 40.
  • the oxide semiconductor thin film 40 is a channel layer and is provided on the gate insulating film 30.
  • the oxide semiconductor thin film 40 the crystalline oxide semiconductor thin film according to one embodiment of the present invention is used.
  • the source electrode 50 and the drain electrode 60 are conductive terminals for allowing the source current and the drain current to flow through the oxide semiconductor thin film 40, and are provided so as to be in contact with the vicinity of both ends of the oxide semiconductor thin film 40. It is electrically connected to the thin film 40.
  • the interlayer insulating film 70 is an insulating film that blocks conduction other than the contact portion between the source electrode 50 and the drain electrode 60 and the oxide semiconductor thin film 40.
  • the interlayer insulating film 70 ⁇ / b> A is an insulating film that blocks conduction other than the contact portion between the source electrode 50 and the drain electrode 60 and the oxide semiconductor thin film 40.
  • the interlayer insulating film 70 ⁇ / b> A is also an insulating film that blocks conduction between the source electrode 50 and the drain electrode 60.
  • the interlayer insulating film 70A is also a channel layer protective layer.
  • the structure of the thin film transistor 100 ⁇ / b> A is the same as that of the thin film transistor 100, but the source electrode 50 and the drain electrode 60 are provided in contact with both the gate insulating film 30 and the oxide semiconductor thin film 40.
  • the point is different.
  • an interlayer insulating film 70B is integrally provided so as to cover the gate insulating film 30, the oxide semiconductor thin film 40, the source electrode 50, and the drain electrode 60.
  • the material for forming the drain electrode 60, the source electrode 50, and the gate electrode is not particularly limited, and a commonly used material can be arbitrarily selected.
  • a silicon wafer is used as a substrate, and the silicon wafer also acts as an electrode, but the electrode material is not limited to silicon.
  • transparent electrodes such as indium tin oxide (ITO), indium zinc oxide (IZO), ZnO, and SnO 2 , metal electrodes such as Al, Ag, Cu, Cr, Ni, Mo, Au, Ti, and Ta, Alternatively, a metal electrode or a laminated electrode of an alloy containing these can be used.
  • a gate electrode may be formed on a substrate such as glass.
  • the material for forming the interlayer insulating films 70, 70A, and 70B is not particularly limited, and a generally used material can be arbitrarily selected.
  • Interlayer insulating film 70 and 70A, as a material for forming a 70B specifically, for example, SiO 2, SiN x, Al 2 O 3, Ta 2 O 5, TiO 2, MgO, ZrO 2, CeO 2, K 2 O, Li 2 O, Na 2 O, Rb 2 O, Sc 2 O 3 , Y 2 O 3 , HfO 2 , CaHfO 3 , PbTiO 3 , BaTa 2 O 6 , SrTiO 3 , Sm 2 O 3 , AlN, etc.
  • Compounds can be used.
  • the thin film transistor according to one embodiment of the present invention is a back channel etch type (bottom gate type)
  • a protective film over the drain electrode, the source electrode, and the channel layer.
  • the durability is easily improved even when the TFT is driven for a long time.
  • a gate insulating film is formed on a channel layer.
  • the protective film or the insulating film can be formed by, for example, CVD, but at that time, the process may be performed at a high temperature.
  • the protective film or the insulating film often contains an impurity gas immediately after film formation, and it is preferable to perform heat treatment (annealing treatment). By removing the impurity gas by heat treatment, a stable protective film or insulating film is formed, and a highly durable TFT element can be easily formed.
  • the influence of the temperature in the CVD process and the subsequent heat treatment are less affected, so even when a protective film or an insulating film is formed, The stability of TFT characteristics can be improved.
  • the threshold voltage (Vth) is preferably ⁇ 3.0 V or more and 3.0 V or less, more preferably ⁇ 2.0 V or more and 2.0 V or less, and further preferably ⁇ 1.0 V or more and 1.0 V or less.
  • the threshold voltage (Vth) is ⁇ 3.0 V or higher, a high mobility thin film transistor can be formed.
  • the threshold voltage (Vth) is 3.0 V or less, a thin film transistor with a small off-state current and a large on-off ratio can be obtained.
  • the on-off ratio is preferably 10 6 or more and 10 12 or less, more preferably 10 7 or more and 10 11 or less, and even more preferably 10 8 or more and 10 10 or less.
  • the on-off ratio is 10 6 or more
  • the liquid crystal display can be driven.
  • the on-off ratio is 10 12 or less
  • an organic EL with a large contrast can be driven.
  • the off current can be reduced to 10 -12 A or less, and when used for a transfer transistor or a reset transistor of a CMOS image sensor, an image holding time can be lengthened and sensitivity can be improved.
  • Off current value is preferably 10 -10 A or less, more preferably 10 -11 A or less, more preferably 10 -12 A or less.
  • the organic EL with a large contrast can be driven.
  • the defect density of the amorphous oxide semiconductor thin film according to one embodiment of the present invention used for the semiconductor layer of the thin film transistor is preferably 5.0 ⁇ 10 16 cm ⁇ 3 or less, and 1.0 ⁇ 10 16 cm ⁇ 3 or less. Is more preferable.
  • the defect density By reducing the defect density, the mobility of the thin film transistor is further increased, the stability during light irradiation and the stability against heat are increased, and the TFT is stably operated.
  • the oxide semiconductor thin film according to one embodiment of the present invention can also be used for a quantum tunnel field effect transistor (FET).
  • FET quantum tunnel field effect transistor
  • FIG. 5 is a schematic diagram (longitudinal sectional view) of a quantum tunnel field effect transistor (FET) according to one embodiment of the present invention.
  • the quantum tunnel field effect transistor 501 includes a p-type semiconductor layer 503, an n-type semiconductor layer 507, a gate insulating film 509, a gate electrode 511, a source electrode 513, and a drain electrode 515.
  • the p-type semiconductor layer 503, the n-type semiconductor layer 507, the gate insulating film 509, and the gate electrode 511 are stacked in this order.
  • the source electrode 513 is provided on the p-type semiconductor layer 503.
  • the drain electrode 515 is provided on the n-type semiconductor layer 507.
  • the p-type semiconductor layer 503 is a p-type IV group semiconductor layer, and here is a p-type silicon layer.
  • the n-type semiconductor layer 507 is an n-type oxide semiconductor thin film used for the image sensor according to one embodiment of the present invention.
  • the source electrode 513 and the drain electrode 515 are conductive films.
  • an insulating layer may be formed on the p-type semiconductor layer 503.
  • the p-type semiconductor layer 503 and the n-type semiconductor layer 507 are connected via a contact hole that is a region in which an insulating layer is partially opened.
  • the quantum tunnel field effect transistor 501 may include an interlayer insulating film covering the upper surface thereof.
  • the quantum tunnel field effect transistor 501 is a quantum tunnel field effect transistor that performs current switching, in which a current that tunnels an energy barrier formed by the p-type semiconductor layer 503 and the n-type semiconductor layer 507 is controlled by the voltage of the gate electrode 511. (FET).
  • FET field effect transistor
  • FIG. 6 shows a schematic diagram (longitudinal sectional view) of a quantum tunnel field effect transistor 501A according to another embodiment.
  • the configuration of the quantum tunnel field effect transistor 501A is the same as that of the quantum tunnel field effect transistor 501 except that a silicon oxide layer 505 is formed between the p-type semiconductor layer 503 and the n-type semiconductor layer 507.
  • the presence of the silicon oxide layer can reduce the off current.
  • the thickness of the silicon oxide layer 505 is preferably 10 nm or less. By setting it to 10 nm or less, it is possible to prevent the tunnel current from flowing, it is difficult to form the formed energy barrier or the barrier height is changed, and the tunneling current is reduced or changed. I can prevent it.
  • FIG. 7 shows a TEM photograph of a portion where the silicon oxide layer 505 is formed between the p-type semiconductor layer 503 and the n-type semiconductor layer 507.
  • the n-type semiconductor layer 507 is an n-type oxide semiconductor.
  • the oxide semiconductor included in the n-type semiconductor layer 507 may be amorphous. Since it is amorphous, it can be etched with an organic acid such as oxalic acid, the difference in etching rate with other layers becomes large, and etching can be performed satisfactorily without affecting metal layers such as wiring.
  • the oxide semiconductor included in the n-type semiconductor layer 507 may be crystalline. By being crystalline, the band gap becomes larger than that in the case of amorphous, and the off-current can be reduced. Since the work function can also be increased, the current tunneling through the energy barrier formed by the p-type IV group semiconductor material and the n-type semiconductor layer 507 can be easily controlled.
  • the manufacturing method of the quantum tunnel field effect transistor 501 is not specifically limited, the following method can be illustrated.
  • an insulating film 505A is formed on the p-type semiconductor layer 503, and a part of the insulating film 505A is opened by etching or the like to form a contact hole 505B.
  • an n-type semiconductor layer 507 is formed over the p-type semiconductor layer 503 and the insulating film 505A. At this time, the p-type semiconductor layer 503 and the n-type semiconductor layer 507 are connected through the contact hole 505B.
  • a gate insulating film 509 and a gate electrode 511 are formed in this order on the n-type semiconductor layer 507.
  • an interlayer insulating film 519 is provided so as to cover the insulating film 505A, the n-type semiconductor layer 507, the gate insulating film 509, and the gate electrode 511.
  • a part of the insulating film 505A and the interlayer insulating film 519 over the p-type semiconductor layer 503 is opened to form a contact hole 519A, and a source electrode 513 is provided in the contact hole 519A.
  • a part of the gate insulating film 509 and the interlayer insulating film 519 over the n-type semiconductor layer 507 is opened to form a contact hole 519B, and a drain electrode 515 is formed in the contact hole 519B.
  • the quantum tunnel field effect transistor 501 can be manufactured by the above procedure.
  • the n-type semiconductor layer 507 is formed over the p-type semiconductor layer 503, heat treatment is performed at a temperature of 150 ° C. to 600 ° C., whereby the p-type semiconductor layer 503 is interposed between the p-type semiconductor layer 503 and the n-type semiconductor layer 507.
  • a silicon oxide layer 505 can be formed. By adding this step, the quantum tunnel field effect transistor 501A can be manufactured.
  • the TFT in one embodiment of the present invention can be suitably used for display devices such as solar cells, liquid crystals, organic electroluminescence, and inorganic electroluminescence, and electronic devices such as power semiconductor devices and touch panels. It can be suitably used for equipment.
  • display devices such as solar cells, liquid crystals, organic electroluminescence, and inorganic electroluminescence
  • electronic devices such as power semiconductor devices and touch panels. It can be suitably used for equipment.
  • an in-vehicle display device for example, an in-vehicle display device such as an instrument panel using a TFT according to one embodiment of the present invention can be given.
  • the thin film transistor according to one embodiment of the present invention can be applied to various integrated circuits such as a field-effect transistor, a logic circuit, a memory circuit, and a differential amplifier circuit, and can be applied to an electronic device or the like. Further, the thin film transistor according to one embodiment of the present invention can be applied to a static induction transistor, a Schottky barrier transistor, a Schottky diode, and a resistance element in addition to a field effect transistor.
  • the thin film transistor according to one embodiment of the present invention can be favorably used for a display device such as a vehicle-mounted display device, a solid-state imaging element, or the like. The case where the thin film transistor according to one embodiment of the present invention is used for a display device and a solid-state imaging element is described below.
  • FIG. 9A is a top view of a display device of one embodiment of the present invention.
  • FIG. 9B is a circuit diagram illustrating a circuit of a pixel portion in the case where a liquid crystal element is applied to the pixel portion of the display device of one embodiment of the present invention.
  • FIG. 9C is a circuit diagram illustrating a circuit of the pixel portion in the case where an organic EL element is applied to the pixel portion of the display device of one embodiment of the present invention.
  • a thin film transistor according to one embodiment of the present invention can be used for a transistor provided in the pixel portion. Since the thin film transistor according to one embodiment of the present invention can easily be an n-channel transistor, part of a driver circuit that can be formed using an n-channel transistor is formed over the same substrate as the transistor in the pixel portion. By using the thin film transistor described in this embodiment for a pixel portion or a driver circuit, a highly reliable display device can be provided.
  • FIG. 9A An example of a top view of the active matrix display device is shown in FIG. 9A.
  • a pixel portion 301, a first scan line driver circuit 302, a second scan line driver circuit 303, and a signal line driver circuit 304 are formed over the substrate 300 of the display device.
  • a plurality of signal lines are extended from the signal line driver circuit 304, and a plurality of scan lines are extended from the first scan line driver circuit 302 and the second scan line driver circuit 303.
  • Pixels each having a display element are provided in a matrix in the intersection region between the scanning line and the signal line.
  • the substrate 300 of the display device is connected to a timing control circuit (also referred to as a controller or a control IC) through a connection unit such as an FPC (Flexible Printed Circuit).
  • a timing control circuit also referred to as a controller or a control IC
  • connection unit such as an FPC (Flexible Printed Circuit).
  • the first scan line driver circuit 302, the second scan line driver circuit 303, and the signal line driver circuit 304 are formed over the same substrate 300 as the pixel portion 301. For this reason, the number of components such as a drive circuit provided outside is reduced, so that cost can be reduced. Further, when the drive circuit is provided outside the substrate 300, it is necessary to extend the wiring, and the number of connections between the wirings increases. In the case where a driver circuit is provided over the same substrate 300, the number of connections between the wirings can be reduced, and reliability or yield can be improved.
  • FIG. 9B shows an example of the circuit configuration of the pixel.
  • a circuit of a pixel portion that can be applied to the pixel portion of a VA liquid crystal display device is shown.
  • This circuit of the pixel portion can be applied to a configuration having a plurality of pixel electrodes in one pixel. Each pixel electrode is connected to a different transistor, and each transistor is configured to be driven by a different gate signal. As a result, signals applied to the individual pixel electrodes of the multi-domain designed pixel can be controlled independently.
  • the gate wiring 312 of the transistor 316 and the gate wiring 313 of the transistor 317 are separated so that different gate signals can be given.
  • the source or drain electrode 314 functioning as a data line is used in common by the transistor 316 and the transistor 317.
  • a transistor according to one embodiment of the present invention can be used. Thereby, a highly reliable liquid crystal display device can be provided.
  • the first pixel electrode is electrically connected to the transistor 316, and the second pixel electrode is electrically connected to the transistor 317.
  • the first pixel electrode and the second pixel electrode are separated.
  • the shapes of the first pixel electrode and the second pixel electrode are not particularly limited.
  • the first pixel electrode may be V-shaped.
  • the gate electrode of the transistor 316 is connected to the gate wiring 312 and the gate electrode of the transistor 317 is connected to the gate wiring 313. Different gate signals are supplied to the gate wiring 312 and the gate wiring 313, whereby the operation timings of the transistor 316 and the transistor 317 are made different so that the alignment of the liquid crystal can be controlled.
  • a storage capacitor may be formed using the capacitor wiring 310, a gate insulating film functioning as a dielectric, and a capacitor electrode electrically connected to the first pixel electrode or the second pixel electrode.
  • the multi-domain structure includes a first liquid crystal element 318 and a second liquid crystal element 319 in one pixel.
  • the first liquid crystal element 318 includes a first pixel electrode, a counter electrode, and a liquid crystal layer therebetween
  • the second liquid crystal element 319 includes a second pixel electrode, a counter electrode, and a liquid crystal layer therebetween.
  • the pixel portion is not limited to the configuration shown in FIG. 9B.
  • a switch, a resistor, a capacitor, a transistor, a sensor, or a logic circuit may be added to the pixel portion illustrated in FIG. 9B.
  • FIG. 9C shows another example of the circuit configuration of the pixel.
  • a structure of a pixel portion of a display device using an organic EL element is shown.
  • FIG. 9C is a diagram illustrating an example of a circuit of the applicable pixel unit 320.
  • the oxide semiconductor film according to one embodiment of the present invention can be used for a channel formation region of an n-channel transistor.
  • Digital time grayscale driving can be applied to the circuit of the pixel portion.
  • a thin film transistor according to one embodiment of the present invention can be used. Thereby, an organic EL display device with high reliability can be provided.
  • the circuit configuration of the pixel portion is not limited to the configuration illustrated in FIG. 9C.
  • a switch, a resistor, a capacitor, a sensor, a transistor, or a logic circuit may be added to the circuit of the pixel portion illustrated in FIG. 9C.
  • the above is the description in the case where the thin film transistor according to one embodiment of the present invention is used for a display device.
  • a CMOS (Complementary Metal Oxide Semiconductor) image sensor is a solid-state imaging device that holds a potential in a signal charge storage unit and outputs the potential to a vertical output line via an amplification transistor. If there is a leak current in the reset transistor and / or the transfer transistor included in the CMOS image sensor, charging or discharging occurs due to the leak current, and the potential of the signal charge storage portion changes. When the potential of the signal charge storage portion changes, the potential of the amplification transistor also changes, resulting in a value that deviates from the original potential, and the captured image deteriorates.
  • CMOS Complementary Metal Oxide Semiconductor
  • the thin film transistor according to one embodiment of the present invention is applied to a reset transistor and a transfer transistor of a CMOS image sensor will be described.
  • the amplification transistor either a thin film transistor or a bulk transistor may be applied.
  • FIG. 10 is a diagram illustrating an example of a pixel configuration of a CMOS image sensor.
  • a pixel includes a photodiode 3002, which is a photoelectric conversion element, a transfer transistor 3004, a reset transistor 3006, an amplification transistor 3008, and various wirings.
  • a plurality of pixels are arranged in a matrix to form a sensor.
  • a selection transistor electrically connected to the amplification transistor 3008 may be provided.
  • “OS” described in the transistor symbol indicates an oxide semiconductor (Oxide Semiconductor), and “Si” indicates silicon, which is a preferable material when applied to each transistor. The same applies to the subsequent drawings.
  • the photodiode 3002 is connected to the source side of the transfer transistor 3004, and a signal charge accumulation unit 3010 (FD: also called floating diffusion) is formed on the drain side of the transfer transistor 3004.
  • the signal charge storage unit 3010 is connected to the source of the reset transistor 3006 and the gate of the amplification transistor 3008.
  • the reset power line 3110 can be deleted.
  • the oxide semiconductor film of the present invention may be used for the photodiode 3002, and the same material as the oxide semiconductor film used for the transfer transistor 3004 and the reset transistor 3006 may be used. The above is the description in the case where the thin film transistor according to one embodiment of the present invention is used for a solid-state imaging element.
  • Example 1 Manufacture of TFT> A thin film transistor was manufactured through the following steps. (1) Formation of oxide semiconductor layer 92% by mass of indium oxide (90.4 atomic% of indium element), 5% by mass of gallium oxide (7.3 atomic% of gallium element), 3% by mass of samarium oxide (2. 50 nm oxide by sputtering through a metal mask on a silicon wafer (gate electrode) with a thermal oxide film (gate insulating film) using a sputtering target obtained from a raw material mixture in a ratio of 3 atomic%) A semiconductor thin film (oxide semiconductor layer) was formed. The film forming conditions are as shown in Table 1. As a sputtering gas, a mixed gas of high purity argon and high purity oxygen (impurity gas concentration: 0.01% by volume) was used.
  • a sputtering gas a mixed gas of high purity argon and high purity oxygen (impurity gas concentration: 0.01% by volume) was used.
  • Titanium metal was formed by sputtering on the obtained oxide semiconductor layer using a metal mask to provide a source electrode and a drain electrode.
  • an SiO 2 film (protective insulating film (interlayer insulating film) having a film thickness of 100 nm at a substrate temperature of 300 ° C. by chemical vapor deposition (CVD). )
  • CVD chemical vapor deposition
  • the atmosphere is depressurized to 10 ⁇ 3 Pa
  • the temperature is increased to the substrate temperature (300 ° C.) at a temperature increase rate of 20 ° C./min, and then a film forming gas (SiH 4 / N 2 , N 2 O , N 2 gas) was allowed to flow at a pressure of 66 Pa to form a SiO 2 film.
  • an SiO 2 film was formed on the oxide semiconductor thin film of the Hall effect measurement sample in the same manner as in “(3) Formation of protective insulating film” in ⁇ TFT production>.
  • the sample was set in a Hall effect / specific resistance measuring apparatus (“ResiTest 8300 type” manufactured by Toyo Corporation), and the Hall effect was evaluated at room temperature to determine the carrier density and mobility. The results are shown in “After SiO 2 film formation” in “Hall effect measurement” in “Characteristics of oxide semiconductor thin film” in Table 1.
  • the surface morphology of the oxide semiconductor thin film after the heat treatment was confirmed by EBSD and the ferret diameter was measured, facet-like crystal particles having an average crystal grain size (grain size) of 2 ⁇ m or more were confirmed.
  • the average crystal grain size is determined by measuring the grain size of facet-like crystal grains observed within a 5 ⁇ m ⁇ 5 ⁇ m frame centered on the central portion (intersection of diagonal lines) of the oxide semiconductor thin film, and calculating the arithmetic average value of these Calculated and determined.
  • the ratio of the faceted crystal particles on the surface of the oxide semiconductor thin film is more than 95%, and the particles other than the faceted crystal particles are radial particles and microcrystalline particles present in the grain boundary. .
  • the ratio of the facet-like crystal particles is determined from the surface image of the oxide semiconductor thin film obtained by EBSD, and the crystal particles represented by a single color are determined as facet-like crystal particles, and the facet-like crystal particles occupy the surface image It calculated by calculating
  • TFT> ⁇ Characteristic evaluation of TFT> The following evaluation was performed about TFT obtained by ⁇ manufacture of TFT>. The results are shown in Table 1.
  • the field-effect mobility ⁇ in the linear region is desirably obtained from transfer characteristics when 0.1 V is applied to the drain voltage. Specifically, a graph of the transfer characteristic Id-Vg is created, the transconductance (Gm) of each Vg is calculated, and the field-effect mobility is derived from the linear region equation. Gm is represented by ⁇ (Id) / ⁇ (Vg). Vg is applied from ⁇ 15 to 20 V, and the maximum mobility in the range is defined as field effect mobility. Id is a current between the source and drain electrodes, and Vg is a gate voltage when a voltage Vd is applied between the source and drain electrodes.
  • the equation for the saturation region generally holds when Vg ⁇ Vd, and it is necessary to apply a sufficiently large Vd and measure the Vg dependency. Which affects device destruction. Accordingly, in order to discuss the mobility under a low gate voltage, it is desirable to discuss the mobility in the linear region (Vg> Vd) when Vd is small. Therefore, the field effect mobility in the linear region was evaluated by this method.
  • the voltage acts as the gate voltage of the oxide semiconductor, so that high field-effect mobility can be obtained at a low gate voltage. Becomes important.
  • Example 2 As a sputtering target, obtained from a raw material mixture of indium oxide 90 mass% (indium element 88.8 at%), gallium oxide 5 mass% (gallium element 7.3 at%): samarium oxide 5 mass% (samarium element 3.9 at%).
  • a TFT was manufactured and evaluated in the same manner as in Example 1 except that the obtained sputtering target was used, and an oxide semiconductor thin film was manufactured and evaluated. The results are shown in “Characteristics of TFT” and “Characteristics as fast response TFT” in Table 1.
  • a thin film transistor was manufactured through the following steps. (1) Formation of oxide semiconductor layer Using a sputtering target having the composition shown in Tables 1 and 2, sputtering is performed on a silicon wafer (gate electrode) with a thermal oxide film (gate insulating film) through a metal mask. A 50 nm oxide semiconductor thin film (oxide semiconductor layer) was formed. The film forming conditions are as shown in Tables 1 and 2.
  • Protective Insulating Film A SiO 2 film (protective insulating film (interlayer insulating film) having a film thickness of 100 nm and a substrate temperature of 300 ° C. is formed on the heat-treated oxide semiconductor layer by chemical vapor deposition (CVD). )) Formed. Specific conditions are the same as those in the first embodiment.
  • a contact hole was formed in the protective insulating film, and titanium metal was formed by sputtering on the protective insulating film using a metal mask to provide a source electrode and a drain electrode. After that, heat treatment was performed according to “heat treatment conditions after film formation of protective insulating film” in Tables 1 and 2 to complete the TFT.
  • an SiO 2 film was formed on the oxide semiconductor thin film of the Hall effect measurement sample in the same manner as in “(3) Formation of protective insulating film” in ⁇ TFT production>.
  • the sample was set in a Hall effect / specific resistance measuring apparatus (“ResiTest 8300 type” manufactured by Toyo Corporation), and the Hall effect was evaluated at room temperature to determine the carrier density and mobility. The results are shown in “After film formation of SiO 2 film” in “Hall effect measurement” in “Characteristics of oxide semiconductor thin film” in Tables 1 and 2.
  • the heat treatment is performed in the same manner as the heat treatment described in “(4) Formation of source / drain electrodes” in ⁇ TFT production>, and the obtained sample is evaluated for the Hall effect in the same manner as described above.
  • the mobility was determined. The results are shown in “After heat treatment after deposition of SiO 2 film” in “Hall effect measurement” in “Characteristics of oxide semiconductor thin film” in Tables 1 and 2.
  • the numerical value indicated by “mass%” indicates the mass ratio (preparation amount) of indium oxide, gallium oxide and samarium oxide, and “at%”.
  • the numerical value shown shows the atomic ratio of an indium element, a gallium element, and a samarium element.
  • Example 1 and Example 2 are examples in which no heat treatment was performed after the oxide semiconductor layer was formed. Including surface crystal grains having a single crystal orientation, the band gap was 3.90 eV or more. Comparative Examples 1 to 4 are examples in which heat treatment was performed after the formation of the oxide semiconductor layer, and the band gap was less than 3.90 eV.
  • the crystalline oxide semiconductor thin film of the present invention can be suitably used for display devices such as solar cells, liquid crystal elements, organic electroluminescence elements, inorganic electroluminescence elements, electronic devices such as power semiconductor elements, touch panels, and the like. It can be suitably used for electronic devices such as display devices.
  • Oxide sintered body 3 Backing plate 20: Silicon wafer 30: Gate insulating film 40: Oxide semiconductor thin film 50: Source electrode 60: Drain electrode 70: Interlayer insulating film 70A: Interlayer insulating film 70B: Interlayer insulating film 100 : Thin film transistor 100A: Thin film transistor 300: Substrate 301: Pixel unit 302: First scanning line driving circuit 303: Second scanning line driving circuit 304: Signal line driving circuit 310: Capacitor wiring 312: Gate wiring 313: Gate wiring 314: Drain electrode 316: Transistor 317: Transistor 318: First liquid crystal element 319: Second liquid crystal element 320: Pixel portion 321: Switching transistor 322: Driving transistor 3002: Photodiode 3004: Transfer transistor 3006: Reset transistor Star 3008: amplification transistor 3010: signal charge storage unit 3100: power supply line 3110: reset power supply line 3120: vertical output line

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Abstract

L'invention concerne une couche mince semi-conductrice d'oxyde cristalline qui comprend de l'oxyde d'indium comme composant principal. Cette couche comporte des particules de cristal de surface ayant une orientation de monocristal, et présente une bande interdite égale ou supérieure à 3,90 eV.
PCT/JP2018/002432 2017-02-01 2018-01-26 Couche mince semi-conductrice d'oxyde cristalline, procédé de fabrication de stratifié, transistor à couches minces, procédé de fabrication de transistor à couches minces, dispositif électronique et dispositif d'affichage embarqué WO2018143073A1 (fr)

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CN114438449A (zh) * 2021-12-30 2022-05-06 中国科学院宁波材料技术与工程研究所 一种金属辅助氧化镓结晶薄膜及其制备方法
WO2023189004A1 (fr) * 2022-03-30 2023-10-05 株式会社ジャパンディスプレイ Film semi-conducteur d'oxyde, transistor à couches minces et dispositif électronique
WO2023189003A1 (fr) * 2022-03-30 2023-10-05 株式会社ジャパンディスプレイ Transistor à couches minces et dispositif électronique
WO2023189002A1 (fr) * 2022-03-30 2023-10-05 株式会社ジャパンディスプレイ Transistor à couches minces et dispositif électronique
WO2024029438A1 (fr) * 2022-08-01 2024-02-08 株式会社ジャパンディスプレイ Film semi-conducteur d'oxyde, transistor à couches minces, et appareil électronique
WO2024029437A1 (fr) * 2022-08-01 2024-02-08 株式会社ジャパンディスプレイ Transistor à couches minces, et appareil électronique

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CN113614276B (zh) * 2019-03-28 2022-10-11 出光兴产株式会社 晶体氧化物薄膜、层叠体以及薄膜晶体管
CN114438449A (zh) * 2021-12-30 2022-05-06 中国科学院宁波材料技术与工程研究所 一种金属辅助氧化镓结晶薄膜及其制备方法
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WO2023189003A1 (fr) * 2022-03-30 2023-10-05 株式会社ジャパンディスプレイ Transistor à couches minces et dispositif électronique
WO2023189002A1 (fr) * 2022-03-30 2023-10-05 株式会社ジャパンディスプレイ Transistor à couches minces et dispositif électronique
WO2024029438A1 (fr) * 2022-08-01 2024-02-08 株式会社ジャパンディスプレイ Film semi-conducteur d'oxyde, transistor à couches minces, et appareil électronique
WO2024029437A1 (fr) * 2022-08-01 2024-02-08 株式会社ジャパンディスプレイ Transistor à couches minces, et appareil électronique

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