WO2023189003A1 - Transistor à couches minces et dispositif électronique - Google Patents

Transistor à couches minces et dispositif électronique Download PDF

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WO2023189003A1
WO2023189003A1 PCT/JP2023/006037 JP2023006037W WO2023189003A1 WO 2023189003 A1 WO2023189003 A1 WO 2023189003A1 JP 2023006037 W JP2023006037 W JP 2023006037W WO 2023189003 A1 WO2023189003 A1 WO 2023189003A1
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oxide semiconductor
crystal orientation
crystal
thin film
film transistor
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PCT/JP2023/006037
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English (en)
Japanese (ja)
Inventor
創 渡壁
将志 津吹
俊成 佐々木
尊也 田丸
絵美 川嶋
勇輝 霍間
大地 佐々木
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株式会社ジャパンディスプレイ
出光興産株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • One embodiment of the present invention relates to a thin film transistor including an oxide semiconductor film. Further, one embodiment of the present invention relates to an electronic device including a thin film transistor.
  • a thin film transistor including such an oxide semiconductor film has a simple structure and can be formed using a low-temperature process, like a thin film transistor including an amorphous silicon film. Further, it is known that a thin film transistor including an oxide semiconductor film has higher mobility than a thin film transistor including an amorphous silicon film.
  • JP 2021-141338 Publication Japanese Patent Application Publication No. 2014-099601 JP 2021-153196 Publication Japanese Patent Application Publication No. 2018-006730 Japanese Patent Application Publication No. 2016-184771 JP 2021-108405 Publication
  • one of the objects of an embodiment of the present invention is to provide a thin film transistor including an oxide semiconductor film having a novel crystal structure. Further, one embodiment of the present invention relates to an electronic device including a thin film transistor.
  • a thin film transistor includes a substrate, a crystalline oxide semiconductor layer provided on the substrate, a gate electrode provided to overlap with the oxide semiconductor layer, and an oxide semiconductor layer.
  • an insulating layer provided between the layer and the gate electrode, and the oxide semiconductor layer has a crystal orientation of ⁇ 001> and a crystal orientation of ⁇ 101, respectively, which are obtained by an EBSD (electron beam backscatter diffraction) method. >, and a crystal orientation ⁇ 111>, and the crystal orientation difference with respect to the normal direction of the surface of the substrate is 0° or more and 15° or less.
  • the occupancy of crystal orientation ⁇ 111> is larger than the occupancy of crystal orientation ⁇ 001> and the occupancy of crystal orientation ⁇ 101>.
  • An electronic device includes the thin film transistor described above.
  • 1 is an IPF map of an oxide semiconductor film (Example 1) according to an embodiment of the present invention.
  • 1 is an IPF map of an oxide semiconductor film (Example 1) according to an embodiment of the present invention.
  • 1 is a map showing the distribution of GOS in an oxide semiconductor film (Example 1) according to an embodiment of the present invention.
  • 3 is an IPF map of an oxide semiconductor film (Example 2) according to an embodiment of the present invention.
  • 3 is an IPF map of an oxide semiconductor film (Example 2) according to an embodiment of the present invention.
  • 2 is a map showing the distribution of GOS in an oxide semiconductor film (Example 2) according to an embodiment of the present invention.
  • 1 is a cross-sectional view schematically showing a thin film transistor according to an embodiment of the present invention.
  • 1 is a plan view schematically showing a thin film transistor according to an embodiment of the present invention.
  • 1 is a flowchart illustrating a method for manufacturing a thin film transistor according to an embodiment of the present invention.
  • 1 is a cross-sectional view showing a method for manufacturing a thin film transistor according to an embodiment of the present invention.
  • 1 is a cross-sectional view showing a method for manufacturing a thin film transistor according to an embodiment of the present invention.
  • 1 is a cross-sectional view showing a method for manufacturing a thin film transistor according to an embodiment of the present invention.
  • 1 is a cross-sectional view showing a method for manufacturing a thin film transistor according to an embodiment of the present invention.
  • 1 is a cross-sectional view showing a method for manufacturing a thin film transistor according to an embodiment of the present invention.
  • 1 is a cross-sectional view showing a method for manufacturing a thin film transistor according to an embodiment of the present invention.
  • 1 is a cross-sectional view showing a method for manufacturing a thin film transistor according to an embodiment of the present invention.
  • 1 is a cross-sectional STEM image of a thin film transistor according to an embodiment of the present invention.
  • 1 is a cross-sectional STEM image of a thin film transistor according to an embodiment of the present invention.
  • 1 is a schematic diagram showing an electronic device according to an embodiment of the present invention. It is an IPF map of a conventional oxide semiconductor film (comparative example). It is an IPF map of a conventional oxide semiconductor film (comparative example). It is a map showing the distribution of GOS of a conventional oxide semiconductor film (comparative example).
  • the direction from the substrate toward the oxide semiconductor layer is referred to as upward. Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as downward or downward.
  • the terms “upper” and “lower” are used in the description; however, for example, the substrate and the oxide semiconductor layer may be arranged so that the vertical relationship is reversed from that shown in the drawing.
  • the expression “an oxide semiconductor layer on a substrate” merely explains the vertical relationship between the substrate and the oxide semiconductor layer as described above; Other members may also be arranged.
  • Upper or lower refers to the stacking order in a structure in which multiple layers are stacked, and when expressed as a pixel electrode above a transistor, it means a positional relationship in which the transistor and pixel electrode do not overlap in plan view. You can. On the other hand, when expressed as a pixel electrode vertically above a transistor, it means a positional relationship in which the transistor and the pixel electrode overlap in plan view.
  • film and the term “layer” can be interchanged depending on the case.
  • Display device refers to a structure that displays images using an electro-optic layer.
  • the term display device may refer to a display panel that includes an electro-optic layer, or may refer to a structure in which display cells are equipped with other optical components (e.g., polarizing components, backlights, touch panels, etc.).
  • the "electro-optic layer” may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, unless a technical contradiction arises. Therefore, the embodiments to be described later will be explained by exemplifying a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer as display devices. It can be applied to a display device including an optical layer.
  • ⁇ includes A, B, or C
  • ⁇ includes any one of A, B, and C
  • ⁇ includes one selected from the group consisting of A, B, and C
  • ⁇ includes multiple combinations of A to C, unless otherwise specified.
  • these expressions do not exclude cases where ⁇ includes other elements.
  • the oxide semiconductor film according to this embodiment includes an indium (In) element and a metal (M) element other than indium element.
  • the composition ratio of the oxide semiconductor film it is preferable that the atomic ratio of indium element and metal elements other than indium element satisfies formula (1).
  • the ratio of indium element to all metal elements including indium element in the oxide semiconductor film is preferably 50% or more.
  • the crystal structure of the oxide semiconductor film preferably has a bixbite structure. By increasing the ratio of indium element, an oxide semiconductor film having a bixbite structure can be formed.
  • metal elements other than the indium element are not limited to one type of metal element.
  • the elements other than the indium element may include multiple types of metal elements.
  • the oxide semiconductor film can be formed using a sputtering method.
  • the composition of an oxide semiconductor film formed by sputtering depends on the composition of a sputtering target.
  • the sputtering target having the above-described composition, an oxide semiconductor film without any deviation in the composition of metal elements can be formed by sputtering. Therefore, the composition of the metal elements (for example, indium element and other metal elements) of the oxide semiconductor film may be the same as the composition of the metal elements of the sputtering target.
  • the composition of the metal element of the oxide semiconductor film can be specified based on the composition of the metal element of the sputtering target. Note that the oxygen element contained in the oxide semiconductor film changes depending on the sputtering process conditions and the like, so this is not the case.
  • composition of the metal element of the oxide semiconductor film can also be specified by fluorescent X-ray analysis, EPMA (Electron Probe Micro Analyzer) analysis, or the like. Furthermore, since the oxide semiconductor film has crystallinity, the composition of the metal element in the oxide semiconductor film can also be specified from the crystal structure and lattice constant using an XRD (X-ray diffraction) method.
  • XRD X-ray diffraction
  • the oxide semiconductor film according to this embodiment has crystallinity.
  • the crystal structure of the oxide semiconductor film is not particularly limited, but preferably has a bixbite structure.
  • the crystal structure of the oxide semiconductor film can be specified using an XRD method or an electron beam diffraction method.
  • the oxide semiconductor film according to this embodiment includes a plurality of crystal grains.
  • the present inventors discovered that the crystal grains of the oxide semiconductor film according to this embodiment have different characteristics from the crystal grains of conventional oxide semiconductor films. Specifically, the present inventors discovered an oxide semiconductor film having a novel crystal structure including crystal grains different from conventional crystal grains. An oxide semiconductor film having such a novel crystal structure can be measured using an electron beam backscatter diffraction (EBSD) method. Therefore, measurement of an oxide semiconductor film using the EBSD method will be described below.
  • EBSD electron beam backscatter diffraction
  • the EBSD method involves irradiating an object to be measured with an electron beam, analyzing the electron beam backscatter diffraction generated on each crystal plane of the crystal structure of the object, and determining the crystal structure in the measurement area of the object. It is an analytical method to measure The EBSD method analyzes data acquired from an EBSD detector attached to a scanning electron microscope (SEM) or transmission electron microscope (TEM) to determine the crystal grains or crystal orientation of an oxide semiconductor film in a measurement area. information can be obtained.
  • SEM scanning electron microscope
  • TEM transmission electron microscope
  • IPF map An IPF (Inverse Pole Figure) map is an image in which crystal orientations are color-coded according to a predetermined color key. In measurement using the EBSD method, information on crystal orientation can be acquired, so an IPF map can be created based on the acquired information on crystal orientation. In the IPF map, it is also possible to acquire the area of each color-coded region of multiple crystal orientations, calculate the ratio to the area of the entire measurement region (hereinafter referred to as "occupancy rate”), and compare quantitatively. .
  • the IPF map may be an image obtained by extracting data of measurement points where the crystal orientation difference with respect to the normal direction of the surface of the substrate (or the surface of the oxide semiconductor film) is within a predetermined range.
  • the predetermined range is 0° or more and 15° or less.
  • measurement points with crystal orientations that are significantly tilted from the normal direction of the substrate surface are excluded, so it is possible to exclude measurement points that have crystal orientations that are highly inclined from the normal direction of the substrate surface. Crystal orientation can be revealed. Therefore, in the IPF map from which data of specific measurement points are extracted, the occupancy of each of a plurality of crystal orientations can be compared, and the crystal orientation that is easily oriented can be specified more clearly.
  • the occupancy rate of crystal orientation ⁇ 111> is in the range where the crystal orientation difference with respect to the normal direction of the surface of the substrate is 0° or more and 15° or less. It is larger than the occupancy rate of crystal orientation ⁇ 001> and the occupancy rate of crystal orientation ⁇ 101>. Further, the occupancy rate of crystal orientation ⁇ 101> is larger than the occupancy rate of crystal orientation ⁇ 001>. In particular, in the oxide semiconductor film according to this embodiment, the occupancy rate of crystal orientation ⁇ 001> is significantly small at 5% or less, which is a feature not found in conventional oxide semiconductor films.
  • the total occupancy of the crystal orientation ⁇ 101> and the crystal orientation ⁇ 111> is 10 times or more the occupancy of the crystal orientation ⁇ 001>.
  • the total occupancy rate of crystal orientation ⁇ 101> and crystal orientation ⁇ 111> is less than 10 times the occupancy rate of crystal orientation ⁇ 001>.
  • the occupancy rate of crystal orientation ⁇ 101> is preferably four times or more as the occupancy rate of crystal orientation ⁇ 001>.
  • the occupancy rate of crystal orientation ⁇ 111> is preferably four times or more as the occupancy rate of crystal orientation ⁇ 001>.
  • the crystal orientation ⁇ 001> represents [001] and equivalent [100] and [010].
  • the crystal orientation ⁇ 101> represents [101] and equivalent [110] and [011].
  • the crystal orientation ⁇ 111> represents [111].
  • "1" may be "-1", and the axis is considered to be equivalent to each direction.
  • crystal orientations include ⁇ hk0> (h ⁇ k, h and k are natural numbers), ⁇ hhl> (h ⁇ l, h and l are natural numbers), and ⁇ hhl> (h ⁇ l, h and l are natural numbers). natural numbers), and ⁇ hkl> (h ⁇ k ⁇ l, h, k, and l are natural numbers).
  • a grain is a crystalline region surrounded by grain boundaries.
  • grain boundaries can be defined based on the crystal orientation. Generally, when the crystal orientation difference between two adjacent measurement points exceeds 5°, it is defined that a grain boundary exists between them. Therefore, the above definition is also applied to the oxide semiconductor film according to this embodiment.
  • the oxide semiconductor film according to this embodiment includes multiple regions with different crystal orientations within the crystal grains.
  • the oxide semiconductor film according to this embodiment has a bixbite structure
  • the crystal grain size is a value indicating the size of crystal grains.
  • the diameter of a circle corresponding to the area S is defined as the crystal grain size d.
  • the average crystal grain size is the average value of the crystal grain sizes of a plurality of crystal grains. Since the oxide semiconductor film according to this embodiment includes a plurality of crystal grains, the oxide semiconductor film can be evaluated using the average crystal grain size.
  • the average crystal grain size dAVE is calculated using equation (2).
  • a j is the area ratio of the j-th crystal grain (the ratio of the area of the crystal grain to the area of the entire EBSD measurement region (measurement region)), and d j is the crystal grain size of the j-th crystal grain.
  • N is the number of crystal grains.
  • the average crystal grain size d AVE is an area average within the measurement region weighted by the area of the crystal grains. When the average crystal grain size dAVE is large, it can be said that the oxide semiconductor film contains many crystal grains with large crystal grain sizes.
  • the crystal grains of the oxide semiconductor film according to this embodiment have a larger average crystal grain size than the crystal grains of a conventional oxide semiconductor film.
  • the average crystal grain size of the plurality of crystal grains included in the oxide semiconductor film according to this embodiment is, for example, 0.1 ⁇ m or more, preferably 0.3 ⁇ m or more, and more preferably 0.5 ⁇ m or more. .
  • the maximum crystal grain size is the maximum value of the crystal grain sizes of a plurality of crystal grains.
  • the crystal grains of the oxide semiconductor film according to this embodiment have a larger maximum crystal grain size than the crystal grains of a conventional oxide semiconductor film.
  • the maximum crystal grain size of the crystal grains included in the oxide semiconductor film according to this embodiment is, for example, 0.5 ⁇ m or more, preferably 1.0 ⁇ m or more, and more preferably 1.5 ⁇ m or more.
  • GOS Gram Orientation Spread
  • GOS is a value indicating a crystal orientation difference within a crystal grain.
  • GOS is calculated using equation (3). In other words, GOS calculates the difference between the crystal orientation ⁇ i at the i-th measurement point within the crystal grain and the average crystal orientation ⁇ AVE at the n measurement points within the crystal grain. This is the value divided by . In other words, GOS is a value obtained by averaging crystal orientations within crystal grains.
  • GOS represents the magnitude of strain within crystal grains, and it can be said that the larger GOS is, the greater the strain within crystal grains.
  • the GOS average value is the average value of GOS of a plurality of crystal grains. Since the oxide semiconductor film according to this embodiment includes a plurality of crystal grains, the oxide semiconductor film can be evaluated using the GOS average value.
  • the GOS average value GOS AVE is calculated using equation (4).
  • a j is the area ratio of the j-th crystal grain
  • GOS j is the GOS of the j-th crystal grain
  • N is the number of crystal grains.
  • the GOS average value GOS AVE is an area average within the measurement region weighted by the area of the crystal grain. When the GOS average value GOS AVE is large, it can be said that the oxide semiconductor film contains many crystal grains whose crystal orientation changes significantly.
  • the oxide semiconductor film according to this embodiment includes crystal grains whose crystal orientation changes significantly, and the number of such crystal grains is reflected as the GOS average value.
  • the average GOS value is 5° or more.
  • the average GOS value of a conventional oxide semiconductor film is 1° or less, and one of the characteristics of the oxide semiconductor film according to this embodiment is that the average GOS value is large.
  • the oxide semiconductor film In conventional oxide semiconductor films, if the crystal orientation within the crystal grains changes significantly, the distortion of the crystal grains becomes large and the crystal growth of the crystal grains is inhibited. Therefore, in the conventional oxide semiconductor film, changes in crystal orientation within crystal grains are small, and the average crystal grain size or maximum crystal grain size is also small. In contrast, in the oxide semiconductor film according to this embodiment, large crystal grains are formed despite the large change in the crystal orientation within the crystal grains, and the oxide semiconductor film according to this embodiment is different from the conventional oxide semiconductor film. The average crystal grain size or maximum crystal grain size is larger than that of the semiconductor film.
  • the oxide semiconductor film according to this embodiment the amount of oxygen vacancies in the film after heat treatment is suppressed by generating crystal nuclei with a specific crystal orientation by optimizing the sputtering film formation conditions, and the insulation properties deteriorate.
  • a thin film transistor using an oxide semiconductor film as a channel has high mobility and excellent electrical characteristics.
  • the measurement of the crystal structure of the oxide semiconductor film according to this embodiment is not limited to the EBSD method. Crystal orientation or change in crystal orientation within a crystal grain, etc. may be measured using a measurement method other than the EBSD method.
  • the oxide semiconductor film according to this embodiment is manufactured by a sputtering process and an annealing process.
  • an oxide semiconductor film is formed on the substrate.
  • the oxide semiconductor film after the sputtering process is preferably a film with a small amount of crystalline components, and is particularly preferably amorphous.
  • ions generated in the plasma and atoms recoil by the sputtering target collide with the substrate, so even if the substrate temperature at the start of sputtering is room temperature, the substrate temperature rises during film formation. .
  • microcrystals are included in the oxide semiconductor film immediately after film formation, and crystal grains with crystal orientation ⁇ 001> are likely to be generated in the subsequent annealing process.
  • the oxide semiconductor film be formed while controlling the substrate temperature.
  • the substrate temperature is, for example, 100°C or lower, preferably 70°C or lower, and more preferably 50°C or lower.
  • the substrate temperature may be 30° C. or lower.
  • Substrate temperature can be controlled, for example, by cooling the substrate.
  • the oxide semiconductor film may be deposited at a deposition rate that does not cause the substrate temperature to exceed a predetermined temperature.
  • the substrate temperature may be controlled by increasing the distance between the target and the substrate so that the substrate is not affected by the sputtering target.
  • the substrate on which the oxide semiconductor film is formed a rigid substrate such as a glass substrate, a quartz substrate, and a sapphire substrate, or a flexible substrate such as a polyimide substrate, an acrylic substrate, a siloxane substrate, and a fluororesin substrate is used.
  • the substrate on which the oxide semiconductor film is formed is a silicon oxide (SiO x ) film, a silicon oxynitride (SiO x N y ) film, a silicon nitride (SiN x ) film, or a silicon nitride oxide (SiN x O y ) film.
  • the substrate may be a substrate on which a film, an aluminum oxide (AlO x ) film, an aluminum oxynitride (AlO x N y ), an aluminum nitride oxide (AlN x O y ), or an aluminum nitride (AlN x ) is formed.
  • AlO x aluminum oxide
  • AlO x N y aluminum oxynitride
  • AlN x O y aluminum nitride oxide
  • AlN x aluminum nitride
  • the oxide semiconductor film is formed under conditions where the oxygen partial pressure is 10% or less.
  • the oxygen partial pressure is, for example, 2% or more and 20% or less, preferably 3% or more and 15% or less, and more preferably 3% or more and 10% or less.
  • the oxide semiconductor film is crystallized.
  • Annealing is performed by maintaining a predetermined temperature at a predetermined temperature for a predetermined time.
  • the predetermined attained temperature is 300°C or more and 500°C or less, preferably 350°C or more and 450°C or less.
  • the holding time at the final temperature is 15 minutes or more and 120 minutes or less, preferably 30 minutes or more and 60 minutes or less.
  • Example 10 The oxide semiconductor film according to this embodiment will be described in more detail based on specific examples. Note that the example described below is an example of the oxide semiconductor film according to this embodiment, and the structure of the oxide semiconductor according to this embodiment is not limited to the structure of the example described below. .
  • Example 1 As Example 1, the oxide semiconductor film according to this embodiment was formed on a substrate using the above-described sputtering process and annealing process.
  • the sputtering process an oxide semiconductor film was formed on a glass substrate using a sputtering target in which the atomic ratio of indium to all metal elements contained in the sintered body was 70% or more.
  • the oxygen partial pressure during film formation was 5.1 (%), and the substrate temperature was controlled so that the substrate temperature during film formation was 100° C. or less.
  • the oxide semiconductor film was subjected to an annealing process in an air atmosphere. In the annealing process, the final temperature was controlled to be 400° C. and maintained at the final temperature for 30 minutes.
  • the chemical composition of the oxide semiconductor film was similar to that of the sputtering target.
  • Example 2 As Example 2, the oxide semiconductor film according to this embodiment was manufactured in the same manner as Example 1, except that only the conditions of the annealing process were changed. In the annealing process, the final temperature was controlled to be 450° C., and the final temperature was maintained for 60 minutes.
  • a conventional oxide semiconductor film was formed on a substrate using a conventional sputtering process and an annealing process.
  • a sputtering process an oxide semiconductor film was formed on a quartz substrate using a sputtering target in which the atomic ratio of indium to all metal elements contained in the sintered body was 70% or more.
  • the oxygen partial pressure during film formation was 10.0 (%), and the substrate temperature was not controlled during film formation.
  • the oxide semiconductor film was subjected to an annealing process in an air atmosphere. In the annealing process, the final temperature was controlled to be 450° C., and the final temperature was maintained for 60 minutes.
  • the chemical composition of the oxide semiconductor film was similar to that of the sputtering target.
  • Table 1 shows the manufacturing conditions (film forming conditions and annealing conditions) of Example 1, Example 2, and Comparative Example. Although there is a difference in the thickness of the oxide semiconductor film between Examples 1 and 2 and the comparative example, the major differences are whether or not the substrate temperature was controlled during film formation and the oxygen partial pressure.
  • Crystal orientation analysis using EBSD method Crystal orientation analysis of the oxide semiconductor films of Example 1 and Example 2 and the oxide semiconductor film of Comparative Example was performed using the EBSD method.
  • the measurement conditions of the EBSD method are as shown in Table 2. Further, the crystal orientation was analyzed using OIM-Analysis (ver. 7.1) manufactured by TSL Solutions Co., Ltd.
  • OIM-Analysis ver. 7.1
  • ICSD Inorganic Crystal Structure Database: Chemical Information Association
  • IPF maps of the oxide semiconductor film of Example 1 are shown in FIGS. 1 and 2. Further, IPF maps of the oxide semiconductor film of Example 2 are shown in FIGS. 4 and 5. Further, IPF maps of the oxide semiconductor film of the comparative example are shown in FIGS. 20 and 21.
  • black lines represent grain boundaries. That is, a plurality of crystal grains surrounded by black lines can be confirmed in both the oxide semiconductor films of Examples 1 and 2 and the oxide semiconductor film of the comparative example.
  • the IPF maps shown in FIGS. 1, 2, 4, 5, 20, and 21 are color-coded according to the color key shown in each figure. Mainly, crystal orientation ⁇ 001> is colored red, crystal orientation ⁇ 101> is colored green, and crystal orientation ⁇ 111> is colored blue.
  • FIGS. 2, 5, and 21 show the crystal orientation difference of crystal orientation ⁇ 001>, crystal orientation ⁇ 101>, or crystal orientation ⁇ 111> with respect to the normal direction of the surface of the substrate (or the surface of the oxide semiconductor film) Measurement points within the range of 0° or more and 15° or less are extracted and color-coded.
  • FIGS. 2, 5, and 21 show the crystal orientation ⁇ 001>, crystal orientation ⁇ 101>, or crystal orientation with respect to the normal direction of the surface of the substrate in FIGS. 1, 4, and 20, respectively. This is an image in which measurement points where the ⁇ 111> crystal orientation difference exceeds 15° are excluded.
  • the average crystal grain sizes of the oxide semiconductor films of Example 1 and Example 2 were calculated to be 1.04 ( ⁇ m) and 1.06 ( ⁇ m), respectively.
  • the average crystal grain size of the oxide semiconductor film of the comparative example was calculated to be 0.65 ( ⁇ m).
  • the average crystal grain size of the oxide semiconductor films of Example 1 and Example 2 was more than 1.5 times the average crystal grain size of the oxide semiconductor film of the comparative example.
  • the maximum crystal grain size of the oxide semiconductor films of Example 1 and Example 2 was both 1.7 ( ⁇ m).
  • the maximum crystal grain size of the oxide semiconductor film of the comparative example was 1.1 ( ⁇ m).
  • the maximum crystal grain size of the oxide semiconductor films of Examples 1 and 2 was approximately 1.5 times the maximum crystal grain size of the oxide semiconductor film of the comparative example.
  • the IPF map shown in FIGS. 2 and 5 Comparing the IPF map shown in FIGS. 2 and 5 with the IPF map shown in FIG. 21, the IPF map shown in FIGS. 2 and 5 has many regions colored in blue, whereas the IPF map shown in Many areas are colored green.
  • the crystal orientation of the oxide semiconductor film of Example 1 in the measurement region is When the occupancy rates of crystal orientation ⁇ 001>, crystal orientation ⁇ 101>, and crystal orientation ⁇ 111> were calculated, they were 3.4 (%), 16.5 (%), and 34.5 (%), respectively. Furthermore, based on FIG.
  • the occupancy rate of crystal orientation ⁇ 001> is lower than the occupancy rate of crystal orientation ⁇ 101> and crystal orientation ⁇ 111>. In other words, the occupancy rates of crystal orientation ⁇ 101> and ⁇ 111> are higher than the occupancy rate of crystal orientation ⁇ 001>.
  • the occupancy rate of crystal orientation ⁇ 101> and the occupancy rate of crystal orientation ⁇ 111> are 4.9 times and 10.1 times the occupancy rate of crystal orientation ⁇ 001>, respectively. be.
  • the occupancy rate of crystal orientation ⁇ 101> and the occupancy rate of crystal orientation ⁇ 111> are 8.7 times and 16.1 times the occupancy rate of crystal orientation ⁇ 001>, respectively. It's double.
  • the occupancy rate of crystal orientation ⁇ 101> and the occupancy rate of crystal orientation ⁇ 111> are 4.2 times and 3.5 times the occupancy rate of crystal orientation ⁇ 001>, respectively. It is.
  • FIG. 3 shows a GOS distribution map in which multiple crystal grains are color-coded based on the GOS of each of the multiple crystal grains included in the oxide semiconductor film of Example 1.
  • FIG. 6 shows a GOS distribution map in which a plurality of crystal grains are color-coded based on the GOS of each of the plurality of crystal grains included in the oxide semiconductor film of Example 2.
  • FIG. 22 shows a GOS distribution map in which a plurality of crystal grains are color-coded based on the GOS of each of the plurality of crystal grains included in the oxide semiconductor film of the comparative example.
  • FIGS. 3, 6, and 22 are distribution maps showing the magnitude of crystal orientation difference within a crystal grain.
  • FIGS. 3, 6, and 22 are distribution maps showing the magnitude of crystal orientation difference within a crystal grain.
  • the GOS of each of a plurality of crystal grains is color-coded based on the color bar shown in the figures, and the color of the crystal grains changes from blue to red, that is, the wavelength of visible light changes. As the grain size increases, the crystal orientation difference within the crystal grains increases.
  • the average GOS values of the oxide semiconductor films of Example 1 and Example 2 were 8.12° and 8.61°, respectively.
  • the average GOS value of the oxide semiconductor film of the comparative example was 0.71°. It can also be seen from the GOS average value that the oxide semiconductor films of Examples 1 and 2 have significantly larger changes in crystal orientation within crystal grains than the oxide semiconductor films of Comparative Examples.
  • Table 3 shows information regarding the crystal structures of the oxide semiconductor films of Examples 1 and 2 and the oxide semiconductor films of Comparative Examples. As shown in Table 3, the oxide semiconductor films of Examples 1 and 2 and the oxide semiconductor film of the comparative example have the same bixbite structure, but the crystal grains contained in each are the same. The characteristics of crystal orientation are significantly different.
  • the oxide semiconductor film according to the present embodiment has remarkable characteristics in the crystal orientation of crystal grains, and has a novel crystal structure different from that of conventional oxide semiconductors.
  • the thin film transistor using the oxide semiconductor film according to this embodiment has higher field effect mobility than the thin film transistor using the conventional oxide semiconductor film. Therefore, it is presumed that the oxide semiconductor film itself according to this embodiment also has high mobility.
  • a thin film transistor according to an embodiment of the present invention will be described with reference to FIGS. 7 to 16.
  • the thin film transistor according to this embodiment can be used for, for example, a display device, an integrated circuit (IC) such as a microprocessor (Micro-Processing Unit: MPU), or a memory circuit.
  • IC integrated circuit
  • MPU Micro-Processing Unit
  • FIG. 7 is a cross-sectional view schematically showing a thin film transistor 10 according to an embodiment of the present invention.
  • FIG. 8 is a plan view schematically showing a thin film transistor 10 according to an embodiment of the present invention.
  • the thin film transistor 10 is provided on a substrate 100.
  • the thin film transistor 10 includes a gate electrode 105, gate insulating layers 110 and 120, an oxide semiconductor layer 140, a gate insulating layer 150, a gate electrode 160, insulating layers 170 and 180, a source electrode 201, and a drain electrode 203.
  • the source electrode 201 and the drain electrode 203 are not particularly distinguished, they may be collectively referred to as the source/drain electrode 200.
  • the gate electrode 105 is provided on the substrate 100.
  • Gate insulating layers 110 and 120 are provided on substrate 100 and gate electrode 105.
  • the oxide semiconductor layer 140 is provided on the gate insulating layer 120.
  • the oxide semiconductor layer 140 is in contact with the gate insulating layer 120.
  • the surface in contact with the gate insulating layer 120 is referred to as a lower surface 142.
  • the gate electrode 160 faces the oxide semiconductor layer 140.
  • Gate insulating layer 150 is provided between oxide semiconductor layer 140 and gate electrode 160.
  • the gate insulating layer 150 is in contact with the oxide semiconductor layer 140.
  • the surface in contact with the gate insulating layer 150 is referred to as an upper surface 141.
  • the surface between the upper surface 141 and the lower surface 142 is referred to as a side surface 143.
  • Insulating layers 170 and 180 are provided on gate insulating layer 150 and gate electrode 160.
  • the insulating layers 170 and 180 are provided with openings 171 and 173 through which the oxide semiconductor layer 140 is exposed.
  • the source electrode 201 is provided so as to fill the inside of the opening 171.
  • the source electrode 201 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 171.
  • the drain electrode 203 is provided so as to fill the inside of the opening 173.
  • the drain electrode 203 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 173.
  • the gate electrode 105 has a function as a bottom gate of the thin film transistor 10 and a function as a light shielding film for the oxide semiconductor layer 140.
  • the gate insulating layer 110 has a function as a barrier film that blocks impurities that diffuse from the substrate 100 toward the oxide semiconductor layer 140.
  • the gate insulating layers 110 and 120 have a function as a gate insulating layer for the bottom gate.
  • the oxide semiconductor layer 140 is divided into a source region S, a drain region D, and a channel region CH.
  • the channel region CH is a region of the oxide semiconductor layer 140 that is vertically below the gate electrode 160.
  • the source region S is a region of the oxide semiconductor layer 140 that does not overlap with the gate electrode 160 and is a region closer to the source electrode 201 than the channel region CH.
  • the drain region D is a region of the oxide semiconductor layer 140 that does not overlap with the gate electrode 160 and is a region closer to the drain electrode 203 than the channel region CH.
  • the oxide semiconductor layer 140 in the channel region CH has physical properties as a semiconductor.
  • the oxide semiconductor layer 140 in the source region S and drain region D has physical properties as a conductor.
  • the gate electrode 160 has a function as a light shielding film for the top gate of the thin film transistor 10 and the oxide semiconductor layer 140.
  • the gate insulating layer 150 has a function as a gate insulating layer for the top gate, and has a function of releasing oxygen through heat treatment in the manufacturing process.
  • the insulating layers 170 and 180 have the function of insulating the gate electrode 160 and the source/drain electrode 200 and reducing the parasitic capacitance between them.
  • the operation of the thin film transistor 10 is mainly controlled by the voltage supplied to the gate electrode 160.
  • An auxiliary voltage is supplied to the gate electrode 105.
  • the gate electrode 105 is simply used as a light shielding film, a specific voltage may not be supplied to the gate electrode 105, and the gate electrode 105 may be floating. In other words, the gate electrode 105 may simply be called a "light shielding film".
  • a dual-gate transistor in which the gate electrode is provided both above and below the oxide semiconductor layer is used as the thin film transistor 10, but the structure is not limited to this.
  • the thin film transistor 10 a bottom gate transistor in which the gate electrode is provided only below the oxide semiconductor layer 140 or a top gate transistor in which the gate electrode is provided only above the oxide semiconductor layer 140 is used. Good too.
  • the above configuration is just one embodiment, and the present invention is not limited to the above configuration.
  • the width of the gate electrode 105 is larger than the width of the gate electrode 160 in the D1 direction.
  • the D1 direction is a direction that connects the source electrode 201 and the drain electrode 203, and is a direction that indicates the channel length L of the thin film transistor 10.
  • the length of the region (channel region CH) where the oxide semiconductor layer 140 and the gate electrode 160 overlap in the D1 direction is the channel length L
  • the width of the channel region CH in the D2 direction is the channel width W. be.
  • Gate insulating layer 150 may be patterned.
  • the gate insulating layer 150 may be patterned so that not only the top surface of the oxide semiconductor layer 140 but also the side surfaces of the oxide semiconductor layer 140 are exposed.
  • FIG. 8 illustrates a configuration in which the source/drain electrodes 200 do not overlap the gate electrodes 105 and 160 in plan view
  • the configuration is not limited to this.
  • the source/drain electrode 200 may overlap with at least one of the gate electrodes 105 and 160 in plan view.
  • the above configuration is just one embodiment, and the present invention is not limited to the above configuration.
  • a rigid substrate having light-transmitting properties is used, such as a glass substrate, a quartz substrate, a sapphire substrate, or the like. If the substrate 100 needs to have flexibility, a substrate containing resin, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, a fluororesin substrate, etc., is used as the substrate 100. When a substrate containing a resin is used as the substrate 100, impurities may be introduced into the resin in order to improve the heat resistance of the substrate 100.
  • the substrate 100 does not need to be transparent, so an impurity that reduces the transparency of the substrate 100 may be used.
  • the substrate 100 may be a semiconductor substrate such as a silicon substrate, a silicon carbide substrate, or a compound semiconductor substrate, or a conductive substrate such as a stainless steel substrate, which does not have light-transmitting properties. used.
  • General metal materials are used for the gate electrode 105, the gate electrode 160, and the source/drain electrodes 200.
  • these materials include aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), and tungsten. (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof.
  • the above materials may be used in a single layer or in a stacked layer.
  • General insulating material is used for the gate insulating layers 110 and 120 and the insulating layers 170 and 180.
  • these insulating layers include silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon nitride oxide (SiN x O y ), aluminum oxide (AlO x ), and silicon oxide.
  • Inorganic insulating layers such as aluminum nitride (AlO x N y ), aluminum nitride oxide (AlN x O y ), and aluminum nitride (AlN x ) are used.
  • an insulating layer containing oxygen among the above insulating layers is used.
  • an inorganic insulating layer such as silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), aluminum oxynitride (AlO x N y ) is used.
  • the gate insulating layer 120 an insulating layer having a function of releasing oxygen through heat treatment is used.
  • the temperature of the heat treatment at which the gate insulating layer 120 releases oxygen is, for example, 600° C. or less, 500° C. or less, 450° C. or less, or 400° C. or less. That is, the gate insulating layer 120 releases oxygen at a heat treatment temperature performed in the manufacturing process of the thin film transistor 10 when a glass substrate is used as the substrate 100, for example.
  • the gate insulating layer 150 an insulating layer with few defects is used.
  • the gate insulating layer The oxygen composition ratio in 150 is closer to the stoichiometric ratio for the insulating layer than the oxygen composition ratio in the other insulating layer.
  • silicon oxide ( SiOx ) is used for each of the gate insulating layer 150 and the insulating layer 180
  • the composition ratio of oxygen in the silicon oxide used as the gate insulating layer 150 is the same as that of the oxide used as the insulating layer 180.
  • a layer in which no defects are observed when evaluated by electron spin resonance (ESR) may be used as the gate insulating layer 150.
  • SiO x N y and AlO x N y are silicon compounds and aluminum compounds containing nitrogen (N) in a smaller proportion (x>y) than oxygen (O).
  • SiN x O y and AlN x O y are silicon and aluminum compounds containing a smaller proportion of oxygen than nitrogen (x>y).
  • the oxide semiconductor film according to the first embodiment can be used as the oxide semiconductor layer 140.
  • the oxide semiconductor layer 140 has crystallinity. Oxygen vacancies are less likely to be formed in a crystalline oxide semiconductor than in an amorphous oxide semiconductor. However, the grain boundaries of the oxide semiconductor layer 140 may include an amorphous region.
  • FIG. 9 is a flowchart showing a method for manufacturing the thin film transistor 10 according to an embodiment of the present invention.
  • 10 to 16 are cross-sectional views showing a method for manufacturing a thin film transistor 10 according to an embodiment of the present invention.
  • a gate electrode 105 is formed as a bottom gate on the substrate 100, and gate insulating layers 110 and 120 are formed on the gate electrode 105 ("Bottom" in step S3001 in FIG. 9).
  • GI/GE formation For example, silicon nitride is formed as the gate insulating layer 110.
  • silicon oxide is formed as the gate insulating layer 120.
  • the gate insulating layers 110 and 120 are formed by a CVD (Chemical Vapor Deposition) method.
  • the gate insulating layer 110 can block impurities that diffuse toward the oxide semiconductor layer 140 from the substrate 100 side, for example.
  • the silicon oxide used as the gate insulating layer 120 is a physical silicon oxide that releases oxygen by heat treatment.
  • an oxide semiconductor layer 140 is formed on the gate insulating layer 120 ("OS film formation" in step S3002 in FIG. 9). Regarding this step, the oxide semiconductor layer 140 is sometimes formed over the substrate 100.
  • the oxide semiconductor layer 140 is formed by a sputtering method.
  • the thickness of the oxide semiconductor layer 140 is, for example, 10 nm or more and 100 nm or less, 15 nm or more and 70 nm or less, or 20 nm or more and 40 nm or less.
  • the oxide semiconductor layer 140 before heat treatment (OS annealing) described below is amorphous.
  • the oxide semiconductor layer 140 after film formation and before OS annealing is preferably amorphous (a state in which the crystalline component of the oxide semiconductor is small).
  • the conditions for forming the oxide semiconductor layer 140 are preferably such that the oxide semiconductor layer 140 immediately after being formed does not crystallize as much as possible.
  • the oxide semiconductor layer 140 is formed by a sputtering method, the oxide semiconductor layer 140 is is deposited. Further, the oxide semiconductor layer 140 is formed under conditions where the oxygen partial pressure is 10% or less.
  • a pattern of the oxide semiconductor layer 140 is formed ("OS pattern formation" in step S3003 in FIG. 9).
  • a resist mask is formed over the oxide semiconductor layer 140, and the oxide semiconductor layer 140 is etched using the resist mask.
  • Wet etching may be used to etch the oxide semiconductor layer 140, or dry etching may be used.
  • Wet etching can be performed using an acidic etchant. For example, oxalic acid or hydrofluoric acid can be used as the etchant.
  • oxide semiconductor layer 140 After patterning the oxide semiconductor layer 140, heat treatment (OS annealing) is performed on the oxide semiconductor layer 140 ("OS annealing" in step S3004 in FIG. 9). In this embodiment, the oxide semiconductor layer 140 is crystallized by this OS annealing.
  • a gate insulating layer 150 is formed on the oxide semiconductor layer 140 ("GI formation" in step S3005 in FIG. 9).
  • silicon oxide is formed as the gate insulating layer 150.
  • Gate insulating layer 150 is formed by a CVD method.
  • the gate insulating layer 150 may be formed at a film forming temperature of 350° C. or higher.
  • the thickness of the gate insulating layer 150 is, for example, 50 nm or more and 300 nm or less, 60 nm or more and 200 nm or less, or 70 nm or more and 150 nm or less.
  • oxidation annealing heat treatment (oxidation annealing) is performed to supply oxygen to the oxide semiconductor layer 140 ("oxidation annealing" in step S3006 in FIG. 9). ”).
  • Oxygen deficiency occurs.
  • oxygen released from the gate insulating layers 120 and 150 is supplied to the oxide semiconductor layer 140, and oxygen vacancies are repaired.
  • a gate electrode 160 is formed on the gate insulating layer 150 ("GE formation" in step S3007 in FIG. 9).
  • the gate electrode 160 is formed by a sputtering method or an atomic layer deposition method, and is patterned through a photolithography process. Gate electrode 160 is formed so as to be in contact with gate insulating layer 150.
  • the resistance of the source region S and drain region D of the oxide semiconductor layer 140 is reduced (“SD resistance reduction” in step S3008 in FIG. 9).
  • impurities are implanted into the oxide semiconductor layer 140 from the gate electrode 160 side through the gate insulating layer 150 by ion implantation.
  • argon (Ar), phosphorus (P), and boron (B) are implanted into the oxide semiconductor layer 140 by ion implantation.
  • Oxygen vacancies are formed in the oxide semiconductor layer 140 by ion implantation, so that the resistance of the oxide semiconductor layer 140 is reduced. Since the gate electrode 160 is provided above the oxide semiconductor layer 140 functioning as the channel region CH of the thin film transistor 10, no impurity is implanted into the oxide semiconductor layer 140 in the channel region CH.
  • insulating layers 170 and 180 are formed as interlayer films on the gate insulating layer 150 and gate electrode 160 ("interlayer film formation" in step S3009 in FIG. 9).
  • Insulating layers 170 and 180 are formed by CVD.
  • silicon nitride is formed as the insulating layer 170
  • silicon oxide is formed as the insulating layer 180.
  • the materials used for the insulating layers 170 and 180 are not limited to those described above.
  • the thickness of the insulating layer 170 is 50 nm or more and 500 nm or less.
  • the thickness of the insulating layer 180 is 50 nm or more and 500 nm or less.
  • openings 171 and 173 are formed in the gate insulating layer 150 and the insulating layers 170 and 180 ("contact opening” in step S3010 in FIG. 9).
  • the oxide semiconductor layer 140 in the source region S is exposed through the opening 171.
  • the oxide semiconductor layer 140 in the drain region D is exposed through the opening 173.
  • the electrodes shown in FIG. 7 are formed.
  • Thin film transistor 10 is completed.
  • the mobility is 30 [cm 2 /Vs ] or more, 35 [cm 2 /Vs] or more, or 40 [cm 2 /Vs] or more can be obtained.
  • the mobility in this embodiment refers to the field effect mobility in the saturation region of the thin film transistor 10, where the potential difference (Vd) between the source electrode and the drain electrode is equal to the voltage (Vg) supplied to the gate electrode. It means the maximum value of the field effect mobility in a region larger than the value (Vg ⁇ Vth) obtained by subtracting the threshold voltage (Vth) of the thin film transistor 10 from the threshold voltage (Vth) of the thin film transistor 10.
  • FIG. 17 and 18 are cross-sectional STEM images of the thin film transistor 10 according to one embodiment of the present invention. Regions (a) to (c) surrounded by a rectangle in FIG. 17 are regions including the oxide semiconductor layer OS, and FIG. 18 is a cross-sectional STEM image of the regions (a) to (c) enlarged.
  • the oxide semiconductor layer OS has a continuous crystal structure in the thickness direction.
  • FIG. 19 is a schematic diagram showing an electronic device 1000 according to an embodiment of the present invention.
  • FIG. 19 shows a smartphone that is an example of the electronic device 1000.
  • Electronic device 1000 includes a display device 1100 with curved sides.
  • the display device 1100 includes a plurality of pixels for displaying images, and the plurality of pixels are controlled by a pixel circuit, a driving circuit, and the like.
  • the pixel circuit and the drive circuit include the thin film transistor 10 described in the second embodiment. Since the thin film transistor 10 has high field effect mobility, it can improve the responsiveness of the pixel circuit and the drive circuit, and as a result, the performance of the electronic device 1000 can be improved.
  • the electronic device 1000 is not limited to a smartphone.
  • the electronic device 1000 includes, for example, a watch, a tablet, a notebook computer, a car navigation system, or an electronic device having a display device such as a television.
  • the oxide semiconductor film described in the first embodiment or the thin film transistor 10 described in the second embodiment can be applied to any electronic device, regardless of whether or not it includes a display device.

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Abstract

Un transistor à couches minces selon la présente invention comprend un substrat, une couche semi-conductrice d'oxyde qui est disposée sur le substrat et a une cristallinité, une électrode de grille qui est superposée sur la couche semi-conductrice d'oxyde, et une couche isolante qui est disposée entre la couche semi-conductrice d'oxyde et l'électrode de grille. La couche semi-conductrice d'oxyde contient une pluralité de grains cristallins, dont chacun présente au moins une orientation cristalline < 001 >, une orientation cristalline < 101 > et une orientation cristalline < 111 > telle qu'obtenue par un procédé de diffraction à rétrodiffusion d'électrons (EBSD) ; et par rapport aux occupations des orientations cristallines telles que calculées sur la base de points de mesure qui ont des orientations cristallines ayant une mauvaise orientation cristalline de 0° à 15° par rapport à la direction normale de la surface du substrat, l'occupation de l'orientation cristalline < 111 > est supérieure à l'occupation de l'orientation cristalline < 001 > et l'occupation de l'orientation cristalline < 101 >.
PCT/JP2023/006037 2022-03-30 2023-02-20 Transistor à couches minces et dispositif électronique WO2023189003A1 (fr)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012253315A (ja) * 2010-12-28 2012-12-20 Idemitsu Kosan Co Ltd 酸化物半導体薄膜層を有する積層構造及び薄膜トランジスタ
WO2018143073A1 (fr) * 2017-02-01 2018-08-09 出光興産株式会社 Couche mince semi-conductrice d'oxyde cristalline, procédé de fabrication de stratifié, transistor à couches minces, procédé de fabrication de transistor à couches minces, dispositif électronique et dispositif d'affichage embarqué

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012253315A (ja) * 2010-12-28 2012-12-20 Idemitsu Kosan Co Ltd 酸化物半導体薄膜層を有する積層構造及び薄膜トランジスタ
WO2018143073A1 (fr) * 2017-02-01 2018-08-09 出光興産株式会社 Couche mince semi-conductrice d'oxyde cristalline, procédé de fabrication de stratifié, transistor à couches minces, procédé de fabrication de transistor à couches minces, dispositif électronique et dispositif d'affichage embarqué

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