WO2018126732A1 - 移位寄存器电路、驱动方法、goa电路和显示装置 - Google Patents

移位寄存器电路、驱动方法、goa电路和显示装置 Download PDF

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Publication number
WO2018126732A1
WO2018126732A1 PCT/CN2017/102174 CN2017102174W WO2018126732A1 WO 2018126732 A1 WO2018126732 A1 WO 2018126732A1 CN 2017102174 W CN2017102174 W CN 2017102174W WO 2018126732 A1 WO2018126732 A1 WO 2018126732A1
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Prior art keywords
pull
transistor
node
control
circuit
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PCT/CN2017/102174
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English (en)
French (fr)
Inventor
赵剑
王慧
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US15/779,386 priority Critical patent/US20210166647A1/en
Publication of WO2018126732A1 publication Critical patent/WO2018126732A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/027—Arrangements or methods related to powering off a display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection

Definitions

  • the present disclosure relates to the field of display driving technologies, and in particular, to a shift register circuit, a driving method, a GOA (Gate On Array) circuit, and a display device.
  • a shift register circuit a driving method
  • a GOA (Gate On Array) circuit a driving method
  • a GOA (Gate On Array) circuit a display device.
  • the gate driver chip (Gate Driver IC) has a function of Xon (gate line turn-off at the moment of shutdown), and the Xon function is implemented in such a manner that the Xon signal is set to a high level at the moment of shutdown, and the gate drive chip is triggered. All output channels simultaneously output a TFT (thin film transistor) turn-on voltage, causing all rows of TFTs (thin film transistors) to be turned on, releasing the residual charge on the pixel electrodes.
  • TFT thin film transistor
  • the voltage value of the turn-on voltage is generally the same as the high voltage Vgh, which is about 27V
  • Vgh the high voltage
  • the related art does not reset the potential of the pull-up node in the shift register unit included in the gate driving circuit when the display panel is turned off, thereby causing the pull-up after the shutdown due to the residual voltage of the pull-up node.
  • the characteristics of the node-controlled transistors drift, which can cause display failure.
  • embodiments of the present disclosure provide a shift register circuit including
  • a gate drive signal output of the GOA sub-circuit is configured to output a gate drive signal, and the GOA sub-circuit includes a pull-up node;
  • a shutdown control circuit wherein the shutdown control circuit is respectively connected to a gate drive signal output end and a pull-up node of the GOA sub-circuit, and an open voltage output line and a turn-off voltage output line of the shift register circuit, configured to Controlling the turn-on voltage output line to apply an turn-on voltage to the gate drive signal output terminal in a state in which the shutdown control signal is received, so that the pixel connected to the corresponding row gate line is a thin film transistor in the circuit is turned on, and controls the pull-up node to be connected to the off voltage output line;
  • the off voltage output line is a ground line or a negative voltage output line.
  • the shutdown control circuit includes:
  • An output control circuit is respectively connected to the gate driving signal output end and the turn-on voltage output line, and configured to control the turn-on voltage output line to the gate driving signal in a state in which a shutdown control signal is received The turn-on voltage is applied to the output.
  • the shutdown control circuit further includes:
  • a first pull-up node control circuit respectively connected to the pull-up node and the off voltage output line, configured to control the pull-up node and the off voltage output line in a state in which a shutdown control signal is received connection.
  • the output control circuit includes:
  • An output control transistor wherein a gate of the output control transistor is connected to a shutdown control signal output line for outputting the shutdown control signal, and a first pole of the output control transistor is connected to the turn-on voltage output line a second pole of the output control transistor is coupled to the gate drive signal output terminal;
  • the first pull-up node control circuit includes: a first pull-up node control transistor, wherein a gate of the first pull-up node control transistor is connected to the shutdown control signal output line, the first pull-up node A first pole of the control transistor is coupled to the pull up node, and a second pole of the first pull up node control transistor is coupled to the off voltage output line.
  • the GOA sub-circuit includes:
  • a second pull-up node control circuit is respectively connected to the input end, the reset end, the first clock signal output end, the pull-down node, and the pull-up node, and is configured to be at the input end, the reset end, and the first Controlling a potential of the pull-up node under control of a clock signal output terminal, a pull-down node, and the pull-up node;
  • a charging and discharging circuit the first end is connected to the pull-up node, and the second end is connected to the gate driving signal output end;
  • a pull-down node control circuit respectively connected to the first clock signal output end and the pull-up node, configured to control the pull-down node under control of the first clock signal output end and the pull-up node Potential;
  • the output circuit is respectively connected to the gate driving signal output end, the pull-up node, the pull-down node, the first clock signal output end, the second clock signal output end, and the low level output end;
  • the output circuit is configured to control the gate driving signal output end to be connected to the second clock signal output end in a state that the potential of the pull-up node is at a first level
  • the output circuit is configured to control a gate driving signal output end and the state in a state where a potential of the pull-down node and/or a first clock signal outputted by the first clock signal output terminal is at a first level The low level output is connected.
  • the GOA sub-circuit further includes:
  • a reset circuit connected to the reset terminal, the gate driving signal output end and the low level output end, respectively, configured to control the gate driving output end and the low under the control of the reset end
  • the level output is connected or disconnected from the low level output.
  • the pull-down node control circuit includes:
  • a first pull-down node control transistor wherein a gate of the first pull-down node control transistor is connected to the pull-up node, and a first pole of the first pull-down node control transistor is connected to the pull-down node,
  • the first pull-down node controls the second pole of the transistor to be connected to the low-level output terminal
  • the second pull-down node controls the transistor, wherein the gate and the first pole of the second pull-down node control transistor are both connected to the first clock signal output end;
  • a third pull-down node control transistor wherein a gate of the third pull-down node control transistor is coupled to a second pole of the second pull-down node control transistor, the third pull-down node controls a second pole of the transistor and the Drop-down node connection;
  • a fourth pull-down node control transistor wherein a gate of the fourth pull-down node control transistor is connected to the pull-up node, and the fourth pull-down node controls a first pole of the transistor and the third pull-down node controls a transistor a gate connection, wherein the second pull-down node controls the second pole of the transistor to be connected to the low-level output terminal;
  • the output circuit includes:
  • a pull-up transistor wherein a gate of the pull-up transistor is connected to the pull-up node, a first pole of the pull-up transistor is connected to the second clock signal output, and a second of the pull-up transistor a pole connected to the gate drive signal output end;
  • a pull-down transistor wherein a gate of the pull-down transistor is connected to the pull-down node, a first pole of the pull-down transistor is connected to the gate drive signal output terminal, and a second pole of the pull-down transistor is low Level output connection;
  • An output transistor wherein a gate of the output transistor is coupled to the output of the first clock signal
  • the first pole of the output transistor is connected to the gate driving signal output end, and the second pole of the output transistor is connected to the low level output end;
  • the shutdown control circuit is configured to control the pull-up node to be connected to the off voltage output line in a state in which the shutdown control signal is received, such that the first pull-down node controls a transistor and the upper The pull transistors are turned off.
  • an embodiment of the present disclosure further provides a driving method of a shift register circuit, which is applied to the above-described shift register circuit, and the driving method of the shift register circuit includes:
  • the shutdown control circuit In a state in which the shutdown control circuit receives the shutdown control signal, the shutdown control circuit controls the turn-on voltage output line to apply a turn-on voltage to the gate drive signal output terminal, so that the thin film transistors in the pixel circuit connected to the corresponding row gate lines are both Turn on, and control the pull-up node to connect to the off voltage output line;
  • the off voltage output line is a ground line or a negative voltage output line.
  • an embodiment of the present disclosure further provides a GOA circuit including a plurality of cascaded shift register circuits as described above;
  • the input terminals of the GOA sub-circuits included in each stage of the shift register circuit are connected to the gate drive signal output terminals of the GOA sub-circuits included in the adjacent upper stage shift register circuit. ;
  • the reset terminal of the GOA sub-circuit included in each stage shift register circuit is connected to the gate drive signal output terminal of the GOA sub-circuit included in the adjacent next-stage shift register circuit.
  • an embodiment of the present disclosure further provides a display device including the GOA circuit described above.
  • FIG. 1 is a structural diagram of a shift register circuit according to at least one embodiment of the present disclosure
  • FIG. 2 is a structural diagram of a shift register circuit according to at least one embodiment of the present disclosure
  • FIG. 3 is a structural diagram of a shift register circuit according to at least one embodiment of the present disclosure.
  • FIG. 4 is a circuit diagram of a shift register circuit of at least one embodiment of the present disclosure.
  • FIG. 5 is a timing chart showing the operation of the shift register circuit of the at least one embodiment of the present disclosure shown in FIG. 4 during normal display;
  • FIG. 6 is a shift register circuit of at least one embodiment of the present disclosure shown in FIG. 4 at the time of shutdown Working sequence diagram
  • FIG. 7 is a block diagram of a GOA circuit of at least one embodiment of the present disclosure.
  • a shift register circuit includes a GOA sub-circuit 10 for outputting a gate driving signal, and a gate driving signal output terminal Output of the GOA sub-circuit 10 is
  • the gate circuit 10 is configured to output a gate drive signal
  • the GOA sub-circuit 10 includes a pull-up node PU
  • the shift register circuit further includes a shutdown control circuit 11;
  • the shutdown control circuit 11 is respectively connected to the gate driving signal output terminal Output, the pull-up node PU, the turn-on voltage output line Von, and the turn-off voltage output line Voff, and is configured to receive the shutdown control signal. Receiving, for example, a shutdown control signal of the display panel, controlling the turn-on voltage output line Von to be connected to the gate drive signal output terminal, such that the thin film transistor in the pixel circuit connected to the corresponding row gate line (in FIG. 1 Not shown) is turned on, and controls the pull-up node PU to be connected to the off voltage output line Voff;
  • the off voltage output line Voff is a ground line or a negative voltage output line.
  • the gate driving signal output terminal Output is connected to a corresponding row gate line, and since the thin film transistor in the pixel circuit connected to the corresponding row gate line is generally an n-type thin film transistor, Von The turn-on voltage of the output is a high level capable of controlling the conduction of the thin film transistors;
  • the off voltage output line may be a ground line or a negative voltage output line to prevent the pull-up node after shutdown.
  • the residual voltage of the PU causes the transistor controlled by the pull-up node PU to turn on or have characteristic drift.
  • the shift register circuit controls the turn-on voltage output line Von to apply an turn-on voltage to the gate drive signal output terminal Output by using the shutdown control circuit 11 when the display panel is turned off, so as to be associated with the corresponding row.
  • Thin film transistors in pixel circuits connected by gate lines are guided Passing, thereby releasing the residual charge on the pixel electrode to eliminate the shutdown image, since the shift register circuit according to at least one embodiment of the present disclosure does not drive all gate lines through the gate driver chip (Gate Driver IC), There is no problem that the gate driving chip is insufficient in driving ability, all the gate lines cannot be turned on, there is a problem of line sticking or the like, and the shift register circuit according to at least one embodiment of the present disclosure passes through the shutdown control circuit 11 When the display panel is powered off, the control pull-up node PU is connected to the off voltage output line Voff to prevent the residual voltage of the pull-up node PU after the shutdown, so that the transistor controlled by the pull-up node PU is turned on or has characteristic drift, thereby being to a certain extent Prevent bad occurrences.
  • the control pull-up node PU is connected to the off voltage output line Voff to prevent the residual voltage of the pull-up node PU after the shutdown, so that the transistor
  • the shutdown control circuit may include:
  • An output control circuit is respectively connected to the gate driving signal output end and the turn-on voltage output line, and configured to receive the shutdown control signal of the display panel, for example, receiving the shutdown control signal, and controlling the opening
  • the voltage output line applies an turn-on voltage to the gate drive signal output.
  • the shutdown control circuit may further include:
  • a first pull-up node control circuit respectively connected to the pull-up node and the off voltage output line, configured to control the pull-up node and the off voltage output line in a state in which a shutdown control signal is received connection.
  • the shutdown control circuit 11 may include:
  • the output control circuit 111 is respectively connected to the gate driving signal output terminal Output and the turn-on voltage output line Von, and configured to control the turn-on voltage output line Von to the state in a state where the shutdown control signal is received
  • the gate drive signal output terminal Output applies an open voltage
  • a first pull-up node control circuit 112 connected to the pull-up node PU and the off voltage output line Voff, respectively, configured to control the pull-up node PU and the state in a state in which a shutdown control signal is received Close the voltage output line Voff connection.
  • the shutdown control circuit 11 can control the voltage state of the gate drive signal output terminal and the voltage state of the pull-up node PU by the output control circuit 111 and the first pull-up node control circuit 112 respectively.
  • the output control circuit includes: an output control transistor, the gate is connected to a shutdown control signal output line for outputting the shutdown control signal, and the first pole is connected to the turn-on voltage output line a second pole connected to the gate drive signal output end;
  • the first pull-up node control circuit includes: a first pull-up node control transistor, a gate and the The shutdown control signal output line is connected, the first pole is connected to the pull-up node, and the second pole is connected to the shutdown voltage output line.
  • the output control circuit 111 includes an output control transistor MOC, a gate connected to a shutdown control signal output line T1 for outputting the shutdown control signal, and a source connected to the turn-on voltage output line Von. a drain connected to the gate drive signal output terminal Output;
  • the first pull-up node control circuit includes: a first pull-up node control transistor MUC, a gate connected to the shutdown control signal output line T1, a source connected to the pull-up node PU, a drain and the Close the voltage output line Voff connection.
  • the GOA sub-circuit may include:
  • a second pull-up node control circuit is respectively connected to the input end, the reset end, the first clock signal output end, the pull-down node, and the pull-up node, and is configured to be at the input end, the reset end, the first clock signal output end, Controlling a potential of the pull-up node under control of a pull-down node and the pull-up node;
  • a charging and discharging circuit the first end is connected to the pull-up node, and the second end is connected to the gate driving signal output end;
  • a pull-down node control circuit respectively connected to the first clock signal output end and the pull-up node, configured to control the pull-down node under control of the first clock signal output end and the pull-up node Potential;
  • an output circuit connected to the gate driving signal output end, the pull-up node, the pull-down node, the first clock signal output end, the second clock signal output end, and the low level output end, respectively, configured to be Controlling, by the first pull-up node, a state in which the gate drive signal output terminal is connected to the second clock signal output terminal, and the potential of the pull-down node and/or the first
  • the control gate drive signal output terminal is connected to the low level output terminal in a state where the first clock signal outputted by the clock signal output terminal is at the first level.
  • the GOA sub-circuit further includes:
  • a reset circuit connected to the reset terminal, the gate driving signal output end and the low level output end, respectively, configured to control whether the gate driving output end is controlled by the reset end
  • the low level output is connected.
  • the pull-down node control circuit may include:
  • the first pull-down node controls the transistor, the gate is connected to the pull-up node, the first pole is connected to the pull-down node, and the second pole is connected to the low-level output terminal;
  • a second pull-down node controls the transistor, and the gate and the first pole are both connected to the first clock signal output end;
  • a third pull-down node controls a transistor, a gate is connected to the second pole of the second pull-down node control transistor, and a second pole is connected to the pull-down node;
  • a fourth pull-down node controls a transistor, a gate of the pull-up node is connected, a first pole is connected to a gate of the third pull-down node control transistor, and a second pole is connected to the low-level output terminal;
  • the output circuit includes:
  • a pull-up transistor a gate connected to the pull-up node, a first pole connected to the second clock signal output end, and a second pole connected to the gate drive signal output end;
  • a pull-down transistor a gate connected to the pull-down node, a first pole connected to the gate drive signal output, and a second pole connected to the low-level output;
  • An output transistor a gate connected to the first clock signal output end, a first pole connected to the gate drive signal output end, and a second pole connected to the low level output end;
  • the shutdown control circuit is configured to control the pull-up node to be connected to the off voltage output line in a state in which the shutdown control signal is received, such that the first pull-down node controls a transistor and the upper The pull transistors are turned off.
  • the shutdown control circuit controls to pull down the potential of the pull-up node such that both the pull-up transistor and the first pull-down control transistor are turned off.
  • the peripheral control line of the GOA sub-circuit of the at least one embodiment of the present disclosure increases the shutdown control signal output line T1 and the turn-on voltage output line Von with respect to the shift register circuit in the related art;
  • the shift register circuit of at least one embodiment of the present disclosure includes 14 TFTs (Thin Film Transistor). , thin film transistor), 1 capacitor, 2 clock signals (first clock signal CLK1 and second clock signal CLK2), turn-on voltage output line Von, shutdown control signal output line T1 (for controlling to eliminate shutdown afterimage), input Terminal INPUT, low-level output line VSS, reset terminal RESET, and gate drive signal output terminal Output; VSS output DC low-level signal, CLK1 and CLK2 are clock signals with the same period and different amplitudes (alternating control shift register circuit ), CLK1 and CLK2 are inverted.
  • TFTs Thin Film Transistor
  • N+1th shift register circuit (N is an odd number) is an even-numbered shift register circuit.
  • the structure is CLK1. Interchanged with the CLK2 position, The rest of the basic structure is the same, there is not much to introduce here.
  • the label is PU for the pull-up node
  • the label for the PD is the pull-down node
  • the label for the PD CN is the pull-down control node.
  • the off voltage output line uses a low level output line VSS, that is, the off voltage is a low level, and the low level may be a ground level or a negative voltage.
  • M15 is an output control transistor
  • M14 is a first pull-up node control transistor
  • M6 is a first pull-down node control transistor
  • M9 is a second pull-down node control transistor
  • M8 is the fourth pull-down node control transistor
  • M3 is the pull-up transistor
  • M11 is the pull-down transistor
  • M12 is the output transistor
  • the second pull-up node control circuit includes an input transistor M1, a reset transistor M2, a second pull-up node control transistor M13, and a third pull-up node control transistor M10;
  • the reset circuit includes an output reset transistor M4; the charge and discharge circuit includes a storage capacitor C1.
  • the normal display timing is described by taking the Nth stage shift register circuit (N is an odd number) as an example.
  • N is an odd number
  • the operation timing of the Nth stage shift register circuit is as shown in FIG. 5.
  • T1 outputs a low level
  • M14 and M15 are both turned off
  • the input signal input by the INPUT turns M3 on
  • the second clock signal CLK2 is input to the Output to generate an output gate drive signal.
  • the reset signal of the RESET output is input, M1 is turned off, M2 is turned on, PU is connected to VSS, the potential of PU is pulled low, and M3 is turned off.
  • the first clock signal CLK1 is a high level signal
  • M9 is turned on
  • the potential of the pull-down control node PD CN is set to a high level
  • M5 is turned on
  • M11 is turned on
  • the output is output by the VSS.
  • the low level signal is placed low.
  • the N-stage shift register circuit (N is an odd number) is taken as an example to describe the shutdown timing.
  • the operation timing of the Nth stage shift register circuit is as shown in FIG. 6.
  • T1 outputs a high level signal.
  • both M14 and M15 are turned on.
  • the potential of PU is pulled low by VSS, and is set to a low level.
  • M3 is turned off.
  • the gate drive signal of Output is changed to Von output.
  • Turn-on voltage (the voltage value of the turn-on voltage of the Von output is generally the same as the high voltage Vgh, which is about 27V), and a thin film transistor connected to the corresponding gate line (the thin film transistor is a thin film transistor located in the pixel circuit) Open, release the charge in the pixel electrode, to achieve the effect of eliminating the residual image.
  • the Nth stage shift register circuit, the N+1th stage shift register circuit, the N+2 stage shift register circuit ... respectively generate corresponding gate drive signals, and the AA area on the liquid crystal panel (Active)
  • the thin film transistors connected to all the gate lines in the Area, effective display area are turned on, and the charge in the pixel electrodes is released, so as to eliminate the effect of the shutdown of the entire display panel.
  • An embodiment of the present disclosure provides a driving method of the shift register circuit, which is applied to the shift register circuit described above, and the driving method of the shift register circuit includes:
  • the shutdown control circuit In a state in which the shutdown control circuit receives the shutdown control signal, the shutdown control circuit controls the turn-on voltage output line to apply a turn-on voltage to the gate drive signal output terminal, so that the thin film transistors in the pixel circuit connected to the corresponding row gate lines are both Turn on, and control the pull-up node to connect to the off voltage output line;
  • the off voltage output line is a ground line or a negative voltage output line.
  • One embodiment of the present disclosure provides a GOA circuit comprising a plurality of cascaded shift register circuits as described above.
  • each stage shift register circuit in addition to the first stage shift register circuit, each stage shift register circuit includes an input terminal of the GOA sub-circuit and is adjacent to the adjacent upper stage shift register circuit.
  • the gate drive signal output terminal of the GOA sub-circuit is connected;
  • the reset terminal of the GOA sub-circuit included in each stage shift register circuit is connected to the gate drive signal output terminal of the GOA sub-circuit included in the adjacent next-stage shift register circuit.
  • S1 designates a first stage shift register circuit
  • S2 designates a second shift register circuit
  • S3 designates a third shift register circuit
  • S4 designates a fourth shift register circuit
  • VSS is a low level output line.
  • CLK1 is the first clock signal
  • CLK2 is the second clock signal
  • T1 is the shutdown control signal output line
  • Von is the turn-on voltage output line;
  • the input terminal INPUT of S1 is connected to the start signal STV;
  • G1 indicates the gate drive signal output end of the first stage shift register circuit S1;
  • the reset end of S1 is connected to the gate drive signal output terminal G2 of S2;
  • G1 is connected to the input end of S2;
  • G2 is connected to the input end of S3; the reset end of S2 is connected to the gate drive signal output end G3 of S3;
  • G3 is connected to the input of S4, and G4 is connected to the reset end of S3.
  • At least one embodiment of the present disclosure provides a display device including the GOA circuit described above.
  • the shift register circuit, the driving method, the GOA circuit and the display device of at least one embodiment of the present disclosure control all gate driving signal output terminals and turn-on voltages when the display panel is turned off by using a shutdown control circuit
  • the output lines are connected such that the thin film transistors in the pixel circuits connected to the respective row gate lines are turned on, thereby releasing residual charges on the pixel electrodes to eliminate shutdown artifacts, as described in at least one embodiment of the present disclosure
  • the shift register circuit does not drive all gate lines to be turned on by the gate driver chip (Gate Driver IC). Therefore, there is no shortage of driving ability of the gate driving chip, and all the gate lines cannot be turned on, and there is a line residual image.
  • the problem, and the shift register circuit of at least one embodiment of the present disclosure controls the pull-up node to be connected to the shutdown voltage output line when the display panel is turned off by the shutdown control circuit, preventing the residual voltage of the pull-up node after the shutdown, so that the The characteristic of the transistor controlled by the pull-up node is drifted, thereby preventing the defect to a certain extent Students.

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Abstract

公开了一种移位寄存器电路、驱动方法、阵列基板行驱动GOA电路和显示装置。移位寄存器电路包括GOA子电路(10)，GOA子电路(10)包括上拉节点(PU)，移位寄存器电路还包括关机控制电路(11)；关机控制电路被配置为在接收到关机控制信号的状态下，控制开启电压输出线(Von)向栅极驱动信号输出端施加开启电压，并控制所述上拉节点(PU)与关闭电压输出线(Voff)连接。

Description

移位寄存器电路、驱动方法、GOA电路和显示装置
相关申请的交叉引用
本申请主张在2017年1月3日在中国提交的中国专利申请号No.201710004565.0的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示驱动技术领域，尤其涉及一种移位寄存器电路、驱动方法、GOA(Gate On Array，阵列基板行驱动)电路和显示装置。
背景技术
在相关技术中，栅极驱动芯片(Gate Driver IC)具有Xon(关机瞬间的栅线开启)功能，Xon功能的实现方式为：在关机瞬间Xon信号被置于高电平，触发栅极驱动芯片所有输出通道同时输出TFT(薄膜晶体管)开启电压，使所有行的TFT(薄膜晶体管)全部开启，释放像素电极上残留的电荷。然而该技术存在一定问题，如关机瞬间所有电压都处于下降阶段，此时所有通道同时输出开启电压(开启电压的电压值一般与高电压Vgh相同，约为27V)，会导致栅极驱动芯片驱动能力不足，不能使所有的栅线都打开，会存在线残影等。并且，相关技术未在显示面板关机时对栅极驱动电路包括的移位寄存器单元中的上拉节点的电位进行复位，从而会导致关机后由于上拉节点的残留电压使得该被所述上拉节点控制的晶体管的特性漂移，从而会导致显示不良发生。
发明内容
在本公开的一个方面，本公开的实施例提供了一种移位寄存器电路，包括
GOA子电路，所述GOA子电路的栅极驱动信号输出端被配置为输出栅极驱动信号，所述GOA子电路包括上拉节点；
关机控制电路，所述关机控制电路分别与所述GOA子电路的栅极驱动信号输出端和上拉节点、以及所述移位寄存器电路的开启电压输出线和关闭电压输出线连接，被配置为在接收到关机控制信号的状态下，控制所述开启电压输出线向所述栅极驱动信号输出端施加开启电压，以使得与相应行栅线连接的像素 电路中的薄膜晶体管都导通，并控制所述上拉节点与所述关闭电压输出线连接；
所述关闭电压输出线为地线或负电压输出线。
可选的，所述关机控制电路包括：
输出控制电路，分别与所述栅极驱动信号输出端和所述开启电压输出线连接，被配置为在接收到关机控制信号的状态下，控制所述开启电压输出线向所述栅极驱动信号输出端施加所述开启电压。
可选的，所述关机控制电路还包括：
第一上拉节点控制电路，分别与所述上拉节点和所述关闭电压输出线连接，被配置为在接收到关机控制信号的状态下，控制所述上拉节点与所述关闭电压输出线连接。
可选的，所述输出控制电路包括：
输出控制晶体管，其中，所述输出控制晶体管的栅极与用于输出所述关机控制信号的关机控制信号输出线连接，所述输出控制晶体管的第一极与所述开启电压输出线连接，所述输出控制晶体管的第二极与所述栅极驱动信号输出端连接；
所述第一上拉节点控制电路包括：第一上拉节点控制晶体管，其中，所述第一上拉节点控制晶体管的栅极与所述关机控制信号输出线连接，所述第一上拉节点控制晶体管的第一极与所述上拉节点连接，所述第一上拉节点控制晶体管的第二极与所述关闭电压输出线连接。
可选的，所述GOA子电路包括：
第二上拉节点控制电路，分别与输入端、复位端、第一时钟信号输出端、下拉节点和所述上拉节点连接，用于在所述输入端、所述复位端、所述第一时钟信号输出端、下拉节点和所述上拉节点的控制下控制所述上拉节点的电位；
充放电电路，第一端与所述上拉节点连接，第二端与所述栅极驱动信号输出端连接；
下拉节点控制电路，分别与所述第一时钟信号输出端和所述上拉节点连接，被配置为在所述第一时钟信号输出端和所述上拉节点的控制下控制所述下拉节点的电位；以及，
输出电路，分别与所述栅极驱动信号输出端、所述上拉节点、所述下拉节点、所述第一时钟信号输出端、第二时钟信号输出端和低电平输出端连接；
所述输出电路被配置为在所述上拉节点的电位为第一电平的状态下，控制所述栅极驱动信号输出端与所述第二时钟信号输出端连接；
所述输出电路被配置为在所述下拉节点的电位和/或所述第一时钟信号输出端输出的第一时钟信号为第一电平的状态下，控制栅极驱动信号输出端与所述低电平输出端连接。
可选的，所述GOA子电路还包括：
复位电路，分别与所述复位端、所述栅极驱动信号输出端和所述低电平输出端连接，被配置为在所述复位端的控制下控制所述栅极驱动输出端与所述低电平输出端连接或与所述低电平输出端断开连接。
可选的，所述下拉节点控制电路包括：
第一下拉节点控制晶体管，其中，所述第一下拉节点控制晶体管的栅极与所述上拉节点连接，所述第一下拉节点控制晶体管的第一极与所述下拉节点连接，所述第一下拉节点控制晶体管的第二极与低电平输出端连接；
第二下拉节点控制晶体管，其中，所述第二下拉节点控制晶体管的栅极和第一极都与所述第一时钟信号输出端连接；
第三下拉节点控制晶体管，其中，所述第三下拉节点控制晶体管的栅极与所述第二下拉节点控制晶体管的第二极连接，所述第三下拉节点控制晶体管的第二极与所述下拉节点连接；以及，
第四下拉节点控制晶体管，其中，所述第四下拉节点控制晶体管的栅极与所述上拉节点连接，所述第四下拉节点控制晶体管的第一极与所述第三下拉节点控制晶体管的栅极连接，所述第四下拉节点控制晶体管的第二极与所述低电平输出端连接；
所述输出电路包括：
上拉晶体管，其中，所述上拉晶体管的栅极与所述上拉节点连接，所述上拉晶体管的第一极与所述第二时钟信号输出端连接，所述上拉晶体管的第二极与所述栅极驱动信号输出端连接；
下拉晶体管，其中，所述下拉晶体管的栅极与所述下拉节点连接，所述下拉晶体管的第一极与所述栅极驱动信号输出端连接，所述下拉晶体管的第二极与所述低电平输出端连接；以及，
输出晶体管，其中，所述输出晶体管的栅极与所述第一时钟信号输出端连 接，所述输出晶体管的第一极与所述栅极驱动信号输出端连接，所述输出晶体管的第二极与所述低电平输出端连接；
所述关机控制电路被配置为在接收到所述关机控制信号的状态下，控制所述上拉节点与所述关闭电压输出线连接，以使得所述第一下拉节点控制晶体管和所述上拉晶体管都关闭。
在本公开的另一方面，本公开的实施例还提供了一种移位寄存器电路的驱动方法，应用于上述的移位寄存器电路，所述移位寄存器电路的驱动方法包括：
在关机控制电路接收到关机控制信号的状态下，所述关机控制电路控制开启电压输出线向栅极驱动信号输出端施加开启电压，以使得与相应行栅线连接的像素电路中的薄膜晶体管都导通，并控制上拉节点与关闭电压输出线连接；
所述关闭电压输出线为地线或负电压输出线。
在本公开的又一方面本公开的实施例还提供了一种GOA电路，包括多个级联的上述的移位寄存器电路；
除了第一级移位寄存器电路之外，每一级移位寄存器电路包括的GOA子电路的输入端都与相邻上一级移位寄存器电路包括的GOA子电路的栅极驱动信号输出端连接；
除了最后一级移位寄存器电路之外，每一级移位寄存器电路包括的GOA子电路的复位端都与相邻下一级移位寄存器电路包括的GOA子电路的栅极驱动信号输出端连接。
在本公开的还一方面，本公开的实施例还提供了一种显示装置，包括上述的GOA电路。
附图说明
图1是本公开的至少一个实施例所述的移位寄存器电路的结构图；
图2是本公开的至少一个实施例所述的移位寄存器电路的结构图；
图3是本公开的至少一个实施例所述的移位寄存器电路的结构图；
图4是本公开的至少一个实施例的移位寄存器电路的电路图；
图5是图4所示的本公开的至少一个实施例的移位寄存器电路在正常显示时的工作时序图；
图6是图4所示的本公开的至少一个实施例的移位寄存器电路在关机时的 工作时序图；
图7是本公开的至少一个实施例的GOA电路的结构图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开的一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
如图1所示，本公开的至少一个实施例所述的移位寄存器电路，包括用于输出栅极驱动信号的GOA子电路10，所述GOA子电路10的栅极驱动信号输出端Output被配置为输出栅极驱动信号，所述GOA子电路10包括上拉节点PU，所述移位寄存器电路还包括关机控制电路11；
所述关机控制电路11分别与所述栅极驱动信号输出端Output、所述上拉节点PU、开启电压输出线Von和关闭电压输出线Voff连接，被配置为在接收到关机控制信号的状态下，例如接收到显示面板的关机控制信号，控制所述开启电压输出线Von向所述栅极驱动信号输出端Output连接，以使得与相应行栅线连接的像素电路中的薄膜晶体管(图1中未示出)都导通，并控制所述上拉节点PU与所述关闭电压输出线Voff连接；
所述关闭电压输出线Voff为地线或负电压输出线。
在本公开的一个实施例中，所述栅极驱动信号输出端Output与相应行栅线连接，由于与所述相应行栅线连接的像素电路中的薄膜晶体管一般为n型薄膜晶体管，因此Von输出的开启电压为能够控制所述薄膜晶体管都导通的高电平；
由于所述GOA子电路10包括的晶体管的类型一般也为n型，在本公开的一个实施例中，所述关闭电压输出线可以为地线或负电压输出线，以防止关机后上拉节点PU的残留电压使得该被所述上拉节点PU控制的晶体管打开或存在特性漂移。
本公开的至少一个实施例所述的移位寄存器电路通过采用关机控制电路11在显示面板关机时控制开启电压输出线Von向栅极驱动信号输出端Output施加开启电压，以使得与所述相应行栅线连接的像素电路中的薄膜晶体管都导 通，从而释放像素电极上残留的电荷，以消除关机残影，由于本公开的至少一个实施例所述的移位寄存器电路不是通过栅极驱动芯片(Gate DriverIC)来驱动所有栅线开启，因此不存在由于栅极驱动芯片驱动能力不足，不能使所有的栅线都打开，会存在线残影等的问题，并且本公开的至少一个实施例所述的移位寄存器电路通过关机控制电路11在显示面板关机时控制上拉节点PU与关闭电压输出线Voff连接，以防止关机后上拉节点PU的残留电压使得该被所述上拉节点PU控制的晶体管打开或存在特性漂移，从而在一定程度上防止不良发生。
具体的，所述关机控制电路可以包括：
输出控制电路，分别与所述栅极驱动信号输出端和所述开启电压输出线连接，被配置为在接收到关机控制信号的状态下，例如接收到显示面板的关机控制信号，控制所述开启电压输出线向所述栅极驱动信号输出端施加开启电压。
在本公开的一个实施例中，所述关机控制电路还可以包括：
第一上拉节点控制电路，分别与所述上拉节点和所述关闭电压输出线连接，被配置为在接收到关机控制信号的状态下，控制所述上拉节点与所述关闭电压输出线连接。
在本公开的一个实施例中，如图2所示，所述关机控制电路11可以包括：
输出控制电路111，分别与所述栅极驱动信号输出端Output和所述开启电压输出线Von连接，被配置为在接收到关机控制信号的状态下，控制所述开启电压输出线Von向所述栅极驱动信号输出端Output施加开启电压；以及，
第一上拉节点控制电路112，分别与所述上拉节点PU和所述关闭电压输出线Voff连接，被配置为在接收到关机控制信号的状态下，控制所述上拉节点PU与所述关闭电压输出线Voff连接。
所述关机控制电路11可以通过其包括的输出控制电路111、第一上拉节点控制电路112，分别在关机时控制栅极驱动信号输出端Output的电压状态、上拉节点PU的电压状态。
在本公开的一个实施例中，所述输出控制电路包括：输出控制晶体管，栅极与用于输出所述关机控制信号的关机控制信号输出线连接，第一极与所述开启电压输出线连接，第二极与所述栅极驱动信号输出端连接；
所述第一上拉节点控制电路包括：第一上拉节点控制晶体管，栅极与所述 关机控制信号输出线连接，第一极与所述上拉节点连接，第二极与所述关闭电压输出线连接。
如图3所示，所述输出控制电路111包括：输出控制晶体管MOC，栅极与用于输出所述关机控制信号的关机控制信号输出线T1连接，源极与所述开启电压输出线Von连接，漏极与所述栅极驱动信号输出端Output连接；
所述第一上拉节点控制电路包括112：第一上拉节点控制晶体管MUC，栅极与所述关机控制信号输出线T1连接，源极与所述上拉节点PU连接，漏极与所述关闭电压输出线Voff连接。
在本公开的一个实施例中，所述GOA子电路可以包括：
第二上拉节点控制电路，分别与输入端、复位端、第一时钟信号输出端、下拉节点和所述上拉节点连接，被配置为在输入端、复位端、第一时钟信号输出端、下拉节点和所述上拉节点的控制下控制所述上拉节点的电位；
充放电电路，第一端与所述上拉节点连接，第二端与所述栅极驱动信号输出端连接；
下拉节点控制电路，分别与所述第一时钟信号输出端和所述上拉节点连接，被配置为在所述第一时钟信号输出端和所述上拉节点的控制下控制所述下拉节点的电位；以及，
输出电路，分别与所述栅极驱动信号输出端、所述上拉节点、所述下拉节点、第一时钟信号输出端、第二时钟信号输出端和低电平输出端连接，被配置为在所述上拉节点的电位为第一电平的状态下，控制所述栅极驱动信号输出端与所述第二时钟信号输出端连接，在所述下拉节点的电位和/或所述第一时钟信号输出端输出的第一时钟信号为第一电平的状态下，控制栅极驱动信号输出端与所述低电平输出端连接。
在本公开的一个实施例的移位寄存器电路中，所述GOA子电路还包括：
复位电路，分别与所述复位端、所述栅极驱动信号输出端和所述低电平输出端连接，被配置为在所述复位端的控制下控制所述栅极驱动输出端是否与所述低电平输出端连接。
在本公开的一个实施例中，所述下拉节点控制电路可以包括：
第一下拉节点控制晶体管，栅极与所述上拉节点连接，第一极与所述下拉节点连接，第二极与低电平输出端连接；
第二下拉节点控制晶体管，栅极和第一极都与所述第一时钟信号输出端连接；
第三下拉节点控制晶体管，栅极与所述第二下拉节点控制晶体管的第二极连接，第二极与所述下拉节点连接；以及，
第四下拉节点控制晶体管，栅极所述上拉节点连接，第一极与所述第三下拉节点控制晶体管的栅极连接，第二极与所述低电平输出端连接；
所述输出电路包括：
上拉晶体管，栅极与所述上拉节点连接，第一极与所述第二时钟信号输出端连接，第二极与所述栅极驱动信号输出端连接；
下拉晶体管，栅极与所述下拉节点连接，第一极与所述栅极驱动信号输出端连接，第二极与所述低电平输出端连接；以及，
输出晶体管，栅极与所述第一时钟信号输出端连接，第一极与所述栅极驱动信号输出端连接，第二极与所述低电平输出端连接；
所述关机控制电路被配置为在接收到所述关机控制信号的状态下，控制所述上拉节点与所述关闭电压输出线连接，以使得所述第一下拉节点控制晶体管和所述上拉晶体管都关闭。
在接收到关机控制信号的状态下，关机控制电路控制将上拉节点的电位拉低，从而使得所述上拉晶体管和所述第一下拉控制晶体管都关闭。
下面通过本公开的一个实施例来说明本公开所述的移位寄存器电路。
相对于相关技术中的移位寄存器电路，本公开的至少一个实施例所述的GOA子电路的外围控制线增加了关机控制信号输出线T1和开启电压输出线Von；
以GOA电路包括的第N级移位寄存器电路(N为奇数)驱动电路为例，其电路图如图4所示，本公开的至少一个实施例的移位寄存器电路包括14个TFT(Thin Film Transistor，薄膜晶体管)、1个电容、2个时钟信号(第一时钟信号CLK1和第二时钟信号CLK2)、开启电压输出线Von、关机控制信号输出线T1(用于控制消除关机残影)、输入端INPUT，低电平输出线VSS、复位端RESET以及栅极驱动信号输出端Output；VSS输出直流低电平信号，CLK1与CLK2为周期相同、幅值不同的时钟信号(交替控制移位寄存器电路)，CLK1与CLK2反相，这里需要说明的是，第N+1级移位寄存器电路(N为奇数)为偶数级移位寄存器电路，相比于第N级移位寄存器电路，结构上CLK1与CLK2位置互换， 其余基本结构相同，这里不多做介绍。
在图4中，标号为PU的为上拉节点，标号为PD的为下拉节点，标号为PD CN的为下拉控制节点。
在图4中，关闭电压输出线采用低电平输出线VSS，也即关闭电压为低电平，所述低电平可以为地电平，也可以为负电压。
本公开的一个实施例中，如图4所示，M15为输出控制晶体管，M14为第一上拉节点控制晶体管，M6为第一下拉节点控制晶体管，M9为第二下拉节点控制晶体管，M5为第三下拉节点控制晶体管，M8为第四下拉节点控制晶体管，M3为上拉晶体管，M11为下拉晶体管，M12为输出晶体管；
第二上拉节点控制电路包括输入晶体管M1、复位晶体管M2、第二上拉节点控制晶体管M13、第三上拉节点控制晶体管M10；
复位电路包括输出复位晶体管M4；充放电电路包括存储电容C1。
在图4中，所有的晶体管都为n型晶体管，当第一极为源极时，第二极为漏极；当第一极为漏极时，第二极为源极。
以第N级移位寄存器电路(N为奇数)为例进行正常显示时序说明。当液晶面板正常显示时，第N级移位寄存器电路的工作时序如图5所示。此时，T1输出低电平，M14和M15都关闭，由INPUT输入的输入信号将M3打开，将第二时钟信号CLK2输入Output，产生输出的栅极驱动信号。当RESET输出的复位信号输入后，M1关闭，M2开启，PU与VSS相连，PU的电位被拉至低电平，M3关闭。此时第一时钟信号CLK1为高电平信号，M9开启，下拉控制节点PD CN的电位被置于高电平，M5开启，PD的电位升到高电平，M11开启，Output被VSS输出的低电平信号置于低电平。以此类推，第N级移位寄存器电路、第N+1级移位寄存器电路、第N+2级移位寄存器电路……依次产生相应的栅极驱动信号，对液晶面板进行驱动，完成液晶面板的正常显示。
同样以第N级移位寄存器电路(N为奇数)为例进行关机瞬间时序说明。在液晶面板关机瞬间，第N级移位寄存器电路的工作时序如图6所示。在关机瞬间T1输出高电平信号，此时M14和M15都打开，PU的电位被VSS拉低，被置于低电平，M3关闭，此时Output输出的栅极驱动信号变为Von输出的开启电压(Von输出的开启电压的电压值一般与高电压Vgh相同，约为27V)，与相应的栅线连接的薄膜晶体管(该薄膜晶体管为位于像素电路内的薄膜晶体管) 打开，释放像素电极中的电荷，达到消除关机残影的效果。以此类推，第N级移位寄存器电路、第N+1级移位寄存器电路、第N+2级移位寄存器电路……分别产生相应的栅极驱动信号，液晶面板上的AA区(Active Area，有效显示区)中的与所有栅线连接的薄膜晶体管都打开，同时释放像素电极中的电荷，达到对整个显示面板消除关机残影的效果。这里需要说明的是，在关机瞬间，在T1输出的信号的控制下，M15打开，通过VSS将PU的电位拉低，不仅将M3关闭，Output输出开启电压，还有一个重要作用就是在关机瞬间将PU的电位拉低，防止关机后PU的残留电压对移位寄存器电路内M3、M6等TFT特性的影响。如果不对PU进行放电，M3和M6可能被误打开，并且M3的TFT特性和M6的TFT特性会相应漂移，造成不良显示，影响液晶面板的品质。
本公开的一个实施例提供了所述的移位寄存器电路的驱动方法，应用于上述的移位寄存器电路，所述移位寄存器电路的驱动方法包括：
在关机控制电路接收到关机控制信号的状态下，所述关机控制电路控制开启电压输出线向栅极驱动信号输出端施加开启电压，以使得与相应行栅线连接的像素电路中的薄膜晶体管都导通，并控制上拉节点与关闭电压输出线连接；
所述关闭电压输出线为地线或负电压输出线。
本公开的一个实施例提供的GOA电路，包括多个级联的上述的移位寄存器电路。
在本公开的一个实施例的GOA电路中，除了第一级移位寄存器电路之外，每一级移位寄存器电路包括的GOA子电路的输入端都与相邻上一级移位寄存器电路包括的GOA子电路的栅极驱动信号输出端连接；
除了最后一级移位寄存器电路之外，每一级移位寄存器电路包括的GOA子电路的复位端都与相邻下一级移位寄存器电路包括的GOA子电路的栅极驱动信号输出端连接。
在图7中，S1标示第一级移位寄存器电路，S2标示第二移位寄存器电路，S3标示第三移位寄存器电路，S4标示第四移位寄存器电路，VSS为低电平输出线，CLK1为第一时钟信号，CLK2为第二时钟信号，T1为关机控制信号输出线，Von为开启电压输出线；
S1的输入端INPUT接入起始信号STV；
G1标示第一级移位寄存器电路S1的栅极驱动信号输出端；
S1的复位端与S2的栅极驱动信号输出端G2连接；
G1与S2的输入端连接；
G2与S3的输入端连接；S2的复位端与S3的栅极驱动信号输出端G3连接；
G3与S4的输入端连接，G4与S3的复位端连接。
本公开的至少一个实施例提供了一种显示装置，包括上述的GOA电路。
与相关技术相比，本公开的至少一个实施例的移位寄存器电路、驱动方法、GOA电路和显示装置，通过采用关机控制电路在显示面板关机时控制所有的栅极驱动信号输出端与开启电压输出线连接，以使得与所述相应行栅线连接的像素电路中的薄膜晶体管都导通，从而释放像素电极上残留的电荷，以消除关机残影，由于本公开的至少一个实施例所述的移位寄存器电路不是通过栅极驱动芯片(Gate Driver IC)来驱动所有栅线开启，因此不存在由于栅极驱动芯片驱动能力不足，不能使所有的栅线都打开，会存在线残影等的问题，并且本公开的至少一个实施例所述的移位寄存器电路通过关机控制电路在显示面板关机时控制上拉节点与关闭电压输出线连接，防止关机后上拉节点的残留电压使得该被所述上拉节点控制的晶体管的特性漂移，从而在一定程度上防止不良发生。
以上所述是本公开的一些实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (13)

  1. 一种移位寄存器电路，包括
    GOA子电路，所述GOA子电路的栅极驱动信号输出端被配置为输出栅极驱动信号，所述GOA子电路包括上拉节点；
    关机控制电路，所述关机控制电路分别与所述GOA子电路的栅极驱动信号输出端和上拉节点、以及所述移位寄存器电路的开启电压输出线和关闭电压输出线连接，被配置为在接收到关机控制信号的状态下，控制所述开启电压输出线向所述栅极驱动信号输出端施加开启电压，以使得与相应行栅线连接的像素电路中的薄膜晶体管都导通，并控制所述上拉节点与所述关闭电压输出线连接；
    所述关闭电压输出线为地线或负电压输出线。
  2. 如权利要求1所述的移位寄存器电路，其中，所述关机控制电路包括：
    输出控制电路，分别与所述栅极驱动信号输出端和所述开启电压输出线连接，被配置为在接收到所述关机控制信号的状态下，控制所述开启电压输出线向所述栅极驱动信号输出端施加所述开启电压。
  3. 如权利要求2所述的移位寄存器电路，其中，所述关机控制电路还包括：
    第一上拉节点控制电路，分别与所述上拉节点和所述关闭电压输出线连接，被配置为在接收到所述关机控制信号的状态下，控制所述上拉节点与所述关闭电压输出线连接。
  4. 如权利要求3所述的移位寄存器电路，其中，所述输出控制电路包括：输出控制晶体管，其中，所述输出控制晶体管的栅极与用于输出所述关机控制信号的关机控制信号输出线连接，所述输出控制晶体管的第一极与所述开启电压输出线连接，所述输出控制晶体管的第二极与所述栅极驱动信号输出端连接；
    所述第一上拉节点控制电路包括：第一上拉节点控制晶体管，其中，所述第一上拉节点控制晶体管的栅极与所述关机控制信号输出线连接，所述第一上拉节点控制晶体管的第一极与所述上拉节点连接，所述第一上拉节点控制晶体管的第二极与所述关闭电压输出线连接。
  5. 如权利要求1至4中任一权利要求所述的移位寄存器电路，其中，所述GOA子电路包括：
    第二上拉节点控制电路，分别与输入端、复位端、第一时钟信号输出端、下拉节点和所述上拉节点连接，被配置为在所述输入端、所述复位端、所述第一时钟信号输出端、所述下拉节点和所述上拉节点的控制下控制所述上拉节点的电位；
    充放电电路，第一端与所述上拉节点连接，第二端与所述栅极驱动信号输出端连接；
    下拉节点控制电路，分别与所述第一时钟信号输出端和所述上拉节点连接，被配置为在所述第一时钟信号输出端和所述上拉节点的控制下控制所述下拉节点的电位；以及，
    输出电路，分别与所述栅极驱动信号输出端、所述上拉节点、所述下拉节点、所述第一时钟信号输出端、第二时钟信号输出端和低电平输出端连接；
    其中，在所述上拉节点的电位为第一电平的状态下，所述控制电路被配置为控制所述栅极驱动信号输出端与所述第二时钟信号输出端连接。
  6. 如权利要求5所述的移位寄存器电路，其中，所述GOA子电路还包括：
    复位电路，分别与所述复位端、所述栅极驱动信号输出端和所述低电平输出端连接，被配置为在所述复位端的控制下控制所述栅极驱动输出端与所述低电平输出端连接或与所述低电平输出端断开连接。
  7. 如权利要求5所述的移位寄存器电路，其中，
    所述下拉节点控制电路包括：
    第一下拉节点控制晶体管，其中，所述第一下拉节点控制晶体管的栅极与所述上拉节点连接，所述第一下拉节点控制晶体管的第一极与所述下拉节点连接，所述第一下拉节点控制晶体管的第二极与所述低电平输出端连接；
    第二下拉节点控制晶体管，其中，所述第二下拉节点控制晶体管的栅极和第一极都与所述第一时钟信号输出端连接；
    第三下拉节点控制晶体管，其中，所述第三下拉节点控制晶体管的栅极与所述第二下拉节点控制晶体管的第二极连接，所述第三下拉节点控制晶体管的第二极与所述下拉节点连接；以及，
    第四下拉节点控制晶体管，其中，所述第四下拉节点控制晶体管的栅极所述上拉节点连接，所述第四下拉节点控制晶体管的第一极与所述第三下拉节点控制晶体管的栅极连接，所述第四下拉节点控制晶体管的第二极与所述低电平 输出端连接；
    所述输出电路包括：
    上拉晶体管，其中，所述上拉晶体管的栅极与所述上拉节点连接，所述上拉晶体管的第一极与所述第二时钟信号输出端连接，所述上拉晶体管的第二极与所述栅极驱动信号输出端连接；
    下拉晶体管，其中，所述下拉晶体管的栅极与所述下拉节点连接，所述下拉晶体管的第一极与所述栅极驱动信号输出端连接，所述下拉晶体管的第二极与所述低电平输出端连接；以及，
    输出晶体管，其中，所述输出晶体管的栅极与所述第一时钟信号输出端连接，所述输出晶体管的第一极与所述栅极驱动信号输出端连接，所述输出晶体管的第二极与所述低电平输出端连接；
    所述关机控制电路被配置为在接收到所述关机控制信号的状态下，控制所述上拉节点与所述关闭电压输出线连接，以使得所述第一下拉节点控制晶体管和所述上拉晶体管都关闭。
  8. 如权利要求1至4中任一权利要求所述的移位寄存器电路，其中，所述GOA子电路包括：
    第二上拉节点控制电路，分别与输入端、复位端、第一时钟信号输出端、下拉节点和所述上拉节点连接，被配置为在所述输入端、所述复位端、所述第一时钟信号输出端、所述下拉节点和所述上拉节点的控制下控制所述上拉节点的电位；
    充放电电路，第一端与所述上拉节点连接，第二端与所述栅极驱动信号输出端连接；
    下拉节点控制电路，分别与所述第一时钟信号输出端和所述上拉节点连接，被配置为在所述第一时钟信号输出端和所述上拉节点的控制下控制所述下拉节点的电位；以及，
    输出电路，分别与所述栅极驱动信号输出端、所述上拉节点、所述下拉节点、所述第一时钟信号输出端、第二时钟信号输出端和低电平输出端连接；
    其中，所述下拉节点的电位和/或所述第一时钟信号输出端输出的第一时钟信号为第一电平，所述控制电路被配置为控制所述栅极驱动信号输出端与所述低电平输出端连接。
  9. 如权利要求8所述的移位寄存器电路，其中，所述GOA子电路还包括：
    复位电路，分别与所述复位端、所述栅极驱动信号输出端和所述低电平输出端连接，被配置为在所述复位端的控制下控制所述栅极驱动输出端与所述低电平输出端连接或与所述低电平输出端断开连接。
  10. 如权利要求8所述的移位寄存器电路，其中，
    所述下拉节点控制电路包括：
    第一下拉节点控制晶体管，其中，所述第一下拉节点控制晶体管的栅极与所述上拉节点连接，所述第一下拉节点控制晶体管的第一极与所述下拉节点连接，所述第一下拉节点控制晶体管的第二极与所述低电平输出端连接；
    第二下拉节点控制晶体管，其中，所述第二下拉节点控制晶体管的栅极和第一极都与所述第一时钟信号输出端连接；
    第三下拉节点控制晶体管，其中，所述第三下拉节点控制晶体管的栅极与所述第二下拉节点控制晶体管的第二极连接，所述第三下拉节点控制晶体管的第二极与所述下拉节点连接；以及，
    第四下拉节点控制晶体管，其中，所述第四下拉节点控制晶体管的栅极所述上拉节点连接，所述第四下拉节点控制晶体管的第一极与所述第三下拉节点控制晶体管的栅极连接，所述第四下拉节点控制晶体管的第二极与所述低电平输出端连接；
    所述输出电路包括：
    上拉晶体管，其中，所述上拉晶体管的栅极与所述上拉节点连接，所述上拉晶体管的第一极与所述第二时钟信号输出端连接，所述上拉晶体管的第二极与所述栅极驱动信号输出端连接；
    下拉晶体管，其中，所述下拉晶体管的栅极与所述下拉节点连接，所述下拉晶体管的第一极与所述栅极驱动信号输出端连接，所述下拉晶体管的第二极与所述低电平输出端连接；以及，
    输出晶体管，其中，所述输出晶体管的栅极与所述第一时钟信号输出端连接，所述输出晶体管的第一极与所述栅极驱动信号输出端连接，所述输出晶体管的第二极与所述低电平输出端连接；
    所述关机控制电路被配置为在接收到所述关机控制信号的状态下，控制所述上拉节点与所述关闭电压输出线连接，以使得所述第一下拉节点控制晶体管 和所述上拉晶体管都关闭。
  11. 一种移位寄存器电路的驱动方法，应用于如权利要求1至10中任一权利要求所述的移位寄存器电路，其中，所述移位寄存器电路的驱动方法包括：
    在关机控制电路接收到关机控制信号的状态下，所述关机控制电路控制开启电压输出线向栅极驱动信号输出端施加开启电压，以使得与相应行栅线连接的像素电路中的薄膜晶体管都导通，并控制上拉节点与关闭电压输出线连接；
    所述关闭电压输出线为地线或负电压输出线。
  12. 一种GOA电路，包括多个级联的如权利要求1至10中任一权利要求所述的移位寄存器电路；
    除了第一级移位寄存器电路之外，每一级移位寄存器电路包括的GOA子电路的输入端都与相邻上一级移位寄存器电路包括的GOA子电路的栅极驱动信号输出端连接；
    除了最后一级移位寄存器电路之外，每一级移位寄存器电路包括的GOA子电路的复位端都与相邻下一级移位寄存器电路包括的GOA子电路的栅极驱动信号输出端连接。
  13. 一种显示装置，包括如权利要求12所述的GOA电路。
PCT/CN2017/102174 2017-01-03 2017-09-19 移位寄存器电路、驱动方法、goa电路和显示装置 WO2018126732A1 (zh)

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