WO2018126716A1 - 移位寄存器单元及其驱动方法、栅极驱动装置和显示装置 - Google Patents

移位寄存器单元及其驱动方法、栅极驱动装置和显示装置 Download PDF

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Publication number
WO2018126716A1
WO2018126716A1 PCT/CN2017/099388 CN2017099388W WO2018126716A1 WO 2018126716 A1 WO2018126716 A1 WO 2018126716A1 CN 2017099388 W CN2017099388 W CN 2017099388W WO 2018126716 A1 WO2018126716 A1 WO 2018126716A1
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WIPO (PCT)
Prior art keywords
pull
node
voltage terminal
shift register
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/099388
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English (en)
French (fr)
Inventor
熊雄
刘荣铖
刘金良
张晓哲
李环宇
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to US15/765,214 priority Critical patent/US10650904B2/en
Publication of WO2018126716A1 publication Critical patent/WO2018126716A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to a shift register unit and a driving method thereof, a gate driving device, and a display device.
  • TFT-LCDs Thin film transistor liquid crystal displays
  • the driving circuit of the TFT-LCD mainly includes a gate driving circuit and a data driving circuit.
  • the data driving circuit is configured to sequentially latch the input data according to the clock signal timing and input the latched data to the data line of the display panel.
  • the gate driving circuit is usually implemented by a shift register unit that converts a clock signal into an on/off voltage, which are respectively output to respective gate lines of the display panel.
  • a gate line on the display panel is typically interfaced to a shift register unit (ie, the stage of the shift register unit).
  • the progressive scan of the pixels in the display panel is realized by causing the respective shift register units to sequentially output the turn-on voltages.
  • the GOA technology directly integrates the gate driving circuit of the TFT-LCD on the array substrate, thereby replacing the driving chip made of the silicon chip bonded on the outer edge of the panel. Since the technology can directly drive the driving circuit on the array substrate, there is no need to bond the IC and the wiring around the panel, which reduces the manufacturing process of the panel, reduces the product cost, and improves the integration degree of the TFT-LCD panel, so that the panel can be realized. Narrow borders and high resolution.
  • the present disclosure provides a shift register unit and a driving method thereof, a gate driving device, and a display device.
  • the pull-up node control circuit realizes sufficient discharge of the shift register unit, so that the potential of the pull-up node in the shift register unit can be completely released, thereby preventing the shift register unit from working normally due to abnormal shutdown, thereby ensuring the product Quality, extending the life of the TFT-LCD to which the shift register unit is applied.
  • a shift register unit comprising: an input circuit having a first end receiving an input signal of the shift register unit, a second end connected to a pull-up node, and the input circuit being The output circuit is configured to output the input signal to the pull-up node; the output circuit has a first end connected to the clock signal end, a second end connected to the pull-up node, and a third end connected to the output end of the shift register unit And the output circuit is configured to output the signal of the clock signal end to the output end under the control of the pull-up node; the pull-up node control circuit has a first end connected to the first power supply voltage end, The second end is connected to the third power voltage terminal, and the third end is connected to the pull-up node, and configured to: connect the pull-up node through the third power voltage terminal under the control of the first power voltage terminal Discharge.
  • the pull-up node control circuit passes the third control under the control of the second level when the first power voltage terminal transitions from a first level to a second level
  • the power supply voltage terminal discharges the pull-up node; when the first power supply voltage terminal jumps from the second level to the zero voltage, the pull-up node control circuit continues to pass the third power supply voltage terminal to the upper The pull node is discharged until the pull up node is at zero voltage.
  • the pull-up node control circuit includes: a first transistor having a gate and a first pole connected to the first power voltage terminal; and a first capacitor having a first end and a second pole of the first transistor a second terminal connected to the third power supply voltage terminal; .
  • the first level of the first power voltage terminal is a low level
  • the second level of the first power voltage terminal is a high level
  • the third power source is at a first level when the first power voltage terminal is at a first level
  • the voltage terminal is also at a first level
  • the third supply voltage terminal is still at a first level or at a zero voltage when the first supply voltage terminal is at a second level.
  • a driving method of a shift register unit includes an input circuit, an output circuit, and a pull-up node control circuit, the method comprising: when the first power voltage terminal transitions from the first level to the second level, the pull-up node control circuit is in the Under the control of the second level, the pull-up node is discharged through the third power voltage terminal.
  • the method further includes: when the first power supply voltage terminal transitions from the second level to the zero voltage, the pull-up node control circuit continues to pass the third power supply voltage terminal The pull up node discharges until the pull up node is at zero voltage.
  • the method before the first power voltage terminal transitions from the first level to the second level, the method further includes: a first operation phase, receiving an input signal of the shift register unit and inputting the input a signal is output to the pull-up node, the output circuit outputs a signal of the clock signal end to the output terminal under the control of the pull-up node; in a second operation phase, the output circuit maintains the pull-up The level of the node continues to output the signal at the clock signal end to the output.
  • a gate driving apparatus including a plurality of series-connected shift register units, each of the shift register units being the shift register unit, wherein the last shift register unit is disclosed
  • the output of each of the remaining shift register units is connected to the input of the next shift register unit adjacent thereto; the input of the first shift register unit inputs a frame start signal.
  • a display device including the above-described gate driving device is disclosed.
  • Figure 1 shows a circuit diagram of a shift register unit
  • FIG. 2 is a timing chart showing the operation of the shift register unit of FIG. 1;
  • FIG. 3 illustrates a block diagram of a shift register unit in accordance with an embodiment of the present disclosure
  • FIG. 4 shows a schematic circuit diagram of a shift register unit in accordance with an embodiment of the present invention
  • FIG. 5 illustrates an operation method of a shift register unit according to an embodiment of the present invention
  • FIG. 6 shows a block diagram of a shift register unit in accordance with another embodiment of the present disclosure.
  • FIG. 7 illustrates an example circuit configuration diagram of a shift register unit according to another embodiment of the present disclosure
  • FIG. 8 is a timing chart showing an operation of an example circuit of the shift register unit of FIG. 7;
  • FIG. 9 shows a schematic diagram of a gate driving device formed by cascading a plurality of shift register cells according to an embodiment of the present disclosure.
  • the transistors employed in all embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other device having the same characteristics.
  • the connection modes of the drain and the source of each transistor are interchangeable. Therefore, the drain and source of each transistor in the embodiment of the present disclosure are practically indistinguishable.
  • one of the drain and the source of the transistor is referred to as the first pole of the transistor, and the other is referred to as the second pole of the transistor.
  • FIG. 1 is a circuit diagram of a shift register unit
  • FIG. 2 is a timing chart showing the operation of the shift register unit of FIG. 1.
  • the duty ratio of the clock signal input to the clock signal terminal CLK is 50%
  • the first power supply voltage terminal VSS1 is the low power supply voltage terminal
  • the second power supply voltage terminal VDD is the high power supply voltage terminal, and is the shift.
  • the register unit inputs a noise reduction signal.
  • the input signal of the input terminal INPUT of the shift register unit is at a low level, and the input transistor M1 is turned off, although the clock signal at the clock signal terminal CLK is at a high level, but due to the pull-up node PU The pull-up signal is at a low level, the output transistor M2 is turned off, and the output terminal OUTPUT is outputted at a low level.
  • the input signal of the input terminal INPUT of the shift register unit is at a high level, and the clock signal at the clock signal terminal CLK is at a low level, at which time the input transistor M1 is turned on, and the input terminal INPUT is high.
  • the level is transferred to the pull-up node PU.
  • the pull-up node PU rises to a high level, so that the output transistor M2 is turned on. Since the clock signal of the clock signal terminal CLK is at a low level, the output terminal OUTPUT still outputs a low level.
  • the input signal of the input terminal INPUT of the shift register unit is at a low level, and the clock signal at the clock signal terminal CLK is at a high level, at which time the input transistor M1 is turned off.
  • the potential of the pull-up node PU is continuously maintained at a high level due to the presence of the second capacitor C1, thereby continuing to turn on the output transistor M2. Since the clock signal of the clock signal terminal CLK is at a high level, the output terminal OUTPUT outputs a high level. Further, due to the bootstrap action of the second capacitor C1, the potential of the pull-up node PU continues to rise at this time. Meanwhile, since the potential of the pull-up node PU is at the high level, the transistor M7 is turned on, so that the pull-down node PD is pulled down to the low level of the first power supply voltage terminal VSS1.
  • the signal of the first power supply voltage terminal VSS1 is pulled high to the high level and the second power supply voltage terminal VDD is simultaneously kept at the high level, and then the first power supply The signal of the voltage terminal VSS1 and the second power supply voltage terminal VDD simultaneously rapidly drops to a low level.
  • the voltage pulling of the first power voltage terminal VSS1 is specifically designed to solve the problem of image sticking during shutdown.
  • the voltage of the first power voltage terminal VSS1 is pulled when the power is turned off. It is high enough to enable each gate line to simultaneously output a high level, so that each pixel is discharged to eliminate image sticking.
  • the voltage of the first power supply voltage terminal VSS1 is pulled high, and the potential of the pull-down node PD cannot be pulled high to the high level, so that the transistor M5 cannot be turned on, and the potential of the pull-up node PU cannot be released.
  • Long-term, multiple-time abnormal shutdown will cause the relevant TFT characteristics of the above shift register unit (ie, GOA circuit) to change, which may cause the shift register unit to output an abnormality.
  • the present disclosure provides a shift register unit that achieves full discharge of a shift register unit by a pull-up node control circuit, so that the potential of the pull-up node in the shift register unit can be completely released, thereby avoiding The shift register unit does not work normally due to abnormal shutdown, thereby ensuring the quality of the product and prolonging the service life of the TFT-LCD to which the shift register unit is applied.
  • the third power supply voltage terminal VSS2 is added, and the third power supply voltage terminal VSS2 does not jump from a low level to a high level like the first power supply voltage terminal VSS1 when the power is turned off, but It becomes 0V.
  • the pull-up node control circuit 16 pulls the pull-up node PU to 0V of the second power supply voltage terminal VSS2 under the control of the first power voltage terminal VSS1 and the second power voltage terminal VSS2, Thereby a reliable discharge to the pull-up node PU is achieved.
  • FIG. 3 shows a block diagram of a shift register unit in accordance with an embodiment of the present disclosure.
  • the shift register unit 100 includes an input circuit 11, an output circuit 12, and a pull-up node control circuit 16.
  • the first end of the input circuit 11 receives the input signal INPUT of the shift register unit, The two ends are connected to the pull-up node PU, and the input circuit 11 is configured to output the input signal INPUT to the pull-up node PU.
  • the first end of the output circuit 12 is connected to the clock signal terminal CLK, the second end is connected to the pull-up node PU, the third end is connected to the output terminal OUTPUT of the shift register unit, and the output circuit 12 is configured as The signal of the clock signal terminal CLK is output to the output terminal OUTPUT under the control of the pull-up node PU.
  • the first end of the pull-up node control circuit 16 is connected to the first power supply voltage terminal VSS1, the second end is connected to the third power supply voltage terminal VSS2, the third end is connected to the pull-up node PU, and the pull-up node is controlled.
  • the circuit 16 is configured to discharge the pull-up node PU through the third power supply voltage terminal VSS2 under the control of the first power supply voltage terminal VSS1.
  • the pull-up node control circuit passes the third control under the control of the second level
  • the power supply voltage terminal discharges the pull-up node.
  • the pull-up node control circuit continues to discharge the pull-up node through the third power voltage terminal. Until the pull-up node is at zero voltage.
  • the pull-up node control circuit further includes a fourth end connected to the input terminal INPUT of the shift register unit, and the pull-up node control circuit 16 is further configured as an input at the input end When the signal is at an active level, the pull-up node PU is guaranteed not to be pulled down erroneously.
  • FIG. 4 shows a schematic circuit diagram of a shift register unit in accordance with an embodiment of the present disclosure.
  • input circuit 11 includes an input transistor M1.
  • the gate and the first pole of the input transistor M1 are connected to the input terminal INPUT, and the second pole is connected to the pull-up node PU.
  • the input transistor M1 is turned on, and the input signal of the input terminal INPUT is transmitted to the pull-up node PU.
  • output circuit 12 includes an output transistor M2 and a second capacitor C1.
  • the gate of the output transistor M2 is connected to the pull-up node PU, the first pole is connected to the clock signal terminal CLK, and the second pole is connected to the output terminal OUTPUT.
  • the first end of the second capacitor C1 is connected to the pull-up node PU, and the second end is connected to the output terminal OUTPUT.
  • the pull-up node control circuit 16 includes a first transistor M8, A capacitor C2 and a second transistor M9.
  • the gate and the first pole of the first transistor M8 are connected to the first power supply voltage terminal VSS1, and the second pole is connected to the first terminal of the first capacitor C2.
  • the second end of the first capacitor C2 is connected to the third power supply voltage terminal VSS2.
  • the gate of the second transistor M9 is connected to the first end of the first capacitor C2, the first pole is connected to the pull-up node PU, and the second pole is connected to the third power supply voltage terminal VSS2.
  • the pull-up node control circuit 16 further includes a third transistor M10 whose gate is connected to the input terminal INPUT of the shift register unit, the first pole is connected to the first end of the first capacitor C2, and the second The pole is connected to the first power supply voltage terminal VSS1, so that the gate of the second transistor M9 is discharged through the first power supply voltage terminal VSS1 under the control of the input signal of the input terminal INPUT.
  • FIG. 5 illustrates a driving method of a shift register unit according to an embodiment of the present invention.
  • the driving method of the shift register unit according to an embodiment of the present invention is suitable for an operation when the display device is turned off.
  • a shutdown signal is received.
  • the first power supply voltage terminal transitions from the first level to the second level, and the pull-up node control circuit passes the third power supply voltage terminal under the control of the second level.
  • the pull-up node is described for discharging.
  • step 503 when the first power voltage terminal jumps from the second level to the zero voltage, the pull-up node control circuit continues to discharge the pull-up node through the third power voltage terminal. Until the pull-up node is at zero voltage.
  • FIG. 6 shows another schematic block diagram of a shift register unit in accordance with an embodiment of the present disclosure.
  • the shift register unit 100 includes an input circuit 11, an output circuit 12, a pull-down circuit 14, a pull-down control circuit 15, and a pull-up node control circuit 16.
  • the first end of the input circuit 11 is coupled to the input terminal INPUT of the shift register unit for receiving an input signal from the input terminal INPUT, and the second end is coupled to the pull-up node PU.
  • the input circuit 11 is configured to pass the received input signal to the pull-up node PU when the input signal at the input INPUT is at an active input level.
  • the first end of the output circuit 12 is connected to the clock signal terminal CLK, the second end is connected to the pull-up node PU, and the third end is connected to the output terminal OUTPUT of the shift register unit.
  • the output circuit 12 is configured to output a clock signal of the clock signal terminal CLK to the output terminal OUTPUT when the pull-up signal at the pull-up node PU is at an effective pull-up level.
  • the first end of the pull-down control circuit 15 is connected to the second power supply voltage terminal VDD, the second end is connected to the pull-down node PD, the third end is connected to the first power supply voltage terminal VSS1, and the fourth end is connected to the pull-up node PU. connection.
  • the pull-down control circuit 15 is configured to control the level at the pull-down node PD according to the level at the pull-up node PU, thereby controlling whether the pull-down circuit 14 is operating.
  • the pull-down control circuit 15 causes the level of the pull-down node to be opposite to the level of the pull-up node when the levels of the first power supply voltage terminal and the second power supply voltage terminal are opposite, specifically at the pull-up node PU
  • the pull-up signal is at the effective pull-up level
  • a pull-down signal at the pull-down node PD is generated at the non-active pull-down level
  • the pull-up signal at the pull-up node PU is at the non-active pull-up level
  • a pull-down signal at a valid pull-down level is generated.
  • the first end of the pull-down circuit 14 is connected to the pull-down node PD, the second end is connected to the pull-up node PU, and the third end is connected to the first power supply voltage terminal VSS1.
  • the pull-down circuit 14 is configured to pull down the pull-up node by the first power voltage terminal under the control of the pull-down node PD, for example, when the pull-down signal at the pull-down node PD is at a valid pull-down level The level at the pull-up node PU is pulled down to the power supply voltage of the first power supply voltage terminal VSS1.
  • the first end of the pull-up node control circuit 16 is connected to the first power supply voltage terminal VSS1, the second terminal is connected to the third power supply voltage terminal VSS2, and the third terminal is connected to the pull-up node PU.
  • the pull-up node control circuit 16 is configured to discharge the pull-up node through the third power supply voltage terminal VSS2 under the control of the first power supply voltage terminal VSS1. For example, when the first power voltage terminal VSS1 transitions from the first level to the second level, the pull-up node control circuit 16 passes the third power voltage under the control of the second level.
  • the terminal VSS2 discharges the pull-up node.
  • the pull up node control circuit 16 in the event of an abnormal shutdown, is configured to discharge the pull up node PU when the first supply voltage terminal VSS1 suddenly transitions to a high level. In another embodiment, when the first power voltage terminal jumps from the second level to the zero voltage, the pull-up node control circuit continues to discharge the pull-up node through the third power voltage terminal until The pull up node is at zero voltage.
  • the pull-up node control circuit 16 of the shift register unit 100 further includes a fourth end, and the fourth end and the input terminal INPUT of the shift register unit connection.
  • the pull-up node control circuit 16 is configured to control the level at the pull-up node PU according to the first supply voltage terminal VSS1, the third supply voltage terminal VSS2, and the input terminal INPUT.
  • the pull-up node control circuit 16 is configured to discharge the pull-up node through the third power supply voltage terminal VSS2 under the control of the first power supply voltage terminal VSS1.
  • the pull-up node control circuit 16 is further configured to ensure that the pull-up node PU is not erroneously pulled down when the input terminal INPUT is at an active level under the control of the input signal at the input.
  • the first power supply voltage terminal VSS1 and the third power supply voltage terminal VSS2 are low power supply voltage terminals, and the second power supply voltage terminal VDD is a high power supply voltage terminal.
  • the shift register unit 100 further includes a reset circuit 13.
  • the first end of the reset circuit 13 is connected to the reset signal terminal RESET, the second end is connected to the pull-up node PU, the third end is connected to the first power supply voltage terminal VSS1, and the fourth end is connected to the output terminal OUTPUT of the shift register unit. .
  • the reset circuit 13 is configured to reset the pull-up signal at the pull-up node PU to the power supply voltage of the first power supply voltage terminal VSS1 and reset the output signal of the output terminal OUTPUT when the reset signal of the reset signal terminal RESET is at the active control level.
  • the power supply voltage to the first power supply voltage terminal VSS1.
  • the present disclosure also provides a driving method of the above shift register unit.
  • the method will be described below with reference to Figs. 6-8.
  • the shift register unit 100 includes an input circuit 11, an output circuit 12, a pull-down circuit 14, a pull-down control circuit 15, and a pull-up node control circuit 16.
  • the method includes:
  • the received input signal is passed to the pull-up node PU by the input circuit 11.
  • the clock signal of the clock signal terminal CLK is output from the output circuit 12 to the output terminal OUTPUT of the shift register unit.
  • the shutdown signal is received, and the first power supply voltage terminal VSS1 transitions from a low level to a high level.
  • the pull-up node control circuit 16 discharges the pull-up node PU.
  • the first power supply voltage terminal VSS1 transitions from a high level to a zero voltage.
  • the pull-up node control circuit 16 continues to discharge the pull-up node PU until the pull-up node PU reaches zero voltage.
  • the shift register unit 100 further includes a reset circuit 13, and the driving method of the shift register unit further includes a pull-up signal at the pull-up node PU by the reset circuit 13.
  • the power supply voltage reset to the first power supply voltage terminal VSS1 and the output signal of the output terminal OUTPUT of the shift register unit are reset to the power supply voltage of the first power supply voltage terminal VSS1.
  • FIG. 7 illustrates an example circuit configuration diagram of a shift register unit in accordance with an embodiment of the present disclosure.
  • the transistors in FIG. 7 are all N-type transistors as an example. As is well known to those skilled in the art, the N-type transistor is turned on when the gate input is high.
  • input circuit 11 includes an input transistor M1.
  • the gate and the first pole of the input transistor M1 are connected to the input terminal INPUT, and the second pole is connected to the pull-up node PU.
  • the input transistor M1 is turned on, and the input signal of the input terminal INPUT is transmitted to the pull-up node PU.
  • output circuit 12 includes an output transistor M2 and a second capacitor C1.
  • the gate of the output transistor M2 is connected to the pull-up node PU, the first pole is connected to the clock signal terminal CLK, and the second pole is connected to the output terminal OUTPUT.
  • the first end of the second capacitor C1 is connected to the pull-up node PU, and the second end is connected to the output terminal OUTPUT.
  • pull-down control circuit 15 includes a first pull-down control transistor M6 and a second pull-down control transistor M7.
  • the gate and the first pole of the first pull-down control transistor M6 are connected to the second power supply voltage terminal VDD, and the second pole is connected to the pull-down node PD.
  • the gate of the second pull-down control transistor M7 is connected to the pull-up node PU, the first pole is connected to the pull-down node PD, and the second pole is connected to the first power supply voltage terminal VSS1.
  • the high-level signal outputted by the second power supply voltage terminal VDD causes the first pull-down control transistor M6 to be turned on, and generates a high level at the pull-down node PD.
  • the pull-down signal is such that the pull-down transistor M5 is turned on; and when the pull-up signal PU at the pull-up node PU is at a high level, the second pull-down control transistor M7 is turned on, by reasonably selecting the first pull-down control transistor M6 and the second
  • the channel parameters e.g., channel width to length ratio
  • the control transistor M7 are pulled down to generate a pull-down signal at a low level at the pull-down node PD, so that the pull-down transistor M5 is not turned on.
  • the pull down circuit 14 includes a pull down transistor M5.
  • the gate of the pull-down transistor M5 is connected to the pull-down node PD, the first pole is connected to the pull-up node PU, and the second pole is connected to the first power supply voltage terminal VSS1.
  • the pull-down transistor M5 is turned on, pulling down the pull-up signal at the pull-up node PU to the power supply voltage of the first power supply voltage terminal VSS1.
  • the pull up node control circuit 16 includes a first transistor M8, a first capacitor C2, and a second transistor M9.
  • the gate and the first pole of the first transistor M8 are connected to the first power supply voltage terminal VSS1, and the second pole is connected to the first terminal of the first capacitor C2.
  • the second end of the first capacitor C2 is connected to the third power supply voltage terminal VSS2.
  • the gate of the second transistor M9 is connected to the first end of the first capacitor C2, the first pole is connected to the pull-up node PU, and the second pole is connected to the third power supply voltage terminal VSS2.
  • the pull-up node control circuit 16 further includes a third crystal
  • the tube M10 has a gate connected to the input terminal INPUT of the shift register unit, a first pole connected to the first end of the first capacitor C2, and a second pole connected to the first power supply voltage terminal VSS1.
  • the shift register unit 100 further includes a reset circuit 13.
  • the reset circuit 13 includes a node reset transistor M3 and an output reset transistor M4.
  • the gate of the node reset transistor M3 is connected to the reset signal terminal RESET, the first pole is connected to the pull-up node PU, and the second pole is connected to the first power supply voltage terminal VSS1.
  • the gate of the output reset transistor M4 is connected to the reset signal terminal RESET, the first pole is connected to the output terminal OUTPUT, and the second pole is connected to the first power supply voltage terminal VSS1.
  • the node reset transistor M3 When the reset signal at the reset signal terminal RESET is at a high level, the node reset transistor M3 is turned on, the pull-up signal at the pull-up node PU is reset to the power supply voltage of the first power supply voltage terminal VSS1, and the output reset transistor M4 is turned on. The output signal of the output terminal OUTPUT is reset to the power supply voltage of the first power supply voltage terminal VSS1.
  • the first power supply voltage terminal VSS1 and the third power supply voltage terminal VSS2 are low power supply voltage terminals, and the second power supply voltage terminal VDD is a high power supply voltage terminal.
  • the pull-up node control circuit 16 realizes the complete release of the potential of the pull-up node PU in the shift register unit during the abnormal shutdown, thereby preventing the shift register unit from being damaged due to the abnormal shutdown. In turn, the quality of the product is ensured, thereby extending the service life of the TFT-LCD to which the shift register unit is applied.
  • FIG. 8 shows an operational timing diagram of an example circuit of the shift register unit of FIG.
  • the driving method of the shift register unit in Fig. 7 will be described below with reference to Figs. 7 and 8.
  • the input signal to the INPUT input is at a low level.
  • the input transistor M1 is turned off.
  • the clock signal at the clock signal terminal CLK is at a high level, since the pull-up signal at the pull-up node PU is at a low level, the output transistor M2 is turned off, and the output terminal OUTPUT is outputted at a low level.
  • the input signal of the input terminal INPUT is at a high level, and the clock signal at the clock signal terminal CLK is at a low level.
  • the input transistor M1 is turned on, and the high level of the input terminal INPUT is transmitted to the pull-up node PU.
  • the pull-up node PU is at the first high voltage, so that the output transistor M2 is turned on, because the clock signal of the clock signal terminal CLK is low. Level, output OUTPUT output low level.
  • the second pull-down control transistor M7 is turned on, thereby generating a pull-down signal at a low level at the pull-down node PD.
  • the input signal of the input terminal INPUT is at a low level, and the input transistor M1 is turned off. Since the voltage of the second capacitor C1 remains active, the pull-up node PU continues to make The output transistor M2 is turned on, and since the clock signal of the clock signal terminal CLK is at a high level, the output terminal OUTPUT outputs a high level, and thus the pull-up node PU is driven from the first high due to the voltage coupling of the second capacitor C1. The voltage is raised to the second high voltage. Further, in this stage, since the pull-up node PU is at the high level, the second pull-down control transistor M7 remains turned on, and the pull-down node PD is still at the low level.
  • the signal of the first power supply voltage terminal VSS1 is simultaneously pulled high to the high level and the second power supply voltage terminal VDD is simultaneously kept high, and then The signals of the first power supply voltage terminal VSS1 and the second power supply voltage terminal VDD are simultaneously simultaneously lowered to a low level (see VSS1 and VDD shown in the fourth stage 4 of FIG. 8).
  • a third power voltage terminal VSS2 is introduced, and the signal of the third power voltage terminal VSS2 is substantially consistent with the signal of the first power voltage terminal VSS1, but is not pulled high to the high level when the power is turned off. (This part of the PCBA can be implemented), but is pulled to 0V.
  • the first power supply voltage terminal VSS1 transitions from a low level to a high level, and the third power supply voltage terminal VSS2 is 0V.
  • the first transistor M8 is turned on, charging the first capacitor C2, and
  • the second transistor M9 is turned on.
  • the second transistor M9 continues to be turned on due to the voltage holding function of the first capacitor C2, so that the potential of the pull-up node PU is pulled down to 0V. , the discharge of the pull-up node PU is realized.
  • the pull-up node control circuit may further include a third transistor M10. For each frame, at the beginning of each line scan, the third transistor M10 is turned on, causing the first capacitor C2 to discharge, thereby not affecting the charging function of the normal pull-up node PU.
  • the first power supply voltage terminal VSS1 and the third power supply voltage terminal VSS2 are low power supply voltage terminals, and the second power supply voltage terminal VDD is a high power supply voltage terminal.
  • the pull-up node control circuit 16 realizes the complete release of the potential of the pull-up node PU in the shift register unit during the abnormal shutdown, thereby preventing the shift register unit from being damaged due to the abnormal shutdown. In turn, the quality of the product is ensured, thereby extending the service life of the TFT-LCD to which the shift register unit is applied.
  • sufficient discharge of the shift register unit is implemented by the pull-up node control circuit, so that the potential of the pull-up node in the shift register unit can be completely released, thereby avoiding The abnormal power on/off causes the shift register unit to not work properly. In turn, the quality of the product is ensured, thereby extending the service life of the TFT-LCD to which the shift register unit is applied.
  • FIG. 9 shows a schematic diagram of a gate driving device formed by cascading a plurality of shift register cells according to an embodiment of the present disclosure.
  • each shift register unit Ri (1 ⁇ except for the last shift register unit Rm)
  • the output terminal OUTPUT of i ⁇ m) is connected to the input terminal INPUT of the next shift register unit Ri+1 adjacent thereto.
  • a plurality of the above-described shift register units in FIG. 7 are connected in series. Except for the last shift register unit Rm, the output terminal OUTPUT of each of the shift register units Ri (1 ⁇ i ⁇ m) is connected to the input terminal INPUT of the next shift register unit Ri+1 adjacent thereto.
  • the output terminal OUTPUT of each of the shift register units Ri (1 ⁇ i ⁇ m) and the reset signal terminal of the previous shift register unit Ri-1 adjacent thereto RESET is connected.
  • the input terminal INPUT of the first shift register unit R1 inputs a frame start signal STV.
  • clock signals input from clock signal terminals of adjacent two-stage shift register units are opposite.
  • the first shift register unit R1 inputs the clock signal CLK
  • the second shift register unit R2 inputs the clock signal CLKB, wherein the CLK signal and the CLKB signal are inverted from each other.
  • the arrangement and connection of the shift register unit in the above-described gate driving device are not limited to the above.
  • it can be set for each of the six shift register units.
  • a set of clock signals CLK1 to CLK6 are required. That is, every six shift register units are a group, the clock signal end of the first shift register unit inputs the first clock signal CLK1, the clock signal end of the second shift register unit inputs the clock signal CLK2, and the third shift register The clock signal terminal of the unit inputs the clock signal CLK3, and so on, and so on.
  • the output signal of the fourth shift register unit serves as a reset signal of the first shift register unit, the output signal of the fifth shift register unit as a reset signal of the second shift register unit, and the like, and so on.
  • each shift register unit in the scanning of the gate driving apparatus is similar to the working process described with reference to FIGS. 7 and 8, and details are not described herein again.
  • the gate driving device may employ GOA technology as a gate driving circuit of a display device to provide a progressive scanning function to transmit a scanning signal to a display area.
  • the gate driving device can avoid shift registration due to abnormal shutdown The unit does not work properly, thereby ensuring the quality of the product, thereby extending the life of the TFT-LCD to which the shift register unit is applied.
  • the present disclosure also provides a display device including the above-described gate driving device.
  • the display device here can be: electronic paper, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator and the like with any display product or component.
  • the display device can prevent the shift register unit from malfunctioning due to the abnormal switching machine, thereby ensuring the quality of the product, thereby prolonging the service life of the TFT-LCD.

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Abstract

一种移位寄存器单元（100）及其驱动方法、栅极驱动装置和显示装置。该移位寄存器单元（100）包含：输入电路（11），其第一端接收该移位寄存器单元（100）的输入信号（INPUT），第二端与上拉节点（PU）连接，并且输入电路（11）被配置为将输入信号（INPUT）输出至上拉节点（PU）；输出电路（12），其第一端与时钟信号端（CLK）连接，第二端与上拉节点（PU）连接，第三端与该移位寄存器单元（100）的输出端（OUTPUT）连接，并且输出电路（12）被配置为在上拉节点（PU）的控制下将时钟信号端（CLK）的信号输出至输出端（OUTPUT）；上拉节点控制电路（16），其第一端与第一电源电压端（VSS1）连接，第二端与第三电源电压端（VSS2）连接，第三端与上拉节点（PU）连接，其被配置为：在第一电源电压端（VSS1）的控制下，通过第三电源电压端（VSS2）对上拉节点（PU）进行放电。

Description

移位寄存器单元及其驱动方法、栅极驱动装置和显示装置
本申请要求2017年01月04日提交的申请号为201710004514.8且发明名称为“移位寄存器单元及其驱动方法、栅极驱动装置和显示装置”的中国优先申请的优先权，通过引用将其全部内容并入于此。
技术领域
本公开涉及一种移位寄存器单元及其驱动方法、栅极驱动装置和显示装置。
背景技术
薄膜晶体管液晶显示器(TFT-LCD)广泛应用于生产生活的各个领域，其采用M*N点排列的逐行扫描矩阵显示。在进行显示时，TFT-LCD通过驱动电路来驱动显示面板中的各个像素进行显示。TFT-LCD的驱动电路主要包含栅极驱动电路和数据驱动电路。其中，数据驱动电路用于依据时钟信号定时将输入的数据顺序锁存并将锁存的数据输入到显示面板的数据线。栅极驱动电路通常用移位寄存器单元来实现，所述移位寄存器单元将时钟信号转换成开启/断开电压，分别输出到显示面板的各条栅线上。显示面板上的一条栅线通常与一个移位寄存器单元(即移位寄存器单元的一级)对接。通过使得各个移位寄存器单元依序轮流输出开启电压，实现对显示面板中像素的逐行扫描。
另一方面，随着平板显示的发展，高分辨率、窄边框成为发展的趋势。针对这一趋势，出现了阵列基板栅极驱动(Gate Driver on Array，GOA)技术。GOA技术直接将TFT-LCD的栅极驱动电路集成制作在阵列基板上，由此来代替在面板外沿粘接的、由硅芯片制作的驱动芯片。由于该技术可以将驱动电路直接做在阵列基板上，面板周围无需再粘接IC和布线，减少了面板的制作程序，降低了产品成本，同时提高了TFT-LCD面板的集成度，使面板实现窄边框和高分辨率。
目前，随着终端客户对美观的高要求、产品的市场价格的不断走低，且对TFT-LCD面板画面高品质的需求越来越高，各个TFT-LCD面板正在逐渐使用GOA技术取代传统的COG/COF技术，一方面是降低生产成本，另一方 面使得产品更加美观。
发明内容
本公开提供了一种移位寄存器单元及其驱动方法、栅极驱动装置和显示装置。通过上拉节点控制电路实现了对移位寄存器单元的充分放电，使得移位寄存器单元内上拉节点的电位能完全被释放，避免由于异常关机导致移位寄存器单元不能正常工作，进而保证产品的品质，延长应用该移位寄存器单元的TFT-LCD的使用寿命。
根据本公开的一方面，公开了一种移位寄存器单元，包括：输入电路，其第一端接收该移位寄存器单元的输入信号，第二端与上拉节点连接，并且所述输入电路被配置为将所述输入信号输出至所述上拉节点；输出电路，其第一端与时钟信号端连接，第二端与上拉节点连接，第三端与该移位寄存器单元的输出端连接，并且所述输出电路被配置为在所述上拉节点的控制下将所述时钟信号端的信号输出至所述输出端；上拉节点控制电路，其第一端与第一电源电压端连接，第二端与第三电源电压端连接，第三端与上拉节点连接，其被配置为：在所述第一电源电压端的控制下，通过所述第三电源电压端对所述上拉节点进行放电。
在一个实施例中，在所述第一电源电压端从第一电平跳变至第二电平时，所述上拉节点控制电路在所述第二电平的控制下，通过所述第三电源电压端对所述上拉节点进行放电；在所述第一电源电压端再从第二电平跳变零电压时，所述上拉节点控制电路继续通过第三电源电压端对所述上拉节点放电，直至所述上拉节点处于零电压。
在一个实施例中，所述上拉节点控制电路包括：第一晶体管，其栅极和第一极与第一电源电压端连接；第一电容，其第一端与第一晶体管的第二极连接，第二端与第三电源电压端连接；以及第二晶体管，其栅极与第一电容的第一端连接，第一极与上拉节点连接，第二极与第三电源电压端连接。
在一个实施例中，第一电源电压端的第一电平为低电平，第一电源电压端的第二电平为高电平，在所述第一电源电压端处于第一电平时第三电源电压端也处于第一电平，在所述第一电源电压端处于第二电平时所述第三电源电压端仍处于第一电平或处于零电压。
根据本公开的又一方面，公开了一种移位寄存器单元的驱动方法，该移 位寄存器单元包含输入电路、输出电路和上拉节点控制电路，该方法包含：在所述第一电源电压端从第一电平跳变至第二电平时，所述上拉节点控制电路在所述第二电平的控制下，通过所述第三电源电压端对所述上拉节点进行放电。
在一个实施例中，所述方法还包含：在所述第一电源电压端再从第二电平跳变至零电压时，所述上拉节点控制电路继续通过第三电源电压端对所述上拉节点放电，直至所述上拉节点处于零电压。
在一个实施例中，在所述第一电源电压端从第一电平跳变至第二电平之前还包括：第一操作阶段，接收所述移位寄存器单元的输入信号并将所述输入信号输出至所述上拉节点，所述输出电路在所述上拉节点的控制下将所述时钟信号端的信号输出至所述输出端；第二操作阶段，所述输出电路保持所述上拉节点的电平并继续将所述时钟信号端的信号输出至所述输出端。
根据本公开的再一方面，公开了一种栅极驱动装置，包括多个串联的移位寄存器单元，每个所述移位寄存器单元是上述移位寄存器单元，其中除最后一个移位寄存器单元外，其余每个移位寄存器单元的输出端均和与其相邻的下一个移位寄存器单元的输入端相连；所述第一个移位寄存器单元的输入端输入帧起始信号。
根据本公开的另一方面，公开了一种包含上述栅极驱动装置的显示装置。
附图说明
通过结合附图对本发明的优选实施例进行详细描述，本发明的上述和其他目的、特性和优点将会变得更加清楚，其中相同的标号指定相同结构的单元，并且在其中：
图1示出了一种移位寄存器单元的电路图；
图2示出了图1的移位寄存器单元的操作时序图；
图3示出了根据本公开实施例的移位寄存器单元的框图；
图4示出了根据本发明实施例的移位寄存器单元的示意性电路图；
图5示出了根据本发明实施例的移位寄存器单元的操作方法；
图6示出了根据本公开另一实施例的移位寄存器单元的框图；
图7示出了根据本公开另一实施例的移位寄存器单元的一种示例电路结构图；
图8示出了图7中的移位寄存器单元的示例电路的操作时序图；
图9示出了由根据本公开实施例的多个移位寄存器单元级联形成的栅极驱动装置的示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本实施例中，每个晶体管的漏极和源极的连接方式可以互换，因此，本公开实施例中各晶体管的漏极、源极实际是没有区别的。这里，为了描述方便，将晶体管的漏极和源极之一称作晶体管的第一极，而将另一个称作晶体管的第二极。
图1示出了一种移位寄存器单元的电路图，图2示出了图1的移位寄存器单元的操作时序图。
在图1中，时钟信号端CLK输入的时钟信号的占空比为50％，第一电源电压端VSS1是低电源电压端，第二电源电压端VDD是高电源电压端，并为该移位寄存器单元输入降噪信号。
下面，参考图1和图2描述如图1所示的移位寄存器单元的操作。
在第一阶段1，该移位寄存器单元的输入端INPUT的输入信号处于低电平，输入晶体管M1截止，虽然时钟信号端CLK处的时钟信号处于高电平，但是由于上拉节点PU处的上拉信号处于低电平，输出晶体管M2截止，输出端OUTPUT输出低电平。
在第二阶段2，该移位寄存器单元的输入端INPUT的输入信号处于高电平，时钟信号端CLK处的时钟信号处于低电平，此时输入晶体管M1导通，将输入端INPUT的高电平传递到上拉节点PU，此时上拉节点PU升到高电平，使得输出晶体管M2导通，由于时钟信号端CLK的时钟信号处于低电平，输出端OUTPUT仍输出低电平。
在第三阶段3，该移位寄存器单元的输入端INPUT的输入信号处于低电平，时钟信号端CLK处的时钟信号处于高电平，此时输入晶体管M1截止， 上拉节点PU的电位由于第二电容C1的存在会持续保持在高电平，从而继续使得输出晶体管M2导通，由于时钟信号端CLK的时钟信号处于高电平，输出端OUTPUT输出高电平，进一步由于第二电容C1的自举作用，此时上拉节点PU的电位继续升高。同时，由于上拉节点PU的电位处于高电平，晶体管M7导通，使得下拉节点PD被下拉至第一电源电压端VSS1的低电平。
若此时异常关机，如图2中的第四阶段4所示，第一电源电压端VSS1的信号被拉高至高电平并且第二电源电压端VDD同时保持为高电平，然后第一电源电压端VSS1、第二电源电压端VDD的信号同时迅速地降至低电平。
应了解，所述第一电源电压端VSS1的电压拉高是为了解决关机时残影的问题而专门设计的，在正常操作情况下，在关机时将所述第一电源电压端VSS1的电压拉高至能够实现各条栅线同时输出高电平，从而使得各像素放电以消除残影。然而，由于异常关机，所述第一电源电压端VSS1的电压拉高也导致下拉节点PD的电位无法被拉高至高电平，使得晶体管M5无法导通，进而使得上拉节点PU的电位无法释放。长时间、多次的异常关机，会导致上述移位寄存器单元(即，GOA电路)的相关TFT特性发生变化，从而会使得移位寄存器单元输出异常。
为了解决上述问题，本公开提供了一种移位寄存器单元，其通过上拉节点控制电路实现对移位寄存器单元的充分放电，使得移位寄存器单元内上拉节点的电位能完全被释放，避免由于异常关机导致移位寄存器单元不能正常工作，进而保证产品的品质，延长应用该移位寄存器单元的TFT-LCD的使用寿命。
具体地，根据本发明实施例，增加了第三电源电压端VSS2，并且在关机时第三电源电压端VSS2不会像第一电源电压端VSS1那样从低电平跳变至高电平，而是变为0V。
根据本发明实施例，在关机时，上拉节点控制电路16在第一电源电压端VSS1和第二电源电压端VSS2的控制下，将上拉节点PU下拉到第二电源电压端VSS2的0V，从而实现对上拉节点PU的可靠放电。
图3示出了根据本公开实施例的移位寄存器单元的框图。如图3所示，在一个实施例中，该移位寄存器单元100包含输入电路11、输出电路12和上拉节点控制电路16。
所述输入电路11的第一端接收该移位寄存器单元的输入信号INPUT，第 二端与上拉节点PU连接，并且所述输入电路11被配置为将所述输入信号INPUT输出至所述上拉节点PU。
所述输出电路12的第一端与时钟信号端CLK连接，第二端与上拉节点PU连接，第三端与该移位寄存器单元的输出端OUTPUT连接，并且所述输出电路12被配置为在所述上拉节点PU的控制下将所述时钟信号端CLK的信号输出至所述输出端OUTPUT。
所述上拉节点控制电路16的第一端与第一电源电压端VSS1连接，第二端与第三电源电压端VSS2连接，第三端与上拉节点PU连接，并且所述上拉节点控制电路16被配置为：在所述第一电源电压端VSS1的控制下，通过所述第三电源电压端VSS2对所述上拉节点PU进行放电。
根据本发明实施例，在所述第一电源电压端从第一电平跳变至第二电平时，所述上拉节点控制电路在所述第二电平的控制下，通过所述第三电源电压端对所述上拉节点进行放电。
更进一步，根据本发明实施例，在所述第一电源电压端再从第二电平跳变零电压时，所述上拉节点控制电路继续通过第三电源电压端对所述上拉节点放电，直至所述上拉节点处于零电压。
可选地，该上拉节点控制电路还包括第四端，该第四端与该移位寄存器单元的输入端INPUT连接，并且该上拉节点控制电路16还被配置为在所述输入端的输入信号处于有效电平时，保证上拉节点PU不被错误地下拉。
图4示出了根据本公开实施例的移位寄存器单元的一种示意性电路图。
如图4所示，在一个实施例中，例如，输入电路11包括输入晶体管M1。输入晶体管M1的栅极和第一极与输入端INPUT连接，第二极与上拉节点PU连接。在输入端INPUT的输入信号处于高电平时，输入晶体管M1导通，将输入端INPUT的输入信号传递到上拉节点PU。
在一个实施例中，例如，输出电路12包括输出晶体管M2和第二电容C1。输出晶体管M2的栅极与上拉节点PU连接，第一极与时钟信号端CLK连接，第二极与输出端OUTPUT连接。第二电容C1的第一端与上拉节点PU连接，第二端与输出端OUTPUT连接。在上拉节点PU处的上拉信号处于高电平时，输出晶体管M2导通，将时钟信号端CLK的时钟信号输出到输出端OUTPUT。
在一个实施例中，例如，上拉节点控制电路16包括第一晶体管M8、第 一电容C2和第二晶体管M9。第一晶体管M8的栅极和第一极与第一电源电压端VSS1连接，第二极与第一电容C2的第一端连接。第一电容C2的第二端与第三电源电压端VSS2连接。第二晶体管M9的栅极与第一电容C2的第一端连接，第一极与上拉节点PU连接，第二极与第三电源电压端VSS2连接。
在一个实施例中，上拉节点控制电路16还包括第三晶体管M10，其栅极与该移位寄存器单元的输入端INPUT连接，第一极与第一电容C2的第一端连接，第二极与第一电源电压端VSS1连接，从而在所述输入端INPUT的输入信号的控制下，通过所述第一电源电压端VSS1对所述第二晶体管M9的栅极进行放电。
图5示出了根据本发明实施例的移位寄存器单元的驱动方法。根据本发明实施例的移位寄存器单元的驱动方法适用于显示装置关机时的操作。
在步骤501，接收到关机信号。
在步骤502，第一电源电压端从第一电平跳变至第二电平，所述上拉节点控制电路在所述第二电平的控制下，通过所述第三电源电压端对所述上拉节点进行放电。
可选地，在步骤503，在所述第一电源电压端再从第二电平跳变至零电压时，所述上拉节点控制电路继续通过第三电源电压端对所述上拉节点放电，直至所述上拉节点处于零电压。
图6示出了根据本公开实施例的移位寄存器单元的另一示意性框图。如图6所示，在一个实施例中，该移位寄存器单元100包含输入电路11、输出电路12、下拉电路14、下拉控制电路15和上拉节点控制电路16。
输入电路11的第一端与该移位寄存器单元的输入端INPUT连接用于从该输入端INPUT接收输入信号，第二端与上拉节点PU连接。该输入电路11被配置为在输入端INPUT的输入信号处于有效输入电平时，将所接收的输入信号传递到上拉节点PU。
输出电路12的第一端与时钟信号端CLK连接，第二端与上拉节点PU连接，第三端与该移位寄存器单元的输出端OUTPUT连接。该输出电路12被配置来在上拉节点PU处的上拉信号处于有效上拉电平时将时钟信号端CLK的时钟信号输出到输出端OUTPUT。
下拉控制电路15的第一端与第二电源电压端VDD连接，第二端与下拉节点PD连接，第三端与第一电源电压端VSS1连接，第四端与上拉节点PU 连接。该下拉控制电路15被配置为根据上拉节点PU处的电平控制下拉节点PD处的电平，从而控制下拉电路14是否进行操作。例如，下拉控制电路15在第一电源电压端和第二电源电压端的电平相反时，使得所述下拉节点的电平与所述上拉节点的电平相反，具体地在上拉节点PU处的上拉信号处于有效上拉电平时，在下拉节点PD处产生处于非有效下拉电平的下拉信号，而在上拉节点PU处的上拉信号处于非有效上拉电平时，在下拉节点PD处产生处于有效下拉电平的下拉信号。
下拉电路14的第一端与下拉节点PD连接，第二端与上拉节点PU连接，第三端与第一电源电压端VSS1连接。该下拉电路14被配置来在所述下拉节点PD的控制下，通过所述第一电源电压端对所述上拉节点进行下拉，例如，在下拉节点PD处的下拉信号处于有效下拉电平时将所述上拉节点PU处的电平下拉至所述第一电源电压端VSS1的电源电压。
上拉节点控制电路16的第一端与第一电源电压端VSS1连接，第二端与第三电源电压端VSS2连接，第三端与上拉节点PU连接。该上拉节点控制电路16被配置为在所述第一电源电压端VSS1的控制下，通过所述第三电源电压端VSS2对所述上拉节点进行放电。例如，在所述第一电源电压端VSS1从第一电平跳变至第二电平时，所述上拉节点控制电路16在所述第二电平的控制下，通过所述第三电源电压端VSS2对所述上拉节点进行放电。在一个实施例中，在异常关机的情况下，该上拉节点控制电路16被配置为在第一电源电压端VSS1突然跳变至高电平时，对上拉节点PU放电。在另一实施例中，在所述第一电源电压端再从第二电平跳变零电压时，所述上拉节点控制电路继续通过第三电源电压端对所述上拉节点放电，直至所述上拉节点处于零电压。
可选地，在另一实施例中，如图6所示，该移位寄存器单元100的上拉节点控制电路16进一步包含第四端，该第四端与该移位寄存器单元的输入端INPUT连接。该上拉节点控制电路16被配置为根据第一电源电压端VSS1、第三电源电压端VSS2和输入端INPUT控制上拉节点PU处的电平。该上拉节点控制电路16被配置为在所述第一电源电压端VSS1的控制下，通过所述第三电源电压端VSS2对所述上拉节点进行放电。该上拉节点控制电路16还被配置为在所述输入端的输入信号的控制下，保证在输入端INPUT处于有效电平时，上拉节点PU不被错误地下拉。
在该实施例中，第一电源电压端VSS1和第三电源电压端VSS2是低电源电压端，第二电源电压端VDD是高电源电压端。
可选地，在另一实施例中，该移位寄存器单元100还包含复位电路13。
复位电路13的第一端与复位信号端RESET连接，第二端与上拉节点PU连接，第三端与第一电源电压端VSS1连接，第四端与该移位寄存器单元的输出端OUTPUT连接。该复位电路13被配置来在复位信号端RESET的复位信号处于有效控制电平时将上拉节点PU处的上拉信号复位至第一电源电压端VSS1的电源电压以及将输出端OUTPUT的输出信号复位至第一电源电压端VSS1的电源电压。
本公开还提供了一种上述移位寄存器单元的驱动方法。下面结合图6-图8对该方法进行说明。在一个实施例中，例如，如图6所示，该移位寄存器单元100包含输入电路11、输出电路12、下拉电路14、下拉控制电路15和上拉节点控制电路16。该方法包含：
由输入电路11将所接收的输入信号传递到上拉节点PU。
由输出电路12将时钟信号端CLK的时钟信号输出到该移位寄存器单元的输出端OUTPUT。
接收关机信号，并且第一电源电压端VSS1从低电平跳变至高电平。由上拉节点控制电路16在第一电源电压端VSS1从低电平跳变至高电平时，对上拉节点PU放电。
第一电源电压端VSS1从高电平跳变至零电压。由上拉节点控制电路16在第一电源电压端VSS1从高电平跳变至零电压时，继续对上拉节点PU放电，直至上拉节点PU达到零电压。
在一个实施例中，例如，如图6所示，该移位寄存器单元100还包含复位电路13，该移位寄存器单元的驱动方法还包含由复位电路13将上拉节点PU处的上拉信号复位至第一电源电压端VSS1的电源电压以及将该移位寄存器单元的输出端OUTPUT的输出信号复位至第一电源电压端VSS1的电源电压。
图7示出了根据本公开实施例的移位寄存器单元的一种示例电路结构图。下面以图7中的晶体管均为N型晶体管为例进行说明。如本领域技术人员所熟知的，N型晶体管在栅极输入高电平时导通。
如图7所示，在一个实施例中，例如，输入电路11包括输入晶体管M1。 输入晶体管M1的栅极和第一极与输入端INPUT连接，第二极与上拉节点PU连接。在输入端INPUT的输入信号处于高电平时，输入晶体管M1导通，将输入端INPUT的输入信号传递到上拉节点PU。
在一个实施例中，例如，输出电路12包括输出晶体管M2和第二电容C1。输出晶体管M2的栅极与上拉节点PU连接，第一极与时钟信号端CLK连接，第二极与输出端OUTPUT连接。第二电容C1的第一端与上拉节点PU连接，第二端与输出端OUTPUT连接。在上拉节点PU处的上拉信号处于高电平时，输出晶体管M2导通，将时钟信号端CLK的时钟信号输出到输出端OUTPUT。
在一个实施例中，例如，下拉控制电路15包括第一下拉控制晶体管M6和第二下拉控制晶体管M7。第一下拉控制晶体管M6的栅极和第一极与第二电源电压端VDD连接，第二极与下拉节点PD连接。第二下拉控制晶体管M7的栅极与上拉节点PU连接，第一极与下拉节点PD连接，第二极与第一电源电压端VSS1连接。例如，在上拉节点PU处的上拉信号处于低电平时，第二电源电压端VDD输出的高电平信号使得第一下拉控制晶体管M6导通，在下拉节点PD处产生处于高电平的下拉信号，使得下拉晶体管M5导通；而在上拉节点PU处的上拉信号PU处于高电平时，第二下拉控制晶体管M7导通，通过合理选择第一下拉控制晶体管M6和第二下拉控制晶体管M7的沟道参数(例如沟道宽长比)，从而在下拉节点PD处产生处于低电平的下拉信号，使得下拉晶体管M5不导通。
在一个实施例中，例如，下拉电路14包括下拉晶体管M5。下拉晶体管M5的栅极与下拉节点PD连接，第一极与上拉节点PU连接，第二极与第一电源电压端VSS1连接。在下拉节点PD处的下拉信号处于高电平时，下拉晶体管M5导通，将所述上拉节点PU处的上拉信号下拉至所述第一电源电压端VSS1的电源电压。
在一个实施例中，例如，上拉节点控制电路16包括第一晶体管M8、第一电容C2和第二晶体管M9。第一晶体管M8的栅极和第一极与第一电源电压端VSS1连接，第二极与第一电容C2的第一端连接。第一电容C2的第二端与第三电源电压端VSS2连接。第二晶体管M9的栅极与第一电容C2的第一端连接，第一极与上拉节点PU连接，第二极与第三电源电压端VSS2连接。
可选地，在一个实施例中，例如，上拉节点控制电路16还包括第三晶体 管M10，其栅极与该移位寄存器单元的输入端INPUT连接，第一极与第一电容C2的第一端连接，第二极与第一电源电压端VSS1连接。
可选地，在另一实施例中，该移位寄存器单元100还包含复位电路13。例如，复位电路13包括节点复位晶体管M3和输出复位晶体管M4。节点复位晶体管M3的栅极与复位信号端RESET连接，第一极与上拉节点PU连接，第二极与第一电源电压端VSS1连接。输出复位晶体管M4的栅极与所述复位信号端RESET连接，第一极与所述输出端OUTPUT连接，第二极与所述第一电源电压端VSS1连接。在复位信号端RESET处的复位信号处于高电平时，节点复位晶体管M3导通，将上拉节点PU处的上拉信号复位至第一电源电压端VSS1的电源电压，并且输出复位晶体管M4导通，将输出端OUTPUT的输出信号复位至第一电源电压端VSS1的电源电压。
在该实施例中，第一电源电压端VSS1和第三电源电压端VSS2是低电源电压端，第二电源电压端VDD是高电源电压端。
在本公开实施例的移位寄存器单元中，通过上拉节点控制电路16实现对异常关机时移位寄存器单元内上拉节点PU的电位的完全释放，避免由于异常关机使得移位寄存器单元损伤，进而保证产品的品质，从而可以延长应用该移位寄存器单元的TFT-LCD的使用寿命。
图8示出了图7中的移位寄存器单元的示例电路的操作时序图。下面结合图7和图8对图7中的移位寄存器单元的驱动方法进行说明。
在第一阶段1(初始阶段)，输入端INPUT的输入信号处于低电平。输入晶体管M1截止，虽然时钟信号端CLK处的时钟信号处于高电平，但是由于上拉节点PU处的上拉信号处于低电平，输出晶体管M2截止，输出端OUTPUT输出低电平。
在第二阶段2(输入阶段)，输入端INPUT的输入信号处于高电平，时钟信号端CLK处的时钟信号处于低电平。输入晶体管M1导通，将输入端INPUT的高电平传递到上拉节点PU，此时上拉节点PU处于第一高电压，使得输出晶体管M2导通，由于时钟信号端CLK的时钟信号处于低电平，输出端OUTPUT输出低电平。并且，由于上拉节点PU处于第一高电压，使得第二下拉控制晶体管M7导通，从而在下拉节点PD处产生处于低电平的下拉信号。
在第三阶段3(输出阶段)，输入端INPUT的输入信号处于低电平，输入晶体管M1截止。由于第二电容C1的电压保持作用，上拉节点PU继续使得 输出晶体管M2导通，并且由于时钟信号端CLK的时钟信号处于高电平，输出端OUTPUT输出高电平，进而由于第二电容C1的电压耦合作用，此时上拉节点PU被从第一高电压抬升到第二高电压。此外，在该阶段中，由于上拉节点PU处于高电平，第二下拉控制晶体管M7保持导通，下拉节点PD仍处于低电平。
若在上述第三阶段3(输出阶段)出现异常关机，如前所述，第一电源电压端VSS1的信号同时被拉高至高电平并且第二电源电压端VDD同时保持为高电平，然后第一电源电压端VSS1、第二电源电压端VDD的信号迅速地同时降至低电平(参见图8第四阶段4所示的VSS1和VDD)。
在本公开实施例中引入了第三电源电压端VSS2，该第三电源电压端VSS2的信号基本与第一电源电压端VSS1的信号一致，但在关机时不会被拉高至上述高电平(该部分PCBA可实现)，而是被拉至0V。
下面将参照图7的电路图以及图8的第四阶段4具体描述在异常关机情况下根据本发明实施例的上拉节点控制电路16的操作。
在该第四阶段4，第一电源电压端VSS1从低电平跳变至高电平，第三电源电压端VSS2为0V，此时第一晶体管M8导通，给第一电容C2充电，并使得第二晶体管M9导通。接下来，当第一电源电压端VSS1的电压信号降低至0V后，由于第一电容C2的电压保持功能，使得第二晶体管M9继续导通，从而使得上拉节点PU的电位被拉低至0V，实现上拉节点PU的放电。
进一步地，上拉节点控制电路还可以包括第三晶体管M10。对于每一帧，在每一行扫描开始的时候，第三晶体管M10导通，使得第一电容C2放电，从而不影响正常的上拉节点PU的充电功能。
在该实施例中，第一电源电压端VSS1和第三电源电压端VSS2是低电源电压端，第二电源电压端VDD是高电源电压端。
在本公开实施例的移位寄存器单元中，通过上拉节点控制电路16实现对异常关机时移位寄存器单元内上拉节点PU的电位的完全释放，避免由于异常关机使得移位寄存器单元损伤，进而保证产品的品质，从而可以延长应用该移位寄存器单元的TFT-LCD的使用寿命。
在本公开实施例的移位寄存器单元及其驱动方法中，通过上拉节点控制电路实现对移位寄存器单元的充分放电，使得移位寄存器单元内上拉节点的电位能完全被释放，避免由于异常开关机导致移位寄存器单元不能正常工作， 进而保证产品的品质，从而可以延长应用该移位寄存器单元的TFT-LCD的使用寿命。
图9示出了由根据本公开实施例的多个移位寄存器单元级联形成的栅极驱动装置的示意图。
如图9所示，在该栅极驱装置中，多个图4中的上述移位寄存器单元串联连接，其中除最后一个移位寄存器单元Rm外，其余每个移位寄存器单元Ri(1≤i＜m)的输出端OUTPUT均和与其相邻的下一个移位寄存器单元Ri+1的输入端INPUT相连。或者，多个图7中的上述移位寄存器单元串联连接。其中除最后一个移位寄存器单元Rm外，其余每个移位寄存器单元Ri(1≤i＜m)的输出端OUTPUT均和与其相邻的下一个移位寄存器单元Ri+1的输入端INPUT相连；除第一个移位寄存器单元R1外，其余每个移位寄存器单元Ri(1＜i≤m)的输出端OUTPUT均和与其相邻的上一个移位寄存器单元Ri-1的复位信号端RESET相连。所述第一个移位寄存器单元R1的输入端INPUT输入帧起始信号STV。
如图6所示，在该栅极驱动装置中，相邻两级移位寄存器单元的时钟信号端输入的时钟信号相反。例如第一个移位寄存器单元R1输入时钟信号CLK，则第二个移位寄存器单元R2输入时钟信号CLKB，其中CLK信号和CLKB信号互为反相。
值得注意的是，上述栅极驱动装置中移位寄存器单元的布置和连接不限于上述方式。例如，可以每6个移位寄存器单元为一组进行设置。在这种情况下，需要一组时钟信号CLK1至CLK6。即，每6个移位寄存器单元为一组，第一移位寄存器单元的时钟信号端输入第一时钟信号CLK1，第二移位寄存器单元的时钟信号端输入时钟信号CLK2，第三移位寄存器单元的时钟信号端输入时钟信号CLK3，等等，依此类推。第四移位寄存器单元的输出信号作为第一移位寄存器单元的复位信号，第五移位寄存器单元的输出信号作为第二移位寄存器单元的复位信号，等等，依此类推。
根据本公开实施例的栅极驱动装置在扫描时各移位寄存器单元的具体工作过程与参照图7和图8描述的工作过程相似，在此不再赘述。
根据本公开实施例的栅极驱动装置可以采用GOA技术，用作显示装置的栅极驱动电路，以提供逐行扫描功能，将扫描信号传送至显示区域。
根据本公开实施例的栅极驱动装置可以避免由于异常关机导致移位寄存 器单元不能正常工作，进而保证产品的品质，从而可以延长应用该移位寄存器单元的TFT-LCD的使用寿命。
本公开还提供了一种包含上述栅极驱动装置的显示装置。
这里的显示装置可以为：电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
根据本公开实施例的显示装置可以避免由于异常开关机导致移位寄存器单元不能正常工作，进而保证产品的品质，从而可以延长TFT-LCD的使用寿命。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种移位寄存器单元，包含：
    输入电路，其第一端接收该移位寄存器单元的输入信号，第二端与上拉节点连接，并且所述输入电路被配置为将所述输入信号输出至所述上拉节点；
    输出电路，其第一端与时钟信号端连接，第二端与上拉节点连接，第三端与该移位寄存器单元的输出端连接，并且所述输出电路被配置为在所述上拉节点的控制下将所述时钟信号端的信号输出至所述输出端；
    上拉节点控制电路，其第一端与第一电源电压端连接，第二端与第三电源电压端连接，第三端与上拉节点连接，其被配置为：在所述第一电源电压端的控制下，通过所述第三电源电压端对所述上拉节点进行放电。
  2. 根据权利要求1所述的移位寄存器单元，其中，在所述第一电源电压端从第一电平跳变至第二电平时，所述上拉节点控制电路在所述第二电平的控制下，通过所述第三电源电压端对所述上拉节点进行放电。
  3. 根据权利要求2所述的移位寄存器单元，其中，在所述第一电源电压端再从第二电平跳变零电压时，所述上拉节点控制电路继续通过第三电源电压端对所述上拉节点放电，直至所述上拉节点处于零电压。
  4. 根据权利要求3所述的移位寄存器单元，其中该上拉节点控制电路的第四端与该移位寄存器单元的输入端连接，并且该上拉节点控制电路16还被配置为在所述输入端的输入信号处于有效电平时，保证上拉节点PU不被下拉。
  5. 根据权利要求3所述的移位寄存器单元，其中，上拉节点控制电路包括：
    第一晶体管，其栅极和第一极与第一电源电压端连接；
    第一电容，其第一端与第一晶体管的第二极连接，第二端与第三电源电压端连接；以及
    第二晶体管，其栅极与第一电容的第一端连接，第一极与上拉节点连接，第二极与第三电源电压端连接。
  6. 根据权利要求4所述的移位寄存器单元，其中，上拉节点控制电路包括：
    第一晶体管，其栅极和第一极与第一电源电压端连接；
    第一电容，其第一端与第一晶体管的第二极连接，第二端与第三电源电压端连接；
    第二晶体管，其栅极与第一电容的第一端连接，第一极与上拉节点连接，第二极与第三电源电压端连接；以及
    第三晶体管，其栅极与该移位寄存器单元的输入端连接，第一极与第一电容的第一端连接，第二极与第一电源电压端连接。
  7. 根据权利要求1所述的移位寄存器单元，还包括：
    下拉电路，其第一端与下拉节点连接，第二端与上拉节点连接，第三端与第一电源电压端连接，并且被配置为在所述下拉节点的控制下，通过所述第一电源电压端对所述上拉节点进行下拉；
    下拉控制电路，其第一端与第二电源电压端连接，第二端与下拉节点连接，第三端与第一电源电压端连接，第四端与上拉节点连接，并且被配置为：在第一电源电压端和第二电源电压端的电平相反时，使得所述下拉节点的电平与所述上拉节点的电平相反。
  8. 根据权利要求1所述的移位寄存器单元，还包括：
    复位电路，其第一端与复位信号端连接，第二端与上拉节点连接，第三端与第一电源电压端连接，第四端与该移位寄存器单元的输出端连接，并且被配置为：在所述复位信号端的控制下，通过所述第一电源电压端对所述上拉节点和所述输出端进行下拉。
  9. 根据权利要求1所述的移位寄存器单元，其中，输入电路包括：
    输入晶体管，其栅极和第一极与该移位寄存器单元的输入端连接，第二极与上拉节点连接。
  10. 根据权利要求1所述的移位寄存器单元，其中，输出电路包括：
    输出晶体管，其栅极与上拉节点连接，第一极与时钟信号端连接，第二极与输出端连接；以及
    第二电容，其第一端与上拉节点连接，第二端与输出端连接。
  11. 根据权利要求7所述的移位寄存器单元，其中，所述下拉电路包括：
    下拉晶体管，其栅极与下拉节点连接，第一极与上拉节点连接，第二极与第一电源电压端连接。
  12. 根据权利要求7所述的移位寄存器单元，其中，所述下拉控制电路包括：
    第一下拉控制晶体管，其栅极和第一极与第二电源电压端连接，第二极与下拉节点连接；
    第二下拉控制晶体管，其栅极与上拉节点连接，第一极与下拉节点连接，第二极与第一电源电压端连接。
  13. 根据权利要求2或3所述的移位寄存器单元，其中，第一电源电压端的第一电平为低电平，第一电源电压端的第二电平为高电平，在所述第一电源电压端处于第一电平时第三电源电压端也处于第一电平，在所述第一电源电压端处于第二电平时所述第三电源电压端仍处于第一电平或处于零电压。
  14. 一种如权利要求1所述的移位寄存器单元的驱动方法，包含：
    在所述第一电源电压端从第一电平跳变至第二电平时，所述上拉节点控制电路在所述第二电平的控制下，通过所述第三电源电压端对所述上拉节点进行放电。
  15. 如权利要求14所述的移位寄存器单元的驱动方法，还包含：
    在所述第一电源电压端再从第二电平跳变至零电压时，所述上拉节点控制电路继续通过第三电源电压端对所述上拉节点放电，直至所述上拉节点处于零电压。
  16. 根据权利要求15所述的驱动方法，其中，上拉节点控制电路包括：
    第一晶体管，其栅极和第一极与第一电源电压端连接；
    第一电容，其第一端与第一晶体管的第二极连接，第二端与第三电源电压端连接；以及
    第二晶体管，其栅极与第一电容的第一端连接，第一极与上拉节点连接，第二极与第三电源电压端连接，
    其中，在所述第一电源电压端从第一电平跳变至第二电平时，所述第一晶体管导通对第一电容充电，并且使第二晶体管导通以通过第三电源电压端对所述上拉节点放电；以及
    在所述第一电源电压端再从第二电平跳变零电压时，所述第一电容使得第二晶体管保持导通并继续通过第三电源电压端对所述上拉节点放电。
  17. 根据权利要求14所述的驱动方法，在所述第一电源电压端从第一电平跳变至第二电平之前还包括：
    第一操作阶段，接收所述移位寄存器单元的输入信号并将所述输入信号 输出至所述上拉节点，所述输出电路在所述上拉节点的控制下将所述时钟信号端的信号输出至所述输出端；
    第二操作阶段，所述输出电路保持所述上拉节点的电平并继续将所述时钟信号端的信号输出至所述输出端。
  18. 根据权利要求14-17中任一项所述的驱动方法，其中，第一电源电压端的第一电平为低电平，第一电源电压端的第二电平为高电平，在所述第一电源电压端处于第一电平时第三电源电压端也处于第一电平，在所述第一电源电压端处于第二电平时所述第三电源电压端仍处于第一电平或处于零电压。
  19. 一种栅极驱动装置，包括多个串联的移位寄存器单元，每个所述移位寄存器单元是如权利要求1-13中任一项所述的移位寄存器单元，
    其中除最后一个移位寄存器单元外，其余每个移位寄存器单元的输出端均和与其相邻的下一个移位寄存器单元的输入端相连；
    所述第一个移位寄存器单元的输入端输入帧起始信号。
  20. 一种包含根据权利要求19所述的栅极驱动装置的显示装置。
PCT/CN2017/099388 2017-01-04 2017-08-29 移位寄存器单元及其驱动方法、栅极驱动装置和显示装置 Ceased WO2018126716A1 (zh)

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