WO2018126508A1 - Tft基板的制作方法 - Google Patents

Tft基板的制作方法 Download PDF

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Publication number
WO2018126508A1
WO2018126508A1 PCT/CN2017/073330 CN2017073330W WO2018126508A1 WO 2018126508 A1 WO2018126508 A1 WO 2018126508A1 CN 2017073330 W CN2017073330 W CN 2017073330W WO 2018126508 A1 WO2018126508 A1 WO 2018126508A1
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WIPO (PCT)
Prior art keywords
layer
photoresist
photoresist layer
fabricating
tft substrate
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French (fr)
Inventor
卢马才
姚江波
覃事建
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US15/513,562 priority Critical patent/US10090414B2/en
Publication of WO2018126508A1 publication Critical patent/WO2018126508A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a TFT substrate.
  • TFT Thin Film Transistor, thin film transistor
  • Mask mask
  • the (pixel) ITO (Indium Tin Oxide) layer was completed in a Mask, but encountered ITO stripping problems on the PR (resistance). Usually Pixel is deposited on the PR Longer stripping time after ITO, affecting the tact time, and PR stripping residue and flashing problems can seriously affect the process or product performance.
  • the current PR/PV low-cut method must be formed by PV layer etching, so that ITO and PV layers have large surface steps, which affect product characteristics.
  • the invention provides a method for fabricating a TFT substrate, comprising the following steps:
  • a second insulating layer on the substrate depositing a second insulating layer on the substrate, forming a photoresist layer on the second insulating layer, patterning the photoresist layer by using a third mask to form a first photoresist layer having a first thickness and having a second thickness a second photoresist layer, the second thickness is greater than the first thickness, the first photoresist layer and the second photoresist layer are spaced apart to form a spacer, and a drain via is formed on the second insulating layer of the spacer;
  • the step of forming a drain via on the second insulating layer of the spacer includes:
  • the step of removing the first photoresist layer comprises:
  • the first photoresist layer is detached by photoresist ashing.
  • the step of performing a texturing process on the second photoresist layer includes:
  • the second photoresist layer is subjected to a texturing process by dry etching.
  • the pile surface formed on the surface of the photoresist is a nano-pillar, and the height of the nano-column on the photoresist plane can be 10A to 10000A.
  • the distance between the nanocolumns can be 10A ⁇ 20000A.
  • the gas used for the photoresist is a single or mixed gas of Ar, O3, He, SF6, CF4, C4F8 gas, and the etching gas pressure may be 5 mT to 10000 mT.
  • the steps of sequentially depositing the first insulating layer, the active layer and the second metal layer on the substrate include:
  • the first insulating layer, the active layer, and the second metal layer are sequentially deposited on the substrate by chemical vapor deposition.
  • the pixel electrode layer is ITO.
  • the second mask is a halftone mask or a gray dimming cover.
  • the active layer is A-Si.
  • the present invention forms a TFT gate by using a first mask process by depositing a first metal layer on a substrate; and sequentially depositing a first insulating layer and an active layer on the substrate. And a second metal layer, wherein the second metal layer forms a source and a drain respectively at both ends of the active layer by using a second mask process; depositing a second insulating layer on the substrate, and forming light on the second insulating layer a resist layer, wherein the photoresist layer is patterned by using a third mask to form a first photoresist layer having a first thickness and a second photoresist layer having a second thickness, the second thickness being greater than the first thickness, the first light
  • the resist layer is spaced apart from the second photoresist layer to form a spacer, and a drain via is formed on the second insulating layer of the spacer; the first photoresist layer is removed, and the second photoresist layer is subjected to a texturing
  • the solution only needs to fabricate the TFT substrate through three masks, and deposits the pixel electrode layer after the photoresist is cured, which can effectively strip the photoresist layer, and the pixel electrode and the second insulating layer have no obvious steps, thereby improving the process efficiency and reducing the efficiency. Process difficulty.
  • FIG. 1 is a schematic flow chart of a preferred embodiment of a method of fabricating a TFT substrate of the present invention.
  • FIG. 2 is a schematic view of a first photomask process in a preferred embodiment of the present invention.
  • FIG. 4 is a schematic view of a third reticle process in a preferred embodiment of the present invention.
  • FIG. 1 is a schematic flow chart of a method for fabricating a TFT substrate according to the present invention.
  • the manufacturing method of the TFT substrate includes the following processes:
  • the first photoresist layer is removed, and the second photoresist layer is subjected to a texturing process to form a suede surface on the surface of the second photoresist layer.
  • FIG. 2 is a schematic diagram of a first photomask process according to a preferred embodiment of the present invention. Step S101 of the present invention will be understood from the top to the bottom in conjunction with FIG.
  • step S101 first in CVD (Chemical Vapor) Deposition, chemical vapor deposition) method forms a first metal layer 10 on the substrate 1000, and the metal layer 10 may be made of chromium (Cr), chromium alloy material or molybdenum crucible (Mo Ta) alloy, aluminum (Al) and aluminum alloy materials. Then, a photoresist 11 having a uniform thickness is applied onto the first metal layer 10, and the applied photoresist 11 is exposed and developed by the first mask, and then etched to form the TFT gate 101.
  • the first mask can be a normal mask.
  • FIG. 3 is a schematic diagram of a second photomask process according to a preferred embodiment of the present invention. Step S102 of the present invention will be understood from the top to the bottom in conjunction with FIG.
  • step S102 first, the first insulating layer 20, the active layer 30, and the second metal layer 40 are sequentially deposited on the portion where the TFT gate 101 and the substrate 1000 are not covered by the TFT gate 101, and then in the second metal layer 40. Coating the photoresist 41, exposing and developing the coated photoresist 41 through the second mask, and then etching to form an active layer 30 opposite to the TFT gate 101 after the patterning process, and making the second
  • the metal layer 40 is formed with a source 401 and a drain 402 which are spaced apart from each other at both ends of the patterned active layer 30.
  • the second mask can be a halftone mask or a gray dimmer.
  • the first insulating layer 20 may be a one-layer structure or a two-layer structure.
  • the first layer structure may be SiO, SiNx or AIO.
  • the second layer structure can generally be made of SiNx.
  • the active layer 30 is opposed to the TFT gate 101, which may be made of a semiconductor material such as A-Si.
  • the second metal layer 40 can be made of aluminum alloy, metal aluminum or metal chromium.
  • the source 401 is for connecting the data signal lines, and the drain 402 is for connecting the pixel electrodes.
  • FIG. 4 is a schematic diagram of a third photomask process according to a preferred embodiment of the present invention. Step S103 of the present invention will be understood from the top to the bottom in conjunction with FIG.
  • step S103 first, the source 401, the drain 402, the portion of the active layer 30 not covered by the source 40 and the drain 402, and the first insulating layer 20 are not covered by the active layer 30 by the CVD method.
  • the portion is formed with a second insulating layer (ie, a passivation layer) 50, which may be made of SiNx, SiO, or the like.
  • a photoresist layer 60 having a uniform thickness is applied on the second insulating layer 50.
  • the photoresist layer 60 is exposed and developed through a third mask to form a first photoresist layer 601 having a first thickness and a second photoresist layer 602 having a second thickness, the second thickness being greater than the first thickness.
  • the first photoresist layer 601 is spaced apart from the second photoresist layer 602 to form a spacer A for defining a portion to be punctured in the second insulating layer 50.
  • the second insulating layer portion under the spacer A is then removed by dry etching, thereby forming a drain via B in the second insulating layer 50 to be exposed for the corresponding drain surface.
  • the exposed drain surface is less than or equal to 1/2 of the upper surface of the source, and the specific implementation time is set to 1/3.
  • the third mask can be a halftone mask or a gray dimmer.
  • the second photoresist layer 602 is subjected to a texturing process, and the second photoresist layer 602 is atomized by etching or other means to form a textured surface on the surface of the photoresist.
  • the suede surface can be a convex nano-column, and the nano-pillar can have a height of 10A ⁇ 10000A on the photoresist plane.
  • the distance between the nanocolumns can be 10A ⁇ 20000A.
  • the gas used for photoresisting can be a single or mixed gas of Ar, O3, He, SF6, CF4, C4F8 gas, and the etching pressure can be 5mT ⁇ 10000mT.
  • step S105 after the photoresist layer 602 is subjected to the texturing process, the pixel electrode ITO or other conductive material is deposited on the entire surface, thereby exposing the textured surface of the cured photoresist layer 602.
  • a pixel electrode layer 70 is formed on the surface of the second insulating layer 50 and the exposed surface of the drain electrode 402. Then, the second photoresist 602 and the pixel electrode ITO or other conductive material covered on the second photoresist layer 602 are removed by photoresist stripping.
  • the pixel electrode ITO or other conductive material will not completely cover the suede of the second photoresist layer 602, so when the photoresist is peeled off, the stripping liquid is easily exposed to the exposed photoresist.
  • the surface contact causes the photoresist layer 60 and the second insulating layer 50 to be efficiently peeled off.
  • the pixel electrode ITO is annealed to form a pixel electrode 70 on the exposed surface of the second insulating layer 50 and the exposed surface of the drain 402.
  • the pixel electrode 70 is connected to the drain electrode 402 through the drain via B.
  • a first metal layer is deposited on the substrate, and a TFT gate is formed by a first mask process; a first insulating layer, an active layer, and a second metal layer are sequentially deposited on the substrate.
  • a second photomask process is used to form a second metal layer respectively forming a source and a drain at opposite ends of the active layer; a second insulating layer is deposited on the substrate, and a photoresist layer is formed on the second insulating layer, The three masks are patterned on the photoresist layer to form a first photoresist layer having a first thickness and a second photoresist layer having a second thickness, the second thickness being greater than the first thickness, the first photoresist layer and the second photoresist layer
  • the photoresist layer is spaced apart to form a spacer, and a drain via is formed on the second insulating layer of the spacer; the first photoresist layer is removed, and the second photoresist layer is subjected to a texturing process, thereby forming a second photoresist layer Forming a surface on the surface; depositing a pixel electrode layer on the substrate, and wet-etching the stripping liquid on the surface of the second photores
  • the invention only needs to fabricate the TFT substrate through three masks, deposits the pixel electrode layer after the photoresist is cured, can effectively strip the photoresist layer, and the pixel electrode and the second insulating layer have no obvious steps, thereby improving the process efficiency and reducing the efficiency. Process difficulty.

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  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

一种TFT基板的制作方法，包括：在基板（1000）上形成TFT栅极（101），再依次形成第一绝缘层（20）、有源层（30）、源极（401）和漏极（402），再形成第二绝缘层（50）并涂布光阻（60），定义像素电极图案，在第二绝缘层（50）上形成漏极通孔（B），光阻制绒后沉积像素电极层（70），从绒面渗入剥离液去除光阻（60）及光阻（60）上的像素电极层（70），形成像素电极（70），使像素电极（70）通过漏极通孔（B）与漏极（402）相连。

Description

TFT基板的制作方法 技术领域
本发明涉及显示器技术领域，特别是涉及一种TFT基板的制作方法。
 背景技术
随着TFT技术的发展，TFT(Thin Film Transistor，薄膜晶体管)制程Mask（光罩）需求从5/6 Mask降到现在主流的4Mask，成本大大降低。每减少一道Mask，机器物料时间成本都会下降较多，大大提高产品竞争力。3Mask TFT因其节约一道Mask，较大幅度降低成本，相关技术较热门。
目前3Mask TFT技术大部分是通过把PV（钝化）层与Pixel （像素）ITO（氧化铟锡）层在一道Mask内完成，但所遇到PR（光阻）上的ITO剥离问题。通常PR上沉积Pixel ITO后剥离时间较长，影响生产节拍时间，以及PR剥离残留和毛边问题都会严重影响制程或产品性能。另外，目前所用的PR/PV低切方法必须经过PV层刻蚀才能形成，因此ITO与PV层出现较大的表面台阶，影响产品特性。
因此，现有技术存在缺陷，急需改进。
 技术问题
本发明的目的在于提供一种改进的TFT基板的制作方法。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明提供一种TFT基板的制作方法，包括以下步骤：
在基板上沉积第一金属层，利用第一道光罩工艺形成TFT栅极；
在该基板上依次沉积第一绝缘层、有源层和第二金属层，利用第二道光罩工艺使得第二金属层在有源层的两端分别形成源极和漏极；
在该基板上沉积第二绝缘层，在第二绝缘层上形成光阻层，利用第三道光罩对光阻层图形化处理，形成具有第一厚度的第一光阻层和具有第二厚度的第二光阻层，第二厚度大于第一厚度，第一光阻层与第二光阻层间隔设置形成间隔区，在间隔区的第二绝缘层上形成一漏极通孔；
去除第一光阻层，对第二光阻层进行制绒处理，从而在第二光阻层表面形成绒面；
在该基板上沉积像素电极层，采用湿法刻蚀在第二光阻层绒面未被像素电极层覆盖的表面渗入剥离液，将第二光阻层以及第二光阻层上覆盖的像素电极层去除，从而形成像素电极，该像素电极通过漏极通孔与漏极相连。
在本发明所述的TFT基板的制作方法中，在间隔区的第二绝缘层上形成一漏极通孔的步骤包括：
采用干法刻蚀在间隔区的第二绝缘层上形成一漏极通孔
本发明所述的TFT基板的制作方法中，去除第一光阻层的步骤包括：
采用光阻灰化方式使得第一光阻层脱落。
在本发明所述的TFT基板的制作方法中，对第二光阻层进行制绒处理的步骤包括：
采用干法刻蚀对第二光阻层进行制绒处理。
在本发明所述的TFT基板的制作方法中，在光阻表面形成的绒面为纳米柱，纳米柱在光阻平面上高度可为10A~10000A ，纳米柱之间距离可以10A~20000A。
本发明所述的TFT基板的制作方法中，光阻制绒采用的气体为Ar、O3、He、SF6、CF4、C4F8气体中的单种或混合气体，刻蚀气压可为5mT~10000mT。
在本发明所述的TFT基板的制作方法中，在该基板上依次沉积第一绝缘层、有源层和第二金属层的步骤包括：
采用化学气相沉积法在基板上依次沉积第一绝缘层、有源层和第二金属层。
在本发明所述的TFT基板的制作方法中，像素电极层为ITO。
在本发明所述的TFT基板的制作方法中，第二道光罩为半色调光罩或灰色调光罩。
在本发明所述的TFT基板的制作方法中，有源层为A-Si。
 有益效果
相较于现有的TFT基板的制作方法，本发明通过在基板上沉积第一金属层，利用第一道光罩工艺形成TFT栅极；在该基板上依次沉积第一绝缘层、有源层和第二金属层，利用第二道光罩工艺使得第二金属层在有源层的两端分别形成源极和漏极；在该基板上沉积第二绝缘层，在第二绝缘层上形成光阻层，利用第三道光罩对光阻层图形化处理，形成具有第一厚度的第一光阻层和具有第二厚度的第二光阻层，第二厚度大于第一厚度，第一光阻层与第二光阻层间隔设置形成间隔区，在间隔区的第二绝缘层上形成一漏极通孔；去除第一光阻层，对第二光阻层进行制绒处理，从而在第二光阻层表面形成绒面；在该基板上沉积像素电极层，采用湿法刻蚀在第二光阻层绒面未被像素电极层覆盖的表面渗入剥离液，将第二光阻层以及第二光阻层上覆盖的像素电极层去除，从而形成像素电极，该像素电极通过漏极通孔与漏极相连。该方案只需通过三道光罩制作TFT基板，进行光阻制绒后沉积像素电极层，可以有效剥离光阻层，且像素电极与第二绝缘层无明显的台阶，提高了制程效率并降低了工艺难度。
 附图说明
图1为本发明的TFT基板制作方法的优选实施例的流程示意图。
图2为本发明优选实施例中第一道光罩工艺示意图。
图3为本发明优选实施例中第二道光罩工艺示意图。
图4为本发明优选实施例中第三道光罩工艺示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的模块是以相同标号表示。
请参照图1，图1为本发明的TFT基板的制作方法的流程示意图。该TFT基板的制作方法包括以下流程：
S101，在基板上沉积第一金属层，利用第一道光罩工艺形成TFT栅极。
S102，在该基板上依次沉积第一绝缘层、有源层和第二金属层，利用第二道光罩工艺使得第二金属层在有源层的两端形成源极和漏极。
S103，在该基板上沉积第二绝缘层，在第二绝缘层上形成光阻层，利用第三道光罩对光阻层图形化处理，形成具有第一厚度的第一光阻层和具有第二厚度的第二光阻层，第二厚度大于第一厚度，第一光阻层与第二光阻层间隔设置形成间隔区，在间隔区的第二绝缘层中形成一漏极通孔。
S104、去除第一光阻层，对第二光阻层进行制绒处理，从而在第二光阻层表面形成绒面。
S105、在该基板上沉积像素电极层，采用湿法刻蚀在第二光阻层绒面未被像素电极层覆盖的表面渗入剥离液，将第二光阻层以及第二光阻层上覆盖的像素电极层去除，从而形成像素电极，该像素电极通过漏极通孔与漏极相连。
以下将结合图2-4对以上TFT基板的制作方法的步骤进行详细描述。
请参考图2，图2为本发明一较佳实施例的第一道光罩工艺示意图。下面结合图2由上至下所示理解本发明步骤S101。
在步骤S101中，首先可以采用在CVD（Chemical Vapor Deposition，化学气相沉积）法在基板1000上形成第一金属层10，该金属层10可以由铬（Cr）、铬的合金材料或者钼钽（Mo Ta）合金、铝（Al）以及铝合金材料制作。然后，在第一金属层10上涂布厚度均匀的光阻11，通过第一道光罩对涂布的光阻11曝光、显影，再进行刻蚀后形成TFT栅极101。第一道光罩可以为普通光罩。
参考图3，图3为本发明一较佳实施例的第二道光罩工艺示意图。下面结合图3由上至下所示理解本发明步骤S102。
在步骤S102中，首先TFT栅极101和基板1000未被TFT栅极101覆盖的部分上，依次沉积第一绝缘层20、有源层30和第二金属层40，然后在第二金属层40上涂布光阻41，通过第二道光罩对涂布的光阻41曝光、显影，然后进行刻蚀，形成图形化处理后与TFT栅极101相对的有有源层30，且使得第二金属层40在图形化处理后的有源层30的两端，分别形成间隔设置的源极401和漏极402。
其中，沉积的方式有多种，比如可采用CVD法沉积。第二道光罩可为半色调光罩或灰色调光罩。第一绝缘层20可以是一层结构，也可以是两层结构。第一层结构可以为SiO、SiNx或AIO。第二层结构一般可采用SiNx制成。有源层30与TFT栅极101相对，其可以由半导体材料制成，如A-Si。第二金属层40，则可以采用铝合金、金属铝或金属铬制作。源极401用于连接数据信号线，漏极402用于连接像素电极。
参考图4，图4为本发明一较佳实施例的第三道光罩工艺示意图。下面结合图4由上至下所示理解本发明步骤S103。
在步骤S103中，首先通过CVD法在源极401、漏极402、有源层30上未被源极40和漏极402覆盖的部分，以及第一绝缘层20上未被有源层30覆盖的部分，形成第二绝缘层（即钝化层）50，其制备材料可以为SiNx、SiO等。然后，在第二绝缘层50上涂布厚度均匀的光阻层60。再通过第三道光罩对光阻层60进行曝光、显影，从而形成具有第一厚度的第一光阻层601和具有第二厚度的第二光阻层602，第二厚度大于第一厚度，使得第一光阻层601与第二光阻层602间隔设置，从而形成用于界定第二绝缘层50中待挖孔部分的间隔区A。然后通过干法刻蚀去除间隔区A下方的第二绝缘层部分，从而在第二绝缘层50中形成一漏极通孔B，露出用于对应的漏极表面。其中，露出的漏极表面小于或等于源极上表面的1/2，具体实施时刻设为1/3。该第三道光罩可以为半色调光罩或灰色调光罩。
继续参考图4，在步骤S104中，在形成漏极通孔B后，可采用光阻灰化方式使得厚度较薄的第一光阻层601脱落，从而露出对应的第二绝缘层表面，同时将厚度较厚的第二光阻层602打薄。比如，在理想情况下，若第一光阻层601的厚度为d，第二光阻层的厚度为3d，则进行光阻灰化后第二光阻层602的厚度为2d。
接着对第二光阻层602进行制绒处理，通过刻蚀或其他方式使得第二光阻层602雾化，从而在光阻表面形成凹凸有致的绒面。其中，该绒面可为凸起的纳米柱，纳米柱在光阻平面上高度可为10A~10000A。纳米柱之间距离可以10A~20000A。光阻制绒采用的气体可为Ar、O3、He、SF6、CF4、C4F8气体中的单种或混合气体，刻蚀气压可为5mT~10000mT。
继续参考图4，在步骤S105中，在对光阻层602进行制绒处理后，接着整面沉积像素电极ITO或其它导电材料，从而在制绒后的光阻层602的绒面、露出的第二绝缘层50表面以及露出的漏极402表面上形成像素电极层70。然后，通过光阻剥离去除第二光阻成602以及第二光阻层602上覆盖的像素电极ITO或其它导电材料。
由于光阻层602中绒面的阴影作用，像素电极ITO或其它导电材料将无法全部覆盖第二光阻层602的绒面，因此在进行光阻剥离时，剥离液很容易与露出的光阻表面接触，使得光阻层60与第二绝缘层50高效剥离。然后进行像素电极ITO退火，从而在露出的第二绝缘层50表面以及露出的漏极402表面上形成像素电极70，该像素电极70通过漏极通孔B与漏极402相连。
本优选实施例的TFT基板制作方法，在基板上沉积第一金属层，利用第一道光罩工艺形成TFT栅极；在该基板上依次沉积第一绝缘层、有源层和第二金属层，利用第二道光罩工艺使得第二金属层在有源层的两端分别形成源极和漏极；在该基板上沉积第二绝缘层，在第二绝缘层上形成光阻层，利用第三道光罩对光阻层图形化处理，形成具有第一厚度的第一光阻层和具有第二厚度的第二光阻层，第二厚度大于第一厚度，第一光阻层与第二光阻层间隔设置形成间隔区，在间隔区的第二绝缘层上形成一漏极通孔；去除第一光阻层，对第二光阻层进行制绒处理，从而在第二光阻层表面形成绒面；在该基板上沉积像素电极层，采用湿法刻蚀在第二光阻层绒面未被像素电极层覆盖的表面渗入剥离液，将第二光阻层以及第二光阻层上覆盖的像素电极层去除，从而形成像素电极，该像素电极通过漏极通孔与漏极相连。本发明只需通过三道光罩制作TFT基板，进行光阻制绒后沉积像素电极层，可以有效剥离光阻层，且像素电极与第二绝缘层无明显的台阶，提高了制程效率并降低了工艺难度。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种TFT基板的制作方法，其特征在于，包括以下步骤：
    在基板上沉积第一金属层，利用第一道光罩工艺形成TFT栅极；
    在该基板上依次沉积第一绝缘层、有源层和第二金属层，利用第二道光罩工艺使得第二金属层在有源层的两端分别形成源极和漏极；
    在该基板上沉积第二绝缘层，在第二绝缘层上形成光阻层，利用第三道光罩对光阻层图形化处理，形成具有第一厚度的第一光阻层和具有第二厚度的第二光阻层，第二厚度大于第一厚度，第一光阻层与第二光阻层间隔设置形成间隔区，在间隔区的第二绝缘层上形成一漏极通孔；
    去除第一光阻层，对第二光阻层进行制绒处理，从而在第二光阻层表面形成绒面；
    在该基板上沉积像素电极层，采用湿法刻蚀在第二光阻层绒面未被像素电极层覆盖的表面渗入剥离液，将第二光阻层以及第二光阻层上覆盖的像素电极层去除，从而形成像素电极，该像素电极通过漏极通孔与漏极相连。
  2. 如权利要求1所述的TFT基板的制作方法，其特征在于，在间隔区的第二绝缘层上形成一漏极通孔的步骤包括：
    采用干法刻蚀在间隔区的第二绝缘层上形成一漏极通孔。
  3. 如权利要求1所述的TFT基板的制作方法，其特征在于，
    去除第一光阻层的步骤包括：
    采用光阻灰化方式使得第一光阻层脱落。
  4. 如权利要求1所述的TFT基板的制作方法，其特征在于，对第二光阻层进行制绒处理的步骤包括：
    采用干法刻蚀对第二光阻层进行制绒处理。
  5. 如权利要求4所述的TFT基板的制作方法，其特征在于，在光阻表面形成的绒面为纳米柱，纳米柱在光阻平面上高度可为10A~10000A ，纳米柱之间距离可以10A~20000A。
  6. 如权利要求4所述的TFT基板的制作方法，其特征在于，光阻制绒采用的气体为Ar、O3、He、SF6、CF4、C4F8气体中的单种或混合气体，刻蚀气压可为5mT~10000mT。
  7. 如权利要求1所述的TFT基板的制作方法，其特征在于，在该基板上依次沉积第一绝缘层、有源层和第二金属层的步骤包括：
    采用化学气相沉积法在基板上依次沉积第一绝缘层、有源层和第二金属层。
  8. 如权利要求1所述的TFT基板的制作方法，其特征在于，像素电极层为ITO。
  9. 如权利要求1所述的TFT基板的制作方法，其特征在于，第二道光罩为半色调光罩或灰色调光罩。
  10. 如权利要求1所述的TFT基板的制作方法，其特征在于，有源层为A-Si。
  11. 一种TFT基板的制作方法，其特征在于，包括以下步骤：
    在基板上沉积第一金属层，利用第一道光罩工艺形成TFT栅极；
    在该基板上依次沉积第一绝缘层、有源层和第二金属层，利用第二道光罩工艺使得第二金属层在有源层的两端分别形成源极和漏极；
    在该基板上沉积第二绝缘层，在第二绝缘层上形成光阻层，利用第三道光罩对光阻层图形化处理，形成具有第一厚度的第一光阻层和具有第二厚度的第二光阻层，第二厚度大于第一厚度，第一光阻层与第二光阻层间隔设置形成间隔区，采用干法刻蚀在间隔区的第二绝缘层上形成一漏极通孔；
    采用光阻灰化方式使得第一光阻层脱落，从而去除第一光阻层；
    对第二光阻层进行制绒处理，从而在第二光阻层表面形成绒面；
    在该基板上沉积像素电极层，采用湿法刻蚀在第二光阻层绒面未被像素电极层覆盖的表面渗入剥离液，将第二光阻层以及第二光阻层上覆盖的像素电极层去除，从而形成像素电极，该像素电极通过漏极通孔与漏极相连。
  12. 如权利要求11所述的TFT基板的制作方法，其特征在于，对第二光阻层进行制绒处理的步骤包括：
    采用干法刻蚀对第二光阻层进行制绒处理。
  13. 如权利要求12所述的TFT基板的制作方法，其特征在于，在光阻表面形成的绒面为纳米柱，纳米柱在光阻平面上高度可为10A~10000A ，纳米柱之间距离可以10A~20000A。
  14. 如权利要求12所述的TFT基板的制作方法，其特征在于，光阻制绒采用的气体为Ar、O3、He、SF6、CF4、C4F8气体中的单种或混合气体，刻蚀气压可为5mT~10000mT。
  15. 如权利要求11所述的TFT基板的制作方法，其特征在于，在该基板上依次沉积第一绝缘层、有源层和第二金属层的步骤包括：
    采用化学气相沉积法在基板上依次沉积第一绝缘层、有源层和第二金属层。
  16. 如权利要求11所述的TFT基板的制作方法，其特征在于，像素电极层为ITO。
  17. 如权利要求11所述的TFT基板的制作方法，其特征在于，第二道光罩为半色调光罩或灰色调光罩。
  18. 如权利要求11所述的TFT基板的制作方法，其特征在于，有源层为A-Si。
  19. 如权利要求11所述的TFT基板的制作方法，其特征在于，第三道光罩为半色调光罩或灰色调光罩。
  20. 如权利要求11所述的TFT基板的制作方法，其特征在于，有源层为SiO。
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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9753590B2 (en) * 2014-06-13 2017-09-05 Lg Display Co., Ltd. Display device integrated with touch screen panel and method of fabricating the same
CN106981456B (zh) * 2017-04-01 2019-08-13 深圳市华星光电半导体显示技术有限公司 Tft基板的制作方法
CN108538855B (zh) * 2018-03-30 2020-06-30 深圳市华星光电半导体显示技术有限公司 一种阵列基板的制作方法
US10720454B2 (en) * 2018-06-05 2020-07-21 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Manufacturing method for array substrate and liquid crystal display device
CN109037238B (zh) * 2018-07-25 2020-10-02 深圳市华星光电技术有限公司 阵列基板及阵列基板的制作方法
CN111430378B (zh) * 2020-04-13 2022-05-03 Tcl华星光电技术有限公司 显示面板的制作方法
CN112864090B (zh) * 2021-01-19 2023-01-24 Tcl华星光电技术有限公司 一种薄膜晶体管基板的制备方法
CN114203630B (zh) * 2021-12-09 2024-11-26 Tcl华星光电技术有限公司 阵列基板的制作方法、阵列基板以及显示装置
CN115132655B (zh) * 2022-06-28 2025-08-22 Tcl华星光电技术有限公司 显示面板的制作方法及显示面板
CN117215148B (zh) * 2023-11-07 2024-01-26 惠科股份有限公司 阵列基板的制备方法、阵列基板及显示面板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5478766A (en) * 1994-03-03 1995-12-26 Samsung Electronics Co., Ltd. Process for formation of thin film transistor liquid crystal display
JP2005064034A (ja) * 2003-08-12 2005-03-10 Toshiba Corp 薄膜トランジスタの製造方法及び表示装置の製造方法
CN105914183A (zh) * 2016-06-22 2016-08-31 深圳市华星光电技术有限公司 Tft基板的制造方法
CN106229294A (zh) * 2016-08-31 2016-12-14 深圳市华星光电技术有限公司 一种tft基板的制作方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2402941B (en) * 2003-06-09 2007-06-27 Kao Corp Method for manufacturing substrate
WO2016016761A1 (en) * 2014-07-31 2016-02-04 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
CN105826329B (zh) * 2016-05-09 2019-04-02 深圳市华星光电技术有限公司 一种阵列基板的制作方法、阵列基板及液晶面板

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5478766A (en) * 1994-03-03 1995-12-26 Samsung Electronics Co., Ltd. Process for formation of thin film transistor liquid crystal display
JP2005064034A (ja) * 2003-08-12 2005-03-10 Toshiba Corp 薄膜トランジスタの製造方法及び表示装置の製造方法
CN105914183A (zh) * 2016-06-22 2016-08-31 深圳市华星光电技术有限公司 Tft基板的制造方法
CN106229294A (zh) * 2016-08-31 2016-12-14 深圳市华星光电技术有限公司 一种tft基板的制作方法

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