WO2018121521A1 - 半导体器件的测试结构和测试方法 - Google Patents

半导体器件的测试结构和测试方法 Download PDF

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Publication number
WO2018121521A1
WO2018121521A1 PCT/CN2017/118584 CN2017118584W WO2018121521A1 WO 2018121521 A1 WO2018121521 A1 WO 2018121521A1 CN 2017118584 W CN2017118584 W CN 2017118584W WO 2018121521 A1 WO2018121521 A1 WO 2018121521A1
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Prior art keywords
active region
polysilicon gate
test
width
resistor
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PCT/CN2017/118584
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English (en)
French (fr)
Inventor
任小兵
刘群
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无锡华润上华科技有限公司
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Priority to US16/474,943 priority Critical patent/US10816589B2/en
Publication of WO2018121521A1 publication Critical patent/WO2018121521A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2648—Characterising semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps

Definitions

  • the present invention relates to the field of semiconductor testing technology, and in particular to a test structure and a testing method for a semiconductor device.
  • the semiconductor device includes a shallow trench isolation structure, a polysilicon gate, and an active region.
  • a semiconductor device such as a MOS (Metal-Oxide-Semiconductor) tube
  • MOS Metal-Oxide-Semiconductor
  • Device parameters have a large impact.
  • PCM Process Control Monitor
  • a test structure is required to monitor the width of the polysilicon gate.
  • the conventional test structure is a structure of a comb-shaped MOS capacitor, and the polysilicon gate of this structure does not change in accordance with the variation of the step height of the STI (Shallow Trench Isolation).
  • the actual situation is that the width of the polysilicon gate of the small-sized active region varies with the height of the STI step. Therefore, this test structure does not monitor the effect of the STI step height on the width of the polysilicon gate on the active region.
  • a test structure of a semiconductor device comprising: a first active region and a first polysilicon gate disposed on the first active region; a width of the first active region is greater than a preset a width value; the predetermined width value is a critical value of an active region width of the semiconductor device when a step height of the shallow trench isolation structure of the semiconductor device affects a width of a polysilicon gate of the semiconductor device;
  • the design width of the first polysilicon gate is the same as the design width of the polysilicon gate of the semiconductor device; and the second resistor structure is electrically connected to the first resistor structure according to a predetermined circuit structure to form a test circuit.
  • the second resistor structure includes a second active region and a second polysilicon gate disposed on the second active region; a width of the second active region is less than the predetermined width value;
  • the design dimension of the second polysilicon gate is the same as the design dimension of the first polysilicon gate; the total resistance of the branch where the second resistor structure is located is equal to the total resistance of the branch where the first resistor structure is located.
  • a test method for a test structure based on a semiconductor device comprising: a first resistor structure including a first active region and a first polysilicon gate disposed on the first active region;
  • the width of the first active region is greater than a preset width value;
  • the predetermined width value is when the step height of the shallow trench isolation structure of the semiconductor device affects the width of the polysilicon gate of the semiconductor device, the semiconductor a threshold value of an active region width of the device;
  • a design width of the first polysilicon gate is the same as a design width of a polysilicon gate of the semiconductor device;
  • a second resistor structure electrically connected to the first resistor structure in a predetermined circuit structure to form a test circuit, the second resistor structure including a second active region and a first disposed on the second active region a second polysilicon gate; a width of the second active region is less than the predetermined width value; a design size of the second polysilicon gate is the same as a design size of the first polysilicon gate; The total resistance of the branch in which the second resistor structure is located is equal to the total resistance of the branch in which the first resistor structure is located;
  • the test method includes the following steps:
  • the influence of the step height of the shallow trench isolation structure on the width of the polysilicon gate is monitored according to the change of the voltage difference.
  • FIG. 1 is a schematic structural view of a first resistor structure in an embodiment
  • FIG. 2 is a schematic diagram of photoresist step coverage in a small-sized active region polysilicon lithography
  • FIG. 3 is a schematic diagram of photoresist step coverage in a large-sized active region polysilicon lithography
  • FIG. 5 is a schematic structural view of a second resistor structure in an embodiment
  • FIG. 6 is a schematic diagram showing the connection of a first resistor structure and a second resistor structure in a test structure of a semiconductor device in an embodiment
  • FIG. 7 is a circuit layout of a test structure of a semiconductor device in an embodiment
  • FIG. 8 is a flow chart showing a method of testing a semiconductor device in an embodiment.
  • the test structure of the semiconductor device in an embodiment is used for monitoring the influence of the step height of the shallow trench isolation structure of the semiconductor device on the width of the polysilicon gate, so that the thickness of the photoresist of the polysilicon lithography can be adjusted according to the degree of influence.
  • the effect of the step height of the shallow trench isolation structure on the width of the polysilicon gate is reduced to ensure that the feature size of the finally prepared semiconductor device is the target feature size.
  • the test structure of the semiconductor device (hereinafter referred to as the test structure) is disposed in the scribe groove region of the silicon wafer.
  • the test structure includes a first resistance structure R1 and a second resistance structure R2 that are independent of each other.
  • the structure of the first resistor structure R1 is as shown in FIG.
  • the first resistance structure R1 includes a first active region 110, a first field region 120, a first polysilicon gate 130, and a contact hole 142 and a contact hole 144.
  • N-type or P-type ion implantation is performed in the first active region 110.
  • the N-type or P-type ion implantation in the first active region 110 is implemented by a non-self-alignment process (Non Salicide), and thus the first resistance structure R1 is an N-type or P-type non-self-aligned silicide (Non Salicide). resistance.
  • the width of the N-type or P-type implanted region is adapted to the width of the first active region 110.
  • the first field region 120 may be disposed around the first active region 110.
  • the first polysilicon gate 130 is disposed on the first active region 110.
  • the contact hole 142 and the contact hole 144 may be disposed on the first field region 120 and located at both ends of the first polysilicon gate 130, specifically at both ends of the first polysilicon gate 130 in the longitudinal direction.
  • the width of the first active region 110 needs to be greater than a preset width value.
  • the preset width value is a critical value of the active region width of the semiconductor device when the step height of the shallow trench isolation structure on the semiconductor device affects the width of the polysilicon gate of the semiconductor device.
  • an active area having a width larger than a preset width value is defined as a large-sized active area
  • an active area having a width smaller than a preset width value is defined as a small-sized active area.
  • the shallow trench isolation structure step height results in the deposition of polysilicon on the interface between the active region and the shallow trench isolation structure. Due to the step coverage characteristics of the photoresist, as shown in FIG.
  • the thickness of the polysilicon photoresist on the independent small-sized active region (that is, the active region having a width smaller than the preset width value) is larger than that of the adjacent shallow trench isolation.
  • the thickness of the photoresist on the structure, this thickness difference is equal to the step height of the shallow trench isolation structure.
  • the photoresist thickness is equal to the thickness of the photoresist on the shallow trench isolation structure, and the shallow trench The isolation structure has no height.
  • the change in the thickness of the photoresist causes a change in the width of the photoresist strip after lithography, which in turn causes the width of the prepared polysilicon gate to also change.
  • Figure 4 shows the critical dimensions of the photoresist thickness to the semiconductor device (CD, also That is, the relationship between the width of the polysilicon gate), in FIG. 4, the horizontal axis is the thickness of the photoresist, and the vertical axis is the critical dimension.
  • the critical dimension changes greatly, that is, when the height of the shallow trench isolation structure is fluctuating, since the width of the polysilicon gate of the independent small-sized active region changes, the independent small size has
  • the thickness of the photoresist in the source region is in other regions of the curve, the variation in the width of the polysilicon gate is greater.
  • the width of the polysilicon gate of the large active area is not affected.
  • the preset width value is 3 microns. Therefore, the width of the first active region 110 is greater than 3 micrometers, which is a large-sized active region, so the width of the first polysilicon gate 130 disposed on the first active region 110 does not follow the step of the shallow trench isolation structure.
  • the longer the length of the first active region 110, the better, and the minimum may be 20 microns.
  • the first active region 110 has a width of 20 microns and a length of 60 microns.
  • the first polysilicon gate 130 may be disposed at an intermediate position of the first active region 110, and the length direction of the first polysilicon gate 130 is parallel to the length direction of the first active region 110.
  • the design width of the first polysilicon gate 130 is the same as the design width of the polysilicon gate of the semiconductor device to be monitored, that is, the design width thereof is the feature size of the semiconductor device to be tested.
  • the design widths mentioned herein refer to the design parameters for preparing polysilicon gates.
  • the first polysilicon gate 130 acts as a resistive strip with its ends extending beyond the first active region 110 and into the first field region 120. Further, a portion of the first polysilicon gate 130 beyond the first active region 110 may be equal in length.
  • the length of the first polysilicon gate 130 in the first active region 110 is the length of the first active region 110.
  • the length of the first polysilicon gate 130 in the first active region 110 is 60 mm, representing the first An active region 110 has a length of 60 microns.
  • the contact hole 142 in the first field region 120 and the contact hole 144 in the first field region 120 are used for connection with a metal wire to realize electrical connection of the first resistor structure R1 with other devices.
  • the contact holes 142 and the contact holes 144 may have the same structure and are symmetrically disposed.
  • the structure of the second resistor structure R2 is as shown in FIG.
  • the second resistance structure R2 includes a second active region 210, a second field region 220, a second polysilicon gate 230, and a contact hole 242 and a contact hole 244. N-type or P-type ion implantation is performed in the second active region 210.
  • the N-type or P-type ion implantation in the second active region 210 is achieved by a non-self-aligned process (Non Salicide), and thus the second resistive structure R2 is an N-type or P-type non-self-aligned silicide resistor.
  • the type of ions implanted in the second active region 210 is the same as the type of ions implanted in the first active region 110, and both are N-type or P-type ions, thereby making the first active region 110 and the first
  • the two active regions 210 are all N-type or P-type non-self-aligned silicide resistors.
  • the thickness uniformity of the self-aligned silicide formed on the small-sized active region is poor, and the thickness has a great influence on the resistance, so that the degree of influence of the polysilicon gate width on the resistance is lowered, which is disadvantageous for analysis, and therefore non-self-aligned Quasi-silicide resistance can well overcome this problem, and the non-self-aligned silicide resistor has a relatively high resistance (such as 260 ohms), which is good for data measurement, while self-aligned silicide has lower resistance (such as 5). Ohm), not easy to measure.
  • the width of the N-type or P-type implanted region is adapted to the width of the second active region 210.
  • the second field region 220 is disposed around the second active region 210.
  • the length of the second field region 220 is the same as the length of the first field region 120.
  • the second polysilicon gate 230 is disposed on the second active region 210.
  • the contact hole 242 and the contact hole 244 may be disposed on the second field region 220 and located at both ends of the second polysilicon gate 230, specifically at both ends of the second polysilicon gate 230 in the longitudinal direction.
  • the width of the second active region 210 is less than a preset width value, and the preset width value may be 3 micrometers. Therefore, the second active region 210 has a width of less than 3 micrometers and is a small-sized active region. Therefore, the width of the second polysilicon gate 230 disposed on the second active region 210 varies according to the variation of the step height of the shallow trench isolation structure, that is, the actual width and design width of the second polysilicon gate 230. There is some fluctuation. The longer the length of the second active region 210, the better, and the minimum may be 20 microns. In one embodiment, the second active region 210 has a width of 1 micron and a length of 60 micrometers.
  • the second polysilicon gate 230 may be disposed at an intermediate position of the second active region 210, and the length direction of the second polysilicon gate 230 is parallel to the length direction of the second active region 210.
  • the design dimension of the second polysilicon gate 230 is the same as the design dimension of the first polysilicon gate 130.
  • the design width of the second polysilicon gate 230 is the same as the design width of the first polysilicon gate 130.
  • the design length of the polysilicon gate 230 is the same as the design length of the first polysilicon gate 130, thereby ensuring the width of the active region and the corresponding N-type (or P) in the first resistance structure R1 and the second resistance structure R2. Type)
  • the width of the injection area is different, and other factors are the same.
  • the second polysilicon gate 230 acts as a resistive strip with its ends extending beyond the second active region 210 and into the second field region 220. Further, the lengths of the ends of the second polysilicon gate 230 beyond the second active region 210 are equal.
  • the length of the second polysilicon gate 230 in the second active region 210 is the length of the second active region 210.
  • the length of the second polysilicon gate 230 in the second active region 210 is 60 micrometers, representing the first The length of the two active regions 110 is 60 microns.
  • the length of the second polysilicon gate 230 on the second field region 220 is the same as the length of the first polysilicon gate 130 on the first field region 120.
  • the first resistor structure R1 and the second resistor structure R2 should have different widths of the active region and the corresponding N-type (or P-type) implant region, and other structures should be the same.
  • the contact hole 242 in the second field region 220 and the contact hole 244 in the second field region 220 are used for connection with a metal wire to realize electrical connection of the second resistor structure R2 with other devices.
  • the contact holes 242 and the contact holes 244 may be identical and symmetrically arranged.
  • the first resistive structure R1 and the second resistive structure R2 are prepared in synchronization with the semiconductor device, that is, the first active region 110 and the second active region 210 are synchronized with the active region of the semiconductor device.
  • the first polysilicon gate 130 and the second polysilicon gate 230 are prepared in synchronization with the polysilicon gate of the semiconductor device.
  • the first resistor structure R1 and the second resistor structure R2 are patterned according to a predetermined circuit structure and electrically connected to form a test circuit.
  • the total resistance of the branch in which the first resistor structure R1 is located is the same as the total resistance of the branch in which the second resistor structure R2 is located, so that the test circuit flows through each of the first resistor structure R1 and the second resistor structure R2.
  • the current is the same. Therefore, by monitoring the voltage difference between the first resistor structure R1 and the second resistor structure R2, the difference in resistance values of the first resistor structure R1 and the second resistor structure R2 can be obtained.
  • the difference between the polysilicon resistors is actually prepared by the polysilicon.
  • the width of the gate is different, and the width of the polysilicon gate is different because the height of the step of the shallow trench isolation structure is fluctuating. Therefore, by monitoring the variation of the voltage difference, it can be monitored that the step height of the shallow trench isolation structure is independent.
  • the effect of the width of the polysilicon gate on the source region allows the degree of influence of the step height of the shallow trench isolation structure on the width of the polysilicon gate on the active region to be reduced by adjusting the thickness of the photoresist of the polysilicon lithography.
  • the test structure in this embodiment also has the advantages of simple structure, easy preparation, no increase in production cost, and shortening of the production cycle.
  • the test structure in different locations on the silicon wafer can be monitored to determine if the measured voltage uniformity is good. If the uniformity is poor, it indicates that the width of the polysilicon gate is easily changed. This change in width is due to the thickness of the photoresist of the polysilicon gate lithography, and this change in thickness is due to the variation in the step height of the shallow trench isolation structure. Therefore, according to the test result, the thickness of the currently used photoresist is not suitable, so that the thickness of the photoresist of the polysilicon gate of the semiconductor device can be adjusted and adjusted to an optimal position to reduce the height variation of the shallow trench step. Significant changes in the width of the polysilicon gate improve product yield and product stability.
  • test structure can also monitor the stability of the lithography process.
  • voltage measurements of test structures between different silicon wafers can be compared, or for different batches.
  • the voltage test results of the test structures are compared to determine whether the thickness of the photoresist needs to be adjusted according to the uniformity of the final test voltage, so that the width of the polysilicon gate of the finally obtained semiconductor device is the target feature size.
  • the first resistor structure R1 and the second resistor structure R2 are electrically connected according to a bridge circuit to form a test circuit.
  • the connection diagram is shown in Figure 6, and its circuit layout design is shown in Figure 7.
  • the bridge circuit includes two parallel branches. A first resistor structure R1 and a second resistor structure R2 are disposed in parallel on the two parallel branches. Moreover, the arrangement of the two resistance structures R1 and R2 on the two parallel branches is reversed. Two junctions of two parallel branches are used as test voltage application pressure points. As shown in Fig. 7, there is a junction point J2 and a junction point J3. The junction point J2 is used as a test voltage application pressure point 2, and the junction point J3 is used as a test voltage application pressure point. 3.
  • the node between the two resistance structures R1 and R2 of each parallel branch is used as the measurement pressure point.
  • node J1 and node J4 there are node J1 and node J4, node J1 is used as measurement pressure point 1, and node J4 is used as measurement pressure point 4. .
  • the test voltage application pressure point and the measurement pressure point are each connected to the corresponding contact hole through a metal wire.
  • the test structure includes two first resistance structures R1 and two second resistance structures R2, and the two first resistance structures R1 are respectively the first resistance structure R1 on the left side and the right side
  • the first resistor structure R1 and the two second resistor structures R2 are respectively a second resistor structure R2 on the left side and a second resistor structure R2 on the right side.
  • the two first resistor structures R1 are respectively provided with two contact holes, respectively The left contact hole and the right contact hole
  • the two second resistor structures R2 are provided with two contact holes, which are a left contact hole and a right contact hole, respectively.
  • the test voltage application pressure point 2 is connected to the left contact hole of the first resistor structure R1 on the left side in the figure and the left contact hole of the second resistor structure R2 on the left side in the figure through the metal connection 320, and the test voltage is applied to the pressure point 3
  • the metal connection 330 is respectively connected to the right contact hole on the first resistor structure R1 on the right side in the figure and the right contact hole of the second resistor structure R2 on the right side in the figure, and the measurement pressure point 1 is respectively connected through the metal connection 310.
  • the right contact hole of the second resistor structure R2 on the left side of the figure, the left contact hole of the first resistor structure R1 on the right side of the figure is connected, and the measurement voltage point 4 passes through the metal connection 340 and the first resistor on the left side in the figure, respectively.
  • the right contact hole of the structure R2 is connected to the left contact hole of the second resistor structure R2 on the right side in the drawing.
  • connection nodes of the circuits and the metal wires are the same and symmetrically arranged. That is, the structures of the metal wires 320 and 330 (the width and length of the metal wires) are the same and symmetrically disposed, and the pressure points 2 and the pressure points 3 are also the same structure and symmetrically disposed.
  • the metal wires 310 and 340 have the same structure and are symmetrically arranged, and the press points 2 and the press points 3 have the same structure and are symmetrically disposed.
  • the metal wires 310, 320, 330, and 340 may each be an aluminum strip. In one embodiment, each pressure point is drawn through the first layer of metal. If the design requirements are not met, the vias and the second layer of metal are taken up.
  • the positive pole of the power supply device can be connected to the pressure point 2, and the negative pole of the power supply device can be connected to the pressure point 3, thereby applying a voltage to the test circuit to make the test circuit work.
  • the power supply device can apply a voltage of 0 to 3V. In other embodiments, the applied voltage of the power supply device can be set as desired.
  • the anode of the voltage measuring device can be connected to the pressure point 1, and the cathode of the voltage measuring device can be connected to the pressure point 4 to realize the monitoring of the voltage difference U 0 on the first resistor structure R1 and the second resistor structure R2. .
  • the relationship of U 0 is:
  • the difference between the polysilicon resistors is determined by the width of the actually prepared polysilicon gate.
  • the difference is caused by the difference in the width of the polysilicon gate because the height of the step of the shallow trench isolation structure is varied.
  • the polysilicon resistors of the two structures also have a fixed difference due to the fixed difference in the width of the polysilicon.
  • this difference also fluctuates.
  • the variation of the difference can monitor the influence of the step height fluctuation of the shallow trench isolation structure on the width of the polysilicon on the independent small-sized active region, and can also be used to evaluate whether the thickness of the photoresist of the polysilicon lithography is appropriate, that is, Whether the SWING setting of the polysilicon lithography is in an optimal position.
  • test method for a semiconductor device based on the test structure described in any of the above embodiments.
  • 8 is a flow chart of a test method in an embodiment, the method comprising the following steps:
  • the step of applying a voltage to the test circuit is to apply voltage to two junctions of the two parallel branches.
  • the first resistor structure and the second resistor structure are electrically connected according to the bridge circuit to form a test circuit (as shown in FIGS. 6 and 7), and the first resistor structure and the second resistor structure are measured.
  • the step of the voltage difference is to monitor the voltage difference across the two resistor structures of each of the parallel branches. As shown in FIG. 6, specifically, the voltage difference between the two points of the node J1 and the node J4 (that is, between the pressure point 1 and the pressure point 4 in FIG. 7) can be detected to implement the first resistance structure R1 and the second. Monitoring of the voltage difference U 0 across the resistor structure R2.
  • the positive terminal of the power supply device is connected to the pressure point 2, and the negative electrode of the power supply device is connected to the pressure point 3, thereby applying a voltage to the test circuit to make the test circuit work.
  • the power supply device can apply a voltage of 0 to 3V. In other embodiments, the applied voltage of the power supply device can be set as desired.
  • the positive pole of the voltage measuring device is connected to the pressure point 1, and the negative pole of the voltage measuring device is connected to the pressure point 4 to achieve monitoring of the voltage difference U 0 on the first resistor structure R1 and the second resistor structure R2.
  • the relationship of U 0 is:
  • the voltage values on the first resistor structure and the second resistor structure may be separately measured, and then the difference between the two is obtained to obtain a voltage difference between the two resistor structures.
  • S830 monitoring the influence of the step height of the shallow trench isolation structure on the width of the polysilicon gate according to the change of the voltage difference.
  • the influence of the step height of the shallow trench isolation structure on the width of the polysilicon gate on the independent active region can be monitored by the variation of the voltage difference, so that the shallow trench can be reduced by adjusting the thickness of the photoresist of the polysilicon lithography.
  • the degree of influence of the isolation structure step height on the width of the polysilicon gate on the active region is such that the width of the polysilicon gate of the finally obtained semiconductor device is the target feature size.

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Abstract

一种半导体器件的测试结构，第一电阻结构(R1)包括第一有源区(110)和设置在第一有源区(110)上的第一多晶硅栅(130)；第一有源区(110)的宽度大于预设宽度值；预设宽度值为半导体器件的浅沟槽隔离结构的台阶高度对多晶硅栅的宽度产生影响时，半导体器件的有源区宽度的临界值；第一多晶硅栅(130)的设计宽度与半导体器件的多晶硅栅的设计宽度相同；第二电阻结构(R2)与第一电阻结构(R1)按预设电路结构连接形成测试电路，包括第二有源区(210)和设置在第二有源区(210)上的第二多晶硅栅(230)；第二有源区(210)宽度小于预设宽度值；第二多晶硅栅(230)的设计尺寸与第一多晶硅栅(130)的设计尺寸相同；第二电阻结构(R2)所在支路的总电阻和第一电阻结构(R1)所在支路的总电阻相等。

Description

半导体器件的测试结构和测试方法 技术领域
本发明涉及半导体测试技术领域，特别是涉及一种半导体器件的测试结构和测试方法。
背景技术
半导体器件包括浅沟槽隔离结构、多晶硅栅以及有源区，随着半导体器件如MOS(Metal-Oxide-Semiconductor，金属氧化物半导体)管尺寸的缩小，半导体器件的多晶硅栅的尺寸对短沟道器件参数影响较大。在PCM(Process Control Monitor，工艺控制监控)测试中，需要采用测试结构来监控多晶硅栅的宽度。传统的测试结构为梳状MOS电容的结构，这种结构的多晶硅栅不会跟随STI(Shallow Trench Isolation，浅沟槽隔离结构)台阶高度(step height)的变动而变动。而实际情况是，小尺寸有源区的多晶硅栅的宽度会随STI台阶高度的变化而变化。因此，这种测试结构并不能监测到STI台阶高度对有源区上的多晶硅栅的宽度的影响。
发明内容
基于此，有必要提供一种半导体器件的测试结构和测试方法。
一种半导体器件的测试结构，第一电阻结构，包括第一有源区和设置在所述第一有源区上的第一多晶硅栅；所述第一有源区的宽度大于预设宽度值；所述预设宽度值为所述半导体器件的浅沟槽隔离结构的台阶高度对所述半导体器件的多晶硅栅的宽度产生影响时，所述半导体器件的有源区宽度的临界值；所述第一多晶硅栅的设计宽度与所述半导体器件的多晶硅栅的设计宽度相同；以及第二电阻结构，与所述第一电阻结构按预设电路结构电性连接从 而形成测试电路，所述第二电阻结构包括第二有源区和设置在所述第二有源区上的第二多晶硅栅；所述第二有源区的宽度小于所述预设宽度值；所述第二多晶硅栅的设计尺寸与所述第一多晶硅栅的设计尺寸相同；所述第二电阻结构所在支路的总电阻和所述第一电阻结构所在支路的总电阻相等。
一种基于半导体器件的测试结构的测试方法，所述测试结构包括：第一电阻结构，包括第一有源区和设置在所述第一有源区上的第一多晶硅栅；所述第一有源区的宽度大于预设宽度值；所述预设宽度值为所述半导体器件的浅沟槽隔离结构的台阶高度对所述半导体器件的多晶硅栅的宽度产生影响时，所述半导体器件的有源区宽度的临界值；所述第一多晶硅栅的设计宽度与所述半导体器件的多晶硅栅的设计宽度相同；以及
第二电阻结构，与所述第一电阻结构按预设电路结构电性连接从而形成测试电路，所述第二电阻结构包括第二有源区和设置在所述第二有源区上的第二多晶硅栅；所述第二有源区的宽度小于所述预设宽度值；所述第二多晶硅栅的设计尺寸与所述第一多晶硅栅的设计尺寸相同；所述第二电阻结构所在支路的总电阻和所述第一电阻结构所在支路的总电阻相等；
所述测试方法包括以下步骤：
对所述测试电路施加电压以使得所述测试电路工作；
测量所述第一电阻结构和所述第二电阻结构上的电压差值；以及
根据所述电压差值的变化监控浅沟槽隔离结构台阶高度对多晶硅栅的宽度的影响情况。
本发明的一个或多个实施例的细节在下面的附图和描述中提出。本发明的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
通过附图中所示的本发明的优选实施例的更具体说明，本发明的上述及 其它目的、特征和优势将变得更加清晰。在全部附图中相同的附图标记指示相同的部分，且并未刻意按实际尺寸等比例缩放绘制附图，重点在于示出本发明的主旨。
图1为一实施例中的第一电阻结构的结构示意图；
图2为小尺寸有源区多晶硅光刻时的光刻胶台阶覆盖示意图；
图3为大尺寸有源区多晶硅光刻时的光刻胶台阶覆盖示意图；
图4为光刻胶厚度和多晶硅栅的宽度的关系曲线图；
图5为一实施例中的第二电阻结构的结构示意图；
图6为一实施例中的半导体器件的测试结构中的第一电阻结构和第二电阻结构的连接示意图；
图7为一实施例中的半导体器件的测试结构的电路版图；
图8为一实施例中的半导体器件的测试方法的流程图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
需要说明的是，当元件被称为“固定于”另一个元件，它可以直接在另一个元件上或者也可以存在居中的元件。当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件或者可能同时存在居中元件。本文所使用的术语“竖直的”、“水平的”、“上”、“下”、“左”、“右”以及类似的 表述只是为了说明的目的。
一实施例中的半导体器件的测试结构，用于监控半导体器件的浅沟槽隔离结构台阶高度对多晶硅栅的宽度的影响，从而可以根据该影响程度对多晶硅光刻的光刻胶厚度进行调整以减少浅沟槽隔离结构台阶高度对多晶硅栅的宽度的影响，确保最终制备得到的半导体器件的特征尺寸为目标特征尺寸。该半导体器件的测试结构(以下简称测试结构)设置在硅片的划片槽区域。在本实施例中，该测试结构包括相互独立的第一电阻结构R1和第二电阻结构R2。
第一电阻结构R1的结构如图1所示。该第一电阻结构R1包括第一有源区110、第一场区120、第一多晶硅栅130和接触孔142和接触孔144。第一有源区110内进行N型或者P型离子注入。第一有源区110内的N型或者P型离子注入采用非自对准工艺(Non Salicide)来实现，因而第一电阻结构R1为N型或者P型非自对准硅化物(Non Salicide)电阻。N型或者P型注入区域的宽度与第一有源区110的宽度相适应。第一场区120可围设于第一有源区110的四周。第一多晶硅栅130设置在第一有源区110上。接触孔142和接触孔144可设置在第一场区120上，且位于第一多晶硅栅130的两端，具体是位于第一多晶硅栅130长度方向的两端。
第一有源区110的宽度需要大于预设宽度值。预设宽度值为半导体器件上的浅沟槽隔离结构台阶高度对半导体器件的多晶硅栅的宽度产生影响时，半导体器件的有源区宽度的临界值。在本实施例中，将宽度大于预设宽度值的有源区定义为大尺寸有源区，而将宽度小于预设宽度值的有源区定义为小尺寸有源区。浅沟槽隔离结构台阶高度会导致淀积在有源区和浅沟槽隔离结构交界处上的多晶硅产生台阶。由于光刻胶的台阶覆盖特性，如图2所示，独立小尺寸有源区(也即宽度小于预设宽度值的有源区)上的多晶硅光刻胶厚度要大于邻近的浅沟槽隔离结构上的光刻胶厚度，这个厚度差异等于浅沟槽隔离结构台阶高度。而在大尺寸有源区(也即宽度大于预设宽度值的有源区)上，如图3所示，光刻胶厚度等于浅沟槽隔离结构上的光刻胶厚度，与 浅沟槽隔离结构台阶高度无关。光刻胶厚度的变化会导致光刻后的光刻胶条宽度发生变化，进而导致制备得到的多晶硅栅的宽度也发生变化，图4为光刻胶厚度对半导体器件的关键尺寸(CD，也即多晶硅栅的宽度)的关系曲线示意图，图4中，横轴为光刻胶厚度，纵轴为关键尺寸，当光刻胶厚度在曲线的波峰或者波谷位置时，厚度对关键尺寸的影响较小，而在其他区域时，则关键尺寸的变化较大，也即当浅沟槽隔离结构台阶高度波动时，由于独立小尺寸有源区的多晶硅栅的宽度会发生变化，则独立小尺寸有源区的光刻胶厚度在曲线的其他区域时，多晶硅栅的宽度的变化就更大。而大尺寸有源区的多晶硅栅的宽度则不会受到影响。
在其中一个实施例中，预设宽度值为3微米。因此，第一有源区110的宽度大于3微米，为大尺寸有源区，故设置在第一有源区110上的第一多晶硅栅130的宽度不会跟随浅沟槽隔离结构台阶高度的变化而变化，也即第一多晶硅栅130的实际宽度与设计宽度相同。第一有源区110的长度越长越好，最小可为20微米。具体地，第一有源区110的宽度为20微米，长度为60微米。
如图1所示，第一多晶硅栅130可设置在第一有源区110的中间位置，并且第一多晶硅栅130的长度方向与第一有源区110的长度方向平行。第一多晶硅栅130的设计宽度与待监控的半导体器件的多晶硅栅的设计宽度相同，也即其设计宽度为待测半导体器件的特征尺寸。在本文所提及的设计宽度均指制备多晶硅栅的设计参数。在其中一个实施例中，第一多晶硅栅130作为电阻条，其两端伸出第一有源区110并延伸至第一场区120内。进一步地，第一多晶硅栅130两端超出第一有源区110的部分长度可相等。第一多晶硅栅130在第一有源区110的长度即为第一有源区110的长度，例如第一多晶硅栅130在第一有源区110的长度为60毫米，代表第一有源区110的长度为60微米。
第一场区120内的接触孔142和第一场区120内的接触孔144用于与金属连线连接，以实现第一电阻结构R1与其他器件的电性连接。接触孔142 与接触孔144结构可相同且对称设置。第二电阻结构R2的结构如图5所示。该第二电阻结构R2包括第二有源区210、第二场区220、第二多晶硅栅230和接触孔242和接触孔244。第二有源区210内进行N型或者P型离子注入。第二有源区210内的N型或者P型离子注入采用非自对准工艺(Non Salicide)来实现，因而第二电阻结构R2为N型或者P型非自对准硅化物电阻。在本实施例中，第二有源区210内注入的离子类型和第一有源区110内注入的离子类型相同，均为N型或者P型离子，从而使得第一有源区110和第二有源区210均为N型或者P型非自对准硅化物电阻。在小尺寸有源区上形成自对准硅化物的厚度均匀性较差，这个厚度对电阻影响很大，从而会使得多晶硅栅宽度对电阻影响的程度降低，不利于分析，因此采用非自对准硅化物电阻可以很好的克服该问题，并且，非自对准硅化物电阻的阻值比较高(如260欧姆)，有利于数据测量，而自对准硅化物阻值较低(如5欧姆)，不便于测量。N型或者P型注入区域的宽度与第二有源区210的宽度相适应。第二场区220围设于第二有源区210的四周。第二场区220的长度与第一场区120的长度相同。第二多晶硅栅230设置在第二有源区210上。接触孔242和接触孔244可设置在第二场区220上，且位于第二多晶硅栅230的两端，具体是位于第二多晶硅栅230长度方向的两端。
第二有源区210的宽度小于预设宽度值，预设宽度值可为3微米。因此，第二有源区210的宽度小于3微米，为小尺寸有源区。故设置在第二有源区210上的第二多晶硅栅230的宽度会跟随浅沟槽隔离结构台阶高度的变化而变化，也即第二多晶硅栅230的实际宽度与设计宽度会存在一定波动。第二有源区210的长度越长越好，最小可为20微米。在一个具体实施例中，第二有源区210的宽度为1微米，长度为60微米。
第二多晶硅栅230可设置于第二有源区210的中间位置，且第二多晶硅栅230的长度方向与第二有源区210的长度方向平行。第二多晶硅栅230的设计尺寸与第一多晶硅栅130的设计尺寸相同，具体是第二多晶硅栅230的设计宽度与第一多晶硅栅130的设计宽度相同，第二多晶硅栅230的设计长 度与第一多晶硅栅130的设计长度相同，从而确保第一电阻结构R1和第二电阻结构R2中，除了有源区的宽度和相应的N型(或者P型)注入区域的宽度不同外，其他因素均相同。在其中一个实施例中，第二多晶硅栅230作为电阻条，其两端伸出第二有源区210并延伸至第二场区220内。进一步地，第二多晶硅栅230两端超出第二有源区210的部分长度相等。第二多晶硅栅230在第二有源区210的长度即为第二有源区210的长度，例如第二多晶硅栅230在第二有源区210的长度为60微米，代表第二有源区110的长度为60微米。在其中一个实施例中，第二多晶硅栅230在第二场区220上的延伸长度与第一多晶硅栅130在第一场区120上的延伸长度相同。在本实施例中，为避免受到寄生电阻的影响，第一电阻结构R1和第二电阻结构R2除了有源区宽度和相应的N型(或者P型)注入区域宽度不同外，其他结构均应该相同。
第二场区220内的接触孔242和第二场区220内的接触孔244用于与金属连线连接，以实现第二电阻结构R2与其他器件的电性连接。接触孔242和接触孔244结构可相同且对称设置。
在其中一个实施例中，第一电阻结构R1、第二电阻结构R2与半导体器件同步制备而成，也即第一有源区110、第二有源区210与半导体器件的有源区是同步制备而成的，第一多晶硅栅130、第二多晶硅栅230与半导体器件的多晶硅栅是同步制备而成的。
第一电阻结构R1和第二电阻结构R2按照预设电路结构进行版图设计并电性连接形成测试电路。测试电路中，第一电阻结构R1所在支路的总电阻和第二电阻结构R2所在支路的总电阻相同，从而使得测试电路中流经每个第一电阻结构R1和第二电阻结构R2上的电流相同。因此，通过对第一电阻结构R1和第二电阻结构R2上的电压差值进行监测即可得到第一电阻结构R1和第二电阻结构R2的阻值差值变化情况。由于第一电阻结构R1和第二电阻结构R2中，除了有源区尺寸和相应的N型(或者P型)注入区域不同外，其他因素完全相同，多晶硅电阻之间的差异由实际制备的多晶硅栅的宽度不同 造成，而多晶硅栅的宽度不同是因为浅沟槽隔离结构台阶高度是变动的，因此，通过监测该电压差值的变化情况，能够监测到浅沟槽隔离结构台阶高度对独立有源区上的多晶硅栅的宽度的影响，从而可以通过调整多晶硅光刻的光刻胶厚度，来减小浅沟槽隔离结构台阶高度对有源区上的多晶硅栅的宽度的影响程度。本实施例中的测试结构还具有结构简单，容易制备，不会增加生产成本和可以缩短生产周期的优点。
在其中一实施例中，可以对硅片上不同位置区域的测试结构进行监测，从而判断测量电压均匀性是否较好。如果均匀性较差，则表明多晶硅栅的宽度容易变化。这个宽度变化是由于多晶硅栅光刻的光刻胶厚度引起的，而这个厚度的变化是由于浅沟槽隔离结构台阶高度变化引起的。因此，根据测试结果即可说明当前使用的光刻胶厚度并不合适，从而可以对半导体器件的多晶硅栅的光刻胶厚度进行调整，调整至最优位置，以减少浅沟槽台阶高度变化导致多晶硅栅的宽度的明显变化，提高产品良率和产品稳定性。也即，本测试结构还可以对光刻工艺的稳定性进行监控。在另一实施例中，除了对同一片硅片上的不同位置的测试结构进行电压监测之外，还可以对不同硅片之间的测试结构的电压测量结果进行比较，或者对不同批次之间的测试结构的电压测试结果进行比较，以根据最终的测试电压的均匀性确定是否需要对光刻胶厚度进行调整，以使得最终得到的半导体器件的多晶硅栅的宽度为目标特征尺寸。
在其中一实施例中，第一电阻结构R1和第二电阻结构R2按照电桥电路电性连接形成测试电路。其连接示意图如图6所示，其电路版图设计如图7所示。该电桥电路中包括两条并联支路。两条并联支路上均并联设置有第一电阻结构R1和第二电阻结构R2。并且，两条并联支路上的两个电阻结构R1和R2的排列顺序相反。两条并联支路两个交汇点作为测试电压施加压点，如图7所示有交汇点J2和交汇点J3，交汇点J2作为测试电压施加压点2，交汇点J3作为测试电压施加压点3。每条并联支路的两个电阻结构R1和R2之间的节点作为测量压点，如图7所示，有节点J1和节点J4，节点J1作为测量 压点1，节点J4作为测量压点4。
在其中一个实施例中，测试电压施加压点和测量压点均通过金属连线与对应的接触孔连接。具体地，如图7所示，该测试结构包括两个第一电阻结构R1，两个第二电阻结构R2，两个第一电阻结构R1分别为左侧的第一电阻结构R1和右侧的第一电阻结构R1，两个第二电阻结构R2分别为左侧的第二电阻结构R2和右侧的第二电阻结构R2，两个第一电阻结构R1均设置了两个接触孔，分别为左接触孔和右接触孔，两个第二电阻结构R2均设置了两个接触孔，分别为左接触孔和右接触孔。测试电压施加压点2通过金属连线320分别与图中左侧的第一电阻结构R1的左接触孔、图中左侧的第二电阻结构R2的左接触孔连接，测试电压施加压点3通过金属连线330分别与图中右侧的第一电阻结构R1上的右接触孔、图中右侧的第二电阻结构R2的右接触孔连接，测量压点1通过金属连线310分别与图中左侧的第二电阻结构R2的右接触孔、图中右侧的第一电阻结构R1的左接触孔连接，测量压点4通过金属连线340分别与图中左侧的第一电阻结构R2的右接触孔、图中右侧的第二电阻结构R2的左接触孔连接。
在本实施例中，为减少实际电路中寄生电阻的影响，需要保证各电路连接节点、金属连线相同且对称设置。也即金属连线320和330的结构(金属连线的宽度和长度)相同且对称设置，并且压点2和压点3同样为相同的结构且对称设置。金属连线310和340的结构相同且对称设置，并且压点2和压点3为相同的结构且对称设置。金属连线310、320、330和340均可以为铝条。在一实施例中，各压点通过第一层金属引出即可。如果无法满足设计需求，则再由通孔和第二层金属引出。
如图7所示，测试过程中，可将电源设备的正极连接在压点2上，将电源设备的负极连接在压点3上，从而对测试电路施加电压以使得测试电路工作。电源设备可以施加0～3V电压。在其他的实施例中，电源设备的施加电压可以根据需要设置。可将电压测量设备的正极连接在压点1上，将电压测量设备的负极连接在压点4上，以实现对第一电阻结构R1和第二电阻结构 R2上的电压差值U 0的监测。其中，U 0的关系式为：
U 0＝[(R1-R2)/(R1+R2)]*U
在实际PCM测量过程中，可以对测试电路施加0～3V的扫描电压，测试对应的U 0，得到的曲线斜率即为(R1-R2)/(R1+R2)。
在这两种电阻结构中，除了有源区的宽度和相应的N型(或者P型)注入区域的宽度不同外，其他因素完全相同，多晶硅电阻之间的差异由实际制备的多晶硅栅的宽度不同造成，而多晶硅栅的宽度不同是因为浅沟槽隔离结构台阶高度是变动的。在浅沟槽隔离结构台阶高度处于正常值时，两种结构的多晶硅电阻因多晶硅宽度的固定差异也有一个固定差值。当浅沟槽隔离结构台阶高度发生波动时，这个差值也会随之波动。因此，通过该差值的变化可以监控浅沟槽隔离结构台阶高度波动对独立小尺寸有源区上的多晶硅宽度的影响，也可以用来评估多晶硅光刻的光刻胶厚度是否合适，也即多晶硅光刻的SWING设置是否处在最优位置。
还提供一种基于上述任一实施例所述的测试结构的半导体器件的测试方法。图8为一实施例中的测试方法的流程图，该方法包括以下步骤：
S810，对测试电路施加电压以使得测试电路工作。
在其中一个实施例中，当第一电阻结构和第二电阻结构按照电桥电路电性连接形成测试电路时，对测试电路施加电压的步骤是对两条并联支路的两个交汇点施加电压。
S820，测量第一电阻结构和第二电阻结构上的电压差值。
在其中一个实施例中，第一电阻结构和第二电阻结构按照电桥电路电性连接形成测试电路(如图6和图7)，测量所述第一电阻结构和所述第二电阻结构上的电压差值的步骤是对每条并联支路的两个电阻结构上的电压差值进行监测。如图6所示，具体可检测节点J1和节点J4两点之间(也即图7中的压点1和压点4之间)的电压差值以实现对第一电阻结构R1和第二电阻结构R2上的电压差值U 0的监测。
如图7所示，测试过程中，将电源设备的正极连接在压点2上，将电源 设备的负极连接在压点3上，从而对测试电路施加电压以使得测试电路工作。电源设备可以施加0～3V电压。在其他的实施例中，电源设备的施加电压可以根据需要设置。将电压测量设备的正极连接在压点1上，将电压测量设备的负极连接在压点4上，以实现对第一电阻结构R1和第二电阻结构R2上的电压差值U 0的监测。其中，U 0的关系式为：
U 0＝[(R1-R2)/(R1+R2)]*U
在实际PCM测量过程中，可以对测试电路施加0～3V的扫描电压，测试对应的U 0，得到的曲线斜率即为(R1-R2)/(R1+R2)。
在其中一实施例中，可以先分别测量第一电阻结构和第二电阻结构上的电压值，然后二者做差得到两个电阻结构上的电压差值。S830，根据电压差值的变化监控浅沟槽隔离结构台阶高度对多晶硅栅的宽度影响情况。
可以将同一硅片的不同测试结构上的电压差值的变压进行比较，也可以将不同硅片上的测试结构的电压差值进行比较或者对不同批次的测试结构的电压差值进行比较来监控浅沟槽隔离结构台阶高度对多晶硅栅的宽度的影响情况。
通过该电压差值的变化情况能够监测到浅沟槽隔离结构台阶高度对独立有源区上的多晶硅栅的宽度的影响，从而可以通过调整多晶硅光刻的光刻胶厚度来减小浅沟槽隔离结构台阶高度对有源区上的多晶硅栅的宽度的影响程度，以使得最终得到的半导体器件的多晶硅栅的宽度为目标特征尺寸。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围 应以所附权利要求为准。

Claims (19)

  1. 一种半导体器件的测试结构，包括：
    第一电阻结构，包括第一有源区和设置在所述第一有源区上的第一多晶硅栅；所述第一有源区的宽度大于预设宽度值；所述预设宽度值为所述半导体器件的浅沟槽隔离结构的台阶高度对所述半导体器件的多晶硅栅的宽度产生影响时，所述半导体器件的有源区宽度的临界值；所述第一多晶硅栅的设计宽度与所述半导体器件的多晶硅栅的设计宽度相同；以及
    第二电阻结构，与所述第一电阻结构按预设电路结构电性连接从而形成测试电路，所述第二电阻结构包括第二有源区和设置在所述第二有源区上的第二多晶硅栅；所述第二有源区的宽度小于所述预设宽度值；所述第二多晶硅栅的设计尺寸与所述第一多晶硅栅的设计尺寸相同；所述第二电阻结构所在支路的总电阻和所述第一电阻结构所在支路的总电阻相等。
  2. 根据权利要求1所述的测试结构，其特征在于，所述预设电路结构为电桥电路；所述电桥电路包括两条并联支路；每一条并联支路上均串联设置所述第一电阻结构和所述第二电阻结构；两条并联支路上的两个电阻结构的排列顺序相反；两条并联支路的两个交汇点作为测试电压施加压点，用于对测试电路施加电压；每条并联支路的两个电阻结构之间的节点作为测量压点，用于对并联支路的两个电阻结构上的电压差值进行监测。
  3. 根据权利要求2所述的测试结构，其特征在于，两个所述测试电压施加压点的结构相同且对称设置；两个所述测量压点的结构相同且对称设置。
  4. 根据权利要求2所述的测试结构，其特征在于，所述第一电阻结构还包括围设于所述第一有源区四周的第一场区，所述第二电阻结构还包括围设于所述第二有源区四周的第二场区；所述第一多晶硅栅延伸至所述第一场区的长度和所述第二多晶硅栅延伸至所述第二场区的长度相同。
  5. 根据权利要求4所述的测试结构，其特征在于，所述第一场区和所述第二场区内均设置有接触孔；
    所述测试电压施加压点和所述测量压点均通过金属连线与对应的接触孔 连接。
  6. 根据权利要求5所述的测试结构，其特征在于，所述第一场区的接触孔位于第一多晶硅栅长度方向的两端；
    所述第二场区的接触孔位于第二多晶硅栅长度方向的两端。
  7. 根据权利要求5所述的测试结构，其特征在于，两个所述测试电压施加压点与对应的接触孔之间的金属连线的结构相同且对称设置；两个所述测量压点与对应的接触孔之间的金属连线的结构相同且对称设置。
  8. 根据权利要求1所述的测试结构，其特征在于，所述预设宽度值为3微米。
  9. 根据权利要求8所述的测试结构，其特征在于，所述第一有源区的宽度为20微米，所述第二有源区的宽度为1微米。
  10. 根据权利要求4所述的测试结构，其特征在于，所述第一多晶硅栅的两端伸出所述第一有源区并延伸至所述第一场区内，所述第一多晶硅栅两端超出所述第一有源区的部分长度相等；
    所述第二多晶硅栅的两端伸出所述第二有源区并延伸至所述第二场区内，所述第二多晶硅栅两端超出所述第二有源区的部分长度相等。
  11. 根据权利要求1所述的测试结构，其特征在于，所述第一有源区的长度与所述第二有源区的长度相同。
  12. 根据权利要求1所述的测试结构，其特征在于，所述第一有源区的长度为20微米以上，所述第二有源区的长度为20微米以上。
  13. 根据权利要求4所述的测试结构，其特征在于，所述第一场区的长度与所述第二场区的长度相同。
  14. 根据权利要求1所述的测试结构，其特征在于，所述第一多晶硅栅设置在所述第一有源区的中间位置，所述第一多晶硅栅的长度方向与所述第一有源区的长度方向平行；
    所述第二多晶硅栅设置在所述第二有源区的中间位置，所述第二多晶硅栅的长度方向与所述第二有源区的长度方向平行。
  15. 根据权利要求1所述的测试结构，其特征在于，所述第一电阻结构和所述第二电阻结构均为N型或者P型非自对准硅化物电阻。
  16. 根据权利要求1所述的测试结构，其特征在于，所述测试结构设置于硅片的划片槽区域。
  17. 一种基于半导体器件的测试结构的测试方法，所述测试结构包括：第一电阻结构，包括第一有源区和设置在所述第一有源区上的第一多晶硅栅；所述第一有源区的宽度大于预设宽度值；所述预设宽度值为所述半导体器件的浅沟槽隔离结构的台阶高度对所述半导体器件的多晶硅栅的宽度产生影响时，所述半导体器件的有源区宽度的临界值；所述第一多晶硅栅的设计宽度与所述半导体器件的多晶硅栅的设计宽度相同；以及
    第二电阻结构，与所述第一电阻结构按预设电路结构电性连接从而形成测试电路，所述第二电阻结构包括第二有源区和设置在所述第二有源区上的第二多晶硅栅；所述第二有源区的宽度小于所述预设宽度值；所述第二多晶硅栅的设计尺寸与所述第一多晶硅栅的设计尺寸相同；所述第二电阻结构所在支路的总电阻和所述第一电阻结构所在支路的总电阻相等；
    所述测试方法包括以下步骤：
    对所述测试电路施加电压以使得所述测试电路工作；
    测量所述第一电阻结构和所述第二电阻结构上的电压差值；以及
    根据所述电压差值的变化监控浅沟槽隔离结构台阶高度对多晶硅栅的宽度的影响情况。
  18. 根据权利要求17所述的测试方法，其特征在于，所述预设电路结构为电桥电路；所述电桥电路包括两条并联支路，每一条并联支路上均串联设置所述第一电阻结构和所述第二电阻结构，两条并联支路上的两个电阻结构的排列顺序相反，所述对所述测试电路施加电压的步骤是对所述两条并联支路的两个交汇点施加电压，所述测量所述第一电阻结构和所述第二电阻结构上的电压差值的步骤是对每条并联支路的两个电阻结构上的电压差值进行监测。
  19. 根据权利要求17所述的测试方法，其特征在于，对所述测试电路施加的电压范围为0V～3V。
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