WO2018120583A1 - 一种显示面板和显示装置 - Google Patents

一种显示面板和显示装置 Download PDF

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Publication number
WO2018120583A1
WO2018120583A1 PCT/CN2017/084125 CN2017084125W WO2018120583A1 WO 2018120583 A1 WO2018120583 A1 WO 2018120583A1 CN 2017084125 W CN2017084125 W CN 2017084125W WO 2018120583 A1 WO2018120583 A1 WO 2018120583A1
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Prior art keywords
layer
wire segment
dielectric constant
sub
silicon
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PCT/CN2017/084125
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English (en)
French (fr)
Inventor
卓恩宗
樊堃
田轶群
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惠科股份有限公司
重庆惠科金渝光电科技有限公司
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Priority to US15/869,136 priority Critical patent/US10355030B2/en
Publication of WO2018120583A1 publication Critical patent/WO2018120583A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks

Definitions

  • the present application relates to the field of display technologies, and more particularly to a display panel and a display device.
  • the display has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • Most of the displays on the market today are backlight-type displays, which include a display panel and a backlight module.
  • the working principle of the display panel is to place liquid crystal molecules in two parallel substrates, and apply driving voltages on the two substrates to control the rotation direction of the liquid crystal molecules to refract the light of the backlight module to generate a picture.
  • the thin film transistor display includes a display panel and a backlight module, and the display panel includes a color filter substrate (CF Substrate, also referred to as a color filter substrate) and a thin film transistor array substrate (Thin Film Transistor Substrate, TFT Substrate).
  • CF Substrate also referred to as a color filter substrate
  • TFT Substrate thin film transistor array substrate
  • a transparent electrode exists on the opposite inner side of the substrate.
  • a layer of liquid crystal molecules (LC) is sandwiched between the two substrates.
  • the display panel controls the orientation of the liquid crystal molecules by an electric field, changes the polarization state of the light, and achieves the purpose of display by the penetration and blocking of the optical path by the polarizing plate.
  • the package density of devices continues to increase, so the performance requirements for various aspects of materials continue to increase. Due to the shrinkage of the device, the thickness of the gate oxide insulating layer of the device is very thin. For devices with a small proportion, the thickness of the gate oxide insulating layer will only become thinner and thinner, which requires a new high-K gate oxide insulation. Dielectric material.
  • the technical problem to be solved by the present application is to provide a display panel and a display device having a large dielectric constant of an insulating dielectric layer.
  • a display panel comprising:
  • An insulating dielectric layer disposed on the plurality of first layer conductors, the dielectric constant of the insulating dielectric layer being greater than a dielectric constant of the silicon oxide layer and the silicon nitride layer, the insulating dielectric layer including the composition
  • the composition includes a first composition and a second composition.
  • the first composition comprises nanoporous silicon.
  • Nanoporous silicon can be made very thin, can reduce the thickness of the insulating dielectric layer, and can meet the ever-decreasing requirements of integrated circuits, chips, and LCDs.
  • the nanoporous silicon itself is hydrophobic.
  • the second composition comprises ruthenium nanoparticles.
  • the dielectric constant of germanium is 16, and the dielectric constant of the dielectric layer is increased by adjusting the proportion of germanium.
  • other metals and other materials having a high dielectric constant can also be used.
  • the first composition comprises nanoporous silicon and the second composition comprises ruthenium nanoparticles.
  • Nanoporous silicon can be made very thin, can reduce the thickness of the insulating dielectric layer, can meet the continuous reduction of the size of integrated circuits, chips and LCDs.
  • the nanoporous silicon itself has hydrophobicity, and the dielectric constant of germanium is 16, nanoporous silicon itself has a lot of silicon pores, bismuth nanoparticles can be stored in the silicon pores, does not increase the thickness of the nanoporous silicon, by adjusting the loading of yttrium nanoparticles Ge to achieve a controllable adjustment of the dielectric constant.
  • the insulating dielectric layer comprises nanoporous silicon
  • the nanoporous silicon comprises a plurality of hollow columnar sub-assemblies connected to each other, the sub-assembly has a hexagonal shape, and the sub-assembly has a circular through-hole therebetween.
  • a plurality of silicon holes are disposed in the circular through hole of the subassembly, and the silicon holes are provided with germanium nanoparticles.
  • the hexagonal shape of the porous component of the porous silicon facilitates the splicing arrangement of a plurality of sub-assemblies, and a plurality of bismuth nanoparticles are disposed in the silicon holes, which does not affect the thickness of the porous silicon.
  • the corresponding gate wire segment on the insulating dielectric layer is provided with an amorphous silicon layer, and the amorphous silicon layer is provided with an ohmic contact layer corresponding to the amorphous silicon layer, and the ohmic contact layer is provided with a separation layer.
  • Source wire segment And a drain wire segment a channel is disposed between the source wire segment and the drain wire segment, the channel passes through an ohmic contact layer, the bottom of the channel is an amorphous silicon layer, and the source wire
  • the width of the segment and drain wire segments is greater than the width of the amorphous silicon layer
  • the source wire segment and the drain wire segment are provided with a second insulating layer
  • the second insulating layer is provided with a pixel electrode layer
  • the second insulating layer is provided with a via hole corresponding to the drain wire segment
  • the pixel electrode layer is connected to the drain wire segment through the via hole.
  • TFT thin film transistor
  • the corresponding gate wire segment on the insulating dielectric layer is provided with an amorphous silicon layer
  • the amorphous silicon layer is provided with an ohmic contact layer corresponding to the amorphous silicon layer
  • the ohmic contact layer is provided with a separation layer.
  • a source wire segment and a drain wire segment a channel is disposed between the source wire segment and the drain wire segment, the channel passes through the ohmic contact layer, and the bottom of the channel is an amorphous silicon layer.
  • the width of the source wire segment and the drain wire segment are equal to the width of the ohmic contact layer in contact therewith, the source wire segment and the drain wire segment are provided with a second insulating layer, and the second insulating layer is provided with a pixel And an electrode layer, wherein the second insulating layer is provided with a via hole corresponding to the drain wire segment, and the pixel electrode layer is connected to the drain wire segment through the via hole.
  • the relative dielectric constant of the second insulating layer is smaller than the relative dielectric constant of silicon nitride and silicon oxide.
  • the use of a low dielectric constant protection layer can improve the performance of thin film transistor TFT devices, improve signal crosstalk problems and RC circuit delay problems.
  • the low dielectric constant protective layer comprises mesoporous silica
  • the thickness of the dielectric constant protective layer of course, the low dielectric constant protective layer may also be other low dielectric constant materials such as nanoporous silicon.
  • the mesoporous silica comprises a plurality of subunits, the subunits comprising subarrays arranged in three rows
  • the middle row of the subunit includes three subcomponents side by side
  • the first row and the third row of the subunit respectively include two subcomponents side by side
  • the two subcomponents of the first row and the third row respectively Arranged between any two sub-components of a row of three sub-components having a hexagonal shape with a circular through-hole in the middle.
  • the subunit has the sub-components arranged in an orderly manner, has a high specific surface area, good thermal stability and hydrothermal stability, uniform size of the through-hole of the sub-component, and the hexagonal shape of the sub-component is convenient for splicing of the plurality of sub-components. arrangement.
  • the dielectric constant of the insulating dielectric layer disposed on the first layer of wires is greater than the dielectric constant of the silicon oxide layer and the silicon nitride layer, increasing the ability of the device to store charge, the insulating dielectric layer comprising the composition, the composition comprising the first composition and the first
  • the second composition the dielectric constant of the first composition is smaller than the dielectric constant of the silicon oxide layer and the silicon nitride layer, and the dielectric constant of the second composition is greater than the dielectric constant of the silicon oxide layer and the silicon nitride layer,
  • the ratio of the first composition to the second composition is such that the dielectric constant of the insulating dielectric layer is adjustable.
  • FIG. 1 is a schematic diagram of a 5-channel TFT device according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a 4-channel TFT device according to an embodiment of the present application.
  • FIG. 3 is another schematic diagram of a 5-channel TFT device according to an embodiment of the present application.
  • FIG. 4 is a schematic view of a nanoporous silicon according to an embodiment of the present application.
  • FIG. 5 is a schematic view of nanoporous silicon and germanium nanoparticles of an embodiment of the present application.
  • FIG. 6 is a schematic view of mesoporous silica according to an embodiment of the present application.
  • FIG. 7 is a schematic view showing a process for preparing mesoporous silica by an organic molecular template self-assembly method according to an embodiment of the present application
  • FIG. 8 is a schematic diagram of a dielectric constant test of an embodiment of the present application.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, features defining “first” and “second” may include one or more of the features either explicitly or implicitly.
  • a plurality means two or more unless otherwise stated.
  • the term “comprises” and its variations are intended to cover a non-exclusive inclusion.
  • connection In the description of the present application, it should be noted that the terms “installation”, “connected”, and “connected” are to be understood broadly, and may be fixed or detachable, for example, unless otherwise specifically defined and defined. Connected, or integrally connected; can be mechanical or electrical; can be directly connected, or indirectly connected through an intermediate medium, can be the internal communication of the two components.
  • Connected, or integrally connected can be mechanical or electrical; can be directly connected, or indirectly connected through an intermediate medium, can be the internal communication of the two components.
  • the specific meanings of the above terms in the present application can be understood in the specific circumstances for those skilled in the art.
  • a display panel of an embodiment of the present application will be described below with reference to FIGS. 1 through 8.
  • the display panel includes a substrate 10 , and the substrate 10 is provided with a plurality of first layers of wires 21 , and the first layer of wires 21 is provided with an insulating dielectric layer 22 .
  • the insulating dielectric layer 22 is made of silicon nitride or silicon oxide, and the gate wiring segment 211 of the insulating dielectric layer 22 corresponding to the first conductive layer 21 is provided with an amorphous silicon layer 23, and the amorphous silicon layer 23 is provided thereon.
  • the width of the silicon layer 23, the source wire segment 25 and the drain wire segment 26 are provided with a protective layer 30.
  • the protective layer 30 is provided with a pixel electrode layer 50, and the protective layer 30 corresponds to the drain wire segment 26.
  • a via hole 28 is provided, and the pixel electrode layer 50 is connected to the drain wire segment 26 through the via 28 .
  • the source wire segment 25 is directly connected to the other side of the insulating dielectric layer 22 on the side of the amorphous silicon layer 23, and directly connected to the protective layer 30.
  • the insulating dielectric layer 22 corresponds to the via 28 portion and the drain wire segment 26. Connected between. Thin film transistor TFTs obtained using 5Mask have better performance.
  • the display panel includes a substrate 10, and the substrate 10 is provided with a plurality of first layers of wires 21, and the first layer of wires 21 is provided with an insulating dielectric layer 22,
  • the insulating dielectric layer 22 is made of silicon nitride or silicon oxide, and the gate wiring segment 211 of the insulating dielectric layer 22 corresponding to the first conductive layer 21 is provided with an amorphous silicon layer 23, and the amorphous silicon layer 23 is provided thereon.
  • a protective layer 30 is disposed on the source wire segment 25 and the drain wire segment 26, and the pixel layer 50 is disposed on the protective layer 30. The protective layer 30 is disposed corresponding to the drain wire segment 26.
  • the protective layer 30 outside the source wire segment 25 is directly connected to the insulating dielectric layer 22, and the insulating dielectric layer An amorphous silicon layer 23, an ohmic contact layer 24, and a drain wire segment 26 are sequentially disposed above the corresponding via holes 28.
  • Thin film transistor TFTs obtained using 4Mask have better performance and can save one-step Mask process.
  • the thickness of the gate oxide insulating layer of the device Due to advances in processes and designs, the size of integrated circuits, chips, and TFT-LCDs continues to decrease, and the package density of devices continues to increase, so the performance requirements for all aspects of materials continue to increase. Due to the shrinkage of the device, the thickness of the gate oxide insulating layer of the device has become very thin. For devices with a small proportion in the future, the thickness of the gate oxide insulating layer will only become thinner and thinner, which requires a new high-K gate oxide. Insulating dielectric material. In the above embodiment, a four-pass process or a five-process TFT-Array array is used. In the TFT transistor, a high voltage exists between the gate dielectric and the upper insulating protective layer. The gate oxide layer is affected by the tunneling current.
  • the display panel comprises: a substrate 10; a plurality of first layer wires 21, and the plurality of first layer wires 21 are disposed. On the substrate 10; an insulating dielectric layer 22, the insulating dielectric layer 22 is disposed on a plurality of first layer wires 21 having a dielectric constant greater than a dielectric constant of the silicon oxide layer and the silicon nitride layer
  • the insulating dielectric layer 22 includes a composition including a first composition and a second composition.
  • the dielectric constant of the insulating dielectric layer 22 disposed on the first layer of wires 21 is greater than the dielectric constant of the silicon oxide layer and the silicon nitride layer to increase the device's ability to store charge.
  • the insulating dielectric layer 22 includes a composition including the first composition. And a second composition, the dielectric constant of the first composition is smaller than the dielectric constant of the silicon oxide layer and the silicon nitride layer, and the dielectric constant of the second composition is greater than the dielectric constant of the silicon oxide layer and the silicon nitride layer
  • the dielectric constant of the insulating dielectric layer 22 is adjusted by adjusting the ratio of the first composition and the second composition.
  • the first composition comprises nanoporous silicon.
  • Nanoporous silicon can be made very thin, can reduce the thickness of the insulating dielectric layer, and can meet the ever-decreasing requirements of integrated circuits, chips, and TFT-LCDs.
  • the nanoporous silicon itself is hydrophobic.
  • the second composition comprises ruthenium nanoparticles.
  • the dielectric constant of germanium is 16, and the dielectric constant of the insulating dielectric layer 22 is increased by adjusting the proportion of germanium.
  • other metals and other materials having a high dielectric constant can be used.
  • the first composition comprises nanoporous silicon and the second composition comprises ruthenium nanoparticles.
  • Nanoporous silicon can be made very thin, which can reduce the thickness of the insulating dielectric layer, and can meet the ever-decreasing requirements of integrated circuits, chips, and TFT-LCDs.
  • the nanoporous silicon itself has hydrophobicity and ⁇ dielectric.
  • the constant is 16, the nanoporous silicon itself has many silicon pores, and the ruthenium nanoparticles can be stored in the silicon pores without increasing the thickness of the nanoporous silicon, and the dielectric constant can be controlled by adjusting the loading amount of the ruthenium nanoparticles Ge.
  • the insulating dielectric layer 22 comprises nanoporous silicon
  • the nanoporous silicon comprises a plurality of hollow columnar sub-assemblies 221 connected to each other, the sub-assembly 221 has a hexagonal shape, and the sub-assembly 221 has a circle in the middle.
  • a through hole is formed in the circular through hole of the sub-assembly 221, and a plurality of silicon holes are disposed, and the silicon holes are provided with germanium nanoparticles.
  • the porous component 221 of the porous silicon facilitates the splicing arrangement of the plurality of sub-assemblies 221, and the plurality of germanium nanoparticles are disposed in the silicon holes, which does not affect the thickness of the porous silicon.
  • the corresponding gate wire segment 211 of the insulating dielectric layer 22 is provided with an amorphous silicon layer 23, and the amorphous silicon layer 23 is provided with an ohmic contact layer 24 corresponding to the amorphous silicon layer 23, and the ohmic contact
  • the layer 24 is provided with a separated source wire segment 25 and a drain wire segment 26.
  • a channel 27 is disposed between the source wire segment 25 and the drain wire segment 26, and the channel 27 passes through the ohmic contact layer.
  • the bottom of the channel 27 is an amorphous silicon layer 23
  • the width of the source wire segment 25 and the drain wire segment 26 is greater than the width of the amorphous silicon layer 23
  • a second insulating layer 30 is disposed on the second insulating layer 30.
  • the second insulating layer 30 is provided with a pixel electrode layer 50.
  • the second insulating layer 30 is provided with a via hole 28 corresponding to the drain wire segment 26, and the pixel electrode layer 50 is provided. It is connected to the drain wire segment 26 via a via 28 .
  • the source wire segment 25 is directly connected to the other side of the insulating dielectric layer 22 on the other side of the amorphous silicon layer 23, and is directly connected to the low dielectric constant protective layer 40.
  • the insulating dielectric layer 22 corresponds to the via 28 portion and the drain.
  • the pole segments 26 are connected to each other.
  • a thin film transistor TFT with better performance can be obtained using 5Mask.
  • the display panel comprises: a plurality of first layer conductors 21 disposed on the substrate 10; an insulating dielectric layer 22 disposed on the plurality of first layer conductors 21,
  • the dielectric constant of the insulating dielectric layer 22 is greater than the dielectric constant of the silicon oxide layer and the silicon nitride layer, and the insulating dielectric layer 22 includes a composition including the first composition and the second composition.
  • the dielectric constant of the insulating dielectric layer 22 disposed on the first layer of wires 21 is greater than the dielectric constant of the silicon oxide layer and the silicon nitride layer to increase the device's ability to store charge.
  • the insulating dielectric layer 22 includes a composition including the first composition. And a second composition, the dielectric constant of the first composition is smaller than the dielectric constant of the silicon oxide layer and the silicon nitride layer, and the dielectric constant of the second composition is greater than the dielectric constant of the silicon oxide layer and the silicon nitride layer
  • the dielectric constant of the insulating dielectric layer 22 is adjusted by adjusting the ratio of the first composition and the second composition.
  • the first composition comprises nanoporous silicon.
  • Nanoporous silicon can be made very thin, can reduce the thickness of the insulating dielectric layer, and can meet the ever-decreasing requirements of integrated circuits, chips, and TFT-LCDs.
  • the nanoporous silicon itself is hydrophobic.
  • the second composition comprises ruthenium nanoparticles.
  • the dielectric constant of germanium is 16, and the dielectric constant of the insulating dielectric layer 22 is increased by adjusting the proportion of germanium.
  • other metals and other materials having a high dielectric constant can be used.
  • the first composition comprises nanoporous silicon and the second composition comprises ruthenium nanoparticles.
  • Nanoporous silicon can be made very thin, which can reduce the thickness of the insulating dielectric layer, and can meet the ever-decreasing requirements of integrated circuits, chips, and TFT-LCDs.
  • the nanoporous silicon itself has hydrophobicity and ⁇ dielectric.
  • the constant is 16, the nanoporous silicon itself has many silicon pores, and the ruthenium nanoparticles can be stored in the silicon pores without increasing the thickness of the nanoporous silicon, and the dielectric constant can be controlled by adjusting the loading amount of the ruthenium nanoparticles Ge.
  • the insulating dielectric layer 22 comprises nanoporous silicon
  • the nanoporous silicon comprises a plurality of hollow columnar sub-assemblies 221 connected to each other, the sub-assembly 221 has a hexagonal shape, and the sub-assembly 221 has a circle in the middle.
  • a through hole is formed in the circular through hole of the sub-assembly 221, and a plurality of silicon holes are disposed, and the silicon holes are provided with germanium nanoparticles.
  • the porous component 221 of the porous silicon facilitates the splicing arrangement of the plurality of sub-assemblies 221, and the plurality of germanium nanoparticles are disposed in the silicon holes, which does not affect the thickness of the porous silicon.
  • the corresponding gate wire segment 211 of the insulating dielectric layer 22 is provided with an amorphous silicon layer 23, and the amorphous silicon layer 23 is provided with an ohmic contact layer 24 corresponding to the amorphous silicon layer 23, and the ohmic contact
  • the layer 24 is provided with a separated source wire segment 25 and a drain wire segment 26.
  • a channel 27 is disposed between the source wire segment 25 and the drain wire segment 26, and the channel 27 passes through the ohmic contact layer.
  • the bottom of the channel 27 is an amorphous silicon layer 23
  • the source wire segment 25 and the drain wire segment 26 have a width equal to the width of the ohmic contact layer 24 in contact therewith, the source wire segment 25 and the drain
  • a second insulating layer 30 is disposed on the wire segment 26, and a pixel electrode layer 50 is disposed on the second insulating layer 30.
  • the second insulating layer 30 is provided with a via hole 28 corresponding to the drain wire segment 26, and the pixel electrode Layer 50 is connected to drain wire segment 26 via via 28 .
  • the low dielectric constant protective layer 40 on the outer side of the source wire segment 25 is directly connected to the insulating dielectric layer 22, and the insulating dielectric layer 22 is sequentially provided with an amorphous silicon layer 23 and an ohmic contact layer 24 corresponding to the via hole 28. And drain wire segment 26.
  • 4Mask can get better performance of thin film transistor TFT, and save one step of Mask.
  • the display panel comprises: a substrate 10; a plurality of first layer wires 21, and the plurality of first layer wires 21 are arranged. On the substrate 10; an insulating dielectric layer 22, the insulating dielectric layer 22 is disposed on a plurality of first layer wires 21 having a dielectric constant greater than a dielectric constant of the silicon oxide layer and the silicon nitride layer
  • the insulating dielectric layer 22 includes a composition including a first composition and a second composition.
  • the relative dielectric constant of the second insulating layer 30 is smaller than the relative dielectric constant of silicon nitride and silicon oxide.
  • the use of a low dielectric constant protection layer can improve the performance of thin film transistor TFT devices, improve signal crosstalk problems and RC circuit delay problems.
  • the corresponding gate wire segment 211 of the insulating dielectric layer 22 is provided with an amorphous silicon layer 23, and the amorphous silicon layer 23 is provided with an ohmic contact layer 24 corresponding to the amorphous silicon layer 23,
  • the ohmic contact layer 24 is provided with a separated source wire segment 25 and a drain wire segment 26, and a channel 27 is disposed between the source wire segment 25 and the drain wire segment 26, and the channel 27 is worn.
  • the bottom of the channel 27 is an amorphous silicon layer 23
  • the source wire segment 25 and the drain wire segment 26 are wider than the width of the amorphous silicon layer 23
  • the source wire segment 25 and A second insulating layer 30 is disposed on the drain wire segment 26, and a pixel electrode layer 50 is disposed on the second insulating layer 30.
  • the second insulating layer 30 is provided with a via hole corresponding to the drain wire segment 26. 28.
  • the pixel electrode layer 50 is connected to the drain wire segment 26 through the via 28 .
  • the source wire segment 25 is directly connected to the other side of the insulating dielectric layer 22 on the other side of the amorphous silicon layer 23, and is directly connected to the low dielectric constant protective layer, and the insulating dielectric layer 22 corresponds to the via 28 portion and the drain.
  • the wire segments 26 are connected to each other.
  • the corresponding gate wire segment 211 of the insulating dielectric layer 22 is provided with an amorphous silicon layer 23, and the amorphous silicon layer 23 is provided with an ohmic contact layer 24 corresponding to the amorphous silicon layer 23,
  • the ohmic contact layer 24 is provided with a separated source wire segment 25 and a drain wire segment 26, and a channel 27 is disposed between the source wire segment 25 and the drain wire segment 26, and the channel 27 is worn.
  • the bottom of the channel 27 is an amorphous silicon layer 23, the source wire segment 25 and the drain wire segment 26 having a width equal to the width of the ohmic contact layer 24 in contact therewith, the source wire segment A second insulating layer 30 is disposed on the drain wire segment 26, and a pixel electrode layer 50 is disposed on the second insulating layer 30.
  • the second insulating layer 30 is provided with a via 28 corresponding to the drain wire segment 26.
  • the pixel electrode layer 50 is connected to the drain wire segment 26 through a via 28 .
  • the low dielectric constant protective layer on the outer side of the source wire segment 25 is directly connected to the insulating dielectric layer 22, and the insulating dielectric layer 22 is sequentially provided with an amorphous silicon layer 23, an ohmic contact layer 24, and a top portion of the via hole 28. Drain wire segment 26.
  • the low dielectric constant protective layer comprises mesoporous silicon oxide.
  • the thickness of the dielectric constant protective layer of course, the low dielectric constant protective layer may also be other low dielectric constant materials such as nanoporous silicon.
  • the mesoporous silica comprises a plurality of sub-units 43 comprising sub-components 42 arranged in three rows, the middle row of the sub-units 43 comprising three sub-components 42 arranged side by side, the sub-unit 43
  • the first row and the third row respectively include two sub-components 42 side by side, and the two sub-components 42 of the first row and the third row are respectively disposed between any two sub-components 42 of the middle row of three sub-components 42.
  • the sub-member 42 has a hexagonal shape and a circular through hole in the middle of the sub-assembly 42.
  • the subunit 43 has a regularly arranged sub-assembly 42 having a high specific surface area, good thermal stability and hydrothermal stability.
  • the sub-port 42 has a uniform through-hole size, and the sub-member 42 has a hexagonal shape, which facilitates the splicing of the plurality of sub-assemblies 42.
  • setting a low dielectric constant protective layer having a relative dielectric constant smaller than that of silicon nitride on an active switch includes:
  • the micelle rods are arranged in a hexagon to form a hexagonal micelle rod
  • the middle portion of the silicon oxide template is burned to remove the template to form mesoporous silica
  • the mesoporous silica is formed into a low dielectric constant protective layer.
  • Relative dielectric constant ⁇ r 7 ⁇ 8
  • the mesoporous silica has a low dielectric constant and is stable, and changes little with time.
  • the amorphous silicon layer is made of an a-Si material, and of course other semiconductor layer materials may be used.
  • the material of the substrate may be glass, plastic or the like.
  • the display panel includes a liquid crystal panel, an OLED panel, a QLED panel, a curved panel, a plasma panel, and the like.
  • the liquid crystal panel includes an array substrate and a color filter substrate (CF), and the array substrate and the color
  • the film substrate is oppositely disposed, and a liquid crystal and a photo spacer (PS) are disposed between the array substrate and the color filter substrate, and a thin film transistor (TFT) is disposed on the array substrate, and color filter is disposed on the color filter substrate.
  • PS liquid crystal and a photo spacer
  • TFT thin film transistor
  • the color filter substrate may include a TFT array
  • the color film and the TFT array may be formed on the same substrate, and the array may substantially include a color filter layer.
  • the display panel of the present application may be a curved type panel.

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Abstract

一种显示面板和显示装置。显示面板包括：基板（10）；若干条第一层导线（21），若干条第一层导线设置在基板上；绝缘介质层（22），绝缘介质层设置在若干条第一层导线上，绝缘介质层的介电常数大于氧化硅层和氮化硅层的介电常数，绝缘介质层包括组合物，组合物包括第一组成物和第二组成物，第一组成物的介电常数小于氧化硅层和氮化硅层的介电常数，第二组成物的介电常数大于氧化硅层和氮化硅层的介电常数。

Description

一种显示面板和显示装置 【技术领域】
本申请涉及显示技术领域，更具体的说，涉及一种显示面板和显示装置。
【背景技术】
显示器具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有市场上的显示器大部分为背光型显示器，其包括显示面板及背光模组(backlight module)。显示面板的工作原理是在两片平行的基板当中放置液晶分子，并在两片基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
其中，薄膜晶体管显示器(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)由于具有低的功耗、优异的画面品质以及较高的生产良率等性能，目前已经逐渐占据了显示领域的主导地位。同样，薄膜晶体管显示器包含显示面板和背光模组，显示面板包括彩膜基板(Color Filter Substrate，CF Substrate，也称彩色滤光片基板)和薄膜晶体管阵列基板(Thin Film Transistor Substrate，TFT Substrate)，上述基板的相对内侧存在透明电极。两片基板之间夹一层液晶分子(Liquid Crystal，LC)。显示面板是通过电场对液晶分子取向的控制，改变光的偏振状态，并藉由偏光板实现光路的穿透与阻挡，实现显示的目的。
由于集成电路、芯片以及TFT-LCD的尺寸不断的减小，器件的封装密度不停的增大，因此对材料各方面性能的要求不断的提高。由于器件的比例缩小，目前器件的栅氧绝缘层厚度变得非常薄，对于比例小的器件而言，栅氧绝缘层厚度只会越来越薄，这需要有新的高K的栅氧绝缘介电材料。
【发明内容】
本申请所要解决的技术问题是提供一种绝缘介质层的介电常数大的显示面板和显示装置。
本申请的目的是通过以下技术方案来实现的：
一种显示面板，包括：
基板；
若干条第一层导线，所述若干条第一层导线设置在基板上；
绝缘介质层，所述绝缘介质层设置在若干条第一层导线上，所述绝缘介质层的介电常数大于氧化硅层和氮化硅层的介电常数，所述绝缘介质层包括组合物，所述组合物包括第一组成物和第二组成物。
其中，所述第一组成物包括纳米多孔硅。
纳米多孔硅可以做的非常薄，可以减小绝缘介电层的厚度，可以满足集成电路、芯片以及LCD的尺寸不断的减小的需求，纳米多孔硅本身具有疏水性。
其中，所述第二组成物包括锗纳米颗粒。
锗的介电常数为16，通过调节锗的比例提高绝缘介质层的介电常数，当然也可以采用其他介电常数高的金属和其他材料。
其中，所述第一组成物包括纳米多孔硅，所述第二组成物包括锗纳米颗粒。
纳米多孔硅可以做的非常薄，可以减小绝缘介电层的厚度，可以满足集成电路、芯片以及LCD的尺寸不断的减小的需求，纳米多孔硅本身具有疏水性，锗的介电常数为16，纳米多孔硅本身具有很多硅孔，锗纳米颗粒可以存入硅孔内，不会增加通过纳米多孔硅的厚度，通过调节锗纳米颗粒Ge的负载量实现介电系数可控调节。
其中，所述绝缘介质层包括纳米多孔硅，所述纳米多孔硅包括多个彼此连接的空心柱状的子组件，所述子组件切面为六边形，所述子组件中间具有圆形通孔，所述子组件的圆形通孔上设有多个硅孔，所述硅孔内设有锗纳米颗粒。
多孔硅的子组件切面六边形方便多个子组件拼接排列，硅孔内设有多个锗纳米颗粒，不影响多孔硅厚度。
其中，所述绝缘介质层上对应栅极导线段设有非晶硅层，所述非晶硅层上设有与非晶硅层对应的欧姆接触层，所述欧姆接触层上设有分隔的源极导线段 和漏极导线段，所述源极导线段和漏极导线段之间设有沟道，所述沟道穿过欧姆接触层，所述沟道底部为非晶硅层，所述源极导线段和漏极导线段宽度大于非晶硅层的宽度，所述源极导线段和漏极导线段上设有第二绝缘层，所述第二绝缘层上设有像素电极层，所述第二绝缘层对应漏极导线段设有过孔，所述像素电极层通过过孔与漏极导线段连接。
使用5Mask可以获取更好性能的薄膜晶体管(TFT)。
其中，所述绝缘介质层上对应栅极导线段设有非晶硅层，所述非晶硅层上设有与非晶硅层对应的欧姆接触层，所述欧姆接触层上设有分隔的源极导线段和漏极导线段，所述源极导线段和漏极导线段之间设有沟道，所述沟道穿过欧姆接触层，所述沟道底部为非晶硅层，所述源极导线段和漏极导线段宽度等于与其接触的欧姆接触层的宽度，所述源极导线段和漏极导线段上设有第二绝缘层，所述第二绝缘层上设有像素电极层，所述第二绝缘层对应漏极导线段设有过孔，所述像素电极层通过过孔与漏极导线段连接。
使用4Mask可以获取更好性能的薄膜晶体管TFT，而且节省一步Mask。
其中，所述第二绝缘层的相对介电常数小于氮化硅和氧化硅的相对介电常数。
采用低介电常数保护层可以提高薄膜晶体管TFT器件性能，改善信号串扰问题和RC电路延时问题。
其中，所述低介电常数保护层包括介孔氧化硅
介孔氧化硅的相对介电常数εr＝1.4～2.4，低介电常数保护层采用介孔氧化硅取代5-mask与4-mask工艺TFT器件中的保护层材料SiNx(相对介电常数εr＝7～8)，介孔氧化硅比一般氧化硅(相对介电常数εr＝3.9～4.1)的εr更低，可以提高TFT器件性能，改善信号串扰问题和RC电路延时问题，减小低介电常数保护层的厚度，当然低介电常数保护层也可以采用其他低介电常数的材料，如纳米多孔硅等。
其中，所述介孔氧化硅包括多个子单元，所述子单元包括成三行排列的子 部件，所述子单元的中间一行包括并排的三个子部件，所述子单元的第一行和第三行分别包括并排的两个子部件，所述第一行和第三行的两个子部件分别设置在中间一行三个子部件的任意两个子部件之间，所述子部件切面为六边形，所述子部件中间具有圆形通孔。
子单元具有排列规则有序的子部件，具有较高的比表面积，较好的热稳定性和水热稳定性,子部件通孔大小均匀，子部件切面为六边形，方便多个子部件拼接排列。
第一层导线上设置的绝缘介质层介电常数大于氧化硅层和氮化硅层的介电常数，增大器件存储电荷能力，绝缘介质层包括组合物，组合物包括第一组成物和第二组成物，第一组成物的介电常数小于氧化硅层和氮化硅层的介电常数，第二组成物的介电常数大于氧化硅层和氮化硅层的介电常数，通过调节第一组成物和第二组成物的比例实现绝缘介质层的介电常数可调。
【附图说明】
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请实施例一种5道工艺TFT器件示意图；
图2是本申请实施例一种4道工艺TFT器件示意图；
图3是本申请实施例一种5道工艺TFT器件另一示意图；
图4是本申请实施例纳米多孔硅示意图；
图5是本申请实施例纳米多孔硅和锗纳米颗粒示意图；
图6是本申请实施例介孔氧化硅示意图；
图7是本申请实施例有机分子模板自组装法制备介孔氧化硅工艺示意图；
图8是本申请实施例介电常数测试示意图。
【具体实施方式】
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
下面结合附图和较佳的实施例对本申请作进一步说明。
下面参考图1至图8描述本申请实施例的显示面板。
如图1所示，在图1的实施例中显示面板包括基板10，所述基板10上设有若干条第一层导线21，所述第一层导线21上设有绝缘介质层22，所述绝缘介质层22采用氮化硅或氧化硅，所述绝缘介质层22上对应第一层导线21的栅极导线段211设有非晶硅层23，所述非晶硅层23上设有与非晶硅层23对应的欧姆接触层24，所述欧姆接触层24上设有分隔的源极导线段25和漏极导线段26，所述源极导线段25和漏极导线段26之间设有沟道27，所述沟道27穿过欧姆接触层24，所述沟道27底部为非晶硅层23，所述源极导线段25和漏极导线段26的宽度大于非晶硅层23的宽度，所述源极导线段25和漏极导线段26上设有保护层30，所述保护层30上设有像素电极层50，所述保护层30对应漏极导线段26设有过孔28，所述像素电极层50通过过孔28与漏极导线段26连接。其中，所述源极导线段25超出非晶硅层23部分一侧直接连接绝缘介质层22另一侧直接连接保护层30，所述绝缘介质层22对应过孔28部分与漏极导线段26之间连接。使用5Mask获取的薄膜晶体管TFT，具有较好的性能。
如图2所示，在图2的实施例中显示面板包括基板10，所述基板10上设有若干条第一层导线21，所述第一层导线21上设有绝缘介质层22，所述绝缘介质层22采用氮化硅或氧化硅，所述绝缘介质层22上对应第一层导线21的栅极导线段211设有非晶硅层23，所述非晶硅层23上设有与非晶硅层23对应的欧姆接触层24，所述欧姆接触层24上设有分隔的源极导线段25和漏极导线段26，所述源极导线段25和漏极导线段26之间设有沟道27，所述沟道27穿过欧姆接触层24，所述沟道27底部为非晶硅层23，所述源极导线段25和漏极导线段26宽度大于非晶硅层23的宽度，所述源极导线段25和漏极导线段26上设有保护层30，所述保护层30上设有像素电极层50，所述保护层30对应漏极导线段26设有过孔28，所述像素电极层50通过过孔28与漏极导线段26连接。其中，所述源极导线段25外侧的保护层30直接与绝缘介质层22连接，所述绝缘介质层 22对应过孔28上方依次设有非晶硅层23、欧姆接触层24和漏极导线段26。使用4Mask获取的薄膜晶体管TFT具有较好的性能，而且可以节省一步Mask工艺。
由于工艺和设计的进步，集成电路、芯片以及TFT-LCD的尺寸不断的减小，器件的封装密度不停的增大，因此对材料各方面性能的要求不断的提高。由于器件的比例缩小，目前器件的栅氧绝缘层厚度变得非常薄，对于未来比例小的器件而言，栅氧绝缘层厚度只会越来越薄，这需要有新的高K的栅氧绝缘介电材料。上述实施例采用的四道工艺或五道工艺TFT-Array阵列，在TFT晶体管中，栅介电极与上级的绝缘保护层之间存在很高的电压。栅氧层会受到隧穿电流的影响，当栅极的绝缘介质层很薄时，电子会在薄膜晶体管中隧穿通过绝缘介质层。这将导致晶体管阀值电压的漂移，无法切换开关状态导致电路失效。传统的栅氧绝缘介电材料(如SiO2、SiNx)已不满足当前TFT-LCD器件高封装密度发展的需要。
如图3、图4和图5所示，在图3、图4和图5的实施例中显示面板包括：基板10；若干条第一层导线21，所述若干条第一层导线21设置在基板10上；绝缘介质层22，所述绝缘介质层22设置在若干条第一层导线21上，所述绝缘介质层22的介电常数大于氧化硅层和氮化硅层的介电常数，所述绝缘介质层22包括组合物，所述组合物包括第一组成物和第二组成物。
第一层导线21上设置的绝缘介质层22介电常数大于氧化硅层和氮化硅层的介电常数，增大器件存储电荷能力，绝缘介质层22包括组合物，组合物包括第一组成物和第二组成物，第一组成物的介电常数小于氧化硅层和氮化硅层的介电常数，第二组成物的介电常数大于氧化硅层和氮化硅层的介电常数，通过调节第一组成物和第二组成物的比例实现绝缘介质层22的介电常数可调。
可选的，其中，所述第一组成物包括纳米多孔硅。纳米多孔硅可以做的非常薄，可以减小绝缘介电层的厚度，可以满足集成电路、芯片以及TFT-LCD的尺寸不断的减小的需求，纳米多孔硅本身具有疏水性。
可选的，其中，所述第二组成物包括锗纳米颗粒。锗的介电常数为16，通过调节锗的比例提高绝缘介质层22的介电常数，当然也可以采用其他介电常数高的金属和其他材料。
可选的，其中，所述第一组成物包括纳米多孔硅，所述第二组成物包括锗纳米颗粒。纳米多孔硅可以做的非常薄，可以减小绝缘介电层的厚度，可以满足集成电路、芯片以及TFT-LCD的尺寸不断的减小的需求，纳米多孔硅本身具有疏水性，锗的介电常数为16，纳米多孔硅本身具有很多硅孔，锗纳米颗粒可以存入硅孔内，不会增加通过纳米多孔硅的厚度，通过调节锗纳米颗粒Ge的负载量实现介电系数可控调节。
其中，所述绝缘介质层22包括纳米多孔硅，所述纳米多孔硅包括多个彼此连接的空心柱状的子组件221，所述子组件221切面为六边形，所述子组件221中间具有圆形通孔，所述子组件221的圆形通孔上设有多个硅孔，所述硅孔内设有锗纳米颗粒。多孔硅的子组件221切面六边形方便多个子组件221拼接排列，硅孔内设有多个锗纳米颗粒，不影响多孔硅厚度。
其中，所述绝缘介质层22上对应栅极导线段211设有非晶硅层23，所述非晶硅层23上设有与非晶硅层23对应的欧姆接触层24，所述欧姆接触层24上设有分隔的源极导线段25和漏极导线段26，所述源极导线段25和漏极导线段26之间设有沟道27，所述沟道27穿过欧姆接触层24，所述沟道27底部为非晶硅层23，所述源极导线段25和漏极导线段26宽度大于非晶硅层23的宽度，所述源极导线段25和漏极导线段26上设有第二绝缘层30，所述第二绝缘层30上设有像素电极层50，所述第二绝缘层30对应漏极导线段26设有过孔28，所述像素电极层50通过过孔28与漏极导线段26连接。其中，所述源极导线段25超出非晶硅层23部分一侧直接连接绝缘介质层22另一侧直接连接低介电常数保护层40，所述绝缘介质层22对应过孔28部分与漏极导线段26之间连接。使用5Mask可以获取更好性能的薄膜晶体管TFT。
如图2、图4和图5所示，在图2、图4和图5的实施例中显示面板包括： 基板10；若干条第一层导线21，所述若干条第一层导线21设置在基板10上；绝缘介质层22，所述绝缘介质层22设置在若干条第一层导线21上，所述绝缘介质层22的介电常数大于氧化硅层和氮化硅层的介电常数，所述绝缘介质层22包括组合物，所述组合物包括第一组成物和第二组成物。
第一层导线21上设置的绝缘介质层22介电常数大于氧化硅层和氮化硅层的介电常数，增大器件存储电荷能力，绝缘介质层22包括组合物，组合物包括第一组成物和第二组成物，第一组成物的介电常数小于氧化硅层和氮化硅层的介电常数，第二组成物的介电常数大于氧化硅层和氮化硅层的介电常数，通过调节第一组成物和第二组成物的比例实现绝缘介质层22的介电常数可调。
可选的，其中，所述第一组成物包括纳米多孔硅。纳米多孔硅可以做的非常薄，可以减小绝缘介电层的厚度，可以满足集成电路、芯片以及TFT-LCD的尺寸不断的减小的需求，纳米多孔硅本身具有疏水性。
可选的，其中，所述第二组成物包括锗纳米颗粒。锗的介电常数为16，通过调节锗的比例提高绝缘介质层22的介电常数，当然也可以采用其他介电常数高的金属和其他材料。
可选的，其中，所述第一组成物包括纳米多孔硅，所述第二组成物包括锗纳米颗粒。纳米多孔硅可以做的非常薄，可以减小绝缘介电层的厚度，可以满足集成电路、芯片以及TFT-LCD的尺寸不断的减小的需求，纳米多孔硅本身具有疏水性，锗的介电常数为16，纳米多孔硅本身具有很多硅孔，锗纳米颗粒可以存入硅孔内，不会增加通过纳米多孔硅的厚度，通过调节锗纳米颗粒Ge的负载量实现介电系数可控调节。
其中，所述绝缘介质层22包括纳米多孔硅，所述纳米多孔硅包括多个彼此连接的空心柱状的子组件221，所述子组件221切面为六边形，所述子组件221中间具有圆形通孔，所述子组件221的圆形通孔上设有多个硅孔，所述硅孔内设有锗纳米颗粒。多孔硅的子组件221切面六边形方便多个子组件221拼接排列，硅孔内设有多个锗纳米颗粒，不影响多孔硅厚度。
其中，所述绝缘介质层22上对应栅极导线段211设有非晶硅层23，所述非晶硅层23上设有与非晶硅层23对应的欧姆接触层24，所述欧姆接触层24上设有分隔的源极导线段25和漏极导线段26，所述源极导线段25和漏极导线段26之间设有沟道27，所述沟道27穿过欧姆接触层24，所述沟道27底部为非晶硅层23，所述源极导线段25和漏极导线段26宽度等于与其接触的欧姆接触层24的宽度，所述源极导线段25和漏极导线段26上设有第二绝缘层30，所述第二绝缘层30上设有像素电极层50，所述第二绝缘层30对应漏极导线段26设有过孔28，所述像素电极层50通过过孔28与漏极导线段26连接。其中，所述源极导线段25外侧的低介电常数保护层40直接与绝缘介质层22连接，所述绝缘介质层22对应过孔28上方依次设有非晶硅层23、欧姆接触层24和漏极导线段26。使用4Mask可以获取更好性能的薄膜晶体管TFT，而且节省一步Mask。
如图2、图3和图6所示，在图2、图3和图6的实施例中显示面板包括：基板10；若干条第一层导线21，所述若干条第一层导线21设置在基板10上；绝缘介质层22，所述绝缘介质层22设置在若干条第一层导线21上，所述绝缘介质层22的介电常数大于氧化硅层和氮化硅层的介电常数，所述绝缘介质层22包括组合物，所述组合物包括第一组成物和第二组成物。
其中，所述第二绝缘层30的相对介电常数小于氮化硅和氧化硅的相对介电常数。采用低介电常数保护层可以提高薄膜晶体管TFT器件性能，改善信号串扰问题和RC电路延时问题。
可选的，其中，所述绝缘介质层22上对应栅极导线段211设有非晶硅层23，所述非晶硅层23上设有与非晶硅层23对应的欧姆接触层24，所述欧姆接触层24上设有分隔的源极导线段25和漏极导线段26，所述源极导线段25和漏极导线段26之间设有沟道27，所述沟道27穿过欧姆接触层24，所述沟道27底部为非晶硅层23，所述源极导线段25和漏极导线段26宽度大于非晶硅层23的宽度，所述源极导线段25和漏极导线段26上设有第二绝缘层30，所述第二绝缘层30上设有像素电极层50，所述第二绝缘层30对应漏极导线段26设有过孔 28，所述像素电极层50通过过孔28与漏极导线段26连接。其中，所述源极导线段25超出非晶硅层23部分一侧直接连接绝缘介质层22另一侧直接连接低介电常数保护层，所述绝缘介质层22对应过孔28部分与漏极导线段26之间连接。
可选的，其中，所述绝缘介质层22上对应栅极导线段211设有非晶硅层23，所述非晶硅层23上设有与非晶硅层23对应的欧姆接触层24，所述欧姆接触层24上设有分隔的源极导线段25和漏极导线段26，所述源极导线段25和漏极导线段26之间设有沟道27，所述沟道27穿过欧姆接触层24，所述沟道27底部为非晶硅层23，所述源极导线段25和漏极导线段26宽度等于与其接触的欧姆接触层24的宽度，所述源极导线段25和漏极导线段26上设有第二绝缘层30，所述第二绝缘层30上设有像素电极层50，所述第二绝缘层30对应漏极导线段26设有过孔28，所述像素电极层50通过过孔28与漏极导线段26连接。其中，所述源极导线段25外侧的低介电常数保护层直接与绝缘介质层22连接，所述绝缘介质层22对应过孔28上方依次设有非晶硅层23、欧姆接触层24和漏极导线段26。
其中，所述低介电常数保护层包括介孔氧化硅。介孔氧化硅的相对介电常数εr＝1.4～2.4，低介电常数保护层采用介孔氧化硅取代5-mask与4-mask工艺TFT器件中的保护层材料SiNx(相对介电常数εr＝7～8)，介孔氧化硅比一般氧化硅(相对介电常数εr＝3.9～4.1)的εr更低，可以提高TFT器件性能，改善信号串扰问题和RC电路延时问题，减小低介电常数保护层的厚度，当然低介电常数保护层也可以采用其他低介电常数的材料，如纳米多孔硅等。
其中，所述介孔氧化硅包括多个子单元43，所述子单元43包括成三行排列的子部件42，所述子单元43的中间一行包括并排的三个子部件42，所述子单元43的第一行和第三行分别包括并排的两个子部件42，所述第一行和第三行的两个子部件42分别设置在中间一行三个子部件42的任意两个子部件42之间，所述子部件42切面为六边形，所述子部件42中间具有圆形通孔。子单元43具有排列规则有序的子部件42，具有较高的比表面积，较好的热稳定性和水热稳 定性,子部件42通孔大小均匀，子部件42切面为六边形，方便多个子部件42拼接排列。
其中，如图7所示，在主动开关(例如薄膜晶体管TFT)上设置相对介电常数小于氮化硅的低介电常数保护层包括：
将胶束形成胶束棒；
将胶束棒按六角形排列形成六角形胶束棒；
将六角形胶束棒根据有机分子模板自组装机制形成氧化硅模板中间组；
将氧化硅模板中间组培烧去除模板形成介孔氧化硅；
将介孔氧化硅形成低介电常数保护层。
介孔氧化硅的相对介电常数εr＝1.4～2.4，低介电常数保护层采用介孔氧化硅取代5-mask与4-mask工艺主动开关(例如薄膜晶体管TFT)上的保护层材料SiNx(相对介电常数εr＝7～8)，介孔氧化硅比一般氧化硅(相对介电常数εr＝3.9～4.1)的εr更低，提高主动开关(例如薄膜晶体管TFT)性能，改善信号串扰问题和RC电路延时问题，减小低介电常数保护层的厚度。
如图8所示，在图8所示的介电常数测试示意图中显示，介孔氧化硅的介电常数较低而且稳定，随着时间的增加变化很小。
在上述实施例中，非晶硅层采用a-Si材料，当然也可以采用其他半导体层材料。
在上述实施例中，所述基板的材料可以选用玻璃、塑料等。
在上述实施例中，显示面板包括液晶面板、OLED面板、QLED面板、曲面面板、等离子面板等，以液晶面板为例，液晶面板包括阵列基板和彩膜基板(CF)，所述阵列基板与彩膜基板相对设置，所述阵列基板与彩膜基板之间设有液晶和间隔单元(photo spacer，PS)，所述阵列基板上设有薄膜晶体管(TFT)，彩膜基板上设有彩色滤光层。
在上述实施例中，彩膜基板可包括TFT阵列，彩膜及TFT阵列可形成于同一基板上，阵列基本可包括彩色滤光层。
在上述实施例中，本申请的显示面板可为曲面型面板。
以上内容是结合具体的优选实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (20)

  1. 一种显示面板，包括：
    基板；
    若干条第一层导线，所述若干条第一层导线设置在基板上；
    绝缘介质层，所述绝缘介质层设置在若干条第一层导线上，所述绝缘介质层的介电常数大于氧化硅层和氮化硅层的介电常数，所述绝缘介质层包括组合物，所述组合物包括第一组成物和第二组成物，所述第一组成物的介电常数小于氧化硅层和氮化硅层的介电常数，所述第二组成物的介电常数大于氧化硅层和氮化硅层的介电常数；
    所述第一组成物包括纳米多孔硅，所述第二组成物包括锗纳米颗粒；
    所述绝缘介质层包括纳米多孔硅，所述纳米多孔硅包括多个彼此连接的空心柱状的子组件，所述子组件切面为六边形，所述子组件中间具有圆形通孔，所述子组件的圆形通孔上设有多个硅孔，所述硅孔内设有锗纳米颗粒；
    所述绝缘介质层上对应栅极导线段设有非晶硅层，所述非晶硅层上设有与非晶硅层对应的欧姆接触层，所述欧姆接触层上设有分隔的源极导线段和漏极导线段，所述源极导线段和漏极导线段之间设有沟道，所述沟道穿过欧姆接触层，所述沟道底部为非晶硅层，所述源极导线段和漏极导线段宽度大于非晶硅层的宽度，所述源极导线段和漏极导线段上设有第二绝缘层，所述第二绝缘层上设有像素电极层，所述第二绝缘层对应漏极导线段设有过孔，所述像素电极层通过过孔与漏极导线段连接；
    所述第二绝缘层的相对介电常数小于氮化硅和氧化硅的相对介电常数；所述低介电常数保护层包括介孔氧化硅；
    所述介孔氧化硅包括多个子单元，所述子单元包括成三行排列的子部件，所述子单元的中间一行包括并排的三个子部件，所述子单元的第一行和第三行分别包括并排的两个子部件，所述第一行和第三行的两个子部件分别设置在中 间一行三个子部件的任意两个子部件之间，所述子部件切面为六边形，所述子部件中间具有圆形通孔。
  2. 一种显示面板，包括：
    基板；
    若干条第一层导线，所述若干条第一层导线设置在基板上；
    绝缘介质层，所述绝缘介质层设置在若干条第一层导线上，所述绝缘介质层的介电常数大于氧化硅层和氮化硅层的介电常数，所述绝缘介质层包括组合物，所述组合物包括第一组成物和第二组成物，所述第一组成物的介电常数小于氧化硅层和氮化硅层的介电常数，所述第二组成物的介电常数大于氧化硅层和氮化硅层的介电常数。
  3. 如权利要求2所述的一种显示面板，其中，所述第一组成物包括纳米多孔硅。
  4. 如权利要求2所述的一种显示面板，其中，所述第二组成物包括锗纳米颗粒。
  5. 如权利要求2所述的一种显示面板，其中，所述第一组成物包括纳米多孔硅，所述第二组成物包括锗纳米颗粒。
  6. 如权利要求2所述的一种显示面板，其中，所述绝缘介质层包括纳米多孔硅，所述纳米多孔硅包括多个彼此连接的空心柱状的子组件，所述子组件切面为六边形，所述子组件中间具有圆形通孔，所述子组件的圆形通孔上设有多个硅孔，所述硅孔内设有锗纳米颗粒。
  7. 如权利要求2所述的一种显示面板，其中，所述绝缘介质层上对应栅极导线段设有非晶硅层，所述非晶硅层上设有与非晶硅层对应的欧姆接触层，所述欧姆接触层上设有分隔的源极导线段和漏极导线段，所述源极导线段和漏极导线段之间设有沟道，所述沟道穿过欧姆接触层，所述沟道底部为非晶硅层，所述源极导线段和漏极导线段宽度大于非晶硅层的宽度，所述源极导线段和漏 极导线段上设有第二绝缘层，所述第二绝缘层上设有像素电极层，所述第二绝缘层对应漏极导线段设有过孔，所述像素电极层通过过孔与漏极导线段连接。
  8. 如权利要求7所述的一种显示面板，其中，所述第二绝缘层的相对介电常数小于氮化硅和氧化硅的相对介电常数。
  9. 如权利要求8所述的一种显示面板，其中，所述低介电常数保护层包括介孔氧化硅。
  10. 如权利要求9所述的一种显示面板，其中，所述介孔氧化硅包括多个子单元，所述子单元包括成三行排列的子部件，所述子单元的中间一行包括并排的三个子部件，所述子单元的第一行和第三行分别包括并排的两个子部件，所述第一行和第三行的两个子部件分别设置在中间一行三个子部件的任意两个子部件之间，所述子部件切面为六边形，所述子部件中间具有圆形通孔。
  11. 如权利要求2所述的一种显示面板，其中，所述绝缘介质层上对应栅极导线段设有非晶硅层，所述非晶硅层上设有与非晶硅层对应的欧姆接触层，所述欧姆接触层上设有分隔的源极导线段和漏极导线段，所述源极导线段和漏极导线段之间设有沟道，所述沟道穿过欧姆接触层，所述沟道底部为非晶硅层，所述源极导线段和漏极导线段宽度等于与其接触的欧姆接触层的宽度，所述源极导线段和漏极导线段上设有第二绝缘层，所述第二绝缘层上设有像素电极层，所述第二绝缘层对应漏极导线段设有过孔，所述像素电极层通过过孔与漏极导线段连接。
  12. 如权利要求11所述的一种显示面板，其中，所述第二绝缘层的相对介电常数小于氮化硅和氧化硅的相对介电常数。
  13. 如权利要求12所述的一种显示面板，其中，所述低介电常数保护层包括介孔氧化硅。
  14. 如权利要求13所述的一种显示面板，其中，所述介孔氧化硅包括多个子单元，所述子单元包括成三行排列的子部件，所述子单元的中间一行包括并排的三个子部件，所述子单元的第一行和第三行分别包括并排的两个子部件， 所述第一行和第三行的两个子部件分别设置在中间一行三个子部件的任意两个子部件之间，所述子部件切面为六边形，所述子部件中间具有圆形通孔。
  15. 一种显示装置，包括显示面板，所述显示面板包括：
    基板；
    若干条第一层导线，所述若干条第一层导线设置在基板上；
    绝缘介质层，所述绝缘介质层设置在若干条第一层导线上，所述绝缘介质层的介电常数大于氧化硅层和氮化硅层的介电常数，所述绝缘介质层包括组合物，所述组合物包括第一组成物和第二组成物，所述第一组成物的介电常数小于氧化硅层和氮化硅层的介电常数，所述第二组成物的介电常数大于氧化硅层和氮化硅层的介电常数。
  16. 如权利要求15所述的一种显示装置，其中，所述第一组成物包括纳米多孔硅，所述第二组成物包括锗纳米颗粒。
  17. 如权利要求15所述的一种显示装置，其中，所述绝缘介质层包括纳米多孔硅，所述纳米多孔硅包括多个彼此连接的空心柱状的子组件，所述子组件切面为六边形，所述子组件中间具有圆形通孔，所述子组件的圆形通孔上设有多个硅孔，所述硅孔内设有锗纳米颗粒。
  18. 如权利要求15所述的一种显示装置，其中，所述绝缘介质层上对应栅极导线段设有非晶硅层，所述非晶硅层上设有与非晶硅层对应的欧姆接触层，所述欧姆接触层上设有分隔的源极导线段和漏极导线段，所述源极导线段和漏极导线段之间设有沟道，所述沟道穿过欧姆接触层，所述沟道底部为非晶硅层，所述源极导线段和漏极导线段宽度大于非晶硅层的宽度，所述源极导线段和漏极导线段上设有第二绝缘层，所述第二绝缘层上设有像素电极层，所述第二绝缘层对应漏极导线段设有过孔，所述像素电极层通过过孔与漏极导线段连接。
  19. 如权利要求18所述的一种显示装置，其中，所述第二绝缘层的相对介电常数小于氮化硅和氧化硅的相对介电常数；所述低介电常数保护层包括介孔氧化硅。
  20. 如权利要求19所述的一种显示装置，其中，所述介孔氧化硅包括多个子单元，所述子单元包括成三行排列的子部件，所述子单元的中间一行包括并排的三个子部件，所述子单元的第一行和第三行分别包括并排的两个子部件，所述第一行和第三行的两个子部件分别设置在中间一行三个子部件的任意两个子部件之间，所述子部件切面为六边形，所述子部件中间具有圆形通孔。
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