WO2018120309A1 - Oled显示装置的阵列基板及其制作方法 - Google Patents

Oled显示装置的阵列基板及其制作方法 Download PDF

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Publication number
WO2018120309A1
WO2018120309A1 PCT/CN2017/071162 CN2017071162W WO2018120309A1 WO 2018120309 A1 WO2018120309 A1 WO 2018120309A1 CN 2017071162 W CN2017071162 W CN 2017071162W WO 2018120309 A1 WO2018120309 A1 WO 2018120309A1
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Prior art keywords
thin film
film transistor
pattern
layer
base substrate
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French (fr)
Inventor
姜春生
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US15/327,403 priority Critical patent/US10068955B2/en
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Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate of an OLED display device and a method of fabricating the same.
  • An array substrate manufacturing process of an existing OLED display device includes: continuously depositing a buffer layer and an amorphous silicon layer in a process of an active layer, wherein the first mask is a thin film transistor channel doping, and the second mask is defined Out of the active region, depositing silicon oxide as a gate oxide layer, depositing a metal layer and defining a first metal layer (or a scan electrode) with a third mask, using the first metal layer as a mask, with low dose ions Injecting a lightly doped drain region with high resistance, and defining the N-doped and P-doped low-temperature polysilicon regions with the fourth and fifth masks using a silicon oxide/silicon nitride film as a protective layer, sixth
  • the contact hole and the second metal layer (or referred to as a signal electrode) are respectively defined with the seventh reticle, and the organic material coated in different manners is used as a planarization protection layer, and the via hole is defined by the eighth reticle, and finally A transparent conductive electrode
  • the array substrate manufacturing process of the prior art OLED display device is complicated, the production efficiency is low, and the manufacturing process is more, which may affect the related process by the conductive particles generated in the process, thereby affecting the quality of the product. .
  • the invention provides a method for fabricating an array substrate of an OLED display device, which has a simple manufacturing process, and solves the complicated manufacturing process of the thin film transistor of the prior art, has low production efficiency, and has many manufacturing processes, which may cause related processes to be generated in the process.
  • the influence of conductive particles which in turn affects the technical quality of the product.
  • the invention provides a method for fabricating an array substrate of an OLED display device, and the manufacturing method comprises the following steps:
  • a conductive channel of the first thin film transistor and a conductive channel of the second thin film transistor are formed on the base substrate by using the second mask pattern, and a channel is formed by an ion implantation process. a doped region, and a source doped region and a drain doped region on both sides of the channel doped region;
  • a pattern of the second metal layer including a source and a drain of the first thin film transistor, and a source and a drain of the second thin film transistor, on the basis of the above pattern, using a fifth mask pattern And a data line and a pixel electrode;
  • a protective layer is formed, and the protective layer on the surface of the pixel electrode is etched away by using the sixth mask pattern.
  • the second metal layer is made of a graphene film material.
  • a buffer layer is formed on the surface of the substrate.
  • the step of forming a pattern of the semiconductor on the base substrate comprises: depositing a layer of a-Si film on the substrate by using a physical vapor deposition process, and then using the first mask pattern pair a The -Si film is subjected to wet etching to form active regions of the first thin film transistor and the second thin film transistor.
  • the invention also provides a method for fabricating an array substrate of an OLED display device, the manufacturing method comprising the following steps:
  • a conductive channel of the first thin film transistor and a conductive channel of the second thin film transistor are formed on the base substrate by using the second mask pattern, and a channel is formed by an ion implantation process. a doped region, and a source doped region and a drain doped region on both sides of the channel doped region;
  • the second metal layer is made of a graphene film material.
  • a buffer layer is formed on the surface of the substrate.
  • the step of forming a pattern of the semiconductor on the base substrate comprises: depositing a layer of a-Si film on the substrate by using a physical vapor deposition process, and then using the first mask pattern pair a The -Si film is subjected to wet etching to form active regions of the first thin film transistor and the second thin film transistor.
  • the present invention further provides an array substrate of an OLED display device, comprising:
  • An active layer formed on the base substrate including a channel doping region, a source doping region, and a drain doping region of the first thin film transistor, and a channel doping region of the second thin film transistor, a source doped region and a drain doped region;
  • a first metal layer formed on the base substrate including a gate of the first thin film transistor, and a gate of the second thin film transistor;
  • a second metal layer formed on the base substrate including a source and a drain of the first thin film transistor, a source and a drain of the second thin film transistor, and a data line and a pixel electrode;
  • the source of the first thin film transistor is connected to the data line, the drain of the first thin film transistor is connected to the gate of the second thin film transistor, and the drain of the second thin film transistor is connected to the pixel. electrode.
  • a protective layer is formed on the base substrate, and a protective layer on the surface of the pixel electrode is etched away.
  • a hole injecting layer and a hole transporting layer are formed on the base substrate.
  • the second metal layer is made of a graphene film material.
  • a buffer layer is formed between the active layer and the base substrate.
  • the invention has the beneficial effects that the data line, the source, the drain and the pixel electrode can be obtained through the same mask by the manufacturing method of the present invention, which saves the requirement for processing different electrodes.
  • the reticle reduces the mask required to form the vias for electrical connection between the different layer electrodes, thereby reducing the exposure process, thereby reducing process complexity, saving material, and reducing processing time while reducing processing time. cost.
  • FIG. 1a to 1f are schematic views showing a manufacturing process of an array substrate of an OLED display device provided by the present invention.
  • FIG. 2 is a schematic cross-sectional view of an array substrate of an OLED display device provided by the present invention.
  • the invention is directed to a method for fabricating an array substrate of an existing OLED display device, which has a complicated manufacturing process, low production efficiency, more manufacturing processes, increased cost, and related processes are affected by conductive particles generated in the process, and further This embodiment can solve the drawback of the technical problem affecting the quality of the product.
  • the method for fabricating an array substrate provided by the present invention mainly comprises the following steps:
  • a substrate substrate 100 is provided; a pattern of a semiconductor is formed on the substrate substrate 100 by using a first mask pattern, including a first thin film transistor and a second thin film in each driving unit Active regions 101, 102 of the transistor.
  • PVD Physical Vapor Deposition
  • a pattern of the insulating layer 109 is formed on the basis of the above figure.
  • chemical vapor deposition (Chemical Vapor Deposition, CVD for short) The process deposits the insulating layer 109 on the base substrate 100 and the semiconductor pattern.
  • a first metal layer is deposited on the insulating layer 109 by using a PVD process, and then the first metal layer is wet-etched by the third mask to form a gate of the first thin film transistor. 110, and a gate 111 of the second thin film transistor.
  • the intermediate dielectric layer 112 and the insulating layer 109 are dry etched by using the fourth mask pattern to form via holes penetrating the insulating layer 109 and the intermediate dielectric layer, including for connecting the first a source and a source doping region 105 of the thin film transistor, a drain and drain doping region 106, a drain and a gate 111 of the second thin film transistor, a source and a source doping region 107 of the second thin film transistor, A via of the drain and drain doping regions 108 of the second thin film transistor.
  • the source of the second thin film transistor is located in the same layer as the drain 116 of the first thin film transistor, and is located behind the drain 116 of the first thin film transistor, so the source of the second thin film transistor is Occlusion, not shown in the figure.
  • the PV protective layer 119 is deposited, and the protective layer 119 located on the surface of the pixel electrode is etched away, and the array substrate is completed.
  • a buffer layer is formed substantially on the substrate before the semiconductor layer is formed.
  • the source and drain of the first thin film transistor and the source and drain of the second thin film transistor are formed in the same layer as the pixel electrode, a graphene film material having high conductivity and high transparency is used.
  • the array substrate of the OLED display device of the present embodiment includes:
  • a base substrate 201 an active layer formed on the base substrate 201, including a channel doping region 202, a source doping region 203, and a drain doping region 204 of the first thin film transistor T1, and a channel doping region 205, a source doping region 206 and a drain doping region 207 of the second thin film transistor T2; a gate insulating layer 208 formed on the base substrate 201; a first metal layer formed in the On the base substrate 201, including the gate 211 of the first thin film transistor T1, and the gate 212 of the second thin film transistor T2; an intermediate dielectric layer 213 formed on the base substrate 201; a hole is formed through the intermediate dielectric layer 213 and the gate insulating layer 208; a second metal layer is formed on the base substrate 201, including a source 214 and a drain 215 of the first thin film transistor T1, a source and a drain 216 of the second thin film transistor T2 and a data line and a pixel electrode; wherein a source
  • a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and a cathode electrode are sequentially formed on the pixel electrode of the array substrate to obtain an OLED display device.
  • the driving unit in the OLED display device is composed of two thin film transistors (Thin Film Transistor, referred to as TFT) And a storage capacitor Cst; wherein the gate of the first thin film transistor T1 inputs the scan signal Vgate, the source of the first thin film transistor T1 inputs the data signal Vdata, and the drain of the first thin film transistor T1 is connected to the second thin film transistor T2
  • the gate of the second thin film transistor T2 is connected to the digital power supply Vdd
  • the drain of the second thin film transistor is connected to the digital ground Vss
  • the storage capacitor Cst is disposed between the gate and the source of the second thin film transistor T2, the hair tube
  • the diode is connected in series between the drain of the second thin film transistor T2 and the digital ground Vss.
  • a protective layer 217 is formed on the base substrate 201, and the protective layer 217 of the surface of the pixel electrode is etched away.
  • a hole injecting layer and a hole transporting layer are formed on the base substrate 201.
  • the second metal layer is made of a graphene film material.
  • a buffer layer is formed between the active layer and the base substrate 201.
  • the invention has the beneficial effects that the data line, the source, the drain and the pixel electrode can be obtained through the same mask by the manufacturing method of the present invention, which saves the requirement for processing different electrodes.
  • the reticle reduces the mask required to form the vias for electrical connection between the different layer electrodes, thereby reducing the exposure process, thereby reducing process complexity, saving material, and reducing processing time while reducing processing time. cost.

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Abstract

一种OLED显示装置的阵列基板制作方法，通过第一光罩形成第一薄膜晶体管T1与第二薄膜晶体管T2的有源区域（101，102），通过第二光罩形成T1与T2的沟道掺杂区（103，104）、源极掺杂区（105，107）及漏极掺杂区（106，108），通过第三光罩形成T1与T2栅极（110，111），通过第四光罩形成过孔（113，114），通过第五光罩形成T1与T2的源漏极（115，116，118），以及数据线及像素电极。本制作方法能够节省工序。

Description

OLED显示装置的阵列基板及其制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种OLED显示装置的阵列基板及其制作方法。
 背景技术
现有的OLED显示装置的阵列基板制作工艺，包括：在主动层的工艺当中以连续沉积缓冲层与非晶硅层，第一道光罩即为薄膜晶体管沟道掺杂，第二道光罩定义出主动区域，沉积氧化硅作为栅极氧化层，沉积金属层并以第三道光罩定义第一金属层（或称之为扫描电极），由第一金属层作为光罩，以低剂量的离子注入形成高阻值的轻掺杂漏区域，再以第四道及第五道光罩定义N型掺杂与P型掺杂低温多晶硅区域利用氧化硅/氮化硅薄膜作为保护层，第六道与第七道光罩分别定义出接触孔与第二金属层（或称之为信号电极），搭配不同方式涂布的有机材料作为平坦化保护层，以第八道光罩定义导通孔，最後沉积透明导电电极，并以第九道光罩对其进行定义，配合高温退火工艺将非晶态氧化铟锡转换成多晶态氧化铟锡薄膜。
综上所述，现有技术的OLED显示装置的阵列基板制作工艺较为复杂，生产效率较低，而且制作工序较多，会使相关流程受到制程中产生的导电粒子的影响，进而影响产品的品质。
 技术问题
本发明提供一种OLED显示装置的阵列基板制作方法，制作工序简单，以解决现有技术的薄膜晶体管制作工艺较为复杂，生产效率较低，而且制作工序较多，会使相关流程受到制程中产生的导电粒子的影响，进而影响产品的品质的技术问题。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明提供的一种OLED显示装置的阵列基板制作方法，所述制作方法包括以下步骤：
提供一衬底基板；
利用第一掩膜板图案，在所述衬底基板上形成半导体的图形，其中包括每个驱动单元中的第一薄膜晶体管与第二薄膜晶体管的有源区域；
在以上图形的基础上，利用第二掩膜板图案，在所述衬底基板上形成第一薄膜晶体管的导电沟道及第二薄膜晶体管的导电沟道，并通过离子注入工艺，形成沟道掺杂区，以及位于沟道掺杂区两侧的源极掺杂区与漏极掺杂区；
在以上图形的基础上，形成绝缘层的图形；
在以上图形的基础上，利用第三掩膜板图案，形成第一金属层的图形，其中包括所述第一薄膜晶体管的栅极，以及所述第二薄膜晶体管的栅极；
在以上图形的基础上，形成中间介质层的图形，利用第四掩膜板图案，形成所述第一薄膜晶体管中的贯穿所述绝缘层及中间介质层的过孔，以及所述第二薄膜晶体管中的贯穿所述绝缘层及中间介质层的过孔；
在以上图形的基础上，利用第五掩膜板图案，形成第二金属层的图形，其中包括所述第一薄膜晶体管的源极与漏极、所述第二薄膜晶体管的源极与漏极以及数据线与像素电极；
在以上图形的基础上，形成保护层，利用第六掩膜板图案，刻蚀掉所述像素电极表面的保护层。
在以上图形的基础上，形成空穴注入层及空穴传输层。
优选的，所述第二金属层选用石墨烯薄膜材料。
优选的，所述在衬底基板上形成半导体的图形之前，在所述衬底基板表面形成缓冲层。
优选的，所述在所述衬底基板上形成半导体的图形的步骤包括：利用物理气相沉积工艺在衬底基板上沉积一层a-Si薄膜，然后利用所述第一掩膜板图案对a-Si薄膜进行湿法蚀刻，形成第一薄膜晶体管与第二薄膜晶体管的有源区域。
本发明还提供一种OLED显示装置的阵列基板制作方法，所述制作方法包括以下步骤：
提供一衬底基板；
利用第一掩膜板图案，在所述衬底基板上形成半导体的图形，其中包括每个驱动单元中的第一薄膜晶体管与第二薄膜晶体管的有源区域；
在以上图形的基础上，利用第二掩膜板图案，在所述衬底基板上形成第一薄膜晶体管的导电沟道及第二薄膜晶体管的导电沟道，并通过离子注入工艺，形成沟道掺杂区，以及位于沟道掺杂区两侧的源极掺杂区与漏极掺杂区；
在以上图形的基础上，形成绝缘层的图形；
在以上图形的基础上，利用第三掩膜板图案，形成第一金属层的图形，其中包括所述第一薄膜晶体管的栅极，以及所述第二薄膜晶体管的栅极；
在以上图形的基础上，形成中间介质层的图形，利用第四掩膜板图案，形成所述第一薄膜晶体管中的贯穿所述绝缘层及中间介质层的过孔，以及所述第二薄膜晶体管中的贯穿所述绝缘层及中间介质层的过孔；
在以上图形的基础上，利用第五掩膜板图案，形成第二金属层的图形，其中包括所述第一薄膜晶体管的源极与漏极、所述第二薄膜晶体管的源极与漏极以及数据线与像素电极。
在以上图形的基础上，形成空穴注入层及空穴传输层。
优选的，所述第二金属层选用石墨烯薄膜材料。
优选的，所述在衬底基板上形成半导体的图形之前，在所述衬底基板表面形成缓冲层。
优选的，所述在所述衬底基板上形成半导体的图形的步骤包括：利用物理气相沉积工艺在衬底基板上沉积一层a-Si薄膜，然后利用所述第一掩膜板图案对a-Si薄膜进行湿法蚀刻，形成第一薄膜晶体管与第二薄膜晶体管的有源区域。
依据上述发明目的，本发明还提供一种OLED显示装置的阵列基板，包括：
衬底基板；
有源层，形成于所述衬底基板上，其中包括第一薄膜晶体管的沟道掺杂区、源极掺杂区及漏极掺杂区，以及第二薄膜晶体管的沟道掺杂区、源极掺杂区及漏极掺杂区；
栅极绝缘层，形成于所述衬底基板上；
第一金属层，形成于所述衬底基板上，其中包括所述第一薄膜晶体管的栅极，以及所述第二薄膜晶体管的栅极；
中间介质层，形成于所述衬底基板上；
过孔，贯穿于所述中间介质层与栅极绝缘层；
第二金属层，形成于所述衬底基板上，其中包括所述第一薄膜晶体管的源极与漏极、所述第二薄膜晶体管的源极与漏极以及数据线与像素电极；
其中，所述第一薄膜晶体管的源极连接所述数据线，所述第一薄膜晶体管的漏极连接所述第二薄膜晶体管的栅极，所述第二薄膜晶体管的漏极连接所述像素电极。
优选的，在所述衬底基板上形成保护层，并蚀刻掉所述像素电极表面的保护层。
优选的，在所述衬底基板上形成空穴注入层及空穴传输层。
优选的，所述第二金属层选用石墨烯薄膜材料。
优选的，在所述有源层与所述衬底基板之间，形成有缓冲层。
 有益效果
本发明的有益效果为：相较于现有的阵列基板制作方法，本发明的制作方法，通过同一道光罩可得到数据线、源极、漏极及像素电极，节省了加工不同电极所需的光罩，减少了形成不同层电极之间电连接的过孔所需的光罩，进而减少了曝光的工艺处理从而降低了工序复杂度，节省了材料，在缩短了加工时间的同时降低了加工成本。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1a至图1f是本发明提供的OLED显示装置的阵列基板的制造过程的示意图；
图2为本发明提供的OLED显示装置的阵列基板截面示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本发明针对现有的OLED显示装置的阵列基板制作方法，制作工艺较为复杂，生产效率较低，而且制作工序较多，成本增加，并且会使相关流程受到制程中产生的导电粒子的影响，进而影响产品的品质的技术问题，本实施例能够解决该缺陷。
本发明所提供的阵列基板制作方法，主要包括以下步骤：
S101，参照图1a，提供一衬底基板100；利用第一掩膜板图案，在所述衬底基板100上形成半导体的图形，其中包括每个驱动单元中的第一薄膜晶体管与第二薄膜晶体管的有源区域101、102。
具体的，利用物理气相沉积(Physical Vapor Deposition，简称PVD )工艺在衬底基板100上沉积一层a-Si（非晶硅）薄膜，然后利用所述第一掩膜板图案对a-Si薄膜进行湿法蚀刻，形成第一薄膜晶体管与第二薄膜晶体管的有源区域101、102。
S102，参照图1b，在以上图形的基础上，利用第二掩膜板图案，在所述衬底基板100上形成第一薄膜晶体管的导电沟道及第二薄膜晶体管的导电沟道，并通过离子注入工艺，形成第一薄膜晶体管的沟道掺杂区103、第二薄膜晶体管的沟道掺杂区104，位于第一薄膜晶体管的沟道掺杂区两侧的源极掺杂区105与漏极掺杂区106，以及位于第二薄膜晶体管的沟道掺杂区104两侧的源极掺杂区107与漏极掺杂区108。
S103，参照图1c，在以上图形的基础上，形成绝缘层109的图形。
具体的，利用化学气相沉积( Chemical Vapor Deposition，简称CVD )工艺在所述衬底基板100及半导体图形上沉积所述绝缘层109。
S104，参照图1c，在以上图形的基础上，利用第三掩膜板图案，形成第一金属层的图形，其中包括所述第一薄膜晶体管的栅极110，以及所述第二薄膜晶体管的栅极111。
具体的，利用PVD工艺在所述绝缘层109上沉积第一金属层，然后利用所述第三掩膜板对所述第一金属层进行湿法蚀刻，形成所述第一薄膜晶体管的栅极110，以及所述第二薄膜晶体管的栅极111。
S105，参照图1d，在以上图形的基础上，形成中间介质层112的图形，利用第四掩膜板图案，形成所述第一薄膜晶体管中的贯穿所述绝缘层109及中间介质层的过孔113，以及所述第二薄膜晶体管中的贯穿所述绝缘层109及中间介质层的过孔114。
具体的，利用所述第四掩膜板图案对所述中间介质层112及绝缘层109进行干法蚀刻，形成贯穿所述绝缘层109及中间介质层的过孔，其中包括用于连接第一薄膜晶体管的源极与源极掺杂区105、漏极与漏极掺杂区106、漏极与第二薄膜晶体管的栅极111、第二薄膜晶体管的源极与源极掺杂区107、第二薄膜晶体管的漏极与漏极掺杂区108的过孔。
S106，参照图1e，在以上图形的基础上，利用第五掩膜板图案，形成第二金属层的图形，其中包括所述第一薄膜晶体管的源极115与漏极116、所述第二薄膜晶体管的源极与漏极118以及数据线与像素电极。
具体的，第二薄膜晶体管的源极于所述第一薄膜晶体管的漏极116位于同一层，且位于所述第一薄膜晶体管的漏极116后方，因此所述第二薄膜晶体管的源极被遮挡，在图中未示出。
最后，参照图1f，在以上图形的基础上，沉积PV保护层119，并将位于所述像素电极表面的保护层119蚀刻掉，阵列基板制备完成。
具体的，在制作半导体层之前，在衬底基本上形成有缓冲层。
具体的，由于所述第一薄膜晶体管的源漏极与第二薄膜晶体管的源漏极与所述像素电极同层制作，因此全部选用具有高导电性、高透明度的石墨烯薄膜材料。
根据本发明的上述方法，得到一种OLED显示装置的阵列基板，参照图2，本实施例的OLED显示装置的阵列基板，包括：
衬底基板201；有源层，形成于所述衬底基板201上，其中包括第一薄膜晶体管T1的沟道掺杂区202、源极掺杂区203及漏极掺杂区204，以及第二薄膜晶体管T2的沟道掺杂区205、源极掺杂区206及漏极掺杂区207；栅极绝缘层208，形成于所述衬底基板201上；第一金属层，形成于所述衬底基板201上，其中包括所述第一薄膜晶体管T1的栅极211，以及所述第二薄膜晶体管T2的栅极212；中间介质层213，形成于所述衬底基板201上；过孔，贯穿于所述中间介质层213与栅极绝缘层208；第二金属层，形成于所述衬底基板201上，其中包括所述第一薄膜晶体管T1的源极214与漏极215、所述第二薄膜晶体管T2的源极与漏极216以及数据线与像素电极；其中，所述第一薄膜晶体管T1的源极214连接所述数据线，所述第一薄膜晶体管T1的漏极215连接所述第二薄膜晶体管T2的栅极212，所述第二薄膜晶体管T2的漏极216连接所述像素电极。
在上述步骤完成之后，在所述阵列基板的像素电极上依次制作空穴注入层、空穴传输层、发光层、电子传输层及阴极电极，即可得到OLED显示装置。
OLED显示装置中的驱动单元，由两个薄膜晶体管(Thin FilmTransistor，简称TFT )和一个存储电容Cst组成；其中，第一薄膜晶体管T1的栅极输入扫描信号Vgate，第一薄膜晶体管T1的源极输入数据信号Vdata，第一薄膜晶体管T1的漏极连接第二薄膜晶体管T2的栅极；第二薄膜晶体管T2的源极连接数字电源Vdd，第二薄膜晶体管的漏极连接数字地Vss，存储电容Cst设置在第二薄膜晶体管T2的栅极与源极之间，发管二极管串联在第二薄膜晶体管T2的漏极与数字地Vss之间。
优选的，在所述衬底基板201上形成保护层217，并蚀刻掉所述像素电极表面的保护层217。
优选的，在所述衬底基板201上形成空穴注入层及空穴传输层。
优选的，所述第二金属层选用石墨烯薄膜材料。
优选的，在所述有源层与所述衬底基板201之间，形成有缓冲层。
本发明的有益效果为：相较于现有的阵列基板制作方法，本发明的制作方法，通过同一道光罩可得到数据线、源极、漏极及像素电极，节省了加工不同电极所需的光罩，减少了形成不同层电极之间电连接的过孔所需的光罩，进而减少了曝光的工艺处理从而降低了工序复杂度，节省了材料，在缩短了加工时间的同时降低了加工成本。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (15)

  1. 一种OLED显示装置的阵列基板制作方法，其中，所述制备方法包括：
    提供一衬底基板；
    利用第一掩膜板图案，在所述衬底基板上形成半导体的图形，其中包括每个驱动单元中的第一薄膜晶体管与第二薄膜晶体管的有源区域；
    在以上图形的基础上，利用第二掩膜板图案，在所述衬底基板上形成第一薄膜晶体管的导电沟道及第二薄膜晶体管的导电沟道，并通过离子注入工艺，形成沟道掺杂区，以及位于沟道掺杂区两侧的源极掺杂区与漏极掺杂区；
    在以上图形的基础上，形成绝缘层的图形；
    在以上图形的基础上，利用第三掩膜板图案，形成第一金属层的图形，其中包括所述第一薄膜晶体管的栅极，以及所述第二薄膜晶体管的栅极；
    在以上图形的基础上，形成中间介质层的图形，利用第四掩膜板图案，形成所述第一薄膜晶体管中的贯穿所述绝缘层及中间介质层的过孔，以及所述第二薄膜晶体管中的贯穿所述绝缘层及中间介质层的过孔；
    在以上图形的基础上，利用第五掩膜板图案，形成第二金属层的图形，其中包括所述第一薄膜晶体管的源极与漏极、所述第二薄膜晶体管的源极与漏极以及数据线与像素电极；
    在以上图形的基础上，形成保护层，利用第六掩膜板图案，刻蚀掉所述像素电极表面的保护层。
  2. 根据权利要求1所述的制作方法，其中，在以上图形的基础上，形成空穴注入层及空穴传输层。
  3. 根据权利要求1所述的制作方法，其中，所述第二金属层选用石墨烯薄膜材料。
  4. 根据权利要求1所述的制作方法，其中，所述在衬底基板上形成半导体的图形之前，在所述衬底基板表面形成缓冲层。
  5. 根据权利要求1所述的制作方法，其中，所述在所述衬底基板上形成半导体的图形的步骤包括：
    利用物理气相沉积工艺在衬底基板上沉积一层a-Si薄膜，然后利用所述第一掩膜板图案对a-Si薄膜进行湿法蚀刻，形成第一薄膜晶体管与第二薄膜晶体管的有源区域。
  6. 一种OLED显示装置的阵列基板制作方法，其中，所述制备方法包括：
    提供一衬底基板；
    利用第一掩膜板图案，在所述衬底基板上形成半导体的图形，其中包括每个驱动单元中的第一薄膜晶体管与第二薄膜晶体管的有源区域；
    在以上图形的基础上，利用第二掩膜板图案，在所述衬底基板上形成第一薄膜晶体管的导电沟道及第二薄膜晶体管的导电沟道，并通过离子注入工艺，形成沟道掺杂区，以及位于沟道掺杂区两侧的源极掺杂区与漏极掺杂区；
    在以上图形的基础上，形成绝缘层的图形；
    在以上图形的基础上，利用第三掩膜板图案，形成第一金属层的图形，其中包括所述第一薄膜晶体管的栅极，以及所述第二薄膜晶体管的栅极；
    在以上图形的基础上，形成中间介质层的图形，利用第四掩膜板图案，形成所述第一薄膜晶体管中的贯穿所述绝缘层及中间介质层的过孔，以及所述第二薄膜晶体管中的贯穿所述绝缘层及中间介质层的过孔；
    在以上图形的基础上，利用第五掩膜板图案，形成第二金属层的图形，其中包括所述第一薄膜晶体管的源极与漏极、所述第二薄膜晶体管的源极与漏极以及数据线与像素电极。
  7. 根据权利要求6所述的制作方法，其中，在以上图形的基础上，形成空穴注入层及空穴传输层。
  8. 根据权利要求6所述的制作方法，其中，所述第二金属层选用石墨烯薄膜材料。
  9. 根据权利要求6所述的制作方法，其中，所述在衬底基板上形成半导体的图形之前，在所述衬底基板表面形成缓冲层。
  10. 根据权利要求6所述的制作方法，其中，所述在所述衬底基板上形成半导体的图形的步骤包括：
    利用物理气相沉积工艺在衬底基板上沉积一层a-Si薄膜，然后利用所述第一掩膜板图案对a-Si薄膜进行湿法蚀刻，形成第一薄膜晶体管与第二薄膜晶体管的有源区域。
  11. 一种OLED显示装置的阵列基板，其包括：
    衬底基板；
    有源层，形成于所述衬底基板上，其中包括第一薄膜晶体管的沟道掺杂区、源极掺杂区及漏极掺杂区，以及第二薄膜晶体管的沟道掺杂区、源极掺杂区及漏极掺杂区；
    栅极绝缘层，形成于所述衬底基板上；
    第一金属层，形成于所述衬底基板上，其中包括所述第一薄膜晶体管的栅极，以及所述第二薄膜晶体管的栅极；
    中间介质层，形成于所述衬底基板上；
    过孔，贯穿于所述中间介质层与栅极绝缘层；
    第二金属层，形成于所述衬底基板上，其中包括所述第一薄膜晶体管的源极与漏极、所述第二薄膜晶体管源极与的漏极以及数据线与像素电极；
    其中，所述第一薄膜晶体管的源极连接所述数据线，所述第一薄膜晶体管的漏极连接所述第二薄膜晶体管的栅极，所述第二薄膜晶体管的漏极连接所述像素电极。
  12. 根据权利要求11的阵列基板，其中，在所述衬底基板上形成保护层，并蚀刻掉所述像素电极表面的保护层。
  13. 根据权利要求11的阵列基板，其中，在所述衬底基板上形成空穴注入层及空穴传输层。
  14. 根据权利要求11所述的阵列基板，其中，所述第二金属层选用石墨烯薄膜材料。
  15. 根据权利要求11所述的阵列基板，其中，在所述有源层与所述衬底基板之间，形成有缓冲层。
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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106057825A (zh) * 2016-08-03 2016-10-26 深圳市华星光电技术有限公司 Oled显示装置的阵列基板及其制造方法
CN107393934B (zh) 2017-08-14 2020-02-21 京东方科技集团股份有限公司 一种阵列基板、其制作方法及显示装置
CN107482064B (zh) * 2017-08-28 2019-10-25 武汉华星光电半导体显示技术有限公司 薄膜晶体管及其制作方法以及阵列基板
CN208489194U (zh) 2018-05-23 2019-02-12 京东方科技集团股份有限公司 阵列基板、显示面板及显示装置
CN109148483B (zh) * 2018-08-22 2021-07-23 武汉华星光电半导体显示技术有限公司 阵列基板的制作方法及阵列基板
CN111725243B (zh) * 2020-07-27 2025-08-05 成都京东方显示科技有限公司 低温多晶氧化物阵列基板及其制作方法
CN112838100B (zh) * 2021-01-07 2023-08-01 深圳市华星光电半导体显示技术有限公司 发光面板及其制作方法
KR20230069360A (ko) * 2021-11-12 2023-05-19 엘지디스플레이 주식회사 표시장치
CN114695391A (zh) * 2022-03-21 2022-07-01 广州华星光电半导体显示技术有限公司 阵列基板及其制备方法、显示面板
CN114582896B (zh) * 2022-04-29 2022-07-26 惠科股份有限公司 像素结构、阵列基板及制作方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050253171A1 (en) * 2004-05-17 2005-11-17 Tae-Wook Kang Organic light emitting display and method of fabricating the same
US20110186847A1 (en) * 2010-02-03 2011-08-04 Samsung Mobile Display Co., Ltd. Organic light emitting diode display and fabricating method of the same
CN102655118A (zh) * 2012-01-10 2012-09-05 京东方科技集团股份有限公司 一种amoled器件及制作方法
CN103489827A (zh) * 2013-09-27 2014-01-01 京东方科技集团股份有限公司 一种薄膜晶体管驱动背板及其制作方法、显示面板
CN203445123U (zh) * 2013-09-27 2014-02-19 京东方科技集团股份有限公司 一种薄膜晶体管驱动背板、显示面板
CN106057825A (zh) * 2016-08-03 2016-10-26 深圳市华星光电技术有限公司 Oled显示装置的阵列基板及其制造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100458714B1 (ko) * 2001-11-06 2004-12-03 네오폴리((주)) Ｏｅｌｄ용 결정질 실리콘 박막트랜지스터 패널 및 제작방법
CN102683276B (zh) 2012-03-02 2015-03-11 京东方科技集团股份有限公司 一种像素驱动电路及其制备方法、阵列基板
CN104078424B (zh) * 2014-06-30 2017-02-15 京东方科技集团股份有限公司 低温多晶硅tft阵列基板及其制备方法、显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050253171A1 (en) * 2004-05-17 2005-11-17 Tae-Wook Kang Organic light emitting display and method of fabricating the same
US20110186847A1 (en) * 2010-02-03 2011-08-04 Samsung Mobile Display Co., Ltd. Organic light emitting diode display and fabricating method of the same
CN102655118A (zh) * 2012-01-10 2012-09-05 京东方科技集团股份有限公司 一种amoled器件及制作方法
CN103489827A (zh) * 2013-09-27 2014-01-01 京东方科技集团股份有限公司 一种薄膜晶体管驱动背板及其制作方法、显示面板
CN203445123U (zh) * 2013-09-27 2014-02-19 京东方科技集团股份有限公司 一种薄膜晶体管驱动背板、显示面板
CN106057825A (zh) * 2016-08-03 2016-10-26 深圳市华星光电技术有限公司 Oled显示装置的阵列基板及其制造方法

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