WO2018113452A1 - 多层全息天线中AlAs-Ge-AlAs结构基等离子pin二极管的制造方法 - Google Patents

多层全息天线中AlAs-Ge-AlAs结构基等离子pin二极管的制造方法 Download PDF

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WO2018113452A1
WO2018113452A1 PCT/CN2017/110915 CN2017110915W WO2018113452A1 WO 2018113452 A1 WO2018113452 A1 WO 2018113452A1 CN 2017110915 W CN2017110915 W CN 2017110915W WO 2018113452 A1 WO2018113452 A1 WO 2018113452A1
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alas
type
layer
pin diode
bias line
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PCT/CN2017/110915
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English (en)
French (fr)
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尹晓雪
张亮
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西安科锐盛创新科技有限公司
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Priority to JP2019534804A priority Critical patent/JP6839792B2/ja
Priority to US15/851,783 priority patent/US10304824B2/en
Publication of WO2018113452A1 publication Critical patent/WO2018113452A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
    • H01Q1/38—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith formed by a conductive layer on an insulating support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q23/00—Antennas with active circuits or circuit elements integrated within them or attached to them
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q7/00—Loop antennas with a substantially uniform current distribution around the loop and having a directional radiation pattern in a plane perpendicular to the plane of the loop

Definitions

  • the invention relates to the field of manufacturing electronic components, and in particular to a method for manufacturing an AlAs-Ge-AlAs structure-based plasma pin diode in a multilayer holographic antenna.
  • the holographic antenna can meet the actual requirements of users in certain occasions and has a good application prospect.
  • Reconfigurable antennas especially frequency reconfigurable antennas, can operate at multiple frequencies, greatly expanding the range of applications and receiving wide attention.
  • the use of materials and processes to produce frequency reconfigurable holographic antennas is an important and significant issue.
  • the materials used in pin diodes for reconfigurable antennas at home and abroad are all bulk silicon materials.
  • This material has a low carrier mobility in the intrinsic region, affecting the carrier concentration of the pin diode intrinsic region, and thus affecting The solid plasma concentration; and the P and N regions of the structure are mostly formed by an implantation process, which requires a large injection dose and energy, requires high equipment, and is incompatible with existing processes;
  • the junction depth is deeper, but at the same time, the area of the P region and the N region is larger, the integration degree is low, and the doping concentration is not uniform, which affects the electrical performance of the pin diode, resulting in poor controllability of the solid plasma concentration and distribution.
  • the present invention provides a method for manufacturing an AlAs-Ge-AlAs structure-based plasma pin diode in a multilayer holographic antenna.
  • an embodiment of the present invention provides a method for manufacturing an AlAs-Ge-AlAs structure-based plasma pin diode in a multilayer holographic antenna, wherein the pin diode is used to prepare the holographic antenna, and the holographic antenna includes: a semiconductor substrate (11), an antenna module (13), a first holographic ring (15), and a second holographic ring (17); the antenna module (13), the first holographic ring (15), and the The two holographic rings (17) are all fabricated on the semiconductor substrate (11) by a semiconductor process; wherein the antenna module (13), the first holographic ring (15) and the second holographic circle Each of the rings (17) includes a string of pin diodes connected in series;
  • the manufacturing method includes:
  • step (e) includes:
  • the second protective layer includes a second SiO 2 layer and a second SiN layer; and correspondingly, the step (e1) includes:
  • step (f) the method further includes:
  • step (f) includes:
  • step (f) the method further includes:
  • step (g) includes:
  • the antenna module (13) includes a first pin diode antenna arm (1301), a second pin diode antenna arm (1302), a coaxial feed line (1303), and a first DC bias line. (1304), a second DC bias line (1305), a third DC bias line (1306), a fourth DC bias line (1307), a fifth DC bias line (1308), and a sixth DC bias line (1309), a seventh DC bias line (1310), and an eighth DC bias line (1311);
  • the inner core wire and the outer conductor of the coaxial feed line (1303) are respectively soldered to the first DC bias line (1304) and the second DC bias line (1305); the first straight a flow bias line (1304), the fifth DC bias line (1308), the third DC bias line (1306), and the fourth DC bias line (1307) along the first pin diode
  • the length direction of the antenna arm (1301) is electrically connected to the first pin diode antenna arm (1301);
  • the second DC bias line (1305), the sixth DC bias line (1309), the seventh DC bias line (1310), and the eighth DC bias line (1311) are along The length direction of the second pin diode antenna arm (1302) is electrically connected to the second pin diode antenna arm (1302), respectively.
  • the pin diode string comprises a plurality of pin diodes, the pin diode comprising a P+ region (27), an N+ region (26) and an intrinsic region (22), and further comprising a first metal contact a region (23) and a second metal contact region (24);
  • One end of the first metal contact region (23) is electrically connected to the P+ region (27) and the other end is electrically connected to a DC bias line (1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311, 15011, 17011).
  • a DC bias line (1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311, 15011, 17011).
  • the second metal contact region (24) of the adjacent pin diode one end of the second metal contact region (24) is electrically connected to the N+ region (26) and the other end is electrically connected to the DC A bias line (1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311, 15011, 17011) or the first metal contact region (23) of the adjacent pin diode.
  • the holographic antenna further includes at least one third holographic ring (19) disposed outside the second holographic ring (17) and fabricated on the semiconductor substrate by a semiconductor process. (11) Upper.
  • the germanium material used in the pin diode can effectively increase the solid plasma concentration of the pin diode due to its high mobility and large carrier lifetime;
  • the pin diode adopts a heterojunction structure. Since the i region is Ge, the carrier mobility is high and the forbidden band width is relatively narrow.
  • the polycrystalline AlAs are filled in the P and N regions to form a heterojunction structure, and the AlAs material is formed.
  • the forbidden band width is larger than Ge, so it can produce a high injection ratio and improve device performance;
  • the pin diode adopts a heterojunction structure, and the lattice mismatch of the Ge in the i region and the polycrystalline AlAs in the P and N regions is relatively low, so there are few defects at the interface of the heterojunction, thereby improving the device. performance;
  • the pin diode adopts an etching-based deep trench dielectric isolation process, which effectively increases the breakdown voltage of the device and suppresses the influence of leakage current on device performance.
  • FIG. 1 is a schematic structural diagram of a reconfigurable multi-layer holographic antenna according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of a method for fabricating a base plasma pin diode of an AlAs-Ge-AlAs structure in a multilayer holographic antenna according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of an antenna module according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a first ring unit according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a second ring unit according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a base plasma pin diode of an AlAs-Ge-AlAs structure in a multilayer holographic antenna according to an embodiment of the present invention
  • FIG. 7 is a schematic structural diagram of a base plasma pin diode string of an AlAs-Ge-AlAs structure in a multilayer holographic antenna according to an embodiment of the present invention
  • FIGS. 8a-8r are schematic diagrams showing a manufacturing method of an AlAs-Ge-AlAs structure-based plasma pin diode in another multilayer holographic antenna according to an embodiment of the present invention
  • FIG. 9 is a schematic structural diagram of a base plasma pin diode of an AlAs-Ge-AlAs structure in another multilayer holographic antenna according to an embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of another reconfigurable multi-layer holographic antenna according to an embodiment of the present invention.
  • the invention provides a method and a device for fabricating a base plasma pin diode suitable for forming an AlAs-Ge-AlAs structure of a solid plasma reconfigurable antenna.
  • the base plasma pin diode of the AlAs-Ge-AlAs structure is formed by a germanium-on-insulator (GeOI) on a dielectric substrate to form a lateral pin diode, and when a DC bias is applied, a direct current is formed on the surface thereof.
  • a solid-state plasma composed of free carriers (electrons and holes), which has a class
  • the metal characteristic that is, the reflection of electromagnetic waves, its reflection characteristics are closely related to the microwave transmission characteristics, concentration and distribution of the surface plasma.
  • the GeOI lateral solid-state plasma pin diode plasma reconfigurable antenna can be assembled by array of GeOI lateral solid-state plasma pin diodes, and selectively connected by a solid-state plasma pin diode in an external control array to form a dynamic solid-state plasma.
  • Stripe, with the function of an antenna, has a transmitting and receiving function for a specific electromagnetic wave, and the antenna can change the shape and distribution of the solid plasma strip by selective conduction of a solid plasma pin diode in the array, thereby realizing antenna reconstruction.
  • National defense communication and radar technology have important application prospects.
  • the embodiment of the present invention provides a method for fabricating an AlAs-Ge-AlAs structure-based plasma pin diode in a multilayer holographic antenna.
  • the pin diode is used to prepare the holographic antenna.
  • FIG. 1 is an embodiment of the present invention.
  • a schematic structural diagram of a reconfigurable multi-layer holographic antenna comprises: a semiconductor substrate (11), an antenna module (13), a first holographic ring (15) and a second holographic ring (17)
  • the antenna module (13), the first holographic ring (15), and the second holographic ring (17) are all fabricated on the semiconductor substrate (11) by a semiconductor process;
  • the antenna module (13), the first holographic ring (15) and the second holographic ring (17) each include a string of pin diodes connected in series;
  • FIG. 2 is a schematic diagram of a method for fabricating a base plasma pin diode of an AlAs-Ge-AlAs structure in a multilayer holographic antenna according to an embodiment of the present invention.
  • the manufacturing method includes:
  • the reason why the GeOI substrate is used in this step is that for a solid plasma antenna, since it requires good microwave characteristics, a solid plasma pin diode needs to have good isolation characteristics and a carrier, that is, a solid plasma, in order to meet this demand.
  • the ability of the body to define, while the GeOI substrate is capable of forming a pin isolation region with the isolation trench, and the silicon dioxide (SiO 2 ) can also define the carrier, ie, the solid plasma, in the top layer Ge, so GeOI is preferably used.
  • the carrier mobility of the germanium material is relatively large, a high plasma concentration can be formed in the I region to improve the performance of the device.
  • the advantage of using the method of the present embodiment to form the first protective layer is that the stress of silicon nitride (SiN) is isolated by the looseness of silicon dioxide (SiO 2 ), so that it cannot be conducted into the top Ge, ensuring the top Ge. Stable performance; based on the high selectivity of silicon nitride (SiN) and Ge in dry etching, silicon nitride (SiN) is used as a masking film for dry etching, which is easy to implement.
  • the number of layers of the protective layer and the material of the protective layer are not limited herein as long as a protective layer can be formed.
  • the depth of the isolation trench is greater than or equal to the thickness of the top Ge, which ensures the connection of the silicon dioxide (SiO 2 ) and the oxide layer of the GeOI substrate in the subsequent trench to form a complete insulating isolation.
  • step (e) includes:
  • the depth of the P-type trench and the N-type trench is greater than the thickness of the second protective layer and smaller than the sum of the thickness of the second protective layer and the top Ge of the GeOI substrate.
  • the bottom of the P-type trench and the N-type trench are at a distance of 0.5 ⁇ m to 30 ⁇ m from the bottom of the top Ge of the GeOI substrate, forming a deep trench generally considered to form a P-type and an N-type active region.
  • the impurity distribution is uniform, the P, N regions with high doping concentration and the steep Pi and Ni junctions can be formed to improve the plasma concentration in the i region.
  • the second protective layer comprises a second SiO 2 layer and a second SiN layer; and correspondingly, step (e1) comprises:
  • step (f) the method further includes:
  • step (f) includes:
  • step (f) the method further includes:
  • step (g) includes:
  • FIG. 3 is a schematic structural diagram of an antenna module according to an embodiment of the present invention.
  • the antenna module (13) includes a first pin diode antenna arm (1301), a second pin diode antenna arm (1302), a coaxial feed line (1303), a first DC bias line (1304), and a second DC bias.
  • the inner core wire and the outer conductor of the coaxial feed line (1303) are respectively soldered to the first DC bias line (1304) and the second DC bias line (1305); the first straight a flow bias line (1304), the fifth DC bias line (1308), the third DC bias line (1306), and the fourth DC bias line (1307) along the first pin diode
  • the length direction of the antenna arm (1301) is electrically connected to the first pin diode antenna arm (1301);
  • the second DC bias line (1305), the sixth DC bias line (1309), the seventh DC bias line (1310), and the eighth DC bias line (1311) are along The length direction of the second pin diode antenna arm (1302) is electrically connected to the second pin diode antenna arm (1302), respectively.
  • the first pin diode antenna arm (1301) includes a first pin diode string (w1), a second pin diode string (w2), and the third (pin) diode string (w3) connected in series.
  • the second pin diode antenna arm (1302) includes a fourth pin diode string (w4), a fifth pin diode string (w5), and a sixth pin diode string (w6) serially connected in series and the first a pin diode string (w1) and the sixth pin diode string (w6), the second pin diode string (w2) and the fifth pin diode string (w5), and the third pin diode string (w3)
  • the same number of pin diodes are included with the fourth pin diode string (w4), respectively.
  • FIG. 4 is a schematic structural diagram of a first ring unit according to an embodiment of the present invention.
  • the first hologram ring 15 includes a plurality of first ring units (1501) uniformly arranged in a ring shape, and the first ring unit (1501) includes a ninth DC bias line 15011 and a seventh pin diode.
  • a string (w7), the ninth DC bias line (15011) is electrically connected to both ends of the seventh pin diode string (w7).
  • FIG. 5 is a schematic structural diagram of a second ring unit according to an embodiment of the present invention.
  • the second holographic ring (17) includes a plurality of second ring units (1701) uniformly arranged in a ring shape, and the second ring unit (1701) includes a tenth DC bias line (17011) and The eighth pin diode string (w8), the tenth DC bias line (17011) is electrically connected to both ends of the eighth pin diode string (w8).
  • the pin diode string includes a plurality of pin diodes
  • FIG. 6 is a schematic structural diagram of a base plasma pin diode of an AlAs-Ge-AlAs structure in a multilayer holographic antenna according to an embodiment of the present invention
  • FIG. 7 is an AlAs in a multilayer holographic antenna according to an embodiment of the present invention
  • Schematic diagram of a base-plasma pin diode string of a Ge-AlAs structure As shown in FIG. 6, the pin diode includes a P+ region (27), an N+ region (26), and an intrinsic region (22), and further includes a first metal contact region (23) and a second metal contact region (24). ;among them,
  • One end of the first metal contact region (23) is electrically connected to the P+ region (27) and the other end is electrically connected to a DC bias line (1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311, 15011, 17011).
  • a DC bias line (1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311, 15011, 17011).
  • the second metal contact region (24) of the adjacent pin diode one end of the second metal contact region (24) is electrically connected to the N+ region (26) and the other end is electrically connected to the DC A bias line (1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311, 15011, 17011) or the first metal contact region (23) of the adjacent pin diode.
  • FIG. 10 is a schematic structural diagram of another reconfigurable multi-layer holographic antenna according to an embodiment of the present invention.
  • the holographic antenna further includes at least one third holographic ring (19) disposed outside the second holographic ring (17) and fabricated on the semiconductor substrate (11) by a semiconductor process.
  • the germanium material used in the pin diode can effectively increase the solid plasma concentration of the pin diode due to its high mobility and large carrier lifetime;
  • the pin diode adopts a heterojunction structure. Since the i region is Ge, the carrier mobility is high and the forbidden band width is relatively narrow.
  • the polycrystalline AlAs are filled in the P and N regions to form a heterojunction structure, and the AlAs material is formed.
  • the forbidden band width is larger than Ge, so it can produce a high injection ratio and improve device performance;
  • the pin diode adopts a heterojunction structure, and the lattice mismatch of the Ge in the i region and the polycrystalline AlAs in the P and N regions is relatively low, so there are few defects at the interface of the heterojunction, thereby improving the device. performance;
  • the pin diode adopts an etching-based deep trench dielectric isolation process, which effectively increases the breakdown voltage of the device and suppresses the influence of leakage current on device performance.
  • FIG. 8a - FIG. 8r are another multi-layer holographic antenna according to an embodiment of the present invention.
  • Step 1 the substrate material preparation steps:
  • the first Si 3 N 4 /SiN layer 202 and the first SiO 2 layer 201 are removed by a chemical mechanical polishing (CMP) method to planarize the surface of the GeOI substrate;
  • CMP chemical mechanical polishing
  • Step 3 Preparation steps of deep grooves in P and N zones:
  • a two-layer material is continuously deposited on the substrate by a CVD method, the first layer being a second SiO 2 layer 601 having a thickness of 300 nm, and the second layer being a second Si 3 having a thickness of 500 nm.
  • the P, N region deep trenches are photolithographically, the P, N regions, the second Si 3 N 4 /SiN layer 602 and the second SiO 2 layer 601 are wet etched to form P and N regions. Using a dry etching, a deep trench 701 having a width of 4 ⁇ m and a depth of 5 ⁇ m is formed in the P and N regions, and the lengths of the P and N regions are determined according to the application in the prepared antenna;
  • the oxide layer 801 of the inner walls of the P and N regions is removed by a wet etching process.
  • Step 4 P, N contact zone preparation steps:
  • a polycrystalline AlAs1001 is deposited in a P- and N-region trench by a Metal-organic Chemical Vapor Deposition (MOCVD) process, and the trench is filled;
  • MOCVD Metal-organic Chemical Vapor Deposition
  • a layer of polycrystalline AlAs1201 is deposited on the surface by CVD method, and the thickness is 200-500 nm;
  • the active region of the lithography P region is subjected to P+ implantation by means of a gel ion implantation method, so that the doping concentration of the source region of the P region is 0.5 ⁇ 10 20 cm -3 , and the photoresist is removed. Forming a P contact 1301;
  • Step 5 forming a PIN diode step:
  • Si 3 N 4 /SiN is deposited to form a passivation layer 1801, and a lithographic PAD is formed to form a PIN diode as a material for preparing a solid plasma antenna.
  • the pin diode applied to the solid plasma reconfigurable antenna prepared by the invention firstly increases the solid plasma concentration of the pin diode due to its high mobility and large carrier lifetime; Due to the poor thermal stability of the oxide GeO, the treatment of the planarization of the deep trench sidewalls in the P and N regions can be automatically performed in a high temperature environment, simplifying the manufacturing method of the material; again, the invention is applied to solid plasma.
  • the GeOI-based pin diode of the reconfigurable antenna uses an etching-based deep trench dielectric isolation process, which effectively increases the breakdown voltage of the device and suppresses the influence of leakage current on device performance.
  • FIG. 9 is a schematic structural diagram of a base plasma pin diode of an AlAs-Ge-AlAs structure in another multilayer holographic antenna according to an embodiment of the present invention.
  • the base plasma pin diode of the AlAs-Ge-AlAs structure is fabricated by the above-described manufacturing method as shown in FIG. 2, specifically, the base plasma pin diode of the AlAs-Ge-AlAs structure is formed on the GeOI substrate 301, and The P region 304, the N region 305 of the pin diode, and the I region laterally between the P region 304 and the N region 305 are both located within the top Ge layer 302 of the GeOI substrate.
  • the pin diode may be separated by STI deep trenches, that is, the P region 304 and the N region 305 are respectively disposed with an isolation trench 303, and the isolation trench 303 has a depth greater than or equal to the thickness of the top Ge layer 302.
  • the germanium material used in the pin diode can effectively increase the solid plasma concentration of the pin diode due to its high mobility and large carrier lifetime;
  • the pin diode adopts a heterojunction structure. Since the i region is Ge, the carrier mobility is high and the forbidden band width is relatively narrow.
  • the polycrystalline AlAs are filled in the P and N regions to form a heterojunction structure, and the AlAs material is formed.
  • the forbidden band width is larger than Ge, so it can produce a high injection ratio and improve device performance;
  • the pin diode adopts a heterojunction structure, and the lattice mismatch of the Ge in the i region and the polycrystalline AlAs in the P and N regions is relatively low, so there are few defects at the interface of the heterojunction, thereby improving the device. performance;
  • the pin diode adopts an etching-based deep trench dielectric isolation process, which effectively increases the breakdown voltage of the device and suppresses the influence of leakage current on device performance.

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Abstract

一种多层全息天线中AlAs-Ge-AlAs结构基等离子pin二极管的制造方法，包括：选取GeOI衬底，并在GeOI衬底内设置隔离区；刻蚀GeOI衬底形成P型沟槽和N型沟槽；在P型沟槽和N型沟槽内淀积AlAs材料，并在P型沟槽和N型沟槽内的AlAs材料进行离子注入形成P型有源区和N型有源区；在P型有源区和N型有源区表面形成引线，以完成AlAs-Ge-AlAs结构基等离子pin二极管的制备。实施例利用深槽隔离技术及离子注入工艺能够制备并提供适用于形成固态等离子天线的高性能Ge基等离子pin二极管。

Description

多层全息天线中AlAs-Ge-AlAs结构基等离子pin二极管的制造方法 技术领域
本发明涉及电子元器件的制造领域，特别涉及一种多层全息天线中AlAs-Ge-AlAs结构基等离子pin二极管的制造方法。
背景技术
全息天线因为其具有全息结构，能在特定的场合很好地满足用户的实际要求，具有较好的应用前景。可重构天线，尤其是频率可重构天线，能工作在多个频率的条件下，极大地扩展了应用范围，受到广泛的关注。采用何种材料和工艺以生产出频率可重构全息天线是个很重要也很有意义的问题。
目前，国内外应用于可重构天线的pin二极管采用的材料均为体硅材料，此材料存在本征区载流子迁移率较低问题，影响pin二极管本征区载流子浓度，进而影响其固态等离子体浓度；并且该结构的P区与N区大多采用注入工艺形成，此方法要求注入剂量和能量较大，对设备要求高，且与现有工艺不兼容；而采用扩散工艺，虽结深较深，但同时P区与N区的面积较大，集成度低，掺杂浓度不均匀，影响pin二极管的电学性能，导致固态等离子体浓度和分布的可控性差。
发明内容
因此，为解决现有技术存在的技术缺陷和不足，本发明提出一种多层全息天线中AlAs-Ge-AlAs结构基等离子pin二极管的制造方法。
具体的，本发明实施例提供一种多层全息天线中AlAs-Ge-AlAs结构基等离子pin二极管的制造方法，所述pin二极管用于制备所述全息天线，所述全息天线包括：半导体基片(11)、天线模块(13)、第一全息圆环(15)及第二全息圆环(17)；所述天线模块(13)、所述第一全息圆环(15)及所述第二全息圆环(17)均采用半导体工艺制作于所述半导体基片(11)上；其中，所述天线模块(13)、所述第一全息圆环(15)及所述第二全息圆环(17)均包括依次串接的pin二极管串；
所述制造方法包括：
(a)选取GeOI衬底，在所述GeOI衬底表面生成SiO2材料以形成第一SiO2层，在所述第一SiO2层表面生成SiN材料以形成第一SiN层，其中，所述第一SiO2层和所述第一SiN层构成所述GeOI衬底表面的第一保护层；
(b)利用光刻工艺在所述第一保护层上形成第一隔离区图形；
(c)利用干法刻蚀工艺，在所述第一隔离区图形的指定位置处刻蚀所述第一保护层及所述GeOI衬底以形成隔离槽，且所述隔离槽的深度大于等于所述GeOI衬底的顶层Ge的厚 度；
(d)填充所述隔离槽以形成隔离区；
(e)刻蚀所述GeOI衬底形成P型沟槽和N型沟槽；
(f)在所述P型沟槽和所述N型沟槽内淀积AlAs材料，并对所述P型沟槽和所述N型沟槽内的AlAs材料进行离子注入形成P型有源区和N型有源区；
(g)在所述P型有源区和所述N型有源区表面形成引线，以完成所述AlAs-Ge-AlAs结构的基等离子pin二极管的制备。
在上述实施例的基础上，步骤(e)包括：
(e1)在所述GeOI衬底表面形成第二保护层；
(e2)利用光刻工艺在所述第二保护层上形成第二隔离区图形；
(e3)利用干法刻蚀工艺在所述第二隔离区图形的指定位置处刻蚀所述第二保护层及所述GeOI衬底的顶层Ge层以在所述顶层Ge层内形成所述P型沟槽和所述N型沟槽。
在上述实施例的基础上，所述第二保护层包括第二SiO2层和第二SiN层；相应地，步骤(e1)包括：
(e11)在所述GeOI衬底表面生成SiO2材料以形成第二SiO2层；
(e12)在所述第二SiO2层表面生成SiN材料以形成第二SiN层。
在上述实施例的基础上，步骤(f)之前，还包括：
(x1)氧化所述P型沟槽和所述N型沟槽以使所述P型沟槽和所述N型沟槽的内壁形成氧化层；
(x2)利用湿法刻蚀工艺刻蚀所述P型沟槽和所述N型沟槽内壁的氧化层以完成所述P型沟槽和所述N型沟槽内壁的平整化。
在上述实施例的基础上，步骤(f)包括：
(f1)利用MOCVD工艺，在所述P型沟槽和所述N型沟槽内及整个衬底表面淀积AlAs材料；
(f2)利用CMP工艺，平整化处理GeOI衬底后，在GeOI衬底上形成AlAs层；
(f3)光刻AlAs层，并采用带胶离子注入的方法对所述P型沟槽和所述N型沟槽所在位置分别注入P型杂质和N型杂质以形成所述P型有源区和所述N型有源区且同时形成P型接触区和N型接触区；
(f4)去除光刻胶；
(f5)利用湿法刻蚀去除P型接触区和N型接触区以外的AlAs材料。
在上述实施例的基础上，步骤(f)之后，还包括：
(y1)在整个衬底表面生成SiO2材料；
(y2)利用退火工艺激活所述P型有源区及所述N型有源区中的杂质。
在上述实施例的基础上，步骤(g)包括：
(g1)利用各向异性刻蚀工艺刻蚀掉所述P型接触区和所述N型接触区表面指定位置的SiO2材料以形成所述引线孔；
(g2)向所述引线孔内淀积金属材料，对整个衬底材料进行钝化处理并光刻PAD以形成所述AlAs-Ge-AlAs结构的基等离子pin二极管。
在上述实施例的基础上，所述天线模块(13)包括第一pin二极管天线臂(1301)、第二pin二极管天线臂(1302)、同轴馈线(1303)、第一直流偏置线(1304)、第二直流偏置线(1305)、第三直流偏置线(1306)、第四直流偏置线(1307)、第五直流偏置线(1308)、第六直流偏置线(1309)、第七直流偏置线(1310)、第八直流偏置线(1311)；
其中，所述同轴馈线(1303)的内芯线和外导体分别焊接于所述第一直流偏置线(1304)和所述第二直流偏置线(1305)；所述第一直流偏置线(1304)、所述第五直流偏置线(1308)、所述第三直流偏置线(1306)及所述第四直流偏置线(1307)沿所述第一pin二极管天线臂(1301)的长度方向分别电连接至所述第一pin二极管天线臂(1301)；
所述第二直流偏置线(1305)、所述第六直流偏置线(1309)、所述第七直流偏置线(1310)及所述第八直流偏置线(1311)沿所述第二pin二极管天线臂(1302)的长度方向分别电连接至所述第二pin二极管天线臂(1302)。
在上述实施例的基础上，所述pin二极管串包括多个pin二极管，所述pin二极管包括P+区(27)、N+区(26)和本征区(22)，且还包括第一金属接触区(23)和第二金属接触区(24)；其中，
所述第一金属接触区(23)一端电连接所述P+区(27)且另一端电连接至直流偏置线(1304、1305、1306、1307、1308、1309、1310、1311、15011、17011)或者相邻的所述pin二极管的所述第二金属接触区(24)，所述第二金属接触区(24)一端电连接所述N+区(26)且另一端电连接至所述直流偏置线(1304、1305、1306、1307、1308、1309、1310、1311、15011、17011)或者相邻的所述pin二极管的所述第一金属接触区(23)。
在上述实施例的基础上，所述全息天线还包括至少一个第三全息圆环(19)，设置于所述第二全息圆环(17)的外侧且采用半导体工艺制作于所述半导体基片(11)上。
本发明提供的多层全息天线中AlAs-Ge-AlAs结构基等离子pin二极管的制造方法具备如下优点：
(1)pin二极管所使用的锗材料，由于其高迁移率和大载流子寿命的特性，能有效提高pin二极管的固态等离子体浓度；
(2)pin二极管采用异质结结构，由于i区为Ge，其载流子迁移率高且禁带宽度比较窄，在P、N区填充多晶AlAs从而形成异质结结构，AlAs材料的禁带宽度大于Ge，故可产生高的注入比，提高器件性能；
(3)pin二极管采用异质结结构，并且i区的Ge和P、N区的多晶AlAs的晶格失配比较低，故在异质结界面处的缺陷很少，从而提高了器件的性能；
(4)pin二极管采用了一种基于刻蚀的深槽介质隔离工艺，有效地提高了器件的击穿电压，抑制了漏电流对器件性能的影响。
通过以下参考附图的详细说明，本发明的其它方面和特征变得明显。但是应当知道，该附图仅仅为解释的目的设计，而不是作为本发明的范围的限定，这是因为其应当参考附加的权利要求。还应当知道，除非另外指出，不必要依比例绘制附图，它们仅仅力图概念地说明此处描述的结构和流程。
附图概述
下面将结合附图，对本发明的具体实施方式进行详细的说明。
图1为本发明实施例提供的一种可重构多层全息天线的结构示意图；
图2为本发明实施例提供的多层全息天线中的AlAs-Ge-AlAs结构的基等离子pin二极管制造方法示意图；
图3为本发明实施例的一种天线模块的结构示意图；
图4为本发明实施例提供的一种第一环形单元的结构示意图；
图5为本发明实施例提供的一种第二环形单元的结构示意图；
图6为本发明实施例提供的一种多层全息天线中的AlAs-Ge-AlAs结构的基等离子pin二极管的结构示意图；
图7为本发明实施例提供的一种多层全息天线中的AlAs-Ge-AlAs结构的基等离子pin二极管串的结构示意图；
图8a-图8r为本发明实施例提供的另一种多层全息天线中AlAs-Ge-AlAs结构基等离子pin二极管的制造方法示意图；
图9为本发明实施例提供的另一种多层全息天线中的AlAs-Ge-AlAs结构的基等离子pin二极管的结构示意图；
图10为本发明实施例提供的另一种可重构多层全息天线的结构示意图。
本发明的较佳实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。
本发明提出了一种适用于形成固态等离子体可重构天线的AlAs-Ge-AlAs结构的基等离子pin二极管的制造方法及器件。该AlAs-Ge-AlAs结构的基等离子pin二极管是基于绝缘衬底上的锗(Germanium-On-Insulator，简称GeOI)形成横向pin二极管，其在加直流偏压时，直流电流会在其表面形成自由载流子(电子和空穴)组成的固态等离子体，该等离子体具有类 金属特性，即对电磁波具有反射作用，其反射特性与表面等离子体的微波传输特性、浓度及分布密切相关。
GeOI横向固态等离子pin二极管等离子可重构天线可以是由GeOI横向固态等离子pin二极管按阵列排列组合而成，利用外部控制阵列中的固态等离子pin二极管选择性导通，使该阵列形成动态固态等离子体条纹、具备天线的功能，对特定电磁波具有发射和接收功能，并且该天线可通过阵列中固态等离子pin二极管的选择性导通，改变固态等离子体条纹形状及分布，从而实现天线的重构，在国防通讯与雷达技术方面具有重要的应用前景。
以下，将对本发明制备的GeOI基固态等离子pin二极管的工艺流程作进一步详细描述。在图中，为了方便说明，放大或缩小了层和区域的厚度，所示大小并不代表实际尺寸。
本发明实施例提供一种多层全息天线中AlAs-Ge-AlAs结构基等离子pin二极管的制造方法，所述pin二极管用于制备所述全息天线，请参考图1，图1为本发明实施例提供的一种可重构多层全息天线的结构示意图；所述全息天线包括：半导体基片(11)、天线模块(13)、第一全息圆环(15)及第二全息圆环(17)；所述天线模块(13)、所述第一全息圆环(15)及所述第二全息圆环(17)均采用半导体工艺制作于所述半导体基片(11)上；其中，所述天线模块(13)、所述第一全息圆环(15)及所述第二全息圆环(17)均包括依次串接的pin二极管串；
请参考图2，图2为本发明实施例提供的多层全息天线中的AlAs-Ge-AlAs结构的基等离子pin二极管制造方法示意图。所述制造方法包括：
(a)选取GeOI衬底，在所述GeOI衬底表面生成SiO2材料以形成第一SiO2层，在所述第一SiO2层表面生成SiN材料以形成第一SiN层，其中，所述第一SiO2层和所述第一SiN层构成所述GeOI衬底表面的第一保护层；
其中，在本步骤中，采用GeOI衬底的原因在于，对于固态等离子天线由于其需要良好的微波特性，而固态等离子pin二极管为了满足这个需求，需要具备良好的隔离特性和载流子即固态等离子体的限定能力，而GeOI衬底由于其具有能够与隔离槽方便的形成pin隔离区域、二氧化硅(SiO2)也能够将载流子即固态等离子体限定在顶层Ge中，所以优选采用GeOI作为固态等离子pin二极管的衬底。并且，由于锗材料的载流子迁移率比较大，故可在I区内形成较高的等离子体浓度，提高器件的性能。
采用本实施例的方法形成第一保护层的好处在于：利用二氧化硅(SiO2)的疏松特性，将氮化硅(SiN)的应力隔离，使其不能传导进顶层Ge，保证了顶层Ge性能的稳定；基于氮化硅(SiN)与Ge在干法刻蚀时的高选择比，利用氮化硅(SiN)作为干法刻蚀的掩蔽膜，易于工艺实现。当然，可以理解的是，保护层的层数以及保护层的材料此处不做限制，只要能够形成保护层即可。
(b)利用光刻工艺在所述第一保护层上形成第一隔离区图形；
(c)利用干法刻蚀工艺，在所述第一隔离区图形的指定位置处刻蚀所述第一保护层及所 述GeOI衬底以形成隔离槽，且所述隔离槽的深度大于等于所述GeOI衬底的顶层Ge的厚度；
隔离槽的深度大于等于顶层Ge的厚度，保证了后续槽中二氧化硅(SiO2)与GeOI衬底的氧化层的连接，形成完整的绝缘隔离。
(d)填充所述隔离槽以形成隔离区；
(e)刻蚀所述GeOI衬底形成P型沟槽和N型沟槽；
(f)在所述P型沟槽和所述N型沟槽内淀积AlAs材料，并对所述P型沟槽和所述N型沟槽内的AlAs材料进行离子注入形成P型有源区和N型有源区；
(g)在所述P型有源区和所述N型有源区表面形成引线，以完成所述AlAs-Ge-AlAs结构的基等离子pin二极管的制备。
进一步地，在上述实施例的基础上，步骤(e)包括：
(e1)在所述GeOI衬底表面形成第二保护层；
(e2)利用光刻工艺在所述第二保护层上形成第二隔离区图形；
(e3)利用干法刻蚀工艺在所述第二隔离区图形的指定位置处刻蚀所述第二保护层及所述GeOI衬底的顶层Ge层以在所述顶层Ge层内形成所述P型沟槽和所述N型沟槽。
其中，P型沟槽和N型沟槽的深度大于第二保护层厚度且小于第二保护层与GeOI衬底顶层Ge厚度之和。优选地，该P型沟槽和N型沟槽的底部距GeOI衬底的顶层Ge底部的距离为0.5微米～30微米，形成一般认为的深槽，这样在形成P型和N型有源区时可以形成杂质分布均匀、且高掺杂浓度的P、N区和陡峭的Pi与Ni结，以利于提高i区等离子体浓度。
进一步地，在上述实施例的基础上，所述第二保护层包括第二SiO2层和第二SiN层；相应地，步骤(e1)包括：
(e11)在所述GeOI衬底表面生成SiO2材料以形成第二SiO2层；
(e12)在所述第二SiO2层表面生成SiN材料以形成第二SiN层。
这样做的好处类似于第一保护层的作用，此处不再赘述。
进一步地，在上述实施例的基础上，步骤(f)之前，还包括：
(x1)氧化所述P型沟槽和所述N型沟槽以使所述P型沟槽和所述N型沟槽的内壁形成氧化层；
(x2)利用湿法刻蚀工艺刻蚀所述P型沟槽和所述N型沟槽内壁的氧化层以完成所述P型沟槽和所述N型沟槽内壁的平整化。这样做的好处在于：可以防止沟槽侧壁的突起形成电场集中区域，造成Pi和Ni结击穿。
进一步地，在上述实施例的基础上，步骤(f)包括：
(f1)利用MOCVD工艺，在所述P型沟槽和所述N型沟槽内及整个衬底表面淀积AlAs 材料；
(f2)利用CMP工艺，平整化处理GeOI衬底后，在GeOI衬底上形成AlAs层；
(f3)光刻AlAs层，并采用带胶离子注入的方法对所述P型沟槽和所述N型沟槽所在位置分别注入P型杂质和N型杂质以形成所述P型有源区和所述N型有源区且同时形成P型接触区和N型接触区；
(f4)去除光刻胶；
(f5)利用湿法刻蚀去除P型接触区和N型接触区以外的AlAs材料。
进一步地，在上述实施例的基础上，步骤(f)之后，还包括：
(y1)在整个衬底表面生成SiO2材料；
(y2)利用退火工艺激活所述P型有源区及所述N型有源区中的杂质。
进一步地，在上述实施例的基础上，步骤(g)包括：
(g1)利用各向异性刻蚀工艺刻蚀掉所述P型接触区和所述N型接触区表面指定位置的SiO2材料以形成所述引线孔；
(g2)向所述引线孔内淀积金属材料，对整个衬底材料进行钝化处理并光刻PAD以形成所述AlAs-Ge-AlAs结构的基等离子pin二极管。
进一步地，在上述实施例的基础上，请参见图3，图3为本发明实施例的一种天线模块的结构示意图。所述天线模块(13)包括第一pin二极管天线臂(1301)、第二pin二极管天线臂(1302)、同轴馈线(1303)、第一直流偏置线(1304)、第二直流偏置线(1305)、第三直流偏置线(1306)、第四直流偏置线(1307)、第五直流偏置线(1308)、第六直流偏置线(1309)、第七直流偏置线(1310)、第八直流偏置线(1311)；
其中，所述同轴馈线(1303)的内芯线和外导体分别焊接于所述第一直流偏置线(1304)和所述第二直流偏置线(1305)；所述第一直流偏置线(1304)、所述第五直流偏置线(1308)、所述第三直流偏置线(1306)及所述第四直流偏置线(1307)沿所述第一pin二极管天线臂(1301)的长度方向分别电连接至所述第一pin二极管天线臂(1301)；
所述第二直流偏置线(1305)、所述第六直流偏置线(1309)、所述第七直流偏置线(1310)及所述第八直流偏置线(1311)沿所述第二pin二极管天线臂(1302)的长度方向分别电连接至所述第二pin二极管天线臂(1302)。
可选地，所述第一pin二极管天线臂(1301)包括依次串接的第一pin二极管串(w1)、第二pin二极管串(w2)及所述第三(pin)二极管串(w3)，所述第二pin二极管天线臂(1302)包括依次串接的第四pin二极管串(w4)、第五pin二极管串(w5)及所述第六pin二极管串(w6)且所述第一pin二极管串(w1)与所述第六pin二极管串(w6)、所述第二pin二极管串(w2)与所述第五pin二极管串(w5)、所述第三pin二极管串(w3)与所述第四pin二极管串(w4)分别包括同等数量的pin二极管。
进一步地，请参见图4，图4为本发明实施例提供的一种第一环形单元的结构示意图。所述第一全息圆环15包括多个呈环状均匀排列的多个第一环形单元(1501)，且所述第一环形单元(1501)包括第九直流偏置线15011及第七pin二极管串(w7)，所述第九直流偏置线(15011)电连接至所述第七pin二极管串(w7)的两端。
进一步地，请参见图5，图5为本发明实施例提供的一种第二环形单元的结构示意图。所述第二全息圆环(17)包括多个呈环状均匀排列的多个第二环形单元(1701)，且所述第二环形单元(1701)包括第十直流偏置线(17011)及所述第八pin二极管串(w8)，所述第十直流偏置线(17011)电连接至所述第八pin二极管串(w8)的两端。
进一步地，在上述实施例的基础上，所述pin二极管串包括多个pin二极管，请参考图6和图7。图6为本发明实施例提供的一种多层全息天线中的AlAs-Ge-AlAs结构的基等离子pin二极管的结构示意图；图7为本发明实施例提供的一种多层全息天线中的AlAs-Ge-AlAs结构的基等离子pin二极管串的结构示意图。如图6所示，所述pin二极管包括P+区(27)、N+区(26)和本征区(22)，且还包括第一金属接触区(23)和第二金属接触区(24)；其中，
所述第一金属接触区(23)一端电连接所述P+区(27)且另一端电连接至直流偏置线(1304、1305、1306、1307、1308、1309、1310、1311、15011、17011)或者相邻的所述pin二极管的所述第二金属接触区(24)，所述第二金属接触区(24)一端电连接所述N+区(26)且另一端电连接至所述直流偏置线(1304、1305、1306、1307、1308、1309、1310、1311、15011、17011)或者相邻的所述pin二极管的所述第一金属接触区(23)。
进一步地，在上述实施例的基础上，请参考图10，图10为本发明实施例提供的另一种可重构多层全息天线的结构示意图。所述全息天线还包括至少一个第三全息圆环(19)，设置于所述第二全息圆环(17)的外侧且采用半导体工艺制作于所述半导体基片(11)上。
本发明提供的AlAs-Ge-AlAs结构的基等离子pin二极管的制造方法具备如下优点：
(1)pin二极管所使用的锗材料，由于其高迁移率和大载流子寿命的特性，能有效提高pin二极管的固态等离子体浓度；
(2)pin二极管采用异质结结构，由于i区为Ge，其载流子迁移率高且禁带宽度比较窄，在P、N区填充多晶AlAs从而形成异质结结构，AlAs材料的禁带宽度大于Ge，故可产生高的注入比，提高器件性能；
(3)pin二极管采用异质结结构，并且i区的Ge和P、N区的多晶AlAs的晶格失配比较低，故在异质结界面处的缺陷很少，从而提高了器件的性能；
(4)pin二极管采用了一种基于刻蚀的深槽介质隔离工艺，有效地提高了器件的击穿电压，抑制了漏电流对器件性能的影响。
请参见图8a-图8r，图8a-图8r为本发明实施例提供的另一种多层全息天线中 AlAs-Ge-AlAs结构基等离子pin二极管的制造方法示意图，在上述实施例的基础上，以制备沟道长度为22nm(固态等离子区域长度为100微米)的AlAs-Ge-AlAs结构的基等离子pin二极管为例进行详细说明，具体步骤如下：
步骤1，衬底材料制备步骤：
(1a)如图8a所示，选取(100)晶向，掺杂类型为p型，掺杂浓度为1014cm-3的GeOI衬底片101，顶层Ge的厚度为50μm；
(1b)如图8b所示，采用化学气相沉积(Chemical vapor deposition,简称CVD)的方法，在GeOI衬底上淀积一层40nm厚度的第一SiO2层201；
(1c)采用化学气相淀积的方法，在衬底上淀积一层2μm厚度的第一Si3N4/SiN层202；
步骤2，隔离制备步骤：
(2a)如图8c所示，通过光刻工艺在上述保护层上形成隔离区，湿法刻蚀隔离区第一Si3N4/SiN层202，形成隔离区图形；采用干法刻蚀，在隔离区形成宽5μm，深为50μm的深隔离槽301；
(2b)如图8d所示，采用CVD的方法，淀积SiO2401将该深隔离槽填满；
(2c)如图8e所示，采用化学机械抛光(Chemical Mechanical Polishing,简称CMP)方法，去除表面第一Si3N4/SiN层202和第一SiO2层201，使GeOI衬底表面平整；
步骤3，P、N区深槽制备步骤：
(3a)如图8f所示，采用CVD方法，在衬底上连续淀积延二层材料，第一层为300nm厚度的第二SiO2层601，第二层为500nm厚度的第二Si3N4/SiN层602；
(3b)如图8g所示，光刻P、N区深槽，湿法刻蚀P、N区第二Si3N4/SiN层602和第二SiO2层601，形成P、N区图形；采用干法刻蚀，在P、N区形成宽4μm，深5μm的深槽701，P、N区槽的长度根据在所制备的天线中的应用情况而确定；
(3c)如图8h所示，在850℃下，高温处理10分钟，氧化槽内壁形成氧化层801，以使P、N区槽内壁平整；
(3d)如图8i所示，利用湿法刻蚀工艺去除P、N区槽内壁的氧化层801。
步骤4，P、N接触区制备步骤：
(4a)如图8j所示，利用有机金属化学气相沉积(Metal-organic Chemical Vapor Deposition,简称MOCVD)工艺，在P、N区槽中淀积多晶AlAs1001，并将沟槽填满；
(4b)如图8k所示，采用CMP，去除表面多晶AlAs1001与第二Si3N4/SiN层602，使表面平整；
(4c)如图8l所示，采用CVD的方法，在表面淀积一层多晶AlAs1201，厚度为200～500nm；
(4d)如图8m所示，光刻P区有源区，采用带胶离子注入方法进行P+注入，使P区有 源区掺杂浓度达到0.5×1020cm-3，去除光刻胶，形成P接触1301；
(4e)光刻N区有源区，采用带胶离子注入方法进行N+注入，使N区有源区掺杂浓度为0.5×1020cm-3，去除光刻胶，形成N接触1302；
(4f)如图8n所示，采用湿法刻蚀，刻蚀掉P、N接触区以外的多晶AlAs1201，形成P、N接触区；
(4g)如图8o所示，采用CVD的方法，在表面淀积SiO21501，厚度为800nm；
(4h)在1000℃，退火1分钟，使离子注入的杂质激活、并且推进AlAs中杂质；
步骤5，构成PIN二极管步骤：
(5a)如图8p所示，在P、N接触区光刻引线孔1601；
(5b)如图8q所示，衬底表面溅射金属，在750℃合金形成金属硅化物1701，并刻蚀掉表面的金属；
(5c)衬底表面溅射金属，光刻引线；
(5d)如图8r所示，淀积Si3N4/SiN形成钝化层1801，光刻PAD，形成PIN二极管，作为制备固态等离子天线材料。
本实施例中，上述各种工艺参数均为举例说明，依据本领域技术人员的常规手段所做的变换均为本申请之保护范围。
本发明制备的应用于固态等离子可重构天线的pin二极管，首先，所使用的锗材料，由于其高迁移率和大载流子寿命的特性，提高了pin二极管的固态等离子体浓度；其次，锗材料由于其氧化物GeO热稳定性差的特性，P区和N区深槽侧壁平整化的处理可在高温环境自动完成，简化了材料的制造方法；再次，本发明制备的应用于固态等离子可重构天线的GeOI基pin二极管采用了一种基于刻蚀的深槽介质隔离工艺，有效地提高了器件的击穿电压，抑制了漏电流对器件性能的影响。
请参照图9，图9为本发明实施例提供的另一种多层全息天线中的AlAs-Ge-AlAs结构的基等离子pin二极管的结构示意图。该AlAs-Ge-AlAs结构的基等离子pin二极管采用上述如图2所示的制造方法制成，具体地，该AlAs-Ge-AlAs结构的基等离子pin二极管在GeOI衬底301上制备形成，且pin二极管的P区304、N区305以及横向位于该P区304和该N区305之间的I区均位于该GeOI衬底的顶层Ge层302内。其中，该pin二极管可以采用STI深槽隔离，即该P区304和该N区305外侧各设置有一隔离槽303，且该隔离槽303的深度大于等于该顶层Ge层302的厚度。
综上所述，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的一般技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制，本发明的保护范围应以所附的权利要求为准。
工业实用性
本发明提供的多层全息天线中AlAs-Ge-AlAs结构基等离子pin二极管的制造方法具备如下优点：
(1)pin二极管所使用的锗材料，由于其高迁移率和大载流子寿命的特性，能有效提高pin二极管的固态等离子体浓度；
(2)pin二极管采用异质结结构，由于i区为Ge，其载流子迁移率高且禁带宽度比较窄，在P、N区填充多晶AlAs从而形成异质结结构，AlAs材料的禁带宽度大于Ge，故可产生高的注入比，提高器件性能；
(3)pin二极管采用异质结结构，并且i区的Ge和P、N区的多晶AlAs的晶格失配比较低，故在异质结界面处的缺陷很少，从而提高了器件的性能；
(4)pin二极管采用了一种基于刻蚀的深槽介质隔离工艺，有效地提高了器件的击穿电压，抑制了漏电流对器件性能的影响。

Claims (10)

  1. 一种多层全息天线中AlAs-Ge-AlAs结构基等离子pin二极管的制造方法，其特征在于，所述pin二极管用于制备所述全息天线，所述全息天线包括：半导体基片、天线模块、第一全息圆环及第二全息圆环；所述天线模块、所述第一全息圆环及所述第二全息圆环均采用半导体工艺制作于所述半导体基片上；其中，所述天线模块、所述第一全息圆环及所述第二全息圆环均包括依次串接的pin二极管串；
    所述制造方法包括：
    (a)选取GeOI衬底，在所述GeOI衬底表面生成SiO2材料以形成第一SiO2层，在所述第一SiO2层表面生成SiN材料以形成第一SiN层，其中，所述第一SiO2层和所述第一SiN层构成所述GeOI衬底表面的第一保护层；
    (b)利用光刻工艺在所述第一保护层上形成第一隔离区图形；
    (c)利用干法刻蚀工艺，在所述第一隔离区图形的指定位置处刻蚀所述第一保护层及所述GeOI衬底以形成隔离槽，且所述隔离槽的深度大于等于所述GeOI衬底的顶层Ge的厚度；
    (d)填充所述隔离槽以形成隔离区；
    (e)刻蚀所述GeOI衬底形成P型沟槽和N型沟槽；
    (f)在所述P型沟槽和所述N型沟槽内淀积AlAs材料，并对所述P型沟槽和所述N型沟槽内的AlAs材料进行离子注入形成P型有源区和N型有源区；
    (g)在所述P型有源区和所述N型有源区表面形成引线，以完成所述AlAs-Ge-AlAs结构的基等离子pin二极管的制备。
  2. 如权利要求1所述的制造方法，其特征在于，步骤(e)包括：
    (e1)在所述GeOI衬底表面形成第二保护层；
    (e2)利用光刻工艺在所述第二保护层上形成第二隔离区图形；
    (e3)利用干法刻蚀工艺在所述第二隔离区图形的指定位置处刻蚀所述第二保护层及所述GeOI衬底的顶层Ge层以在所述顶层Ge层内形成所述P型沟槽和所述N型沟槽。
  3. 如权利要求2所述的制造方法，其特征在于，所述第二保护层包括第二SiO2层和第二SiN层；相应地，步骤(e1)包括：
    (e11)在所述GeOI衬底表面生成SiO2材料以形成第二SiO2层；
    (e12)在所述第二SiO2层表面生成SiN材料以形成第二SiN层。
  4. 如权利要求1所述的制造方法，其特征在于，步骤(f)之前，还包括：
    (x1)氧化所述P型沟槽和所述N型沟槽以使所述P型沟槽和所述N型沟槽的内壁形成氧化层；
    (x2)利用湿法刻蚀工艺刻蚀所述P型沟槽和所述N型沟槽内壁的氧化层以完成所述P 型沟槽和所述N型沟槽内壁的平整化。
  5. 如权利要求1所述的制造方法，其特征在于，步骤(f)包括：
    (f1)利用MOCVD工艺，在所述P型沟槽和所述N型沟槽内及整个衬底表面淀积AlAs材料；
    (f2)利用CMP工艺，平整化处理GeOI衬底后，在GeOI衬底上形成AlAs层；
    (f3)光刻AlAs层，并采用带胶离子注入的方法对所述P型沟槽和所述N型沟槽所在位置分别注入P型杂质和N型杂质以形成所述P型有源区和所述N型有源区且同时形成P型接触区和N型接触区；
    (f4)去除光刻胶；
    (f5)利用湿法刻蚀去除P型接触区和N型接触区以外的AlAs材料。
  6. 如权利要求1所述的制造方法，其特征在于，步骤(f)之后，还包括：
    (y1)在整个衬底表面生成SiO2材料；
    (y2)利用退火工艺激活所述P型有源区及所述N型有源区中的杂质。
  7. 如权利要求6所述的制造方法，其特征在于，步骤(g)包括：
    (g1)利用各向异性刻蚀工艺刻蚀掉所述P型接触区和所述N型接触区表面指定位置的SiO2材料以形成所述引线孔；
    (g2)向所述引线孔内淀积金属材料，对整个衬底材料进行钝化处理并光刻PAD以形成所述AlAs-Ge-AlAs结构的基等离子pin二极管。
  8. 如权利要求1所述的制造方法，其特征在于，所述天线模块包括第一pin二极管天线臂、第二pin二极管天线臂、同轴馈线、第一直流偏置线、第二直流偏置线、第三直流偏置线、第四直流偏置线、第五直流偏置线、第六直流偏置线、第七直流偏置线、第八直流偏置线；
    其中，所述同轴馈线的内芯线和外导体分别焊接于所述第一直流偏置线和所述第二直流偏置线；所述第一直流偏置线、所述第五直流偏置线、所述第三直流偏置线及所述第四直流偏置线沿所述第一pin二极管天线臂的长度方向分别电连接至所述第一pin二极管天线臂；
    所述第二直流偏置线、所述第六直流偏置线、所述第七直流偏置线及所述第八直流偏置线沿所述第二pin二极管天线臂的长度方向分别电连接至所述第二pin二极管天线臂。
  9. 如权利要求8所述的制造方法，其特征在于，所述pin二极管串包括多个pin二极管，所述pin二极管包括P+区、N+区和本征区，且还包括第一金属接触区和第二金属接触区；其中，
    所述第一金属接触区一端电连接所述P+区且另一端电连接至直流偏置线或者相邻的所述pin二极管的所述第二金属接触区，所述第二金属接触区一端电连接所述N+区且另一 端电连接至所述直流偏置线或者相邻的所述pin二极管的所述第一金属接触区。
  10. 如权利要求1所述的制造方法，其特征在于，所述全息天线还包括至少一个第三全息圆环，设置于所述第二全息圆环的外侧且采用半导体工艺制作于所述半导体基片上。
PCT/CN2017/110915 2016-12-20 2017-11-14 多层全息天线中AlAs-Ge-AlAs结构基等离子pin二极管的制造方法 WO2018113452A1 (zh)

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