WO2018100998A1 - 固体撮像素子、固体撮像素子の製造方法、及び、撮像装置 - Google Patents
固体撮像素子、固体撮像素子の製造方法、及び、撮像装置 Download PDFInfo
- Publication number
- WO2018100998A1 WO2018100998A1 PCT/JP2017/040359 JP2017040359W WO2018100998A1 WO 2018100998 A1 WO2018100998 A1 WO 2018100998A1 JP 2017040359 W JP2017040359 W JP 2017040359W WO 2018100998 A1 WO2018100998 A1 WO 2018100998A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- charge holding
- unit
- semiconductor substrate
- solid
- imaging device
- Prior art date
Links
- 238000003384 imaging method Methods 0.000 title claims abstract description 108
- 238000000034 method Methods 0.000 title claims description 31
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 139
- 239000000758 substrate Substances 0.000 claims abstract description 130
- 230000000149 penetrating effect Effects 0.000 claims abstract description 67
- 238000006243 chemical reaction Methods 0.000 claims abstract description 66
- 238000012546 transfer Methods 0.000 claims abstract description 54
- 239000000463 material Substances 0.000 claims abstract description 41
- 238000005192 partition Methods 0.000 claims abstract description 12
- 238000009792 diffusion process Methods 0.000 claims description 32
- 238000007667 floating Methods 0.000 claims description 32
- 230000035515 penetration Effects 0.000 claims description 19
- 238000012545 processing Methods 0.000 claims description 19
- 239000007769 metal material Substances 0.000 claims description 6
- 239000003990 capacitor Substances 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 230000003287 optical effect Effects 0.000 abstract description 13
- 239000010410 layer Substances 0.000 description 29
- 238000010586 diagram Methods 0.000 description 28
- 230000015572 biosynthetic process Effects 0.000 description 15
- 230000000875 corresponding effect Effects 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 230000006870 function Effects 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 238000001459 lithography Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 230000003321 amplification Effects 0.000 description 5
- 238000003199 nucleic acid amplification method Methods 0.000 description 5
- 239000010949 copper Substances 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 238000007740 vapor deposition Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000009412 basement excavation Methods 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 230000001276 controlling effect Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 3
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- 238000005096 rolling process Methods 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 description 2
- 241001312219 Amorphophallus konjac Species 0.000 description 1
- 235000001206 Amorphophallus rivieri Nutrition 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229920002752 Konjac Polymers 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 206010047571 Visual impairment Diseases 0.000 description 1
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000002730 additional effect Effects 0.000 description 1
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 239000000252 konjac Substances 0.000 description 1
- 235000010485 konjac Nutrition 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000000049 pigment Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000000638 solvent extraction Methods 0.000 description 1
- 239000004071 soot Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- 229920005992 thermoplastic resin Polymers 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1462—Coatings
- H01L27/14623—Optical shielding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14638—Structures specially adapted for transferring the charges across the imager perpendicular to the imaging plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14685—Process for coatings or optical elements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/50—Control of the SSIS exposure
- H04N25/53—Control of the integration time
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/62—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1462—Coatings
- H01L27/14621—Colour filter arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14625—Optical elements or arrangements associated with the device
- H01L27/14627—Microlenses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1464—Back illuminated imager structures
Definitions
- the present technology relates to a solid-state imaging device, a method for manufacturing a solid-state imaging device, and an imaging apparatus.
- Solid-state imaging devices are roughly classified into CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal-Oxide-Semiconductor) image sensors.
- CCD Charge Coupled Device
- CMOS Complementary Metal-Oxide-Semiconductor
- the shutter system of the CMOS image sensor includes a mechanical shutter system and an electronic shutter system. 2. Description of the Related Art In recent years, an electronic shutter system is mainly used for a CMOS image sensor mounted on a mobile device such as a camera-equipped mobile phone that has been widely used in order to reduce the size of the device.
- ⁇ Electronic shutter methods include rolling shutter method and global shutter method, depending on the exposure method.
- the rolling shutter system is a system in which signals are sequentially read out line by line, and the so-called “konjac phenomenon” occurs due to the readout time difference that occurs between the lines in one frame because the signals are read out line by line.
- the global shutter system since the entire frame is exposed and read out at the same time, the image is not distorted even if a fast-moving object is photographed.
- CMOS image sensor In the global shutter type CMOS image sensor, in order to realize the simultaneous storage in each pixel, a charge holding element (capacitor) is provided for each pixel, and the charges generated in the photoelectric conversion element are transferred to the charge holding element all at once. By holding, global shutter photography is possible. However, if light leaks into the charge holding element that is holding the charge, optical noise is generated and there is a concern that the image quality may deteriorate.
- Patent Documents 1 and 2 disclose a technique for realizing a global shutter system in a back-illuminated CMOS image sensor and suppressing the above-described optical noise.
- a light shielding metal that covers the charge holding element from the light incident side is provided, and the light shielding metal extends along a region between the charge holding element and the photoelectric conversion unit. It has become.
- the present technology has been made in view of the above-described problems, and aims to reduce optical noise and improve image quality in a global shutter back-illuminated CMOS image sensor.
- One aspect of the present technology includes a semiconductor substrate, a photoelectric conversion unit that photoelectrically converts incident light from the back surface of the semiconductor substrate, a charge holding unit that temporarily holds charges generated by the photoelectric conversion unit, A first penetrating light shielding film that penetrates the front and back surfaces of the semiconductor substrate and partitions the photoelectric conversion unit and the charge holding unit; and is formed of a semiconductor material outside the surface of the semiconductor substrate and straddles the first penetrating light shielding film.
- a first bypass unit that connects the photoelectric conversion unit and the charge holding unit, and a control unit that controls charge transfer from the photoelectric conversion unit to the charge holding unit via the first bypass unit,
- the front end portion of the first through-shielding light-shielding film is formed in the thickness direction of the semiconductor substrate to be approximately the same as the front end of the charge holding portion or longer in the front side direction than the front end of the charge holding portion. It is a solid-state image sensor.
- Another aspect of the present technology includes: a step of forming a photoelectric conversion unit that photoelectrically converts incident light from the back surface on a semiconductor substrate; and a charge holding unit that temporarily holds charges generated by the photoelectric conversion unit.
- a step of forming, a step of forming a first through light-shielding film that penetrates the front and back of the semiconductor substrate and partitions the photoelectric conversion unit and the charge holding unit, and a semiconductor material formed on the outer surface of the semiconductor substrate A step of forming a first bypass unit that connects the photoelectric conversion unit and the charge holding unit across the first penetrating light-shielding film, and the photoelectric conversion unit via the first bypass unit to the charge holding unit.
- a control electrode for controlling the charge transfer of the first through-shielding film, and a front end of the first through-shielding film in a thickness direction of the semiconductor substrate and a front end of the charge holding unit Forming a control electrode for controlling the charge transfer of the first through-shielding film, and a front end of the first through-shielding film in a thickness direction of the semiconductor substrate and a front end of the charge holding unit The same or a table of the charge holding portions It is formed long in the front direction than the end, a method of manufacturing a solid-state imaging device.
- an imaging device including a solid-state imaging device and a signal processing circuit that processes a signal from the solid-state imaging device
- the solid-state imaging device including a semiconductor substrate, A photoelectric conversion unit that photoelectrically converts incident light from the back surface of the semiconductor substrate; a charge holding unit that temporarily holds charges generated by the photoelectric conversion unit; and the photoelectric conversion unit that penetrates the front and back of the semiconductor substrate; A first penetrating light-shielding film that partitions the charge-holding part; a first penetrating light-shielding film that is formed of a semiconductor material outside the surface of the semiconductor substrate and that connects the photoelectric conversion part and the charge-holding part across the first penetrating light-shielding film.
- the front end of the first penetrating light shielding film includes In the thickness direction of the semiconductor substrate It is formed long in the front direction than the front end of the front end and the same level or the charge retaining portion of the charge holding unit, an image pickup device.
- the solid-state imaging device described above includes various modes such as being implemented in another device or implemented together with another method. Moreover, this technique is realizable also as an imaging device provided with the said solid-state image sensor, and the manufacturing method of the solid-state image sensor mentioned above.
- optical noise can be reduced and image quality can be improved in a global shutter type backside illuminated CMOS image sensor.
- effects described in the present specification are merely examples and are not limited, and may have additional effects.
- FIG. 4 is a diagram illustrating a cross-sectional configuration example of a pixel in the AA cross section of FIG. 3.
- FIG. 4 is a diagram illustrating a specific example of the shape of a bypass portion along the AA cross section of FIG. 3.
- FIG. 12 is a diagram illustrating a cross-sectional configuration example of a pixel in the AA cross section of FIG. 11. It is a figure which shows the figure which shows the planar structural example of the pixel which concerns on 3rd Embodiment.
- FIG. 12 is a diagram illustrating a cross-sectional configuration example of a pixel in the AA cross section of FIG. 11. It is a figure which shows the figure which shows the planar structural example of the pixel which concerns on 3rd Embodiment.
- FIG. 14 is a diagram illustrating a cross-sectional configuration example of a pixel in the AA cross section of FIG. 13. It is a figure which shows the planar structural example of the pixel which concerns on 4th Embodiment.
- FIG. 16 is a diagram showing a cross-sectional configuration example of a pixel in the AA cross section of FIG. 15. It is a figure which shows the planar structural example of the pixel which concerns on 5th Embodiment.
- FIG. 18 is a diagram illustrating a cross-sectional configuration example of a pixel in the AA cross section of FIG. 17.
- FIG. 10 is a diagram illustrating a cross-sectional configuration example of a pixel according to a sixth embodiment in a cross section corresponding to a cross section along AA in FIG. 3.
- FIG. 21 is a diagram showing a cross-sectional configuration example of a pixel in the AA cross section of FIG. 20. It is a block diagram which shows the structure of an imaging device.
- FIG. 1 is a diagram illustrating a schematic configuration of a solid-state imaging device 100 according to the present embodiment.
- the solid-state imaging device 100 is a CMOS type solid-state imaging device, and includes a pixel array unit 121, a vertical driving unit 122, a column processing unit 123, a horizontal driving unit 125, an output unit 127, and a driving control unit 124.
- the pixel array unit 121 includes a plurality of pixels 10 arranged in an array, and the pixels 10 are connected to the vertical driving unit 122 via a plurality of horizontal signal lines HSLn corresponding to the number of rows of the pixels 10. Are connected to the column processing unit 123 via a plurality of vertical signal lines VSLm corresponding to the number of columns of the pixels 10. That is, the plurality of pixels 10 included in the pixel array unit 121 are respectively arranged at points where the horizontal signal lines HSLn and the vertical signal lines VSLm intersect.
- the vertical driving unit 122 generates a driving signal (transfer signal, selection signal, reset signal, etc.) for driving each pixel 10 for each row of the plurality of pixels 10 included in the pixel array unit 121, and the horizontal signal line HSLn. To supply sequentially.
- a driving signal transfer signal, selection signal, reset signal, etc.
- the column processing unit 123 extracts a signal level of the pixel signal by performing a CDS (Correlated Double Sampling) process on the pixel signal output from each pixel 10 through the vertical signal line VSLm. Then, pixel data corresponding to the amount of light received by the pixel 10 is acquired.
- CDS Correlated Double Sampling
- the horizontal driving unit 125 outputs a driving signal for causing the column processing unit 123 to output pixel data acquired from each pixel 10 for each column of the plurality of pixels 10 included in the pixel array unit 121. Supply sequentially.
- the pixel data is supplied from the column processing unit 123 to the output unit 127 at a timing according to the drive signal of the horizontal driving unit 125, and the output unit 127 amplifies the pixel data, for example, to the subsequent image processing circuit. Output.
- the heel drive control unit 124 controls the drive of each block inside the solid-state imaging device 100.
- the drive control unit 124 generates a clock signal according to the drive cycle of each block and supplies the clock signal to each block.
- FIG. 2 is a circuit diagram illustrating a configuration example of the pixel 10.
- the pixel 10 includes a PD 11, a first transfer transistor 12, a second transfer transistor 13, a charge holding unit 14, a floating diffusion (FD) 15, an amplification transistor 16, a selection transistor 17, and a reset transistor. 18 is configured.
- the first transfer transistor 12, the second transfer transistor 13, the charge holding unit 14, the amplification transistor 16, the selection transistor 17, and the reset transistor 18 may be collectively referred to as a pixel transistor.
- PD11 receives the light irradiated to the pixel 10, and produces
- the first transfer transistor 12 is driven according to the transfer signal supplied from the vertical drive unit 122, and when the first transfer transistor 12 is turned on, the charge accumulated in the PD 11 is transferred to the charge holding unit 14.
- the second transfer transistor 13 is driven according to the transfer signal supplied from the vertical drive unit 122, and when the second transfer transistor 13 is turned on, the charge accumulated in the charge holding unit 14 is transferred to the FD 15.
- the soot charge holding unit 14 is a capacitor that accumulates charges transferred from the PD 11 via the first transfer transistor 12.
- the FD 15 is a floating diffusion region having a predetermined capacitance formed at a connection point between the second transfer transistor 13 and the gate electrode as the control electrode of the amplification transistor 16.
- the FD 15 holds charge through the second transfer transistor 13. The charges transferred from the unit 14 are accumulated.
- the amplifying transistor 16 is connected to the power supply VDD, and outputs a pixel signal at a level corresponding to the charge accumulated in the FD 15.
- the selection transistor 17 is driven according to the selection signal supplied from the vertical driving unit 122.
- the selection transistor 17 is turned on, the pixel signal output from the amplification transistor 16 can be read to the vertical signal line VSLm via the selection transistor 17. It becomes a state.
- the reset transistor 18 is driven according to a reset signal supplied from the vertical drive unit 122.
- the reset transistor 18 is turned on, the charge accumulated in the FD 15 is discharged to the power supply VDD through the reset transistor 18, and the FD 15 is Reset.
- the global shutter method is adopted, and charges can be transferred from the PD 11 to the charge holding unit 14 simultaneously for all the pixels 10. 10 exposure timings can be made the same. Thereby, it is possible to avoid the occurrence of distortion in the image.
- FIG. 3 is a diagram showing a planar configuration example of the pixel 10
- FIG. 4 is a diagram showing a sectional configuration example of the pixel 10 in the AA section of FIG.
- the pixel 10 has a backside illumination type configuration.
- the PD 11 as a photoelectric conversion unit that photoelectrically converts incident light from the back surface of the semiconductor substrate 20, the charge holding unit 14 that temporarily holds charges generated by the PD 11, and the FD 15 are planar.
- a region where the PD 11 of the semiconductor substrate 20 is formed may be referred to as a PD region, and a region where the charge holding portion 14 is formed in the semiconductor substrate 20 may be referred to as a charge holding region.
- the pixel 10 has a configuration in which a wiring layer 21, a semiconductor substrate 20, a light shielding layer 22, a planarizing layer 23, a color filter layer 24, and an on-chip lens 25 are laminated in order from the lower side of FIG.
- the color filter layer 24 may be formed directly on the semiconductor substrate 20 or the light shielding layer 22 without providing the planarizing layer 23.
- the solid-state imaging device 100 has a so-called back-illuminated CMOS image sensor structure in which incident light is irradiated to a back surface 20R opposite to the front surface 20F on which the wiring layer 21 of the semiconductor substrate 20 is laminated.
- a plurality of wirings 21a for reading out charges from the PD 11 of the semiconductor substrate 20 are embedded in the interlayer insulating film 21b.
- a substrate support (not shown) is provided below the wiring layer 21.
- a gate electrode 32 constituting the first transfer transistor 12 is disposed on the semiconductor substrate 20 via an insulating oxide film (not shown). By applying a predetermined voltage to the gate electrode 32, the charge accumulated in the PD 11 is transferred to the charge holding unit 14.
- the semiconductor substrate 20 is formed with an N-type region constituting the PD 11 and an N-type region constituting the charge holding portion 14.
- the N-type region that constitutes the PD 11 and the N-type region that constitutes the charge holding unit 14 are formed at positions near the surface 20F of the semiconductor substrate 20.
- a surface pinning layer of a P-type region may be provided on the back side of the PD 11 and the charge holding unit 14 and on the front side of the charge holding unit 14.
- an inter-pixel separation region 34 that separates the pixel 10 from other adjacent pixels 10 is formed so as to surround the outer periphery of the pixel 10.
- the light shielding layer 22 is formed in a state in which a back surface light shielding film 35 formed of a light shielding material is embedded in a high dielectric constant material film 36.
- the back surface light-shielding film 35 is formed of a material such as tungsten (W), aluminum (Al), or copper (Cu), and is connected to GND (not shown).
- the high dielectric constant material film 36 is formed of a material such as silicon dioxide (SiO 2 ), hafnium oxide (HfO 2 ), tantalum pentoxide (Ta 2 O 5 ), and zirconium dioxide (ZrO 2 ).
- a penetrating light shielding film 37 as a first penetrating light shielding film is provided between the PD 11 of the pixel 10 and the charge holding unit 14.
- the through light shielding film 37 is formed by forming a high dielectric constant material film on the entire inner surface of the through hole formed in the semiconductor substrate 20 and filling the material with light shielding properties therein.
- the high dielectric constant material film and the light shielding material are the same as those of the back surface light shielding film 35 described above.
- the penetrating light shielding film 37 is formed so as to penetrate the front and back of the semiconductor substrate 20, and has a structure that partitions between the PD 11 and the charge holding unit 14.
- the front side end of the penetrating light-shielding film 37 is formed in the thickness direction of the semiconductor substrate 20 to be approximately the same as the front side end of the charge holding unit 14 or longer in the front side direction than the front side end of the charge holding unit 14. .
- incident light from the back surface 20 ⁇ / b> R side of the semiconductor substrate 20 to the PD 11 is not obliquely incident on the charge holding unit 14.
- At least a part of the charge holding portion 14 is located on the opposite side of the PD 11 across the through light shielding film 37, and the formation range of the PD 11 and the charge holding portion 14 in the direction in which the through light shielding film 37 extends. At least part of the formation range overlaps.
- the connection length between the PD 11 and the charge holding portion 14 can be made as short as possible.
- a penetrating light shielding film 39 is provided in the inter-pixel separation region 34 between the pixel 10 and another adjacent pixel.
- the structure and material of the penetrating light shielding film 39 are the same as those of the penetrating light shielding film 37 described above.
- the penetrating light shielding film 39 is formed to penetrate the front and back of the semiconductor substrate 20 and partitions the pixel 10 from other pixels. As a result, incident light incident on the PD 11 of the pixel 10 from the rear surface 20R side of the semiconductor substrate 20 does not enter the other adjacent pixels 10 obliquely.
- the light shielding layer 22 is provided with a back surface light shielding film 35 that covers the back surface side of the charge holding portion 14.
- the back surface light shielding film 35 is formed along the back surface 20R on the back surface 20R side of the semiconductor substrate 20 where the charge holding portion 14 is provided, and the PD 11 side edge of the back surface light shielding film 35 is the back surface of the through light shielding film 37.
- the other edge of the back light shielding film 35 is connected to the back side edge of the penetrating light shielding film 39. That is, except for the side facing the front surface 20 ⁇ / b> F of the semiconductor substrate 20, the charge holding unit 14 is in a state of being optically blocked by the back surface light shielding film 35 and the through light shielding films 37 and 39.
- the high dielectric constant material film is provided so as to thinly enclose the through light shielding films 37 and 39 formed in the semiconductor substrate 20, and the high dielectric constant material film is also provided between the back light shielding film 35 and the semiconductor substrate 20. These high dielectric constant material films are continuously formed with the high dielectric constant films that cover the outer sides of the through light shielding films 37 and 39.
- the bypass unit 38 connects between the PD 11 and the charge holding unit 14 outside the surface 20F of the semiconductor substrate 20.
- the bypass portion 38 is formed of a semiconductor material to which an N-type impurity is added, and is formed so as to straddle the surface 20F of the semiconductor substrate 20 at a portion where the penetrating light shielding film 37 is provided.
- As a semiconductor material constituting the bypass portion 38 SiGe, InGaAs or the like can be used in addition to silicon.
- the bypass portion 38 is formed at a position / range including the formation ranges of the penetrating light shielding film 37, the PD 11, and the charge holding portion 14.
- the bypass portion 38 has a P-type region 38b (see FIG.
- the P-type region 38b has an N-type impurity to which an N-type impurity is added. It functions as a channel region between the region 38a (see FIG. 5) and the gate electrode 32, and serves as a charge transfer path for transferring charges from the PD 11 to the charge holding unit 14.
- FIG. 5 is a diagram showing a specific example of the shape of the bypass portion 38 along the AA cross section.
- the bypass portion 38 has a tapered side surface extending in a direction substantially orthogonal to the surface 20F of the semiconductor substrate 20, and has a trapezoidal cross section with the long side facing the semiconductor substrate 20 side.
- the basic shape of the bypass portion 38 is the same as that of the specific example shown in FIG. 5A, but the surface 20F of the semiconductor substrate 20 has a dent on both sides of the bypass portion 38. It has a wrenching shape.
- the basic shape of the bypass portion 38 is the same as that in the specific example shown in FIG. 5A, but the corner on the short side of the trapezoidal cross section of the bypass portion 38 is removed. It has a different shape. If the corners are obtuse as shown in these specific examples, electric field concentration is avoided and transfer efficiency is improved.
- a gate electrode 32 is formed as a control unit for controlling charge transfer from the PD 11 to the charge holding unit 14 via the bypass unit 38.
- the gate electrode 32 may be a polysilicon gate, a metal gate using a high-k insulating film, or the like.
- the gate electrode 32 is formed along the front side and the side surface of the bypass portion 38, and is provided at a position and shape straddling the penetrating light shielding film 37.
- a memory gate 40 is provided on the surface 20F of the semiconductor substrate 20 corresponding to the charge holding unit 14.
- the potential of the charge holding unit 14 changes and the charge transfer efficiency from the PD 11 to the charge holding unit 14 is improved. This makes it possible to suppress noise and afterimage during charge transfer.
- the solid-state imaging device 100 configured as described above can suppress the leakage of light to the charge holding unit 14 and can reduce noise components during transfer, and has significantly better characteristics than the conventional structure. Can be obtained.
- FIG. 6 to 10 are diagrams illustrating a flow according to an example of a method for manufacturing the solid-state imaging device 100.
- FIG. 6 to 10 are diagrams illustrating a flow according to an example of a method for manufacturing the solid-state imaging device 100.
- the resist R is patterned by a lithography technique on a portion where the bypass portion 38 of the surface 20F of the semiconductor substrate 20 is provided (FIG. 6A), and the surface 20F of the semiconductor substrate 20 not covered with the resist R is dried.
- Excavation is performed uniformly by etching (FIG. 6B).
- the excavation depth only needs to secure a necessary thickness for the bypass portion 38. Specifically, the range of 50 to 300 nm is exemplified.
- the resist R is peeled and removed. Thereby, the bypass part 38 on the protrusion left on the surface 20F of the semiconductor substrate 20 in the form of a bank is formed.
- the trenching shape shown in FIG. 5B is formed by locally deepening the processing end depending on processing conditions when this dry etching is applied. Note that plasma damage due to dry etching can be recovered by performing high-temperature heat treatment at 1000 ° C. or higher after processing.
- ion implantation is performed for the bypass unit 38, the PD 11, and the charge holding unit 14 (FIG. 6C). Ion implantation is performed so that the bypass unit 38, the PD 11, and the charge holding unit 14 are of the first conductivity type (N + type in this embodiment). Although not shown, necessary ion implantation is also performed on the pixel transistor.
- a second conductive type (P + type in this embodiment) pinning layer is formed by ion implantation. Charges may be prevented from flowing out on the front surface 20F and the back surface 20R of the substrate 20.
- an insulating oxide film is laminated on the surface 20F of the semiconductor substrate 20 (not shown), a gate electrode of the pixel transistor is formed at a predetermined position thereon, and a plurality of wirings 21a and interlayers of the wiring layer 21 are formed thereon. Insulating films 21b are sequentially stacked (FIG. 7D). Thereafter, although not shown, a substrate support material (support substrate, etc.) is bonded to the front surface side of the wiring layer 21, the entire surface is turned upside down, and the semiconductor substrate 20 is polished and ground from the back surface 20 R side to the back side of the PD 11. The substrate 20 may be thinned. Note that the substrate support material may be formed with a logic circuit, a memory element, or the like. In this case, a through electrode penetrating from the semiconductor substrate 20 to the substrate support material is formed, and a predetermined wiring 21a of the wiring layer 21 is formed. Are electrically connected to a logic circuit, a memory element, and the like.
- a resist R is patterned on the back surface 20R of the semiconductor substrate 20 by a lithography technique (FIG. 7E), and through holes H that penetrate the semiconductor substrate 20 from the back surface 20R side to the front surface 20F side by dry etching are formed. It forms (FIG.7 (f)).
- the resist R is peeled off.
- a high dielectric constant material is deposited on the inner surface H1 of the through hole H and the flat portion 20a of the back surface 20R of the semiconductor substrate 20 (FIG. 8G).
- the high dielectric constant material for example, a single film of oxide film (SiO 2 ), hafnium oxide (HfOx), tantalum oxide (TaOx), zirconium oxide (ZrOx), or a laminated film thereof can be applied. Thereafter, the through hole H is filled with a metal material to form the through light shielding films 37 and 39, and the back surface light shielding film 35 is formed by laminating the metal material on the flat portion 20a of the back surface 20R of the semiconductor substrate 20. (FIG. 8 (h)).
- the metal material for example, a single film of tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), or a laminated film thereof is applied. Is possible.
- a resist R is patterned on the back surface light shielding film 35 by a lithography technique, and necessary portions of the back surface light shielding film 35 are removed by dry etching to form openings (FIG. 8 (i)).
- an opening is formed at a site corresponding to the PD region of the PD 11.
- the planarizing layer 23 is formed by, for example, forming a thermoplastic resin film on the backside light-shielding film 35 by a spin coating method and then performing a thermosetting process.
- the color filter layer 24 is formed by applying a coating solution containing a color material such as a pigment or a dye and a photosensitive resin by a coating method such as a spin coating method, and the coating film is formed by a lithography technique. It is formed by pattern processing.
- the on-chip lens 25 is formed, for example, by forming a positive photoresist film on the color filter layer 24 and then processing it.
- the solid-state imaging device 100 according to the first embodiment having a global shutter function can be created.
- the bypass portion 38 is formed by lithography and dry etching, but the bypass portion 38 can also be formed by an epitaxial vapor deposition method.
- 10A to 10C are views for explaining a manufacturing method in the case where the bypass portion 38 is formed by an epitaxial vapor deposition method.
- the insulating film F is formed on the surface 20F of the semiconductor substrate 20, and the resist R in which the portion where the bypass portion 38 of the insulating film F is provided is patterned by the lithography technique and is not covered with the resist R.
- the insulating film F is excavated and removed by dry etching to open (FIG. 10A).
- SiO and SiN are generally used for the insulating film F, but the insulating film F is not limited as long as the selectivity can be secured at the time of film formation by the epitaxial vapor deposition method.
- the natural oxide film on the surface 20F of the semiconductor substrate 20 is removed by wet treatment or hydrogen reduction, and a semiconductor material such as silicon is epitaxially formed (FIG.
- Si epitaxial film formation is performed using a Si—H—Cl-based gas, and the growth rate and shape can be controlled by adjusting the H / Cl ratio.
- the facet shape shown in FIG. 5C described above when this epitaxial vapor deposition method is applied, a plurality of Si surfaces appear depending on processing conditions, and facets are formed.
- the bypass portion 38 is formed at a predetermined position on the surface 20F of the semiconductor substrate 20 (FIG. 10C).
- a bypass portion 38 is formed on the surface 20 ⁇ / b> F of the semiconductor substrate 20 as a protruding portion that is stacked and formed in a banking pattern by selective epitaxial growth.
- the solid-state imaging device 200 according to the present embodiment has the same configuration as that of the solid-state imaging device 100 described above, except that the positional relationship and shape of the PD, the charge holding unit, the bypass unit, and the like in the pixel are different.
- the positional relationship and shape of the PD 211, the charge holding unit 214, the bypass unit 238, and the like of the pixel 210 of the solid-state imaging device 200 will be mainly described, and detailed description of other configurations will be omitted, and as necessary.
- a reference numeral with 2 added to the head of the reference numeral of the configuration of the solid-state imaging device 100 is shown.
- the basic functions of the PD 211, the charge holding unit 214, the bypass unit 238, and the like are the same as those of the PD 11, the charge holding unit 14, the bypass unit 38, and the like.
- FIG. 11 is a diagram showing a planar configuration example of the pixel 210
- FIG. 12 is a diagram showing a sectional configuration example of the pixel 210 in the AA section of FIG.
- the entire gate electrode 232 of the first transfer transistor 212 is provided on the same side as the PD 211 with the penetrating light-shielding film 237 interposed therebetween, in a positional relationship adjacent to the PD 211 while partially overlapping with the formation of the PD 211. It has been.
- the gate electrode 232 has a concave portion 232 a that is not adjacent to the PD 211 but has a concave portion 232 a that is partly cut out at the corner facing the penetrating light shielding film 237.
- the gate electrode 232 is provided at a position not corresponding to the penetrating light shielding film 237 on the bypass portion 238.
- the bypass part 238 connects the gate electrode 232 and the charge holding part 214 so as to straddle the penetration light shielding film 237 outside the surface 220F of the semiconductor substrate 220, and includes the edge of the recess 232a. It is formed in a range extending across the 237 to the charge holding portion 214 side.
- At least a part of the charge holding unit 214 is located on the opposite side of the gate electrode 232 across the through light shielding film 237, and the formation range of the gate electrode 232 and the charge in the extending direction of the through light shielding film 237. At least a part of the formation range of the holding part 214 overlaps.
- bypass unit 238 becomes a charge transfer path for transferring charges from the PD 211 to the charge holding unit 214 via a channel formed under the gate electrode 232.
- the solid-state image sensor 300 according to the present embodiment has the same configuration as the solid-state image sensor 100 described above except that the shape of the gate electrode in the pixel is different.
- the shape of the gate electrode 332 of the pixel 310 of the solid-state imaging device 300 will be mainly described, and detailed description of other configurations will be omitted.
- symbol with attached is shown. Note that the basic function of the gate electrode 332 is the same as that of the gate electrode 32.
- FIG. 13 is a diagram illustrating a planar configuration example of the pixel 310
- FIG. 14 is a diagram illustrating a sectional configuration example of the pixel 310 in the AA section of FIG.
- the gate electrode 332 is formed along the front side and the side surface of the bypass portion 338, and is provided at a position and shape straddling the penetrating light shielding film 337. Accordingly, when a predetermined voltage is applied to the gate electrode 332, the charge accumulated in the PD 311 is transferred to the charge holding unit 314.
- the gate electrode 332 includes a penetrating portion 332 a extending in the thickness direction of the semiconductor substrate 320 along the side surface of the penetrating light shielding film 337 on the PD 311 side.
- a P-type region to which a P-type impurity is added is also formed in a region including the bypass portion 338 and the surface of the PD 311 in contact with the penetration portion 332a. Therefore, by providing the penetration portion 332a, a channel range formed by applying a predetermined voltage to the gate electrode 332 is expanded, and charge transfer efficiency is improved. In addition, the channel formed by the penetration portion 332a enables efficient transfer of charges at a deep position of the PD 311.
- the penetration portion 332a may have a shape in which a flat plate-like member is extended from the gate electrode 332 main body, or may have a shape in which a plurality of columnar members are extended from the gate electrode 332 main body in a comb shape.
- the length of the penetration part 332a is appropriately set according to the potential design of the PD 311.
- a gate insulating film is provided between the penetration part 332a and the semiconductor substrate 320, it is difficult to transmit light and contributes to a reduction in optical noise to the charge holding part 314.
- a metal gate made of a metal material as the gate electrode 332, the light shielding property between the PD 311 and the charge holding unit 314 can be improved, and the optical noise to the charge holding unit can be further reduced. is there.
- a material of the metal electrode for example, tungsten (W), aluminum (Al), titanium (Ti), titanium nitride (TiN), cobalt (Co), or a laminated structure thereof can be used.
- the penetration part 332a may be a metal gate, and the other part may be a silicon gate.
- the solid-state imaging device 400 according to the present embodiment has the same configuration as the solid-state imaging device 100 described above except for the structure between the charge holding unit and the floating diffusion.
- the structure between the charge holding unit 414 and the floating diffusion 415 of the pixel 410 of the solid-state image sensor 400 will be mainly described, and detailed description of other configurations will be omitted, and the solid-state image sensor 100 will be described as necessary.
- symbol head of the structure of is shown.
- the basic functions of the charge holding unit 414 and the floating diffusion 415 are the same as those of the charge holding unit 14 and the floating diffusion 15.
- FIG. 15 is a diagram illustrating a planar configuration example of the pixel 410
- FIG. 16 is a diagram illustrating a sectional configuration example of the pixel 410 in the AA section of FIG.
- a penetrating light shielding film 441 as a second penetrating light shielding film is provided between the charge holding unit 414 and the floating diffusion 415.
- the through-shading film 441 is formed by forming a high dielectric constant material film on the entire inner surface of the through-hole formed in the semiconductor substrate 420 and filling it with a light-shielding material, like the through-shading film 437 and the like.
- the penetrating light shielding film 441 is formed so as to penetrate the front and back of the semiconductor substrate 420 and has a structure for partitioning between the charge holding portion 414 and the floating diffusion 415.
- the front side end of the penetrating light shielding film 441 is formed in the thickness direction of the semiconductor substrate 420 to the same extent as the front side end of the charge holding unit 414 or longer than the front side end of the charge holding unit 414. .
- the penetrating light shielding film 441 By providing the penetrating light shielding film 441, the light shielding property between the charge holding portion 414 and the floating diffusion 415 is improved, and the influence of noise from the floating diffusion 415 side to the charge holding portion 414 can be suppressed.
- the charge holding unit 414 may have a structure in which a penetrating light shielding film similar to the penetrating light shielding film 441 is provided on the opposite side of the floating diffusion 415 of the charge holding unit 414 and the entire periphery thereof is surrounded by the penetrating light shielding film. .
- a penetrating light shielding film similar to the penetrating light shielding film 441 is provided on the opposite side of the floating diffusion 415 of the charge holding unit 414 and the entire periphery thereof is surrounded by the penetrating light shielding film.
- the charge holding unit 414 and the floating diffusion 415 are connected by a bypass unit 442 as a second bypass unit that is formed outside the surface 420F of the semiconductor substrate 420 so as to straddle the penetrating light shielding film 441.
- the bypass portion 442 is formed at a position / range including the formation range of the through light shielding film 441, the charge holding portion 414, and the floating diffusion 415.
- the bypass part 442 is formed of a semiconductor material to which an N-type impurity is added.
- the gate electrode of the second transfer transistor 13 is stacked on the surface side of the bypass unit 442, and when a predetermined voltage is applied to the gate electrode, the charge accumulated in the PD 411 is transferred to the charge holding unit. 414. That is, the bypass unit 442 serves as a charge transfer path for transferring charges from the charge holding unit 414 to the floating diffusion 415.
- the solid-state imaging device 500 according to the present embodiment has the same configuration as the solid-state imaging device 100 described above except that a light shielding film is provided on the surface side of the charge holding unit.
- the shape of the surface light-shielding film 543 of the solid-state imaging device 500 will be mainly described, detailed description of other configurations will be omitted, and 5 is added to the head of the reference numerals of the configuration of the solid-state imaging device 100 as necessary. The sign is shown.
- FIG. 17 is a diagram illustrating a planar configuration example of the pixel 510
- FIG. 18 is a diagram illustrating a sectional configuration example of the pixel 510 in the AA section of FIG.
- the surface light-shielding film 543 is a member that shields light by covering the front side of the charge holding portion 514.
- the surface light-shielding film 543 is formed on the front side of the charge holding portion 514 so as to cover the members (memory gate 540, bypass portion 538, transfer electrode 532, etc.) formed between the semiconductor substrate 520 and the wiring layer 521.
- the range covered with the surface light-shielding film 543 can be expanded or reduced as long as the semiconductor substrate 520 is not electrically interfered with the contact portion connecting the wiring 521a.
- a high dielectric constant material film is provided between the surface light-shielding film 543 and the charge holding portion 514 and various members (memory gate 540, bypass portion 538, transfer electrode 532, etc.). Thereby, the light-shielding property of the charge holding portion 514 can be further improved.
- the solid-state imaging device 600 according to the present embodiment has the same configuration as the solid-state imaging device 100 described above except for the formation range of the bypass portion formed in a raised shape.
- the formation range of the bypass portion 638 of the solid-state imaging device 600 will be mainly described, detailed description of other configurations will be omitted, and 6 will be added to the top of the reference numerals of the configuration of the solid-state imaging device 100 as necessary. The sign is shown.
- FIG. 19 is a diagram showing a cross-sectional configuration example of the pixel 610 in a cross section corresponding to the cross section AA in FIG.
- the bypass portion 638 has a shape extending not only in a portion straddling the penetrating light shielding film 637 but also in the formation range of the PD 611 on the surface 620F of the semiconductor substrate 620.
- the entire surface of the PD 611 has a raised shape that is substantially the same as the surface of the bypass portion 638.
- the solid-state imaging device 700 according to the present embodiment has the same configuration as that of the above-described solid-state imaging device 100 except that the charge holding unit is not provided and an FD accumulation type configuration in which the charge of the PD is directly transferred to the floating diffusion is adopted. It is.
- FIG. 20 is a diagram illustrating a planar configuration example of the pixel 710
- FIG. 21 is a diagram illustrating a sectional configuration example of the pixel 710 in the AA section of FIG.
- a floating diffusion 715 is provided as a configuration for receiving and holding the charge transferred from the PD 711 via the bypass unit 738. That is, at least a part of the floating diffusion 715 is located on the opposite side of the PD 711 with the through light shielding film 737 interposed therebetween, and at least the formation range of the PD 711 and the formation range of the floating diffusion 715 in the direction in which the through light shielding film 737 extends. Some overlap.
- the bypass portion 738 formed in the overlapping portion serves as a charge transfer path from the PD 711 to the floating diffusion 715.
- the charge accumulated in the floating diffusion 715 is output as a pixel signal via the contact 744 and the wiring 745.
- the solid-state imaging device 700 configured in this manner generally has a merit from the viewpoint of chip size because the charge holding portion requiring a large area can be eliminated.
- FIG. 22 is a block diagram illustrating a configuration of an imaging apparatus 800 including the solid-state imaging device 100.
- An imaging apparatus 800 illustrated in FIG. 1 is an example of an electronic device.
- an imaging device refers to a solid-state imaging in an image capturing unit (photoelectric conversion unit) such as an imaging device such as a digital still camera or a digital video camera, or a mobile terminal device such as a mobile phone having an imaging function. It refers to all electronic devices that use elements.
- an electronic apparatus using a solid-state imaging device for the image capturing unit includes a copying machine using a solid-state imaging device for the image reading unit.
- the imaging device may be modularized including a solid-state imaging device for mounting on the electronic device described above.
- an imaging apparatus 800 includes an optical system 811 including a lens group, a solid-state imaging device 100, a DSP 813 (Digital Signal Processor) as a signal processing circuit that processes an output signal of the solid-state imaging device 100, a frame memory 814, a display unit. 815, a recording unit 816, an operation system 817, a power supply system 818, and a control unit 819.
- an optical system 811 including a lens group
- a solid-state imaging device 100 As a signal processing circuit that processes an output signal of the solid-state imaging device 100
- a frame memory 814 includes a display unit. 815, a recording unit 816, an operation system 817, a power supply system 818, and a control unit 819.
- the DSP 813, the frame memory 814, the display unit 815, the recording unit 816, the operation system 817, the power supply system 818, and the control unit 819 are connected so as to be able to transmit and receive data and signals to each other via a communication bus.
- the optical system 811 takes in incident light (image light) from a subject and forms an image on the imaging surface of the solid-state imaging device 100.
- the solid-state imaging device 100 generates an electrical signal corresponding to the amount of incident light received on the imaging surface by the optical system 811 in units of pixels and outputs it as a pixel signal.
- This pixel signal is input to the DSP 813, and image data generated by appropriately performing various image processing is stored in the frame memory 814, recorded on the recording medium of the recording unit 816, or output to the display unit 815.
- image data generated by appropriately performing various image processing is stored in the frame memory 814, recorded on the recording medium of the recording unit 816, or output to the display unit 815.
- the display unit 815 includes a panel type display device such as a liquid crystal display device or an organic EL (electroluminescence) display device, and displays a moving image, a still image, and other information captured by the solid-state image sensor 100.
- the recording unit 816 records a moving image or a still image captured by the solid-state imaging device 100 on a recording medium such as a DVD (Digital Versatile Disk), HD (Hard Disk), or a semiconductor memory.
- the operation system 817 receives various operations from the user, and transmits an operation command corresponding to the user's operation to each unit 813, 814, 815, 816, 818, 819 via the communication bus.
- the power supply system 818 generates various power supply voltages serving as drive power supplies and appropriately supplies them to the supply target (respective units 813, 814, 815, 816, 817, 819).
- the control unit 819 includes a CPU that performs arithmetic processing, a ROM that stores a control program for the imaging apparatus 800, a RAM that functions as a work area for the CPU, and the like.
- the control unit 819 controls the units 813, 814, 815, 816, 817, and 818 through the communication bus by the CPU executing a control program stored in the ROM while using the RAM as a work area.
- the control unit 819 controls a timing generator (not shown) to generate various timing signals, and performs control to supply each timing signal.
- present technology is not limited to the above-described embodiments, and includes configurations in which the configurations disclosed in the above-described embodiments are mutually replaced or combinations are changed, known technologies, and the above-described embodiments. Also included are configurations in which the configurations disclosed in 1 are replaced with each other or combinations are changed. Further, the technical scope of the present technology is not limited to the embodiment described above, It extends to the matters described in the claims and their equivalents.
- a semiconductor substrate A photoelectric conversion unit that photoelectrically converts incident light from the back surface of the semiconductor substrate; A charge holding unit that temporarily holds the charge generated by the photoelectric conversion unit; A first penetrating light-shielding film that penetrates through the front and back of the semiconductor substrate and partitions the photoelectric conversion unit and the charge holding unit; A first bypass part that is formed of a semiconductor material on the outer surface of the semiconductor substrate and connects the photoelectric conversion part and the charge holding part across the first penetrating light shielding film; A control unit that controls charge transfer from the photoelectric conversion unit to the charge holding unit via the first bypass unit; With The front end portion of the first through-shielding light-shielding film is formed in the thickness direction of the semiconductor substrate to be approximately the same as the front end of the charge holding portion or longer in the front side direction than the front end of the charge holding portion. Solid-state image sensor.
- the control unit controls a control electrode provided at a position corresponding to the first penetrating light shielding film on the first bypass unit to transfer the photoelectric conversion unit to the charge holding unit via the first bypass unit.
- the control unit controls a control electrode provided at a position not corresponding to the first penetrating light shielding film on the first bypass unit to transfer the photoelectric conversion unit to the charge holding unit via the first bypass unit.
- the said control electrode has a penetration part extended in the thickness direction of the said semiconductor substrate along the side surface of the said 1st penetration light shielding film on the said photoelectric conversion part side, The said (2) or the said (3) Solid-state image sensor.
- a second bypass part that is formed of a semiconductor material outside the surface of the semiconductor substrate and connects the charge holding part and the floating diffusion across the second penetrating light shielding film;
- An imaging apparatus comprising: a solid-state imaging device; and a signal processing circuit that processes a signal from the solid-state imaging device
- the solid-state imaging device includes a semiconductor substrate, a photoelectric conversion unit that photoelectrically converts incident light from the back surface of the semiconductor substrate, a charge holding unit that temporarily holds charges generated by the photoelectric conversion unit, and the semiconductor substrate
- a first penetrating light-shielding film that divides the photoelectric conversion part and the charge holding part through the front and back surfaces of the semiconductor substrate, and is formed of a semiconductor material on the outer surface of the semiconductor substrate and straddles the first penetrating light-shielding film.
- a first bypass unit that connects the conversion unit and the charge holding unit, and a control unit that controls charge transfer from the photoelectric conversion unit to the charge holding unit via the first bypass unit,
- the front end portion of the first through-shielding light-shielding film is formed in the thickness direction of the semiconductor substrate to be approximately the same as the front end of the charge holding portion or longer in the front side direction than the front end of the charge holding portion.
- DESCRIPTION OF SYMBOLS 10 ... Pixel, 11 ... PD, 12 ... 1st transfer transistor, 13 ... 2nd transfer transistor, 14 ... Charge holding part, 15 ... Floating diffusion (FD), 16 ... Amplification transistor, 17 ... Selection transistor, 18 ... Reset transistor, 20 ... semiconductor substrate, 20F ... front surface, 20R ... back surface, 20a ... flat portion, 21 ... wiring layer, 21a ... wiring, 21b ... interlayer insulating film, 22 ... light shielding layer, 23 ... flattening layer, 24 ... color Filter layer, 25 ... On-chip lens, 32 ... Gate electrode, 34 ... Inter-pixel separation region, 35 ... Back side light shielding film, 36 ...
- PD 514 ... Charge holding part, 520 ... Semiconductor substrate, 521 ... Wiring layer, 521a ... Wiring, 532 ... Transfer electrode, 538 ... Bypass part, 539 ... Penetration light shielding film, 543 ... Surface light shielding film, 600 ... Solid-state imaging device, 610 ... Pixel, 611 ... PD, 620 ... Semiconductor substrate, 620F ... Surface, 638 ... Bypass part, 639 ... Penetration light shielding film, 700 ... Solid-state imaging device, 710 ... Pixel, 711 ... PD, 715 ... Floating Diffusion, 737 ... penetrating light shielding film, 738 ... bypass unit, 744 ...
Abstract
Description
(A)第1の実施形態:
(B)第2の実施形態:
(C)第3の実施形態:
(D)第4の実施形態:
(E)第5の実施形態:
(F)第6の実施形態:
(G)第7の実施形態:
図1は、本実施形態に係る固体撮像素子100の概略構成を説明する図である。
本実施形態に係る固体撮像素子200は、画素におけるPD、電荷保持部、バイパス部等の位置関係や形状が異なる点を除くと、上述した固体撮像素子100と同様の構成である。
本実施形態に係る固体撮像素子300は、画素におけるゲート電極の形状が異なる点を除くと、上述した固体撮像素子100と同様の構成である。
本実施形態に係る固体撮像素子400は、電荷保持部とフローティングディフュージョンの間の構造を除くと、上述した固体撮像素子100と同様の構成である。
本実施形態に係る固体撮像素子500は、電荷保持部の表面側に遮光膜を設けた点を除くと、上述した固体撮像素子100と同様の構成である。
本実施形態に係る固体撮像素子600は、盛上状に形成するバイパス部の形成範囲を除くと、上述した固体撮像素子100と同様の構成である。
本実施形態に係る固体撮像素子700は、電荷保持部を設けず、PDの電荷を直接フローティングディフュージョンへ転送するFD蓄積型の構成とした点を除くと、上述した固体撮像素子100と同様の構成である。
図22は、固体撮像素子100を備える撮像装置800の構成を示すブロック図である。同図に示す撮像装置800は、電子機器の一例である。
請求の範囲に記載された事項とその均等物まで及ぶものである。
半導体基板と、
前記半導体基板の裏面からの入射光を光電変換する光電変換部と、
前記光電変換部が生成する電荷を一時的に保持する電荷保持部と、
前記半導体基板の表裏を貫通して前記光電変換部と前記電荷保持部との間を仕切る第1貫通遮光膜と、
前記半導体基板の表面外側に半導体材料で形成され前記第1貫通遮光膜を跨いで前記光電変換部と前記電荷保持部を接続する第1バイパス部と、
前記第1バイパス部を介した前記光電変換部から前記電荷保持部への電荷転送を制御する制御部と、
を備え、
前記第1貫通遮光膜の表側の端部は、前記半導体基板の厚さ方向において、前記電荷保持部の表側端と同程度又は前記電荷保持部の表側端よりも表側方向に長く形成されている固体撮像素子。
前記制御部は、前記第1バイパス部上の前記第1貫通遮光膜に対応する位置に設けられた制御電極を制御して前記第1バイパス部を介した前記光電変換部から前記電荷保持部への電荷転送を制御する、前記(1)に記載の固体撮像素子。
前記制御部は、前記第1バイパス部上の前記第1貫通遮光膜に対応しない位置に設けられた制御電極を制御して前記第1バイパス部を介した前記光電変換部から前記電荷保持部への電荷転送を制御する、前記(1)に記載の固体撮像素子。
前記制御電極は、前記光電変換部側を前記第1貫通遮光膜の側面に沿って前記半導体基板の厚み方向に延設された貫入部を有する、前記(2)又は前記(3)に記載の固体撮像素子。
前記貫入部は、金属材料で形成されている、前記(4)に記載の固体撮像素子。
前記第1バイパス部は、前記半導体基板の表面をエッチングして盛土状に残存させた突起部である、前記(1)~前記(5)の何れか1つに記載の固体撮像素子。
前記第1バイパス部は、前記半導体基板の表面に選択エピタキシャル成長で盛土状に積層形成した突起部である、前記(1)~前記(5)の何れか1つに記載の固体撮像素子。
前記光電変換部の表面を前記第1バイパス部の表面と略同程度の盛上げ形状とした、前記(7)に記載の固体撮像素子。
前記第1バイパス部の前記第1貫通遮光膜を跨ぐ部位と前記電荷保持部との表側を覆う遮光膜を更に備える、前記(1)~前記(8)の何れか1つに記載の固体撮像素子。
前記電荷保持部は貫通遮光膜で囲われている、前記(1)~前記(9)の何れか1つに記載の固体撮像素子。
前記電荷保持部から転送される電荷を保持するフローティングディフュージョンと、
前記半導体基板の表裏を貫通して前記電荷保持部と前記フローティングディフュージョンの間を仕切る第2貫通遮光膜と、
前記半導体基板の表面外側に半導体材料で形成され前記第2貫通遮光膜を跨いで前記電荷保持部と前記フローティングディフュージョンとを接続する第2バイパス部と、
を更に備える、前記(1)~前記(1)0の何れか1つに記載の固体撮像素子。
前記電荷保持部は、キャパシタである、前記(1)~前記(1)0の何れか1つに記載の固体撮像素子。
前記電荷保持部は、フローティングディフュージョンである、前記(1)~請求項10の何れか1つに記載の固体撮像素子。
半導体基板に裏面からの入射光を光電変換する光電変換部を形成する工程と、
前記光電変換部が生成する電荷を一時的に保持する電荷保持部を形成する工程と、
前記半導体基板の表裏を貫通して前記光電変換部と前記電荷保持部との間を仕切る第1貫通遮光膜を形成する工程と、
前記半導体基板の表面外側に半導体材料で形成され前記第1貫通遮光膜を跨いで前記光電変換部と前記電荷保持部を接続する第1バイパス部を形成する工程と、
前記第1バイパス部を介した前記光電変換部から前記電荷保持部への電荷転送を制御する制御電極を形成する工程と、
を含んで構成され、
前記第1貫通遮光膜の表側の端部は、前記半導体基板の厚さ方向において、前記電荷保持部の表側端と同程度又は前記電荷保持部の表側端よりも表側方向に長く形成されている、固体撮像素子の製造方法。
固体撮像素子と、前記固体撮像素子からの信号を処理する信号処理回路と、を備える撮像装置であって、
前記固体撮像素子は、半導体基板と、前記半導体基板の裏面からの入射光を光電変換する光電変換部と、前記光電変換部が生成する電荷を一時的に保持する電荷保持部と、前記半導体基板の表裏を貫通して前記光電変換部と前記電荷保持部との間を仕切る第1貫通遮光膜と、前記半導体基板の表面外側に半導体材料で形成され前記第1貫通遮光膜を跨いで前記光電変換部と前記電荷保持部を接続する第1バイパス部と、前記第1バイパス部を介した前記光電変換部から前記電荷保持部への電荷転送を制御する制御部と、を備え、
前記第1貫通遮光膜の表側の端部は、前記半導体基板の厚さ方向において、前記電荷保持部の表側端と同程度又は前記電荷保持部の表側端よりも表側方向に長く形成されている、撮像装置。
Claims (15)
- 半導体基板と、
前記半導体基板の裏面からの入射光を光電変換する光電変換部と、
前記光電変換部が生成する電荷を一時的に保持する電荷保持部と、
前記半導体基板の表裏を貫通して前記光電変換部と前記電荷保持部との間を仕切る第1貫通遮光膜と、
前記半導体基板の表面外側に半導体材料で形成され前記第1貫通遮光膜を跨いで前記光電変換部と前記電荷保持部を接続する第1バイパス部と、
前記第1バイパス部を介した前記光電変換部から前記電荷保持部への電荷転送を制御する制御部と、
を備え、
前記第1貫通遮光膜の表側の端部は、前記半導体基板の厚さ方向において、前記電荷保持部の表側端と同程度又は前記電荷保持部の表側端よりも表側方向に長く形成されている固体撮像素子。 - 前記制御部は、前記第1バイパス部上の前記第1貫通遮光膜に対応する位置に設けられた制御電極を制御して前記第1バイパス部を介した前記光電変換部から前記電荷保持部への電荷転送を制御する、請求項1に記載の固体撮像素子。
- 前記制御部は、前記第1バイパス部上の前記第1貫通遮光膜に対応しない位置に設けられた制御電極を制御して前記第1バイパス部を介した前記光電変換部から前記電荷保持部への電荷転送を制御する、請求項1に記載の固体撮像素子。
- 前記制御電極は、前記光電変換部側を前記第1貫通遮光膜の側面に沿って前記半導体基板の厚み方向に延設された貫入部を有する、請求項2に記載の固体撮像素子。
- 前記貫入部は、金属材料で形成されている、請求項4に記載の固体撮像素子。
- 前記第1バイパス部は、前記半導体基板の表面をエッチングして盛土状に残存させた突起部である、請求項1に記載の固体撮像素子。
- 前記第1バイパス部は、前記半導体基板の表面に選択エピタキシャル成長で盛土状に積層形成した突起部である、請求項1に記載の固体撮像素子。
- 前記光電変換部の表面を前記第1バイパス部の表面と略同程度の盛上げ形状とした、請求項7に記載の固体撮像素子。
- 前記第1バイパス部の前記第1貫通遮光膜を跨ぐ部位と前記電荷保持部との表側を覆う遮光膜を更に備える、請求項1に記載の固体撮像素子。
- 前記電荷保持部は貫通遮光膜で囲われている、請求項1に記載の固体撮像素子。
- 前記電荷保持部から転送される電荷を保持するフローティングディフュージョンと、
前記半導体基板の表裏を貫通して前記電荷保持部と前記フローティングディフュージョンの間を仕切る第2貫通遮光膜と、
前記半導体基板の表面外側に半導体材料で形成され前記第2貫通遮光膜を跨いで前記電荷保持部と前記フローティングディフュージョンとを接続する第2バイパス部と、
を更に備える、請求項1に記載の固体撮像素子。 - 前記電荷保持部は、キャパシタである、請求項1に記載の固体撮像素子。
- 前記電荷保持部は、フローティングディフュージョンである、請求項1に記載の固体撮像素子。
- 半導体基板に裏面からの入射光を光電変換する光電変換部を形成する工程と、
前記光電変換部が生成する電荷を一時的に保持する電荷保持部を形成する工程と、
前記半導体基板の表裏を貫通して前記光電変換部と前記電荷保持部との間を仕切る第1貫通遮光膜を形成する工程と、
前記半導体基板の表面外側に半導体材料で形成され前記第1貫通遮光膜を跨いで前記光電変換部と前記電荷保持部を接続する第1バイパス部を形成する工程と、
前記第1バイパス部を介した前記光電変換部から前記電荷保持部への電荷転送を制御する制御電極を形成する工程と、
を含んで構成され、
前記第1貫通遮光膜の表側の端部は、前記半導体基板の厚さ方向において、前記電荷保持部の表側端と同程度又は前記電荷保持部の表側端よりも表側方向に長く形成されている、固体撮像素子の製造方法。 - 固体撮像素子と、前記固体撮像素子からの信号を処理する信号処理回路と、を備える撮像装置であって、
前記固体撮像素子は、半導体基板と、前記半導体基板の裏面からの入射光を光電変換する光電変換部と、前記光電変換部が生成する電荷を一時的に保持する電荷保持部と、前記半導体基板の表裏を貫通して前記光電変換部と前記電荷保持部との間を仕切る第1貫通遮光膜と、前記半導体基板の表面外側に半導体材料で形成され前記第1貫通遮光膜を跨いで前記光電変換部と前記電荷保持部を接続する第1バイパス部と、前記第1バイパス部を介した前記光電変換部から前記電荷保持部への電荷転送を制御する制御部と、を備え、
前記第1貫通遮光膜の表側の端部は、前記半導体基板の厚さ方向において、前記電荷保持部の表側端と同程度又は前記電荷保持部の表側端よりも表側方向に長く形成されている、撮像装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201780072855.7A CN109997229B (zh) | 2016-12-01 | 2017-11-09 | 固态成像元件及其制造方法以及成像设备 |
US16/462,334 US10777594B2 (en) | 2016-12-01 | 2017-11-09 | Solid-state imaging element, solid-state imaging element manufacturing method, and imaging device |
KR1020197010244A KR102476411B1 (ko) | 2016-12-01 | 2017-11-09 | 고체 촬상 소자, 고체 촬상 소자의 제조 방법 및 촬상 장치 |
JP2018553742A JP6967530B2 (ja) | 2016-12-01 | 2017-11-09 | 固体撮像素子、固体撮像素子の製造方法、及び、撮像装置 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016-233931 | 2016-12-01 | ||
JP2016233931 | 2016-12-01 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2018100998A1 true WO2018100998A1 (ja) | 2018-06-07 |
Family
ID=62241476
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2017/040359 WO2018100998A1 (ja) | 2016-12-01 | 2017-11-09 | 固体撮像素子、固体撮像素子の製造方法、及び、撮像装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US10777594B2 (ja) |
JP (1) | JP6967530B2 (ja) |
KR (1) | KR102476411B1 (ja) |
CN (1) | CN109997229B (ja) |
WO (1) | WO2018100998A1 (ja) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2020008907A1 (ja) * | 2018-07-06 | 2020-01-09 | ソニーセミコンダクタソリューションズ株式会社 | 受光素子、測距モジュール、および、電子機器 |
TWI685958B (zh) * | 2018-12-13 | 2020-02-21 | 力晶積成電子製造股份有限公司 | 影像感測器及其製造方法 |
JP2020092126A (ja) * | 2018-12-03 | 2020-06-11 | ソニーセミコンダクタソリューションズ株式会社 | 固体撮像素子、固体撮像素子の製造方法、および電子機器 |
JP2020181944A (ja) * | 2019-04-26 | 2020-11-05 | キヤノン株式会社 | 光電変換装置、撮像システム、および、移動体 |
WO2021149349A1 (ja) * | 2020-01-20 | 2021-07-29 | ソニーセミコンダクタソリューションズ株式会社 | 撮像素子および撮像装置 |
WO2022019307A1 (ja) * | 2020-07-22 | 2022-01-27 | 国立大学法人静岡大学 | 光電変換素子 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6929266B2 (ja) * | 2018-12-17 | 2021-09-01 | キヤノン株式会社 | 光電変換装置、光電変換システム、移動体 |
CA3144668A1 (en) * | 2019-06-28 | 2020-12-30 | Quantum-Si Incorporated | Optical and electrical secondary path rejection |
CN112117291B (zh) * | 2020-10-30 | 2022-11-18 | 联合微电子中心有限责任公司 | 一种背照式电荷域全局快门图像传感器及其制作方法 |
CN112768482B (zh) * | 2021-01-20 | 2023-03-24 | 联合微电子中心有限责任公司 | 一种背照式全局快门像素结构及其制造方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011119711A (ja) * | 2009-11-06 | 2011-06-16 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
JP2013065688A (ja) * | 2011-09-16 | 2013-04-11 | Sony Corp | 固体撮像素子および製造方法、並びに電子機器 |
JP2014022795A (ja) * | 2012-07-13 | 2014-02-03 | Sony Corp | 撮像素子、撮像方法 |
WO2014141898A1 (ja) * | 2013-03-12 | 2014-09-18 | ソニー株式会社 | 固体撮像素子、製造方法、および電子機器 |
JP2015053411A (ja) * | 2013-09-09 | 2015-03-19 | ソニー株式会社 | 固体撮像素子、固体撮像素子の製造方法、および電子機器 |
WO2016136486A1 (ja) * | 2015-02-27 | 2016-09-01 | ソニー株式会社 | 固体撮像装置及び電子機器 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR960015322B1 (ko) * | 1993-07-23 | 1996-11-07 | 현대전자산업 주식회사 | 차폐용 플레이트를 갖는 반도체소자 제조방법 |
US6093936A (en) * | 1995-06-07 | 2000-07-25 | Lsi Logic Corporation | Integrated circuit with isolation of field oxidation by noble gas implantation |
KR100209752B1 (ko) * | 1996-05-16 | 1999-07-15 | 구본준 | 마이크로 렌즈 패턴용 마스크 |
JP5601615B2 (ja) | 2009-10-22 | 2014-10-08 | 日本電気硝子株式会社 | 蓄電デバイス用負極活物質及びその製造方法 |
JP2011216673A (ja) * | 2010-03-31 | 2011-10-27 | Sony Corp | 固体撮像装置、固体撮像装置の製造方法、および電子機器 |
JP5581954B2 (ja) * | 2010-10-07 | 2014-09-03 | ソニー株式会社 | 固体撮像装置、固体撮像装置の製造方法、及び電子機器 |
JP2012230943A (ja) * | 2011-04-25 | 2012-11-22 | Panasonic Corp | X線センサーと、その製造方法と、x線センサーを用いたx線診断装置 |
-
2017
- 2017-11-09 US US16/462,334 patent/US10777594B2/en active Active
- 2017-11-09 CN CN201780072855.7A patent/CN109997229B/zh active Active
- 2017-11-09 WO PCT/JP2017/040359 patent/WO2018100998A1/ja active Application Filing
- 2017-11-09 JP JP2018553742A patent/JP6967530B2/ja active Active
- 2017-11-09 KR KR1020197010244A patent/KR102476411B1/ko active IP Right Grant
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011119711A (ja) * | 2009-11-06 | 2011-06-16 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
JP2013065688A (ja) * | 2011-09-16 | 2013-04-11 | Sony Corp | 固体撮像素子および製造方法、並びに電子機器 |
JP2014022795A (ja) * | 2012-07-13 | 2014-02-03 | Sony Corp | 撮像素子、撮像方法 |
WO2014141898A1 (ja) * | 2013-03-12 | 2014-09-18 | ソニー株式会社 | 固体撮像素子、製造方法、および電子機器 |
JP2015053411A (ja) * | 2013-09-09 | 2015-03-19 | ソニー株式会社 | 固体撮像素子、固体撮像素子の製造方法、および電子機器 |
WO2016136486A1 (ja) * | 2015-02-27 | 2016-09-01 | ソニー株式会社 | 固体撮像装置及び電子機器 |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2020008907A1 (ja) * | 2018-07-06 | 2020-01-09 | ソニーセミコンダクタソリューションズ株式会社 | 受光素子、測距モジュール、および、電子機器 |
CN112219280A (zh) * | 2018-07-06 | 2021-01-12 | 索尼半导体解决方案公司 | 光接收元件、测距模块和电子设备 |
TWI823953B (zh) * | 2018-07-06 | 2023-12-01 | 日商索尼半導體解決方案公司 | 受光元件、測距模組及電子機器 |
JP2020092126A (ja) * | 2018-12-03 | 2020-06-11 | ソニーセミコンダクタソリューションズ株式会社 | 固体撮像素子、固体撮像素子の製造方法、および電子機器 |
CN113169199A (zh) * | 2018-12-03 | 2021-07-23 | 索尼半导体解决方案公司 | 固态摄像元件、制造固态摄像元件的方法和电子设备 |
JP7280034B2 (ja) | 2018-12-03 | 2023-05-23 | ソニーセミコンダクタソリューションズ株式会社 | 固体撮像素子、固体撮像素子の製造方法、および電子機器 |
TWI685958B (zh) * | 2018-12-13 | 2020-02-21 | 力晶積成電子製造股份有限公司 | 影像感測器及其製造方法 |
JP2020181944A (ja) * | 2019-04-26 | 2020-11-05 | キヤノン株式会社 | 光電変換装置、撮像システム、および、移動体 |
JP7346071B2 (ja) | 2019-04-26 | 2023-09-19 | キヤノン株式会社 | 光電変換装置、撮像システム、および、移動体 |
WO2021149349A1 (ja) * | 2020-01-20 | 2021-07-29 | ソニーセミコンダクタソリューションズ株式会社 | 撮像素子および撮像装置 |
WO2022019307A1 (ja) * | 2020-07-22 | 2022-01-27 | 国立大学法人静岡大学 | 光電変換素子 |
Also Published As
Publication number | Publication date |
---|---|
US10777594B2 (en) | 2020-09-15 |
US20190371846A1 (en) | 2019-12-05 |
CN109997229B (zh) | 2023-06-20 |
CN109997229A (zh) | 2019-07-09 |
KR102476411B1 (ko) | 2022-12-12 |
JP6967530B2 (ja) | 2021-11-17 |
JPWO2018100998A1 (ja) | 2019-10-17 |
KR20190086660A (ko) | 2019-07-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2018100998A1 (ja) | 固体撮像素子、固体撮像素子の製造方法、及び、撮像装置 | |
JP7301936B2 (ja) | 固体撮像素子およびその製造方法、並びに電子機器 | |
US10020339B2 (en) | Solid-state imaging device, manufacturing method of solid-state imaging device and electronic apparatus | |
US8692303B2 (en) | Solid-state imaging device, electronic device, and manufacturing method for solid-state imaging device | |
JP5651976B2 (ja) | 固体撮像素子およびその製造方法、並びに電子機器 | |
US20210202565A1 (en) | Imaging device and electronic device | |
US11462582B2 (en) | Solid-state image pickup device, manufacturing method, and electronic apparatus | |
US10536659B2 (en) | Solid-state image capturing element, manufacturing method therefor, and electronic device | |
WO2015125611A1 (ja) | 固体撮像素子および製造方法、並びに電子機器 | |
JP5505709B2 (ja) | 固体撮像素子およびその製造方法、並びに電子機器 | |
WO2018173789A1 (ja) | 撮像素子、電子機器 | |
KR102268707B1 (ko) | 이미지 센서 | |
TW201301493A (zh) | 成像器件,驅動方法及電子裝置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 17877225 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 2018553742 Country of ref document: JP Kind code of ref document: A |
|
ENP | Entry into the national phase |
Ref document number: 20197010244 Country of ref document: KR Kind code of ref document: A |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 17877225 Country of ref document: EP Kind code of ref document: A1 |